Circuit and method for protecting a power switch

Abstract

A method and circuit for protecting a power switch are disclosed. The circuit includes first, second, and third power switch nodes; a feedback circuit coupled to at least one of the first, second, and third power switch nodes for regulating changes in current through the power switch; a detector circuit coupled to the feedback circuit, having an output for indicating that the change in current through the power switch is under regulation; and a timing circuit coupled to the detector circuit. The timing circuit is configured to measure the duration of the regulation of the change in current through the power switch and to compare the duration of the regulation of the change in current through the power switch with a reference. The timing circuit includes an output for generating an overcurrent signal if the duration of the regulation of the change in current through the power switch exceeds the reference.

Description

[0001] This application is a divisional application of patent application No. 201811038302.2 filed on September 6, 2018, entitled "Circuit and Method for Protecting Power Switches". Technical Field

[0002] This invention generally relates to systems and methods for overcurrent and overvoltage protection of power switches incorporating regulated di / dt and dv / dt. Background Technology

[0003] Power converters utilize various types of power switches. The outputs of these power converters may experience short-circuit or overload conditions. While protection circuits are known for handling short-circuit and overvoltage conditions, it is important to detect these conditions as quickly as possible to minimize power dissipation in the power switches. Existing protection circuits may have relatively slow response times and may not be able to prevent internal temperatures from rising to levels that could permanently damage or destroy the power switches. Summary of the Invention

[0004] According to an embodiment of the present invention, a circuit for protecting a power switch includes: a first power switch node, a second power switch node, and a third power switch node; a feedback circuit coupled to at least one of the power switch nodes for regulating changes in current through the power switch; and a detector circuit coupled to the feedback circuit, having an output for identifying changes in current through the power switch that the power switch is regulating. The detector circuit may include an additional output for identifying the level of regulation of the changes in current through the power switch. A timing circuit coupled to the detector circuit has an output for generating an overcurrent signal. The circuit may further include an additional feedback circuit coupled to at least two of the power switch nodes for regulating changes in voltage across the power switch. An additional detector circuit coupled to the additional feedback circuit has an output for identifying changes in voltage across the power switch that the power switch is regulating. The additional detector circuit may include an additional output for identifying the level of regulation of the changes in voltage across the power switch. An additional timing circuit coupled to the additional detector circuit has an output for generating an overvoltage signal. The circuit may be integrated with a power switch in a common integrated circuit or circuit board, or the power switch may be external to and remote from other circuit components.

[0005] According to another embodiment of the present invention, a method for protecting a power switch includes: sensing that a change in current through the power switch is in regulation; measuring the time during which the change in current through the power switch is in regulation; and comparing the time during which the change in current through the power switch is in regulation with a reference time. The method further includes: generating an overcurrent signal if the time during which the change in current through the power switch is in regulation exceeds the reference time. The method further includes: turning off the power switch in response to the overcurrent signal. Sensing that the change in current through the power switch is in regulation occurs simultaneously with a turn-on event. The method may further include sensing that the voltage across the power switch is in regulation.

[0006] According to another embodiment of the present invention, a method for protecting a power switch includes: sensing that a change in voltage across the power switch is in the process of adjustment; measuring the time during which the change in voltage across the power switch is in the process of adjustment; and comparing the time during which the change in voltage across the power switch is in the process of adjustment with a reference time. The method further includes: generating an overvoltage signal if the time during which the change in voltage across the power switch is in the process of adjustment exceeds the reference time. The method further includes: changing a target value of the change in current through the power switch in response to the overvoltage signal, and further counting multiple overvoltage signals. The sensing that the change in voltage across the power switch is in the process of adjustment occurs simultaneously with a shutdown event. Attached Figure Description

[0007] To gain a more complete understanding of the invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 This is a schematic diagram illustrating an exemplary driver circuit with an integrated circuit having analog and digital dv / dt feedback paths but without an external output boost circuit;

[0009] Figure 2 This is a schematic diagram illustrating an exemplary driver circuit with an external output boost circuit and an integrated circuit having analog and digital dv / dt feedback paths;

[0010] Figure 3 This is a schematic diagram illustrating an exemplary driver circuit with an integrated circuit having analog and digital dv / dt and di / dt feedback paths, without an external output boost circuit;

[0011] Figure 4 This is a schematic diagram illustrating an exemplary driver circuit with an external output boost circuit and an integrated circuit having analog and digital dv / dt and di / dt feedback paths;

[0012] Figure 5This is a schematic diagram illustrating an exemplary driver circuit with analog and digital feedback paths;

[0013] Figure 6 This is a schematic diagram illustrating an exemplary driver circuit with modified analog and digital feedback paths;

[0014] Figure 7 This is a schematic diagram illustrating an exemplary driver circuit with further modified analog and digital feedback paths;

[0015] Figure 8 It is a timing diagram showing the conduction waveform associated with the power switch;

[0016] Figure 9 It is a timing diagram showing the turn-off waveform associated with the power switch;

[0017] Figure 10 This is a timing diagram showing the overcurrent protection waveform during conduction according to the method of the present invention;

[0018] Figure 11 This is a timing diagram showing the overvoltage protection waveform during shutdown according to the method of the present invention;

[0019] Figure 12 It is a block diagram of a power switch gate driver circuit that includes dv / dt and di / dt regulation;

[0020] Figure 13 This is a schematic diagram illustrating the implementation of the adjustment circuit;

[0021] Figure 14 It is what is achieved and Figure 13 A schematic diagram of the limiting circuit associated with the circuit;

[0022] Figure 15 This is a schematic diagram of an active di / dt modulation detector according to an embodiment of the present invention;

[0023] Figure 16 An example of a time measurement circuit for generating an overcurrent signal according to an embodiment of the present invention is shown;

[0024] Figure 17 It is a timing diagram of the waveform associated with the overcurrent detection method according to the present invention;

[0025] Figure 18 This is a flowchart of the overcurrent detection method according to the present invention;

[0026] Figure 19 This is a schematic diagram of an active di / dt modulation detector including window detection and "excessive" di / dt detection according to an embodiment of the present invention;

[0027] Figure 20 This is a schematic diagram of an active dv / dt modulation detector according to an embodiment of the present invention;

[0028] Figure 21 It is a timing diagram of the waveform associated with the overvoltage detection method according to the present invention;

[0029] Figure 22 This is a flowchart of the overvoltage detection method according to the present invention;

[0030] Figure 23 This is a schematic diagram of an active di / dt modulation detector according to an embodiment of the present invention; and

[0031] Figure 24 This is a block diagram of the integrated digital path of dv / dt and di / dt according to an embodiment of the present invention. Detailed Implementation

[0032] Figures 1 to 7 The invention generally describes the regulation of voltage variation (dv / dt regulation) and current variation (di / dt regulation) of a power switch as described in German patent application DE102016111449.9 filed on June 22, 2016. Figures 1 to 7 The description provides an context for the short-circuit and overload protection features of embodiments of the present invention. (Refer to...) Figures 8 to 24 A detailed description of embodiments of the present invention is provided. In embodiments of the present invention, a power switch is configured to include both di / dt and dv / dt regulation, and is further configured to detect short-circuit and overload conditions by timing the duration for which di / dt remains in regulation during the on-state and by timing the duration for which dv / dt remains in regulation during the off-state. According to reference... Figures 8 to 24 The embodiments of the present invention describe other short-circuit and overload detection features.

[0033] In simple, common driver circuits, primarily limited by voltage overshoot during turn-off, the feedback signal acts directly on the control terminals of the semiconductor device, such as its gate. This direct feedback structure is disadvantageous because the feedback signal requires a certain amount of current to produce an effective voltage change at the gate when acting against a low gate resistance (less than 1 ohm to a few ohms). In other common driver circuits, the feedback current is lower because it acts on the input of a power amplifier stage that directly drives the gate of the semiconductor device. The input impedance at the power amplifier stage—where the feedback current must produce a voltage—is several orders of magnitude higher than the input impedance at the control terminals of the semiconductor device, such as the gate resistor. Such driver circuits typically use discrete transistors connected as current amplifiers, for example, discrete transistors with an emitter follower configuration. For high current amplification, two or three amplifier stages, such as those with a Darlington configuration, may be required. Standard passive discrete components are typically used to evaluate the voltage change per time dv / dt and / or the current change per time di / dt.

[0034] Figure 1 An exemplary driver circuit for driving a controllable semiconductor device 106—such as an insulated-gate bipolar transistor (IGBT) or any other suitable semiconductor device—is shown. The emitter of semiconductor device 106 may be connected to ground 108 via parasitic inductance 107, and its collector is connected to a load (not shown). The load path for semiconductor device 106 is the path between its emitter and collector and may include parasitic inductance 107. The driver circuit receives an external control signal, such as a control input signal 100, and includes a signal preprocessing stage 101 and a subsequent signal postprocessing stage 102, such as an internal output stage. At least the signal preprocessing stage 101 and the postprocessing stage 102 may be integrated into an integrated circuit device 103. Integrated circuit device 103 may receive the control input signal 100 and at least two feedback signals, such as an analog feedback signal 104 from an external analog dv / dt monitoring stage 105 and a digital feedback signal 114 from an external analog-to-digital converter 112, which converts the voltage into a binary word forming the digital feedback signal 114. The analog-to-digital converter 112 is connected upstream of the internal dv / dt monitoring stage 115 arranged in the integrated circuit device 103.

[0035] Feedback signal 104 (e.g., voltage and / or current) can be combined (e.g., summed) at the input of the post-processing stage in integrated circuit device 103 with internal control signal 111 (e.g., voltage and / or current) from the internal pre-processing stage. Monitoring stage 105 performs analog calculations of the voltage change dv / dt per time based on the voltage on the load path of semiconductor device 106—e.g., the voltage at the collector of the semiconductor device. Monitoring stage 115 performs digital calculations of the voltage change dv / dt per time from digital feedback signal 114, which represents the voltage on the load path of semiconductor device 106. Monitoring stage 115 controls pre-processing stage 101, which outputs analog signal 110 (e.g., voltage and / or current) based on input signal 100 and digital feedback signal 114.

[0036] In addition, external dv / dt monitoring stage 105 and internal dv / dt monitoring stage 115 evaluate the time-per-hour voltage change on the load path of the semiconductor device 106 to be controlled. Voltage evaluation may include at least one of the following operations: monitoring voltage changes, gating feedback signals, detecting voltage rises and falls, amplifying or attenuating at least one feedback signal, etc. Output stage 102 provides a control output signal 116, for example, depending on the controlled voltage and / or current of control input signal 100 and feedback signals 104 and 114, to regulate the voltage change dv / dt at the control path (gate) semiconductor device 106.

[0037] Optionally, integrated circuit device 103 can be connected to the gate of semiconductor device 106 via resistor 109. Alternatively, signal preprocessing stage 101 and post-processing stage 102 can be connected via resistor 110. Resistor 109 can have as small a resistance as possible, just enough to suppress oscillations in the control path (gate) of semiconductor device 106, thereby stabilizing the entire circuit. The current flowing into the control path (gate) of semiconductor device 106 is indirectly controlled through feedback to an output stage that forms part of signal post-processing stage 102 of integrated circuit device 103 in this example. Resistor 110 allows feedback current (forming signal 104) to generate a voltage difference with the voltage provided by preprocessing stage 101, thereby adjusting the input of the output stage of signal post-processing stage 102 to provide slope control for semiconductor device 106.

[0038] Signal preprocessing stage 101 can perform at least one of level shifting, galvanicisolation, and signal shaping. Signal postprocessing stage 102, in this example, is a voltage-to-voltage amplifier that provides any current required to achieve the output voltage, but alternatively could be a current-to-voltage amplifier, current-to-current amplifier, or voltage-to-current amplifier as shown, with the upstream and downstream circuitry of the respective amplifier adaptively adjusted accordingly. Integrated circuit device 103 can be referenced to ground 108, which is one end of parasitic inductance 107, for example, the outer terminal of parasitic inductance 107. It can be seen that feedback signals 104 and 114, representing the voltage change dv / dt, counteract resistor 110.

[0039] Reference Figure 2 It can be modified. Figure 1 The driver circuit shown uses integrated circuit device 200 instead of integrated circuit device 103, and resistor 110 is replaced by digitally controllable current source 201. It can be seen that the feedback signal 104 (current) opposes the current source 201, which ideally provides infinite DC resistance. The current source 201 is controlled by a digital dv / dt monitoring stage 208, which digitally evaluates the voltage change per second on the load path of semiconductor device 106. An analog monitoring stage 207 performs an analog calculation of the voltage change per second (dv / dt) based on the voltage on the load path of semiconductor device 106. A digital-to-analog converter 112 connected between the analog monitoring stage 207 and the digital dv / dt monitoring stage 208 converts the obtained analog dv / dt signal from the analog monitoring stage 207 into a digital dv / dt signal for the digital dv / dt monitoring stage 208. The current source 201 can be further adjusted to provide a specific current for different semiconductor devices 106.

[0040] Furthermore, an external power amplifier 202 can be inserted between the post-processing stage 102 and the resistor 109. In this example, the power amplifier 202 includes an amplifier stage formed by complementary transistor pairs (e.g., having pnp bipolar transistor 203 and npn bipolar transistor 204), the complementary transistor pairs being connected between the negative voltage supply line 205 and the positive voltage supply line 206 in a complementary emitter follower configuration. For example, the post-processing stage 102 may have a current drive capability of up to 1 or 2 amps, and the current amplifier 202 can increase the capability by 10 to 50 times, enabling... Figure 2The circuit shown includes a reduction resistor 109. The post-processing stage 102 and / or current amplifier 202 may alternatively have a Class A or Class A / B amplifier configuration to improve the speed of switching from positive to negative current. Alternatively or additionally, the post-processing stage 102 and / or power amplifier 202 may have more than one amplifier stage to achieve very low parasitic driver inductance. The digital monitoring stage 115 is replaced by a digital monitoring stage 208, which digitally processes the digital input signal and provides a digital output signal.

[0041] By providing access to the inputs of the integrated circuit device's internal output stage, the current supplied by the feedback stage can be further reduced (to approximately 10mA) due to the smaller parasitic capacitance and increased speed and flexibility offered by the integrated circuit. Simultaneously, it reduces the number of cascaded external output stages required. The output stage typically provides a maximum current of 0.5A to 2A, or in some cases, up to 6A. Furthermore, the feedback path requires less current feeding, necessitating smaller feedback capacitors (small additional capacitance at high-voltage switching nodes), resulting in a more efficient circuit in terms of power consumption and size. Amplifying this current through one or more external stages can provide sufficient current to drive very large IGBT devices, power semiconductor modules, etc. Instead of driving the inputs of the internal power stage via a controlled voltage source and resistors, it can be driven by a controlled current source that provides both positive and negative currents. This allows for more linear (if the dv / dt feedback capacitor is linear) and load-independent regulation of dv / dt (and / or di / dt).

[0042] like Figure 3 As shown, it can be modified. Figure 2The driver circuit shown uses integrated circuit device 300 instead of integrated circuit device 200, omits current source 201, and connects feedback processing and superposition stage 301 between preprocessing stage 101 and postprocessor stage 102. Digital dv / dt monitoring stage 207 digitally processes digital input signals, such as binary signals representing the voltage on the load path of semiconductor device 106, and provides digital output signals, such as binary signals representing the derivative of the voltage on the load path of semiconductor device 106. Furthermore, at least one other external feedback stage, such as external analog dv / dt monitoring stage 302 and / or external digital dv / dt monitoring stage 303, is connected to the load path of semiconductor device 106 via analog-to-digital converter 304. Feedback processing and superposition stage 301 receives signals from dv / dt monitoring stages 105 and 207, signal preprocessing stage 101, and also from analog dv / dt monitoring stage 302 and digital dv / dt monitoring stage 303. The digital di / dt monitoring stage 303 digitally processes digital input signals, such as binary signals representing the current through the load path of the semiconductor device 106, and provides digital output signals, such as binary signals representing the derivative of the current through the load path of the semiconductor device 106.

[0043] Figure 3 The driver circuit shown can be as follows Figure 4 The following modification is shown, in which power amplifier 400 is inserted between post-processing stage 102 and resistor 109. In this example, power amplifier 400 includes an amplifier stage formed by complementary transistor pairs (e.g., having pnp bipolar transistor 401 and npn bipolar transistor 402), the complementary transistor pairs being connected in a complementary emitter follower configuration between negative voltage supply line 403 and positive voltage supply line 404. Alternatively, power amplifier 400 may have more than one amplifier stage to achieve very low parasitic driver inductance and / or may have a Class A or Class A / B amplifier configuration to improve the speed of switching from positive to negative current. Furthermore, digital dv / dt monitoring stage 207 is replaced by digital dv / dt monitoring stage 405, and digital di / dt monitoring stage 303 is replaced by digital di / dt monitoring stage 406. dv / dt monitoring stage 405 and di / dt monitoring stage 406 digitally process the digital input signals and provide digital (binary) output signals.

[0044] Reference Figure 5Another exemplary driver circuit includes an integrated circuit device 500 having a low-voltage circuit portion and a higher-voltage circuit portion that is current-isolated from the low-voltage circuit portion. The low-voltage circuit portion includes an undervoltage lockout (UVLO) block 501 that receives a (positive) power supply voltage VCC1 of the integrated circuit device 500 and a first ground GND1 referenced by the integrated circuit device 500. The undervoltage lockout block 501 is an electronic circuit block for disabling and / or shutting off power to the integrated circuit device 500 when the power supply voltage VCC1 drops below an operating value. For example, in the integrated circuit device 500, the undervoltage lockout block 501 may monitor the power supply voltage VCC1 and shut down the circuit if the power supply voltage VCC1 drops below a certain threshold, thereby protecting the integrated circuit device 500 and, depending on the circumstances, also protecting semiconductor devices and / or loads associated with the integrated circuit device 500. The low-voltage circuit portion of the integrated circuit device 500 may also include a logic block 502, which receives an input (control) signal IN for example for switch control and an enable signal EN for example for enabling or disabling, such as the logic block 502, the integrated circuit device 500, or the entire driver circuit.

[0045] Logic block 502 may also provide a digital input / output interface (DIO) for exchanging digital data—such as specific control data, status data, service data, etc.—with other units (not shown). Furthermore, logic block 502 may utilize a clock signal provided by clock signal generator 503 for clock timing and may be connected to a current-isolated bidirectional signal coupler 504, which may provide isolation based on inductance (as shown), capacitance, optical, or any other suitable method. Alternatively, another signal coupler 505, such as a unidirectional coupler, may couple the low-voltage circuit section and the higher-voltage circuit section in terms of signal but isolate them in terms of current.

[0046] In the higher voltage circuit section, signal couplers 504 and (if present) signal coupler 505 are connected to control block 506, which can be a logic block or software block or a combination of both in a processor implementation. Control block 506 receives a clock signal from clock signal generator 507 and a signal from undervoltage lockout block 508 for the higher voltage circuit section. Control block 506 exchanges digital data with central signal processing block 509, which can provide load path voltage / current slope post-processing, regulation, and adaptation. For example, central signal processing block 509 can be adjusted or programmed to implement a digital loop controller including at least one or a combination of proportional (P), integral (I), and derivative (D) control mechanisms, such as PI or PID control mechanisms. Furthermore, control block 506 sends on / off signals to central signal processing block 509 and memory 510, sends sampling control signals to two analog-to-digital converter blocks 511 and 512, and sends another on / off signal along with slope shape data to level conversion block 513. Analog-to-digital converters 511 and 512 send data to memory 510. Analog-to-digital converter 511 receives a voltage sensing signal VSD (e.g., voltage or current) referenced to the second ground GND2, and analog-to-digital converter 512 receives a current sensing signal IS (e.g., voltage or current) referenced to the second ground GND2.

[0047] Level shifting block 513 sends control data to adaptive driver block 514, which may include two digitally controllable current sources 515 and 516 connected in series between (negative) supply voltage VEE2 and (positive) supply voltage VCC2, with a node 517 between the two digitally controllable current sources 515 and 516. At least one of the supply voltages VEE2 and VCC2 may be monitored by undervoltage lockout block 508. Each of the current sources 515 and 516 is controlled by digital data provided by level shifting block 513. Driver output stage 518 is connected to node 517, a line carrying a voltage sensing signal (e.g., voltage or current), and the output of transconductance amplifier block 519, whose non-inverting input is connected to a second ground GND2 and whose inverting input is connected to a line receiving a current sensing signal IS (e.g., the voltage across an inductor corresponding to the change in current to be measured).

[0048] The external wiring of integrated circuit device 500 includes two capacitors 520 and 521, which couple the collector line of semiconductor device 106 to the lines carrying voltage sensing signals VSD and VSA, respectively. The two capacitors 520 and 521 are used to obtain dv / dt from the voltage on the load path. A second ground, GND2, is established through a node between the emitter of semiconductor device 106 and one end of parasitic inductance 107. The current sensing signal IS is picked up at the other end of parasitic inductance 107. Inductance 107 is used to differentiate the current through the load path to obtain di / dt and convert the current into the corresponding voltage to be measured. The gate of semiconductor device 106 is connected to output stage 518 via resistor 522. Power supply voltages VEE2 and VCC2 can be provided by a bipolar voltage source 523, the ground of which is connected to the second ground, GND2. Optionally, a power amplifier 524 with power supply voltages VEE2 and VCC2 can also be connected between the output stage 518 and resistor 522. Figure 5 In the exemplary driver circuit shown, blocks 501-509 and 513 can form a preprocessing stage, blocks 510-512 and 519 can form a feedback processing and superposition stage, and blocks 515-518 can form a signal post-processing stage.

[0049] By adding external feedback capacitors (e.g., capacitors 520 and 521) and providing a power stage (e.g., output stage 518) for the buffered current source driver (e.g., driver block 514), the dv / dt feedback and / or di / dt feedback require much lower peak current on the current source driver. In this way, the current source driver can be designed with lower power components, allowing the current source to change its current value more accurately and quickly. Furthermore, the current source driver can be constructed as a current-output digital-to-analog converter that can be digitally programmed to change dv / dt and / or di / dt. Additional external digital loop conditioning loops can be added to further enhance this. Figure 5 The diagram shows the control of dv / dt and / or di / dt. The programming of dv / dt and di / dt can be changed individually without altering the analog feedback network of dv / dt or di / dt. The digital loop can track changes in the load path voltage and load path current to change the digital-to-analog converter output current at the correct time when a switch occurs between dv / dt and di / dt. Typically, analog feedback paths are faster (smaller delay times due to signal processing and / or higher critical frequencies) but offer lower accuracy and flexibility. Conversely, digital feedback paths are slower (larger delay times due to signal processing and / or lower critical frequencies) but offer greater accuracy and flexibility.

[0050] Figure 5The driver circuit shown is an example of how an integrated driver with high voltage level shifting and analog and digital dv / dt and di / dt feedback paths can be implemented. The di / dt feedback path (e.g., corresponding to signal IS) senses the voltage at the emitter inductor (e.g., parasitic inductance 107), thereby injecting a corresponding (e.g., proportional) current into a summation node (e.g., node 517) of the reference current derived from the current source pre-driver stage (e.g., transconductance amplifier block 519) and the dv / dt analog feedback capacitor (e.g., capacitor 521), or drawing a corresponding (e.g., proportional) current from the summation node (e.g., node 517) of the reference current derived from the current source pre-driver stage (e.g., transconductance amplifier block 519) and the dv / dt analog feedback capacitor (e.g., capacitor 521). The summing node controls the input of a unity-gain amplifier (either an internal stage such as output stage 518 or in combination with an external cascaded stage such as current amplifier 524), which in turn drives the gate voltage of an external semiconductor device (e.g., semiconductor device 106). The dv / dt digital feedback path can be implemented by an analog-to-digital converter (e.g., analog-to-digital converter block 511) that samples the current flowing through the dv / dt digital feedback capacitor (e.g., capacitor 520). The di / dt digital feedback path is implemented by an analog-to-digital converter (e.g., analog-to-digital converter block 512) that samples the voltage change on the emitter inductor (e.g., parasitic inductor 107) representing the current change through the emitter inductor.

[0051] Figure 6 The above combination is shown. Figure 5 The described driver circuit has some modifications and alternative implementations. Two digitally controllable current sources 515 and 516 are connected to each other via a diode series connection 600 of one or more diodes (e.g., four diodes), forming a node 601 between current source 515 and one end of the diode series connection 600, and a node 602 between current source 516 and the other end of the diode series connection 600. Each digitally controllable current source 515, 516 is connected in parallel with constant current sources 603 and 604, respectively. The line carrying the voltage sensing signal VSA is connected to node 601, and the line carrying the current sensing signal IS is connected to node 602 via a resistor 605 and a diode 606 (instead of the transconductance amplifier block 519).

[0052] Figure 5The output stage 518 shown is replaced by a Class A / B amplifier stage, which includes an n-channel MOSFET 607 whose gate is connected to node 601 and whose drain is connected to the supply voltage VCC2, and a p-channel MOSFET 608 whose gate is connected to node 602 and whose drain is connected to the supply voltage VEE2. The sources of transistors 607 and 608 are connected to each other via another diode connected in series 609 having at least one diode (e.g., two diodes). Furthermore, an n-channel MOSFET 610 is connected to a second ground GND2 via its gate and to a line carrying a voltage sensing signal VSA via its drain. The source of transistor 610 is connected to a line carrying a current sensing signal IS via a linearization resistor 611. In addition, resistor 612 can be connected between the line carrying the voltage sensing signal VSD and the second ground GND2, and a voltage divider including two resistors 613 and 614 connected in series is connected between the second ground GND2 and the line carrying the current sensing signal IS to reduce voltage swing at the corresponding analog-to-digital converter input when needed.

[0053] The input of analog-to-digital converter block 512 is now connected to the node between resistors 613 and 614 (instead of being directly connected to the line carrying the current sensing signal IS). Optionally, an external resistor 615 can be connected in parallel to resistor 612. The current amplifier 524 can be implemented in this example using an n-channel MOSFET 616 whose gate is connected to the source of transistor 607 and whose drain is connected to the supply voltage VCC2, and a p-channel MOSFET 617 whose gate is connected to the source of transistor 608 and whose drain is connected to the supply voltage VEE2. The sources of transistors 607 and 608 are connected to each other and to resistor 522.

[0054] exist Figure 6 In the driver circuit, the unity-gain buffer stage ( Figure 5 The output stage 518 consists of two cascaded Class A / B amplifier stages ( Figure 6 The transistors 607, 608, 616, 617 and the diode connected in series (609) and two bias current sources ( Figure 6 The constant current sources 603 and 604 in the original are replaced. The analog dv / dt feedback path remains unchanged. The analog di / dt feedback path is replaced by those used for turning on (transistor 610 and resistor 611) and turning off (transistor 610 and resistor 611). Figure 6 The two separate feedback paths of resistor 605 and diode 606 in the circuit are replaced.

[0055] Combined on the above Figure 6In the driver circuit discussed, resistor 605 and diode 606 can be replaced by n-channel MOSFET 700, resistor 701, p-channel MOSFETs 702 to 704, and current source 705. For example... Figure 7 As shown, transistor 700 can be connected via its gate to the line carrying the current sensing signal IS and via its source to the second ground GND2 through linearization resistor 701, thereby providing voltage-to-current conversion. Transistor 702 is connected via its drain to the power supply voltage line VEE2, via its gate to the drains of transistors 700 and 704, and via its source to the gates of transistors 703 and 704. Current source 705 is connected between the power supply voltage line VCC2 and the gates of transistors 703 and 704. The sources of transistors 703 and 704 are also connected to the power supply voltage line VCC2. The drain of transistor 703 is connected to node 602. Transistors 702 to 704 connected with current source 705 form a current mirror circuit that reverses the turn-off di / dt feedback current from transistor 700. The speed of the current mirror with transistors 703 and 704 is increased by adding transistor 702 as a source follower. Current source 705 is added to accelerate the current mirror in both directions. In addition, diode 706 is inserted between the line carrying the voltage sensing signal VSA and the drain of transistor 610.

[0056] Figure 7 The driver circuit shown also allows operation when ground GND2 is not the same as the supply voltage VEE2, so that the gate driver can also be powered by a bipolar supply. Furthermore, the turn-off di / dt feedback does not feed current directly to the summing node through a resistor, which makes the feedback load dependent, for example, on the load condition of semiconductor device 106 and / or its Miller plateau. For example, if the voltage change dv / dt is directly fed back to the summing node from the collector of semiconductor device 106 through a capacitor (capacitor 520), the feedback current through the feedback capacitor (capacitor 520) will depend on the voltage change dv / dt at the collector of semiconductor device 106 when the gate voltage of semiconductor device 106 is at the Miller plateau. However, if the current is fed directly through a resistor (e.g., ... Figure 6 If the resistor 605 in the circuit is fed back, the current change di / dt will become the voltage difference between the di / dt induced voltage of the inductor (parasitic inductance 107) and the actual voltage level of the gate of the semiconductor device 106 (or the input of the buffer stage).

[0057] exist Figure 7In the driver circuit shown, semiconductor device 106 is driven by a bipolar power supply and load-independent di / dt feedback. For on-di / dt, a simple diode (diode 706) is reverse-biased when the summing node (including the gate of transistor 607) is pulled low below the second ground GND2. Transistor 610, acting as a source follower, automatically generates a switch from positive current regulation to negative current regulation via resistor 611. The current summing node (including the gate of transistor 607), with dV / dt through capacitor 521 and di / dt through inductor 107, automatically switches from dV / dt regulation to di / dt regulation. To make the off-time feedback load-independent, a transconductance amplifier can be configured to differentially measure the voltage across parasitic inductor 107 and then inject a high-side current independent of the summing node voltage into summing node 602. A concept similar to di / dt feedback of the conduction voltage change can be implemented to generate a current proportional to the voltage across the parasitic inductor 107 when the semiconductor device 106 is turned off. However, this current has the wrong polarity. To obtain the correct current polarity, high-side current mirrors (transistors 703 and 704) are used. Transistor 702 and current source 705 are used to achieve the necessary bandwidth in the current mirror. The method outlined above can also be implemented with discrete devices, but when implemented in an integrated circuit, control speed and control of parasitic elements may be more advantageous.

[0058] Combined on the above Figures 1 to 7 In the described example, the analog feedback stage and the digital feedback stage include signal delay times due to their respective signal processing. The signal delay time of the digital feedback stage can be greater than that of the corresponding analog feedback stage. However, the accuracy of the digital feedback stage may be greater than that of the corresponding analog feedback stage. Furthermore, the digital feedback stage or path can include not only digital circuits but also analog and digital (mixed-signal) circuits.

[0059] One embodiment of the invention combines the circuit described above for adjusting the di / dt and dv / dt of the power switch when the power switch is turned on and off with a circuit that uses the adjusted di / dt to detect the overcurrent (SC1) during on-off and a circuit that uses the adjusted dv / dt to detect the overvoltage during off-off. Time measurements can be used to determine the current and voltage levels because the values ​​of di / dt and dv / dt are adjusted and are known. Refer below... Figures 8 to 11 Discuss timing measurements associated with power switches.

[0060] Figure 8This is a timing diagram showing the conduction waveforms associated with a power switch regulated by di / dt and dv / dt. The first timing diagram portion 802 shows a drain-source or collector-regulated current waveform 806, which also shows current overshoot that can be caused by the reverse recovery charge Qrr of the diode or the charging of the capacitor. Timing diagram portion 802 also shows a drain-source or collector-emitter regulated voltage waveform 808. di / dt Time interval 814 indicates the time the switch is in current regulation until the peak current value. The second timing diagram portion 804 shows the gate-source or gate-emitter voltage 810 and the corresponding control signal 812 associated with the turn-on event.

[0061] Figure 9 This is a timing diagram showing the turn-off waveforms associated with a power switch regulated by di / dt and dv / dt. The first timing diagram portion 902 shows a drain-source or collector-emitter regulated current waveform 906. Timing diagram portion 902 also shows a drain-source or collector-emitter regulated voltage waveform 908. dv / dt Time interval 914 indicates the duration of voltage regulation by the switch. The second timing diagram portion 904 shows the gate-source or gate-emitter voltage 910 and the corresponding control signal 912 associated with the turn-off event.

[0062] For a known di / dt, the time during which the target di / dt is in the regulation state is a measure of the peak current when the circuit is on.

[0063] Equation 1

[0064] Therefore, if T di / dt >T di / dt,limit If the switch is turned off, it can be protected from overcurrent conditions, which will be discussed in more detail below according to embodiments of the invention.

[0065] Figure 10 This is a timing diagram showing the overcurrent protection waveforms during conduction according to the method of the embodiment. The first timing diagram portion 1002 shows the drain or collector regulated current waveforms 1006A (high current), 1006B (medium current), and 1006C (low current). Timing diagram portion 1002 also shows the drain-source or collector-emitter regulated voltage waveforms 1008A (high current), 1008B (medium current), and 1008C (low current). di / dt The time interval 1014 indicates the time the switch is in current regulation until the peak current value. For high current conditions, T... di / dt The time interval exceeds T di / dt,limitThe time interval, followed by the switch being turned off. The second timing diagram section 1004 shows the gate-source or gate-emitter voltage waveforms 1010A (high current), 1010B (medium current), and 1010C (low current) and the corresponding control signal 1012 associated with the turn-on event.

[0066] For a known dv / dt, the time during which the target dv / dt is in regulation is a measure of the voltage across the switch when it is turned off.

[0067] Equation 2

[0068] Therefore, if T dv / dt >T dv / dt,limit A lower di / dt can be used to turn off the power switch in order to limit the amount of overvoltage caused by negative di / dt, which will be discussed in further detail below according to an embodiment of the invention.

[0069] Figure 11 This is a timing diagram showing the overvoltage protection waveforms during shutdown according to the method of the embodiment. The first timing diagram portion 1102 shows the drain or collector regulated current waveforms 1106A (high voltage) and 1106B (medium and low voltage). Timing diagram portion 1102 also shows the drain-source or collector-emitter regulated voltage waveforms 1108A (high voltage), 1108B (medium voltage), and 1108C (low voltage). dv / dt Time interval 1114 indicates the duration the switch is in voltage regulation. For high voltage conditions, T... dv / dt The time interval exceeds T dv / dt,limit The time interval, and the subsequent result is a change in the adjusted di / dt value. The second timing diagram section 1104 shows the gate-source or gate-emitter voltage waveforms 1110A (high voltage), 1110B (medium voltage), and 1110C (low voltage) and the corresponding control signal 1112 associated with the turn-off event.

[0070] The advantage of the circuit implementation of the present invention is its fast detection speed, thus preventing damage to the power switch under short-circuit or overload conditions. Another advantage of the circuit implementation of the present invention is that essentially the same hardware discussed above for adjusting di / dt and dv / dt can be reused to detect short-circuit conditions (SC1) and overload conditions (SC2).

[0071] Figure 12This is a block diagram 1200 summarizing a power switch gate driver circuit including dv / dt and di / dt regulation according to an embodiment of the present invention. Block diagram 1200 includes a power switch 1208 and an anti-parallel freewheeling diode 1210. A differentiating circuit 1214 is coupled to the collector node "C" to receive the collector voltage and multiply it by a constant factor 1212. Similarly, a differentiating circuit 1220 is coupled to the emitter node "E" and multiplied by a constant factor 1218, and passes through an optional limiting circuit 1216. The outputs of the differentiating circuit 1212 and the limiting circuit 1216 are summed in an adder 1202, which also receives a reference voltage v. ref,d / dt The output of adder 1202 is coupled to a proportional (P, PI, or PID) controller 1204, which is in turn coupled to a preamplifier 1206. Preamplifier 1206 drives the gate node "G" of power switch 1208. Block diagram 1200 shows a circuit with combined closed-loop current slope control and voltage slope control, which can be extended to include additional gate current control comprising switch 1222, adder 1224, and constant factor 1226. Signal v ref,d / dt It is a reference value for current and voltage slope control, v ctrl,clip It is the control command for the limiting circuit, v ref,iG It is the reference value for gate current control, while v ctrl,iG This is a control command used for gate current control. A limiting circuit is used to remove negative di / dt values ​​during dv / dt adjustment. When di / dt and dv / dt are zero, an optional gate current control circuit is used to adjust the gate current during the turn-on and turn-off delay phases. This helps to preset or prevent overall saturation (windup) of the controller 1204.

[0072] Figure 13 Therefore Figure 12 The block diagram 1300 illustrates the implementation of the adjustment circuit. The circuit diagram 1300 uses an operational amplifier 1302 with amplification k... I An additional amplifier with optional limiting circuitry 1308 and an associated feedback resistor provides closed-loop regulation of di / dt and dv / dt for power switch 1304 and anti-parallel freewheeling diode 1306 to provide the regulation function as described above. Limiting circuitry 1308 is used to prevent negative di / dt feedback when on. Operational amplifier 1310, switch 1312, and associated feedback resistor provide optional gate current control as described above.

[0073] Figure 14 It is what is achieved and Figure 13 The constant factor k associated with the circuit IA schematic diagram of a limiting circuit 1400 is shown, which receives an emitter voltage 1404 and a control voltage 1406 to provide a limiting voltage at node 1408. The limiting circuit 1400 includes a MOS transistor Sc, a Zener diode Dc, capacitors C1, C2, and C3, and resistors R1, R2, and R3. The voltage at the junction between resistors R2 and R3 is sensed by an operational amplifier 1402, which includes feedback resistors Rg1 and Rg2, to provide a limiting voltage at node 1408.

[0074] Figure 15 This is a schematic diagram of an active di / dt modulation detector 1500 according to an embodiment of the present invention. Figure 14 The circuit, and the operational amplifier 1402 corresponds to Figure 15 The operational amplifier 1502 is used. By adding the comparator 1504 and the time measurement circuit discussed below, overcurrent protection can be used to supplement the di / dt and dv / dt regulation according to an embodiment of the invention.

[0075] The comparator 1504, placed after the di / dt attenuator and buffer circuit 1502, can detect whether di / dt is higher or lower than that determined by V. ref,di / dt The voltage gives a specific value. Figure 15 In the text, the reference is given as a negative value when the voltage V Ee,clip Above this value, di / dt is not at the target di / dt or is insufficient to exceed the target value, and the comparator output is low. When V Ee,clip Voltage below V ref,di / dt When this occurs, the comparator 1504 output goes high, indicating that the di / dt adjustment loop is in adjustment. If the active di / dt signal remains high for a longer than a predetermined time, an overcurrent event occurs. Furthermore, in embodiments of the invention, the gate driver can initiate the shutdown of the driven power switch. Because di / dt is adjusted, V... Ee,clip It will have a DC voltage value during regulation.

[0076] Although a representation of the di / dt and dv / dt closed-loop regulation circuit has been shown, and nodes associated with di / dt and dv / dt regulation have been identified, other such regulation circuits are possible, and various nodes in such circuits would be suitable candidates for use with embodiments of the short-circuit and overload protection features of the present invention, as discussed in further detail below.

[0077] Figure 16An example of a time measurement circuit 1600 for generating an overcurrent signal according to an embodiment of the present invention is shown, having an active di / dt indicator as an input and an "overcurrent" indicator as an output. A first timing circuit includes a microcontroller 1602 capable of digitally counting the duration of the active di / dt signal measured between its rising and falling edges. Although a microcontroller 1602 is shown, other digital / logic circuitry (i.e., a time-to-digital converter, TDC) can be used. A second timing circuit includes a resistor and a capacitor 1606 coupled to the positive input of a comparator 1608. The negative input of the comparator 1608 is coupled to a reference voltage. If the active di / dt signal remains active for a sufficient time interval, the comparator 1608 will provide an overcurrent signal. Similarly, a third timing circuit includes a current source 1610 controlled by the active di / dt signal and used to charge a capacitor 1612. If the active di / dt signal remains active for a sufficient time interval, the comparator 1614 will provide an overcurrent signal.

[0078] Figure 17 This is a timing diagram of the relevant waveforms of the overcurrent detection method according to an embodiment of the present invention, associated with the conduction of a power switch. The first timing diagram portion 1702 shows the drain-source or collector-emitter regulated current waveforms 1712A (high current), 1712B (medium current), and 1712C (low current). Timing diagram portion 1702 also shows the drain-source or collector-emitter regulated voltage waveforms 1714A (high current), 1714B (medium current), and 1714C (low current). di / dt Time interval 1728 indicates the time the switch is in current regulation until the peak current value. Second timing diagram section 1704 shows the gate-source or gate-emitter voltage waveforms 1716A (high current), 1716B (medium current), and 1716C (low current) and the corresponding control signal 1718 associated with the turn-on event. Third timing diagram section 1706 shows the limiting voltage waveforms 1720A (high current), 1720B (medium current), and 1720C (low current). Fourth timing diagram section 1708 shows the activation di / dt waveforms 1722A (high current), 1722B (medium current), and 1722C (low current). Fifth timing diagram section 1710 shows the time integrator waveforms 1724A (high current), 1724B (medium current), and 1724C (low current). Timing diagram section 1710 also shows an overcurrent signal 1726 associated with a time interval 1728 exceeding the limit time interval due to the high current flowing through the power switch.

[0079] Figure 18This is a flowchart 1800 of an overcurrent detection method used during the startup conditions of a power switch according to an embodiment of the present invention. The method begins at 1802 and queries at 1804 whether the PWM signal associated with the power switch is active. If not, the method returns to 1802; if yes, the method senses the active di / dt signal at 1806. At 1808, the method queries whether the active di / dt signal is high. If not, the method returns to 1802; if yes, the method senses the time associated with the active di / dt signal at 1810. At 1812, the method queries whether the active di / dt signal has been active for longer than a time limit. If not, the method steps, which will be explained in more detail below, are taken. If yes, the method determines at step 1814 that an overcurrent event has occurred. At step 1816, the PWM signal for the power switch circuit is set low. At step 1818, the overcurrent event is reported to the system monitoring the power switch. At step 1820, the method waits for a reset command associated with the overcurrent event. Once received, the method resets at 1822 and continues via 1824 to 1826. T is reset there. di / dt The method senses the signal, then returns to 1802 and prepares for the next turn-on and sensing. Returning to 1812, if the di / dt activation time limit has not yet been reached, the method queries at 1828 whether the PWM signal is high. If not, the time sensing of the activation di / dt signal is reset at 1826, and the method returns to 1802. If yes, the method queries whether the activation di / dt signal has gone low. If no, the method returns to step 1810. If yes, the method waits for a given time and / or waits for the activation dv / dt signal to go low. Once the wait time has ended and / or the activation dv / dt signal has gone low, secondary short-circuit protection can be activated at step 1834 to detect a short-circuit event (SC2) that occurred during the switch's on state. At 1836, the method queries whether a short-circuit condition has been detected. If yes, the method returns to step 1816. If no, the method queries at 1838 whether the PWM signal is high. If yes, the method returns to 1836; otherwise, it continues to 1824. The method then continues to 1826 and resets T. di / dt The sensor is activated, then returns to 1802 and prepares for the next activation and sensing.

[0080] To add more layers of security, an additional comparator can be added to create a window detection of di / dt. This additional comparator 1906 can be used... Figure 19 I saw it in the middle. Figure 19 Roughly corresponding to Figure 15The circuit described earlier. Amplifier 1902 corresponds to amplifier 1502, and comparator 1904 corresponds to comparator 1504. Figure 19 The diagram also shows an inverter 1910 coupled to comparator 1906 and an AND gate 1908 for generating an activation di / dt signal. The output of comparator 1906 generates the additional signal described below. Note the first and second reference voltages associated with comparators 1904 and 1906.

[0081] By adding window detection, if the previously described signal V Es,clip Within a defined voltage window, the activation di / dt signal will only go high.

[0082] Equation 3V ref,di / dt1 <-V Ee,clip target <V ref,di / dt2 .

[0083] Furthermore, a signal “di / dt too high” can be created associated with the output of comparator 1906, indicating whether di / dt exceeds the regulation and is also higher than expected. The duration this signal is high can also be measured; if this duration exceeds a predetermined value, the driver can decide to shut off the drive switch and report fault behavior.

[0084] To detect the activation dv / dt adjustment time, additional circuitry can be added to the existing power switching circuit, such as... Figure 20 The circuit 2000 is shown in the diagram. Circuit 2000 includes a capacitor 2004 coupled between the collector of the driven switch 2002 and a resistor 2006, which is coupled to a voltage related to the emitter potential of the driven switch 2002. Since dv / dt is adjusted, the voltage across resistor 2006 will be the DC voltage value during adjustment. During turn-off, a displacement current flows from the collector through capacitor 2004 and resistor 2006, generating a positive voltage across resistor 2006. If this voltage is sufficiently higher than the reference voltage V... ref,dv / dt The comparator 2008 then generates an activation dv / dt signal. This signal indicates that dv / dt is in regulation. The time measurement circuit can be of the same type as that used for di / dt. A similar window circuit can be used to activate the dv / dt signal, as previously described regarding the activation of the di / dt signal.

[0085] Figure 21This is a timing diagram of the relevant waveforms of the overvoltage detection method according to an embodiment of the present invention, associated with the turn-off of the power switch. The first timing diagram portion 2102 shows the drain or collector regulated current waveforms 2112A (high voltage) and 2112B (low and medium voltages). Timing diagram portion 2102 also shows the drain-source or collector-emitter regulated voltage waveforms 2114A (high voltage), 2114B (medium voltage), and 2114C (low voltage). dv / dt Time interval 2128 indicates the time the switch is in current regulation until the peak voltage value. Second timing diagram section 2104 shows the gate-source or gate-emitter voltage waveforms 2116A (high voltage), 2116B (medium voltage), and 2116C (low voltage) and the corresponding control signal 2118 associated with the turn-off event. Third timing diagram section 2106 shows the resistor voltage waveforms 2120A (high voltage), 2120B (medium voltage), and 2120C (low voltage). Fourth timing diagram section 2108 shows the activation dv / dt waveforms 2122A (high voltage), 2122B (medium voltage), and 2122C (low voltage). Fifth timing diagram section 2110 shows the time integrator waveforms 2124A (high voltage), 2124B (medium voltage), and 2124C (low voltage). Timing diagram section 2110 also shows an overvoltage signal 2126 associated with a time interval 2128 exceeding the limit time interval due to a high voltage across the power switch.

[0086] Figure 22This is a flowchart 2200 of an overvoltage detection method used during the power switch off condition according to an embodiment of the present invention. The method begins at 2202 and queries at 2204 whether the PWM signal associated with the power switch is active. If not, the method returns to 2202; if yes, the method senses the active dv / dt signal at 2210. At 2212, the method queries whether the active dv / dt signal is high. If not, the method returns to 2202 via 2206 and 2208, which are described in further detail below; if yes, the method senses the time associated with the active dv / dt signal at 2214. At 2216, the method queries whether the time the dv / dt signal is active is greater than a time limit. If not, the method returns to 2202 via 2206 and 2208. If yes, the method changes the target adjustment value of di / dt at 2218 and increments the number of overvoltage events in the counter at 2220. At 2222, the method queries whether the number of overvoltage events exceeds a predetermined overvoltage event limit. If not, the method returns to 2202 via 2206 and 2208. If yes, an overvoltage fault is reported at 2224. At 2226, the method waits for a command to reset the overvoltage fault. Once the command is received, the method continues at 2228, where the overvoltage fault is reset, and the counter associated with the overvoltage fault is also reset. The method then returns to 2202 via 2206 and 2208.

[0087] At 2206, the method queries whether the PWM signal associated with the power switch is high. If yes, the method continues to 2208; otherwise, it returns to 2210 as previously described. Step 2208 resets T. dv / dt At the specified time interval, the overvoltage event counter is reset, and the di / dt target value is set to the nominal value. The method then returns to 2202.

[0088] Simultaneously with the above overvoltage method steps, a monitoring step sequence is also executed. In one embodiment, the monitoring step sequence is used to ensure, for example, that a normal recurring overvoltage indication during a PWM switching cycle that will not directly damage the power switch does not trigger an immediate overvoltage indication. The monitoring method begins at 2230 and queries at 2236 whether an overvoltage event has occurred. If yes, the no-overvoltage counter is reset at 2234, and the method waits for the overvoltage event to reset at 2232. If no, the method queries at 2238 whether the PWM signal has changed from low to high. If no, the method returns to 2230. If yes, the no-overvoltage event counter is incremented at 2240. At 2242, the method queries whether the no-overvoltage event counter is greater than a predetermined limit. If no, the method returns to 2230. If yes, the method queries whether the overvoltage event counter is greater than zero. If no, the method returns to 2230. If yes, the method decrements the overvoltage event counter by 1 and returns to 2230.

[0089] exist Figure 23 An alternative current sensing circuit 2300 for generating an activation di / dt signal is shown. Circuit 2300 includes a reference current i ref 2302 includes a transistor 2304 with its gate coupled to ground, a resistor 2306, and an I_SENSE node. The I_SENSE node receives the voltage across the inductor in the power switch load path, a measure of the change in current through the power switch. The voltage across the gate-source of transistor 2304 and across resistor 2306 generates a current proportional to the change in current through the power switch. The result of comparing this generated current with a reference current 2302 modifies the input voltage of comparator 2308 and generates an activation di / dt signal at its output. Circuit 2300 can be replicated if needed to provide the previously described window detection functionality.

[0090] like Figure 24 As shown in circuit 2400, di / dt and dv / dt regulation and short-circuit protection according to embodiments of the present invention can be summarized in the digital domain. A high-voltage / high-power network 2402 is shown, which includes gate drivers 2404 and 2408 for driving power switches 2406 and 2410. Power switches 2404 and 2408 are equipped with specific v... ce and i c Value switching. The sensing network 2412 is used to sense v. ce The dv / dt information of the signal is used by the sensing network 2414 to sense i. cThe signal's di / dt information. A / D converter 2416 digitizes the voltage output from sensing network 2412, and A / D converter 2418 digitizes the voltage output from sensing network 2418. The digital information is received by memory 2420 and evaluated by 2422. Detecting a target dv / dt or di / dt level serves as an indication that dv / dt or di / dt is in adjustment. The duration of dv / dt or di / dt in adjustment is measured, and an overcurrent or overvoltage signal can be triggered according to the principles of the above embodiments. Optional parameter determination can be performed at 2424 to further enhance the short-circuit or overload protection of the embodiments of the present invention. Information regarding power switch overcurrent and overvoltage events can be applied to the power switch using feedback network 2426. As described above, the power switch is turned off in the event of an overcurrent event, and the di / dt value is changed in the event of an overvoltage event.

[0091] As can be seen from the above description, the embodiments of the present invention disclose, but are not limited to, the following solutions:

[0092] Option 1. A circuit for protecting a power switch, comprising:

[0093] First, second, and third power switching nodes;

[0094] A feedback circuit, coupled to at least one of the first, second, and third power switching nodes, is used to regulate changes in the current through the power switch; and

[0095] The detector circuit coupled to the feedback circuit has an output for indicating that the change in current through the power switch is in regulation.

[0096] Option 2. The circuit according to Option 1, wherein the detector circuit includes an additional output for identifying the adjustment level of the current through the power switch.

[0097] Option 3. Based on the circuit of Option 1, a timing circuit coupled to the detector circuit is also included.

[0098] Option 4. The circuit according to Option 3, wherein the timing circuit includes an output for generating an overcurrent signal.

[0099] Option 5. According to the circuit of Option 1, it further includes an additional feedback circuit coupled to at least two of the first, second and third power switch nodes for regulating the voltage change across the power switch.

[0100] Option 6. The circuit according to Option 5 further includes an additional detector circuit coupled to an additional feedback circuit, the additional detector circuit having an output for indicating that the voltage change across the power switch is in regulation.

[0101] Option 7. The circuit according to Option 6, wherein the additional detector circuit includes an additional output for identifying the adjustment level of the voltage across the power switch.

[0102] Option 8. The circuit according to Option 6 further includes an additional timing circuit coupled to the additional detector circuit.

[0103] Option 9. The circuit according to Option 8, wherein the additional timing circuit includes an output for generating an overvoltage signal.

[0104] Option 10. The circuit according to Option 1 further includes power switches coupled to the first, second and third power switch nodes.

[0105] Option 11. A method for protecting a power switch, comprising:

[0106] The current change sensed through the power switch is in the regulation phase;

[0107] The time during which the change in current through the power switch is in regulation is measured; and

[0108] The time during which the change in current through the power switch is in regulation is compared with a reference time.

[0109] Scheme 12. According to the method of Scheme 11, it further includes: if the change in current through the power switch is in regulation for a period of time exceeding a reference time, an overcurrent signal is generated.

[0110] Option 13. The method according to Option 12 further includes: turning off the power switch in response to an overcurrent signal.

[0111] Option 14. According to the method of Option 11, wherein the sensing of the change in current through the power switch is in the process of regulation and occurs simultaneously with the conduction event.

[0112] Option 15. According to the method of Option 11, it further includes: sensing that the voltage change across the power switch is being regulated.

[0113] Option 16. A method for protecting a power switch, comprising:

[0114] The voltage change across the power switch is being regulated;

[0115] The time during which the voltage change across the power switch is in the adjustment phase; and

[0116] The time during which the voltage change across the power switch is in adjustment is compared with a reference time.

[0117] Scheme 17. According to the method of Scheme 16, it further includes: if the voltage change across the power switch is in regulation for a period of time exceeding a reference time, an overvoltage signal is generated.

[0118] Option 18. The method according to Option 17 further includes: changing a target value of the change in current through the power switch in response to an overvoltage signal.

[0119] Option 19. The method according to Option 17 further includes: counting multiple overvoltage signals within multiple switching cycles.

[0120] Option 20. According to the method of Option 16, the change in voltage across the power switch is regulated and occurs simultaneously with the turn-off event.

[0121] Although the invention has been described with reference to the illustrated embodiments, this description is not intended to be construed as limiting. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art upon reference to this description. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A circuit for protecting a power switch, comprising: First, second, and third power switching nodes; A feedback circuit, coupled to at least one of the first, second, and third power switch nodes, is used to regulate changes in the current through the power switch. A detector circuit coupled to the feedback circuit has an output for indicating that the change in current through the power switch is in regulation; as well as A timing circuit coupled to the detector circuit. The timing circuit is configured to measure the duration of the adjustment period of the change in current through the power switch. The timing circuit is configured to compare the duration of the adjustment of the current change through the power switch with a reference. The timing circuit includes an output terminal for generating an overcurrent signal if the duration of the current change through the power switch being regulated exceeds the reference. The duration during which the change in current through the power switch is in regulation includes the length of time during which the power switch is in current regulation until the peak current value is reached.

2. The circuit of claim 1, wherein, The detector circuit includes an additional output for identifying an adjustment level for detecting changes in the current passing through the power switch.

3. The circuit of claim 1, wherein, The timing circuit is separated from the detector circuit.

4. The circuit of claim 1, wherein, The circuit is integrated with the power switch.

5. The circuit according to claim 1 further includes an additional feedback circuit coupled to at least two of the first, second, and third power switch nodes for adjusting the voltage change across the power switch.

6. The circuit of claim 5 further includes an additional detector circuit coupled to the additional feedback circuit, the additional detector circuit having an output for indicating that a change in voltage across the power switch is in regulation.

7. The circuit of claim 6, wherein, The additional detector circuit includes an additional output terminal for identifying the adjustment level of voltage changes across the power switch.

8. The circuit of claim 6 further includes an additional timing circuit coupled to the additional detector circuit.

9. The circuit of claim 8, wherein, The additional timing circuit includes an output for generating an overvoltage signal.

10. The circuit of claim 1 further includes a power switch coupled to the first, second, and third power switch nodes.

11. The circuit of claim 1, wherein, The timing circuit includes a microcontroller configured to digitally count the duration of the signal at the output of the detector circuit to indicate that the change in current through the power switch is in regulation.

12. The circuit of claim 1, wherein, The timing circuit includes a time-to-digital converter.

13. The circuit of claim 1, wherein, The timing circuit includes a second comparator, a resistor coupled between a first input terminal of the timing circuit and an input terminal of the second comparator, and a capacitor coupled between an input terminal of the second comparator and ground.

14. The circuit of claim 1, wherein, The timing circuit includes a current source, a capacitor, and a second comparator, wherein the current source is controlled by the output of the detector circuit, wherein the current source is configured to charge the capacitor, and wherein the capacitor is coupled to the input of the second comparator.

15. The circuit of claim 1, wherein, The detector circuit includes an operational amplifier for generating a signal corresponding to a change in current through the power switch, and wherein the detector circuit includes a first comparator separated from the operational amplifier, the first comparator having a first input coupled to the output of the operational amplifier, a second input coupled to a reference value configured to change current over time, and an output coupled to the output of the detector circuit.

16. A circuit for protecting a power switch, comprising: First, second, and third power switching nodes; A feedback circuit, coupled to at least one of the first, second, and third power switch nodes, is used to regulate changes in the current through the power switch. A detector circuit coupled to the feedback circuit has an output for indicating that the change in current through the power switch is in regulation; as well as The timing circuit is coupled to the detector circuit and the reference. The timing circuit is configured to measure the duration of the adjustment period of the change in current through the power switch. The timing circuit includes an output terminal for generating an overcurrent signal if the duration of the current change through the power switch being regulated exceeds the reference. The duration during which the change in current through the power switch is in regulation includes the length of time during which the power switch is in current regulation until the peak current value is reached.

17. A method for protecting a power switch, comprising: The current change sensed through the power switch is in the process of adjustment; The duration of the change in current through the power switch under regulation is measured; The duration of the current change through the power switch being in regulation is compared with a reference. as well as If the duration of the current change through the power switch being in regulation exceeds the reference, an overcurrent signal is generated. The duration during which the change in current through the power switch is in regulation includes the length of time during which the power switch is in current regulation until the peak current value is reached.

18. The method according to claim 17, wherein, Sensing a change in current through the power switch in a regulating manner includes: generating a first signal representing a change in current through the power switch, and generating a second signal representing a reference indicating that the first signal is greater than the change in current value.

19. The method of claim 18, further comprising turning off the power switch in response to the overcurrent signal.

20. The method according to claim 19, wherein, The change in current sensed through the power switch is in a state of regulation that occurs simultaneously with the conduction event.

21. The method of claim 20, further comprising sensing that the voltage across the power switch is being regulated.

22. A method for protecting a power switch, comprising: The voltage change across the power switch is being sensed and is being regulated; The duration of the voltage change across the power switch during the adjustment period is measured. The duration of the voltage change across the power switch during adjustment is compared with a reference. as well as If the voltage change across the power switch remains in regulation for a duration exceeding the reference, an overvoltage signal is generated. The duration of voltage regulation across the power switch includes the time from when the power switch is in voltage regulation until the peak voltage value is reached.

23. The method of claim 22, further comprising changing a target value of the voltage change across the power switch in response to the overvoltage signal.

24. The method of claim 23 further includes counting multiple overvoltage signals during multiple switching cycles.

25. The method according to claim 24, wherein, The change in voltage across the power switch is sensed, and the adjustment occurs simultaneously with the shutdown event.

26. A method for protecting a power switch, comprising: Check whether the pulse width modulation signal to the power switch is active, and if no active pulse width modulation signal is detected: During the operation mode of the power switch, the voltage change across the power switch is adjusted such that the voltage change across the power switch is limited to a predetermined non-zero rate of change during the operation mode of the power switch. The voltage change across the power switch is being sensed and is being regulated; The duration of voltage variation across the power switch being regulated is measured only during the operating mode of the power switch. as well as The duration of the voltage change across the power switch during adjustment is compared with a reference time.

27. The method of claim 26, further comprising generating an overvoltage signal if the duration of the voltage change across the power switch being regulated exceeds the reference time.

28. The method of claim 27, further comprising changing a target value of the voltage change across the power switch in response to the overvoltage signal.

29. The method of claim 27 further includes counting multiple overvoltage signals during multiple switching cycles.

30. The method according to claim 26, wherein, The change in voltage across the power switch is sensed, and the adjustment occurs simultaneously with the shutdown event.

31. The method according to claim 26, wherein, The voltage change across the power switch includes a reference change that is greater than the voltage change across the power switch.

32. A method for protecting a power switch during its off-state, the method comprising: Check whether the pulse width modulation signal to the power switch is active, and if no active pulse width modulation signal is detected: During the operation mode of the power switch, the voltage change across the power switch is adjusted such that the voltage change across the power switch is limited to a predetermined non-zero rate of change during the operation mode of the power switch. The change in voltage across the power switch is greater than a reference change in voltage value; The voltage change across the power switch is measured to be greater than a reference voltage change only during the operating mode of the power switch for a specified duration. as well as The duration during which the voltage change across the power switch exceeds the voltage change value is compared with a reference time.

33. The method of claim 32, further comprising determining that the duration for which a change in voltage across the power switch is greater than a reference change in voltage value exceeds the reference time.

34. The method of claim 33, further comprising changing a target adjustment value for the change in voltage across the power switch.

35. The method according to claim 34, wherein, The target adjustment value for the change in voltage across the power switch includes a reference change in voltage across the power switch that is greater than the change in voltage value.

36. The method of claim 33 further includes an incrementing overvoltage event counter.

37. The method of claim 36, further comprising determining that the number of overvoltage events in the overvoltage event counter is greater than an overvoltage event limit.

38. The method of claim 37, further comprising reporting overvoltage fault conditions.

39. The method of claim 38, further comprising resetting the overvoltage fault condition.

40. A method for protecting a power switch, comprising: Check whether the pulse width modulation signal to the power switch is active, and if no active pulse width modulation signal is detected: During the operation mode of the power switch, the voltage change across the power switch is adjusted such that the voltage change across the power switch is limited to a predetermined non-zero rate of change during the operation mode of the power switch. The voltage change across the power switch is being sensed and is being regulated; The duration of voltage variation across the power switch being regulated is measured only during the operating mode of the power switch. The duration of the voltage change across the power switch during adjustment is compared with a reference time; If the duration of the voltage change across the power switch being regulated exceeds the reference time, multiple overvoltage signals are generated. as well as The multiple overvoltage signals are monitored using a counter.

41. The method according to claim 40, wherein, Monitoring the plurality of overvoltage signals using the counter includes selectively incrementing or decrementing the counter in response to the plurality of overvoltage signals and the plurality of pulse width modulation transitions of the power switch.

42. The method of claim 41, further comprising determining that the value of the counter exceeds a counter limit value.

43. The method of claim 42 further includes reporting overvoltage fault conditions.

44. The method of claim 43 further includes resetting the overvoltage fault condition.

45. The method according to claim 40, wherein, The voltage change across the power switch includes a reference change that is greater than the voltage change across the power switch.

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