Frequency modulation control device and power grid frequency modulation control system

Abstract

The present disclosure relates to a frequency modulation control device and a power grid frequency modulation control system, the frequency modulation control device comprising: a low-frequency monitoring circuit, a high-frequency monitoring circuit and a control chip; the low-frequency monitoring circuit is used for outputting a first state of a switching quantity signal to a drop prohibition end of the control chip when the time of the turbine speed being lower than the lower limit of the primary frequency modulation dead zone is within a target time interval, so that the control output end of the control chip outputs a drop prohibition instruction to the turbine main control hand manipulator, to lock the unit load drop regulation function of the secondary frequency modulation; the high-frequency monitoring circuit is used for outputting a first state of a switching quantity signal to a rise prohibition end of the control chip when the time of the turbine speed being higher than the upper limit of the primary frequency modulation dead zone is within a target time interval, so that the control output end of the control chip outputs a rise prohibition instruction to the turbine main control hand manipulator, to lock the unit load rise regulation function of the secondary frequency modulation. The present disclosure can realize the inhibition of the reverse regulation effect of the secondary frequency modulation on the primary frequency modulation.

Description

Technical Field

[0001] This disclosure relates to the field of power system technology, and more specifically, to a frequency regulation control device and a power grid frequency regulation control system. Background Technology

[0002] Power system frequency is one of the basic indicators for measuring power quality. In actual power grid operation, when power consumption and power supply are mismatched, small components with small changes and short fluctuation periods can occur in the power grid frequency. This frequency disturbance is mainly compensated by the automatic adjustment of the turbine valves by the turbine generator set's own regulation system to complete the power grid load compensation and correct the power grid frequency fluctuations. This process is called the primary frequency regulation of the generator set.

[0003] Primary frequency regulation is differential regulation and cannot maintain a constant grid frequency; it can only mitigate the degree of frequency change. Therefore, it is necessary to increase or decrease the load of certain generating units to restore the grid frequency. This process is called secondary frequency regulation. Only after secondary frequency regulation can the grid frequency be accurately maintained at a constant value.

[0004] According to the scheduling rules, primary frequency regulation should take precedence over secondary frequency regulation. However, in actual primary frequency regulation control, primary and secondary frequency regulation often operate simultaneously. Secondary frequency regulation can then reverse the primary frequency regulation, causing the integral charge of the primary frequency regulation to be substandard, resulting in over- or under-regulation, thus affecting the control effect of primary frequency regulation. Existing control methods typically use frequency limits to lock out secondary frequency regulation. However, this approach has several drawbacks: if the setpoint is too small, it will affect the regulation performance of secondary frequency regulation; if the setpoint is too large, it will prevent locking out. Summary of the Invention

[0005] The purpose of this disclosure is to provide a frequency modulation control device and a power grid frequency modulation control system to solve the above-mentioned technical problems.

[0006] To achieve the above objectives, in a first aspect, this disclosure provides a frequency modulation control device, comprising:

[0007] The system includes a low-frequency monitoring circuit, a high-frequency monitoring circuit, and a control chip. The low-frequency monitoring circuit is connected to the down-inhibition terminal of the control chip, the high-frequency monitoring circuit is connected to the up-inhibition terminal of the control chip, and the control output terminal of the control chip is connected to the turbine main control handheld device.

[0008] The low-frequency monitoring circuit is used to time the time when the turbine speed is lower than the lower limit of the primary frequency regulation dead zone. When the time is within the target time interval, it outputs a first-state switch signal to the de-inhibit terminal of the control chip.

[0009] The high-frequency monitoring circuit is used to time the time when the turbine speed is higher than the upper limit of the primary frequency regulation dead zone. When the time is within the target time interval, it outputs a first-state switch signal to the up-disable terminal of the control chip.

[0010] The control chip is used to output a deceleration command to the turbine main control handheld device through the control output terminal when the input of the deceleration prohibition terminal is a switch signal in the first state, and to send an elevation prohibition command to the turbine main control handheld device through the control output terminal when the input of the elevation prohibition terminal is a switch signal in the first state.

[0011] The reduction prohibition command is used to instruct the turbine main control manual controller to lock the unit load reduction regulation function of the secondary frequency regulation, and the increase prohibition command is used to instruct the turbine main control manual controller to lock the unit load increase regulation function of the secondary frequency regulation.

[0012] Optionally, the low-frequency monitoring circuit includes a first low-value monitor, a first timing unit, a second timing unit, and a first AND gate. The output terminal of the first low-value monitor is connected to the input terminal of the first timing unit and the input terminal of the second timing unit, respectively. The first AND gate includes a first input terminal, a second input terminal, and an output terminal. The output terminal of the first timing unit is connected to the first input terminal of the first AND gate, the output terminal of the second timing unit is connected to the second input terminal of the first AND gate, and the output terminal of the first AND gate is connected to the de-inhibit terminal of the control chip.

[0013] The first low-value monitor is used to output a first-state switch signal to the input terminal of the first timing unit and the input terminal of the second timing unit when the turbine speed is lower than the lower limit of the primary frequency regulation dead zone;

[0014] The first timing unit is used to start timing after detecting the input of the switch signal of the first state, and after the timing time reaches the first preset time, output the switch signal of the first state to the first input terminal of the first AND gate;

[0015] The second timing unit is used to start timing after detecting the input of the switch signal of the first state, and to output the switch signal of the first state to the second input terminal of the first AND gate before the timing time reaches the second preset time; wherein, the first preset time is the lower limit of the target time interval, and the second preset time is the upper limit of the target time interval;

[0016] The first AND gate is used to output a first-state switching signal to the de-inhibit terminal of the control chip when all input signals are in the first state.

[0017] Optionally, the second timing unit includes a first timer, a first high-value monitor, and a first NOT gate. The output terminal of the first low-value monitor is connected to the input terminal and the enable terminal of the first timer. The output terminal of the first timer is connected to the input terminal of the first high-value monitor. The output terminal of the first high-value monitor is connected to the input terminal of the first NOT gate. The output terminal of the first NOT gate is connected to the second input terminal of the first AND gate.

[0018] The first timer is used to start timing after detecting a switch signal that is in the first state at its own input terminal and its own enable terminal, and outputs the timing time to the input terminal of the first high-value monitor.

[0019] The first high-value monitor is used to output a second state switching signal to the first NOT gate when the timing time has not reached the second preset time;

[0020] The first NOT gate is used to invert the input switch signal and output the inverted switch signal to the second input terminal of the first AND gate.

[0021] Optionally, the low-frequency monitoring circuit further includes a second high-value monitor and a second NOT gate, the output terminal of the second high-value monitor is connected to the input terminal of the second NOT gate, the first AND gate further includes a third input terminal, and the output terminal of the second NOT gate is connected to the third input terminal of the first AND gate;

[0022] The second high-value monitor is used to output a second-state switching signal to the second NOT gate when the active power of the unit does not reach the target upper limit power.

[0023] The second NOT gate is used to invert the input switch signal and output the inverted switch signal to the third input terminal of the first AND gate.

[0024] Optionally, the first AND gate further includes a fourth input terminal, which is used to receive a status signal of a first state or a status signal of a second state. The status signal of the first state indicates that the unit is in a coordinated automatic control state, and the status signal of the second state indicates that the unit is not in a coordinated automatic control state.

[0025] Optionally, the high-frequency monitoring circuit includes a third high-value monitor, a third timing unit, a fourth timing unit, and a second AND gate. The output terminal of the third high-value monitor is connected to the input terminal of the third timing unit and the input terminal of the fourth timing unit, respectively. The second AND gate includes a first input terminal, a second input terminal, and an output terminal. The output terminal of the third timing unit is connected to the first input terminal of the second AND gate, the output terminal of the fourth timing unit is connected to the second input terminal of the second AND gate, and the output terminal of the second AND gate is connected to the up-inhibit terminal of the control chip.

[0026] The third high-value monitor is used to output a first-state switch signal to the input terminal of the third timing unit and the input terminal of the fourth timing unit when the turbine speed is higher than the upper limit of the primary frequency regulation dead zone;

[0027] The third timing unit is used to start timing after detecting the input of the switch signal of the first state, and after the timing time reaches the first preset time, it outputs the switch signal of the first state to the first input terminal of the second AND gate.

[0028] The fourth timing unit is used to start timing after detecting the input of the switch signal of the first state, and outputs the switch signal of the first state to the second input terminal of the second AND gate before the timing time reaches the second preset time; wherein, the first preset time is the lower limit of the target time interval, and the second preset time is the upper limit of the target time interval;

[0029] The second AND gate is used to output a first-state switching signal to the up-inhibit terminal of the control chip when all input signals are in the first state.

[0030] Optionally, the fourth timing unit includes a second timer, a fourth high-value monitor, and a third NOT gate. The output terminal of the third high-value monitor is connected to the input terminal and the enable terminal of the second timer. The output terminal of the second timer is connected to the input terminal of the fourth high-value monitor. The output terminal of the fourth high-value monitor is connected to the input terminal of the third NOT gate. The output terminal of the third NOT gate is connected to the second input terminal of the second AND gate.

[0031] The second timer is used to start timing after detecting a switch signal that is in the first state at its own input terminal and its own enable terminal, and outputs the timing time to the input terminal of the fourth high-value monitor.

[0032] The fourth high-value monitor is used to output a second state switching signal to the third NOT gate when the timing time has not reached the second preset time.

[0033] The third NOT gate is used to invert the input switch signal and output the inverted switch signal to the second input terminal of the second AND gate.

[0034] Optionally, the high-frequency monitoring circuit further includes a second low-value monitor and a fourth NOT gate, the output terminal of the second low-value monitor is connected to the input terminal of the fourth NOT gate, the second AND gate further includes a third input terminal, and the output terminal of the fourth NOT gate is connected to the third input terminal of the second AND gate;

[0035] The second low-value monitor is used to output a second-state switching signal to the fourth NOT gate when the active power of the turbine unit exceeds the target lower limit power.

[0036] The fourth NOT gate is used to invert the input switch signal and output the inverted switch signal to the third input terminal of the second AND gate.

[0037] Optionally, the second AND gate further includes a fourth input terminal, which is used to receive a status signal of a first state or a status signal of a second state, wherein the status signal of the first state indicates that the unit is in a coordinated automatic control state, and the status signal of the second state indicates that the unit is not in a coordinated automatic control state.

[0038] Secondly, this disclosure provides a power grid frequency regulation control system, comprising:

[0039] The frequency modulation control device described in the first aspect, and the turbine main control manual controller.

[0040] In the above technical solution, based on the primary frequency regulation dead zone, low-frequency monitoring circuits and high-frequency monitoring circuits are constructed to monitor the time it takes for the turbine speed to exceed the primary frequency regulation dead zone. Then, according to this time and the target time interval, corresponding switching signals are output to the control chip. Under the action of the input switching signals, the control chip outputs corresponding reduction prohibition commands or increase prohibition commands to the turbine main control handheld device, thereby locking the turbine main control handheld device's load increase and decrease regulation function for secondary frequency regulation. This solution locks the secondary frequency regulation action based on the relationship between the time it takes for the turbine speed to exceed the primary frequency regulation dead zone and the target time interval, which is more accurate and effective than existing methods.

[0041] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0042] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings:

[0043] Figure 1 A detailed schematic diagram of a power grid frequency regulation control system provided in an exemplary embodiment is shown.

[0044] Figure 2 A schematic diagram of a frequency modulation control device provided in an exemplary embodiment is shown;

[0045] Figure 3 A schematic diagram illustrating a specific implementation of a low-frequency monitoring circuit in an exemplary embodiment is shown;

[0046] Figure 4Another schematic diagram of a frequency modulation control device in an exemplary embodiment is shown;

[0047] Figure 5 A schematic diagram of a specific implementation of a high-frequency monitoring circuit in an exemplary embodiment is shown;

[0048] Figure 6 Another schematic diagram of a frequency modulation control device in an exemplary embodiment is shown.

[0049] Figure label:

[0050] 100 - Power grid frequency regulation control system; 110 - Frequency regulation control device; 120 - Steam turbine main control handheld device; 210 - Low frequency monitoring circuit; 220 - High frequency monitoring circuit; 230 - Control chip; 240 - Second high value monitor; 250 - Second NOT gate; 260 - Second low value monitor; 270 - Fourth NOT gate; 310 - First low value monitor; 320 - First timing unit; 330 - Second timing unit; 331 - First timer; 332 - First high value monitor; 333 - First NOT gate; 340 - First AND gate; 410 - Third high value monitor; 420 - Third timing unit; 430 - Fourth timing unit; 431 - Second timer; 432 - Fourth high value monitor; 433 - Third NOT gate; 440 - Second AND gate. Detailed Implementation

[0051] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0052] It should be noted that all actions involving the acquisition of signals, information, or data in this disclosure are carried out in compliance with the relevant data protection laws and policies of the country where the location is situated, and with authorization from the owner of the relevant device.

[0053] Understandably, in actual primary frequency control, secondary frequency control will reverse the primary frequency control, causing the integral charge of the primary frequency control action to be unqualified, resulting in over-adjustment or under-adjustment, thus affecting the primary frequency control effect.

[0054] However, existing control methods typically lock out secondary frequency modulation by setting a frequency limit. This can lead to problems such as the set value being too small affecting the regulation performance of secondary frequency modulation, or the set value being too large causing the locking to fail.

[0055] To address the aforementioned issues, this disclosure provides a frequency regulation control device and a power grid frequency regulation control system. Based on the primary frequency regulation dead zone, a low-frequency monitoring circuit and a high-frequency monitoring circuit are constructed to monitor the turbine speed. According to the turbine speed, the control chip outputs corresponding switching signals to the control chip. Under the action of the input switching signals, the control chip outputs corresponding instructions to the turbine main control handheld device, thereby enabling the turbine main control handheld device to lock the secondary frequency regulation unit load increase or load decrease adjustment function.

[0056] The frequency regulation control device disclosed herein is effective in suppressing the reverse regulation effect of secondary frequency regulation on primary frequency regulation and can effectively improve the integral power of primary frequency regulation. It is a safe, reliable and effective auxiliary control method, which has practical guiding significance for the stable production and operation of power systems and the optimization of the primary frequency regulation process.

[0057] Figure 1 A detailed schematic diagram of a power grid frequency regulation control system provided in an exemplary embodiment is shown below. Please refer to... Figure 1 The power grid frequency regulation control system 100 includes a frequency regulation control device 110 and a turbine main control handheld device 120. The frequency regulation control device 110 is connected to the turbine main control handheld device 120.

[0058] Figure 2 A schematic diagram of a frequency modulation control device provided in an exemplary embodiment is shown. Please refer to... Figure 2 The frequency modulation control device 110 includes a low-frequency monitoring circuit 210, a high-frequency monitoring circuit 220, and a control chip 230. The low-frequency monitoring circuit 210 is connected to the down-inhibition terminal LWI of the control chip 230, the high-frequency monitoring circuit 220 is connected to the up-inhibition terminal RAI of the control chip 230, and the control output terminal of the control chip 230 is connected to the turbine main control handheld device 120.

[0059] Figure 2 In this process, the operation flow of the frequency modulation control device 110 includes:

[0060] First, it is necessary to set the lower limit and upper limit of the primary frequency regulation dead zone. For example, set the lower limit of the primary frequency regulation dead zone to 2998 rpm and the upper limit to 3002 rpm. When the turbine speed is within the primary frequency regulation dead zone [2998, 3002] rpm, it indicates that the turbine is operating normally.

[0061] The input of the low-frequency monitoring circuit 210 is used to connect to the DEH (Digital Electro-Hydraulic, turbine digital electro-hydraulic control system) to obtain turbine speed information. When the turbine speed is lower than the lower limit of the primary frequency regulation dead zone, timing is started. When the timing time is within the target time interval, a first-state switch signal is output to the lower inhibit terminal LWI of the control chip 230. When the timing time is not within the target time interval, a second-state switch signal is output to the lower inhibit terminal LWI of the control chip 230.

[0062] In this disclosure, the turbine speed is a representation of the power grid frequency.

[0063] For example, the target time interval is set to 8 to 60 seconds. When the turbine speed is below 2998 rpm, the low-frequency monitoring circuit 210 starts timing. When the timing time is within 8 to 60 seconds, it outputs 1 to the LWI terminal of the control chip 230; otherwise (when the timing time is less than 8 seconds or greater than 60 seconds), it outputs 0 to the LWI terminal of the control chip 230.

[0064] When the input of the control chip 230 to the LWI terminal is a switch signal in the first state, it outputs a reduction prohibition command to the turbine main control handheld device 120 through the control output terminal. This reduction prohibition command is used to instruct the turbine main control handheld device 120 to lock the unit load reduction regulation function of the secondary frequency regulation, thereby realizing the unit load increase regulation function that only performs the secondary frequency regulation, adjusting the system frequency, and making the turbine speed return to the primary frequency regulation dead zone.

[0065] The input of the high-frequency monitoring circuit 220 is used to connect to the DEH to obtain turbine speed information. When the turbine speed is higher than the upper limit of the primary frequency dead zone, timing is started. When the timing time is within the target time interval, a first-state switch signal is output to the RAI terminal of the control chip 230. When the timing time is not within the target time interval, a second-state switch signal is output to the RAI terminal of the control chip 230.

[0066] For example, the target time interval is set to 8 to 60 seconds. When the turbine speed is higher than 3002 rpm, the high-frequency monitoring circuit 220 starts timing. When the timing time is within 8 to 60 seconds, it outputs 1 to the RAI terminal of the control chip 230; otherwise (when the timing time is less than 8 seconds or greater than 60 seconds), it outputs 0 to the RAI terminal of the control chip 230.

[0067] When the input of the RAI terminal of the control chip 230 is a switch signal in the first state, the control chip 230 sends an RAI prohibition command to the turbine main control handheld device 120 through the control output terminal. The RAI prohibition command is used to instruct the turbine main control handheld device 120 to lock the unit load increase regulation function of the secondary frequency regulation, thereby realizing the unit load decrease regulation function that only performs the secondary frequency regulation, adjusting the system frequency, and making the turbine speed return to the primary frequency regulation dead zone.

[0068] When the input of the lower prohibition terminal LWI is a second-state switch signal and the input of the upper prohibition terminal RAI is a second-state switch signal, the control chip 230 outputs a release command to the turbine main control handheld device 120 through the control output terminal. This release command is used to instruct the turbine main control handheld device 120 to release the lockout and the turbine can resume normal operation.

[0069] In the above scheme, the turbine speed is monitored by constructing a low-frequency monitoring circuit 210 and a high-frequency monitoring circuit 220. Based on the turbine speed, the turbine main control handheld device 120 is controlled to lock the load increase or decrease adjustment function of the secondary frequency regulation. For example, when the turbine speed is lower than the lower limit of the primary frequency regulation dead zone for 8 to 60 seconds, the load decrease function of the secondary frequency regulation is locked. When the turbine speed is higher than the upper limit of the primary frequency regulation dead zone for 8 to 60 seconds, the load increase function of the secondary frequency regulation is locked, thereby improving the impact of secondary frequency regulation on primary frequency regulation.

[0070] Figure 3 A schematic diagram illustrating a specific implementation of a low-frequency monitoring circuit in an exemplary embodiment is shown below. Please refer to... Figure 3 The low-frequency monitoring circuit 210 includes: a first low-value monitor 310, a first timing unit 320, a second timing unit 330, and a first AND gate 340. The first AND gate 340 includes a first input terminal, a second input terminal, and an output terminal. The output terminal of the first low-value monitor 310 is connected to both the input terminal of the first timing unit 320 and the input terminal of the second timing unit 330. The output terminal of the first timing unit 320 is connected to the first input terminal of the first AND gate 340, the output terminal of the second timing unit 330 is connected to the second input terminal of the first AND gate 340, and the output terminal of the first AND gate 340 is connected to the LWI (low-inhibit) terminal of the control chip 230.

[0071] The input of the first low-value monitor 310 is connected to the DEH to obtain turbine speed information. When the turbine speed is lower than the lower limit of the primary frequency regulation dead zone, the first low-value monitor 310 outputs a first-state switch signal to the input of the first timing unit 320 and the input of the second timing unit 330. The first timing unit 320 starts timing after detecting the input of the first-state switch signal. After the timing time reaches (or exceeds) a first preset time, it outputs the first-state switch signal to the first input of the first AND gate 340. The second timing unit 330 starts timing after detecting the input of the first-state switch signal. If the timing time does not reach (or is less than or equal to) a second preset time, it outputs the first-state switch signal to the second input of the first AND gate 340. The first preset time is the lower limit of the target time interval, and the second preset time is the upper limit of the target time interval. For example, the first preset time is 8 seconds, and the second preset time is 60 seconds.

[0072] Furthermore, when the turbine speed is higher than the lower limit of the primary frequency regulation dead zone, the first low value monitor 310 outputs a second state switch signal to the input terminal of the first timing unit 320 and the input terminal of the second timing unit 330. At this time, the first timing unit 320 and the second timing unit 330 do not start timing, so the outputs of the first timing unit 320 and the second timing unit 330 are both second state switch signals.

[0073] The first AND gate 340 is used to output a first-state switching signal to the disable terminal LWI of the control chip 230 when all input signals are in the first state. When the first AND gate 340 receives any second-state switching signal at its input, it outputs a second-state switching signal to the disable terminal LWI of the control chip 230.

[0074] As can be seen from the above process, if we want the signals of the first input terminal and the second input terminal of the first AND gate 340 to be in the first state, it is necessary to satisfy that the timing time when the turbine speed is lower than the lower limit of the primary frequency regulation dead zone reaches (greater than) the first preset time, but does not reach (less than or equal to) the second preset time.

[0075] In the above scheme, a first low-value monitor 310 is constructed to monitor whether the turbine speed is lower than the lower limit of the primary frequency regulation dead zone, and a first timing unit 320 and a second timing unit 330 are constructed to set the target time interval for realizing the unit load reduction regulation function of locking the secondary frequency regulation.

[0076] Optionally, such as Figure 3As shown, the second timing unit 330 includes: a first timer 331, a first high-value monitor 332, and a first NOT gate 333. The output of the first low-value monitor 310 is connected to the input and enable terminals of the first timer 331; the output of the first timer 331 is connected to the input of the first high-value monitor 332; the output of the first high-value monitor 332 is connected to the input of the first NOT gate 333; and the output of the first NOT gate 333 is connected to the second input of the first AND gate 340.

[0077] For example, the timing cutoff time of the first timer 331 is set. In this disclosure, the timing cutoff time of the first timer 331 can be any value greater than 60 seconds, such as 100 seconds. The purpose of this setting is that after exceeding the upper limit of the frequency regulation dead zone of 60 seconds, the lockout needs to be released according to the rules to allow the turbine to operate normally. Therefore, the first timer 331 should count for at least 60 seconds.

[0078] The input and enable terminals of the first timer 331 are connected to the output terminal of the first low-value monitor 310 to obtain the switching signal output by the first low-value monitor 310. The first timer 331 starts timing after detecting a first-state switching signal at its own input and enable terminals and outputs the timing time to the first high-value monitor 332. The first high-value monitor 332 monitors whether the timing time reaches a second preset time. If the timing time reaches (or exceeds) the second preset time, the first high-value monitor 332 outputs a first-state switching signal to the first NOT gate 333. If the timing time does not reach (or is less than or equal to) the second preset time, the first high-value monitor 332 outputs a second-state switching signal to the first NOT gate 333. The first NOT gate 333 is used to invert the input switching signal and outputs the inverted switching signal to the second input terminal of the first AND gate 340.

[0079] As can be seen from the above process, if we want the signal at the second input terminal of the first AND gate 340 to be in the first state, then we need to satisfy that the output signal of the first NOT gate 333 is in the first state, that is, satisfy that the output of the first high value monitor 332 is in the second state, that is, satisfy that the timing time of the first timer 331 has not reached (less than or equal to) the second preset time, that is, satisfy that the timing time when the turbine speed is lower than the lower limit of the primary frequency regulation dead zone has not reached (less than or equal to) the second preset time.

[0080] In the above scheme, the upper limit of the target time interval for the unit load reduction regulation function of the lockout secondary frequency regulation is set by constructing a first timer 331 and a first high-value monitor 332.

[0081] Figure 4 Another schematic diagram of a frequency modulation control device in an exemplary embodiment is shown. Please refer to... Figure 4The frequency modulation control device 110 further includes a second high-value monitor 240 and a second NOT gate 250. The output of the second high-value monitor 240 is connected to the input of the second NOT gate 250. The first AND gate 340 also includes a third input, and the output of the second NOT gate 250 is connected to the third input of the first AND gate 340.

[0082] First, a lockout power range needs to be set to implement the lockout. This range consists of a target upper limit power and a target lower limit power. For example, the target lower limit power can be set to 317 MW and the target upper limit power to 602 MW. When the unit's active power is within the lockout power range [317, 602] MW, it indicates that the unit's load regulation function for secondary frequency regulation needs to be locked out. When the unit's active power is greater than 602 MW or less than 317 MW, it indicates that the turbine is operating normally.

[0083] The input of the second high-value monitor 240 is connected to the DEH terminal to obtain the unit's active power. When the unit's active power does not reach (is less than or equal to) the target upper limit power, it outputs a second-state switching signal to the second NOT gate 250. When the unit's active power reaches (is greater than) the target upper limit power, it outputs a first-state switching signal to the second NOT gate 250. The second NOT gate 250 is used to invert the input switching signal and outputs the inverted switching signal to the third input terminal of the first AND gate 340.

[0084] As can be seen from the above process, if we want the signal at the third input terminal of the first AND gate 340 to be in the first state, then we need to satisfy that the output of the second NOT gate 250 is in the first state, that is, satisfy that the output of the second high value monitor 240 is in the second state, that is, satisfy that the active power of the unit has not reached (less than or equal to) the target upper limit power.

[0085] In the above scheme, a second high-value monitor 240 is constructed to set the upper limit of active power for implementing the secondary frequency regulation load reduction function. For example, when the active power of the unit does not reach (less than or equal to) 602 MW, a first-state switch signal is output to the third input terminal of the first AND gate 340, so that when all input terminals of the first AND gate 340 are in the first state, the first AND gate 340 outputs a load reduction prohibition command to block the unit load reduction function of the secondary frequency regulation.

[0086] Optionally, such as Figure 4 As shown, the first AND gate 340 also includes a fourth input terminal, which is connected to the CCS (Coordination Control System) to obtain the control status of the unit. The fourth input terminal is used to receive the status signal of the first state or the status signal of the second state. The status signal of the first state indicates that the unit is in the coordinated automatic control state, and the status signal of the second state indicates that the unit is not in the coordinated automatic control state.

[0087] It is evident that if the signal at the fourth input terminal of the first AND gate 340 is to be in the first state, the unit must be in a coordinated automatic control state.

[0088] According to the above implementation method, the conditions for achieving the load reduction regulation function of the secondary frequency regulation unit are controlled through multiple input terminals of the first AND gate 340. Specifically, when all input terminals of the first AND gate 340 are in the first state, the following conditions should be met:

[0089] ① The timing time for the turbine speed to be lower than the lower limit of the primary frequency regulation dead zone reaches (greater than) the first preset time, but does not reach (less than or equal to) the second preset time;

[0090] ②The active power of the unit did not reach (below or equal to) the target upper limit power;

[0091] ③ The unit is in a coordinated automatic control state.

[0092] When all the above conditions are met, all input terminals of the first AND gate 340 are in the first state. Therefore, the output terminal of the first AND gate 340 outputs a switching signal of the first state to the reduction prohibition terminal LWI of the control chip 230. Thus, the control chip 230 outputs a reduction prohibition command to the turbine main control handheld device 120 through the control output terminal, thereby blocking the unit load reduction regulation function of the secondary frequency regulation.

[0093] Figure 5 A schematic diagram illustrating a specific implementation of a high-frequency monitoring circuit in an exemplary embodiment is shown below. Please refer to... Figure 5 The high-frequency monitoring circuit 220 includes: a third high-value monitor 410, a third timing unit 420, a fourth timing unit 430, and a second AND gate 440. The second AND gate 440 includes a first input terminal, a second input terminal, and an output terminal. The output terminal of the third high-value monitor 410 is connected to the input terminal of the third timing unit 420 and the input terminal of the fourth timing unit 430. The output terminal of the third timing unit 420 is connected to the first input terminal of the second AND gate 440, the output terminal of the fourth timing unit 430 is connected to the second input terminal of the second AND gate 440, and the output terminal of the second AND gate 440 is connected to the up-inhibit terminal RAI of the control chip 230.

[0094] The input of the third high-value monitor 410 is connected to the DEH to obtain turbine speed information. When the turbine speed is higher than the upper limit of the primary frequency regulation dead zone, the third high-value monitor 410 outputs a first-state switch signal to the input of the third timing unit 420 and the input of the fourth timing unit 430. The third timing unit 420 starts timing after detecting the input of the first-state switch signal. After the timing time reaches (or exceeds) the first preset time, it outputs the first-state switch signal to the first input of the second AND gate 440. The fourth timing unit 430 starts timing after detecting the input of the first-state switch signal. If the timing time does not reach (or is less than or equal to) the second preset time, it outputs the first-state switch signal to the second input of the second AND gate 440. The first preset time is the lower limit of the target time interval, and the second preset time is the upper limit of the target time interval. For example, the first preset time is 8 seconds, and the second preset time is 60 seconds.

[0095] Furthermore, when the turbine speed is lower than the upper limit of the primary frequency regulation dead zone, the third high value monitor 410 outputs a second state switch signal to the input terminal of the third timing unit 420 and the input terminal of the fourth timing unit 430. At this time, the third timing unit 420 and the fourth timing unit 430 do not start timing, so the outputs of the third timing unit 420 and the fourth timing unit 430 are both second state switch signals.

[0096] The second AND gate 440 is used to output a first-state switching signal to the up-inhibit terminal RAI of the control chip 230 when all input signals are in the first state. When the second AND gate 440 receives any second-state switching signal at its input, it outputs a second-state switching signal to the up-inhibit terminal RAI of the control chip 230.

[0097] As can be seen from the above process, if we want the signals of the first and second input terminals of the second AND gate 440 to be in the first state, we need to satisfy the requirement that the timing time when the turbine speed is higher than the upper limit of the primary frequency regulation dead zone reaches (greater than) the first preset time, but does not reach (less than or equal to) the second preset time.

[0098] In the above scheme, a third high-value monitor 410 is constructed to monitor whether the turbine speed is higher than the upper limit of the primary frequency regulation dead zone, and a third timing unit 420 and a fourth timing unit 430 are constructed to set the target time interval for realizing the unit load increase regulation function of locking the secondary frequency regulation.

[0099] Optionally, such as Figure 5As shown, the fourth timing unit 430 includes: a second timer 431, a fourth high-value monitor 432, and a third NOT gate 433. The output of the third high-value monitor 431 is connected to the input and enable terminals of the second timer 431; the output of the second timer 431 is connected to the input of the fourth high-value monitor 432; the output of the fourth high-value monitor 432 is connected to the input of the third NOT gate 433; and the output of the third NOT gate 433 is connected to the second input of the second AND gate 440.

[0100] For example, the timing cutoff time of the second timer 431 is set. In this disclosure, the timing cutoff time of the second timer 431 can be any value greater than 60 seconds, such as 100 seconds. The purpose of this setting is that after exceeding the upper limit of the primary frequency regulation dead zone of 60 seconds, the lockout needs to be released according to the rules to allow the turbine to operate normally. Therefore, the second timer 431 should count for at least 60 seconds.

[0101] The input and enable terminals of the second timer 431 are connected to the output terminal of the third high-value monitor 410 to obtain the switching signal output by the third high-value monitor 410. The second timer 431 starts timing after detecting a first-state switching signal at its own input and enable terminals, and outputs the timing time to the fourth high-value monitor 432. The fourth high-value monitor 432 monitors whether the timing time reaches a second preset time. If the timing time reaches (or exceeds) the second preset time, the fourth high-value monitor 432 outputs a first-state switching signal to the third NOT gate 433. If the timing time does not reach (or is less than or equal to) the second preset time, the fourth high-value monitor 432 outputs a second-state switching signal to the third NOT gate 433. The third NOT gate 433 is used to invert the input switching signal and outputs the inverted switching signal to the second input terminal of the second AND gate 440.

[0102] As can be seen from the above process, if we want the signal at the second input terminal of the second AND gate 440 to be in the first state, then we need to satisfy that the output signal of the third NOT gate 433 is in the first state, that is, satisfy that the output of the fourth high-value monitor 432 is in the second state, that is, satisfy that the timing time of the second timer 431 has not reached (less than or equal to) the second preset time, that is, satisfy that the timing time when the turbine speed is higher than the upper limit of the primary frequency regulation dead zone has not reached (less than or equal to) the second preset time.

[0103] In the above scheme, the upper limit of the target time interval for the unit load increase regulation function of the lockout secondary frequency regulation is set by constructing a second timer 431 and a fourth high-value monitor 432.

[0104] Figure 6 Another schematic diagram of a frequency modulation control device in an exemplary embodiment is shown. Please refer to... Figure 6The frequency modulation control device 110 further includes a second low-value monitor 260 and a fourth NOT gate 270. The output of the second low-value monitor 260 is connected to the input of the fourth NOT gate 270, and the second AND gate 440 also includes a third input. The output of the fourth NOT gate 270 is connected to the third input of the second AND gate 440.

[0105] First, a lockout power range needs to be set to implement the lockout. This range consists of a target upper limit power and a target lower limit power. For example, the target lower limit power can be set to 317 MW and the target upper limit power to 602 MW. When the unit's active power is within the lockout power range [317, 602] MW, it indicates that the unit's load regulation function for secondary frequency regulation needs to be locked out. When the unit's active power is greater than 602 MW or less than 317 MW, it indicates that the turbine is operating normally.

[0106] The input of the second low-value monitor 260 is connected to the DEH terminal to obtain the unit's active power. When the unit's active power is not lower than (greater than or equal to) the target lower limit power, it outputs a second-state switching signal to the fourth NOT gate 270. When the unit's active power is lower than the target lower limit power, it outputs a first-state switching signal to the fourth NOT gate 270. The fourth NOT gate 270 is used to invert the input switching signal and outputs the inverted switching signal to the third input terminal of the second AND gate 440.

[0107] As can be seen from the above process, if we want the signal at the third input terminal of the second AND gate 440 to be in the first state, then the output of the fourth NOT gate 270 must be in the first state, that is, the output of the second low value monitor 260 must be in the second state, that is, the active power of the unit must not be lower than (greater than or equal to) the target lower limit power.

[0108] In the above scheme, a second low-value monitor 260 is constructed to set the lower limit of active power for implementing the secondary frequency regulation load adjustment function. For example, when the unit's active power is not lower than (greater than or equal to) 317 MW, a first-state switch signal is output to the third input terminal of the second AND gate 440, so that when all input terminals of the second AND gate 440 are in the first state, it outputs a load increase prohibition command to block the unit load increase function of the secondary frequency regulation.

[0109] Optionally, such as Figure 6 As shown, the second AND gate 440 also includes a fourth input terminal, which is connected to the CCS to obtain the control status of the unit. The fourth input terminal is used to receive the status signal of the first state or the status signal of the second state. The status signal of the first state indicates that the unit is in the coordinated automatic control state, and the status signal of the second state indicates that the unit is not in the coordinated automatic control state.

[0110] It is evident that if the signal at the fourth input terminal of the second AND gate 440 is to be in the first state, the unit must be in a coordinated automatic control state.

[0111] According to the above implementation method, the conditions for achieving the load increase regulation function of the secondary frequency regulation unit are controlled through multiple input terminals of the second AND gate 440. Specifically, when all input terminals of the second AND gate 440 are in the first state, the following conditions should be met:

[0112] ① The timing time for the turbine speed to be higher than the upper limit of the primary frequency regulation dead zone reaches (greater than) the first preset time, but does not reach (less than or equal to) the second preset time;

[0113] ②The active power of the unit is not lower than (greater than or equal to) the target lower limit power;

[0114] ③ The unit is in a coordinated automatic control state.

[0115] When all the above conditions are met, all inputs of the second AND gate 440 are in the first state. Therefore, the output of the second AND gate 440 outputs a first-state switching signal to the RAI of the control chip 230, thereby the control chip 230 outputs an RAI command to the turbine main control handheld device 120 through the control output, thereby blocking the unit load increase regulation function of the secondary frequency regulation.

[0116] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0117] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction.

[0118] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. A frequency modulation control device, characterized in that, include: The system includes a low-frequency monitoring circuit, a high-frequency monitoring circuit, and a control chip. The low-frequency monitoring circuit is connected to the down-inhibition terminal of the control chip, the high-frequency monitoring circuit is connected to the up-inhibition terminal of the control chip, and the control output terminal of the control chip is connected to the turbine main control handheld device. The low-frequency monitoring circuit is used to time the time when the turbine speed is lower than the lower limit of the primary frequency regulation dead zone. When the time is within the target time interval, it outputs a first-state switch signal to the de-inhibit terminal of the control chip. The high-frequency monitoring circuit is used to time the time when the turbine speed is higher than the upper limit of the primary frequency regulation dead zone. When the time is within the target time interval, it outputs a first-state switch signal to the up-disable terminal of the control chip. The control chip is used to output a deceleration command to the turbine main control handheld device through the control output terminal when the input of the deceleration prohibition terminal is a switch signal in the first state, and to send an elevation prohibition command to the turbine main control handheld device through the control output terminal when the input of the elevation prohibition terminal is a switch signal in the first state. The reduction prohibition command is used to instruct the turbine main control manual controller to lock the unit load reduction regulation function of the secondary frequency regulation, and the increase prohibition command is used to instruct the turbine main control manual controller to lock the unit load increase regulation function of the secondary frequency regulation. The low-frequency monitoring circuit includes a first low-value monitor, a first timing unit, a second timing unit, and a first AND gate. The output terminal of the first low-value monitor is connected to the input terminal of the first timing unit and the input terminal of the second timing unit. The first AND gate includes a first input terminal, a second input terminal, and an output terminal. The output terminal of the first timing unit is connected to the first input terminal of the first AND gate, the output terminal of the second timing unit is connected to the second input terminal of the first AND gate, and the output terminal of the first AND gate is connected to the de-inhibit terminal of the control chip. The first low-value monitor is used to output a first-state switch signal to the input terminal of the first timing unit and the input terminal of the second timing unit when the turbine speed is lower than the lower limit of the primary frequency regulation dead zone; The first timing unit is used to start timing after detecting the input of the switch signal of the first state, and after the timing time reaches the first preset time, output the switch signal of the first state to the first input terminal of the first AND gate; The second timing unit is used to start timing after detecting the input of the switch signal of the first state, and to output the switch signal of the first state to the second input terminal of the first AND gate before the timing time reaches the second preset time; wherein, the first preset time is the lower limit of the target time interval, and the second preset time is the upper limit of the target time interval; The first AND gate is used to output a first-state switching signal to the de-inhibit terminal of the control chip when all input signals are in the first state.

2. The apparatus according to claim 1, characterized in that, The second timing unit includes a first timer, a first high-value monitor, and a first NOT gate. The output terminal of the first low-value monitor is connected to the input terminal and the enable terminal of the first timer. The output terminal of the first timer is connected to the input terminal of the first high-value monitor. The output terminal of the first high-value monitor is connected to the input terminal of the first NOT gate. The output terminal of the first NOT gate is connected to the second input terminal of the first AND gate. The first timer is used to start timing after detecting a switch signal that is in the first state at its own input terminal and its own enable terminal, and outputs the timing time to the input terminal of the first high-value monitor. The first high-value monitor is used to output a second state switching signal to the first NOT gate when the timing time has not reached the second preset time; The first NOT gate is used to invert the input switch signal and output the inverted switch signal to the second input terminal of the first AND gate.

3. The apparatus according to claim 1 or 2, characterized in that, The low-frequency monitoring circuit further includes a second high-value monitor and a second NOT gate. The output terminal of the second high-value monitor is connected to the input terminal of the second NOT gate. The first AND gate further includes a third input terminal, and the output terminal of the second NOT gate is connected to the third input terminal of the first AND gate. The second high-value monitor is used to output a second-state switching signal to the second NOT gate when the active power of the unit does not reach the target upper limit power. The second NOT gate is used to invert the input switch signal and output the inverted switch signal to the third input terminal of the first AND gate.

4. The apparatus according to claim 3, characterized in that, The first AND gate further includes a fourth input terminal, which is used to receive a status signal of a first state or a status signal of a second state. The status signal of the first state indicates that the unit is in a coordinated automatic control state, and the status signal of the second state indicates that the unit is not in a coordinated automatic control state.

5. The apparatus according to claim 1, characterized in that, The high-frequency monitoring circuit includes a third high-value monitor, a third timing unit, a fourth timing unit, and a second AND gate. The output terminal of the third high-value monitor is connected to the input terminal of the third timing unit and the input terminal of the fourth timing unit, respectively. The second AND gate includes a first input terminal, a second input terminal, and an output terminal. The output terminal of the third timing unit is connected to the first input terminal of the second AND gate, the output terminal of the fourth timing unit is connected to the second input terminal of the second AND gate, and the output terminal of the second AND gate is connected to the up-inhibit terminal of the control chip. The third high-value monitor is used to output a first-state switch signal to the input terminal of the third timing unit and the input terminal of the fourth timing unit when the turbine speed is higher than the upper limit of the primary frequency regulation dead zone; The third timing unit is used to start timing after detecting the input of the switch signal of the first state, and after the timing time reaches the first preset time, it outputs the switch signal of the first state to the first input terminal of the second AND gate. The fourth timing unit is used to start timing after detecting the input of the switch signal of the first state, and outputs the switch signal of the first state to the second input terminal of the second AND gate before the timing time reaches the second preset time; wherein, the first preset time is the lower limit of the target time interval, and the second preset time is the upper limit of the target time interval; The second AND gate is used to output a first-state switching signal to the up-inhibit terminal of the control chip when all input signals are in the first state.

6. The apparatus according to claim 5, characterized in that, The fourth timing unit includes a second timer, a fourth high-value monitor, and a third NOT gate. The output terminal of the third high-value monitor is connected to the input terminal and the enable terminal of the second timer. The output terminal of the second timer is connected to the input terminal of the fourth high-value monitor. The output terminal of the fourth high-value monitor is connected to the input terminal of the third NOT gate. The output terminal of the third NOT gate is connected to the second input terminal of the second AND gate. The second timer is used to start timing after detecting a switch signal that is in the first state at its own input terminal and its own enable terminal, and outputs the timing time to the input terminal of the fourth high-value monitor. The fourth high-value monitor is used to output a second state switching signal to the third NOT gate when the timing time has not reached the second preset time. The third NOT gate is used to invert the input switch signal and output the inverted switch signal to the second input terminal of the second AND gate.

7. The apparatus according to claim 5 or 6, characterized in that, The high-frequency monitoring circuit further includes a second low-value monitor and a fourth NOT gate. The output terminal of the second low-value monitor is connected to the input terminal of the fourth NOT gate. The second AND gate further includes a third input terminal, and the output terminal of the fourth NOT gate is connected to the third input terminal of the second AND gate. The second low-value monitor is used to output a second-state switching signal to the fourth NOT gate when the active power of the turbine unit exceeds the target lower limit power. The fourth NOT gate is used to invert the input switch signal and output the inverted switch signal to the third input terminal of the second AND gate.

8. The apparatus according to claim 7, characterized in that, The second AND gate further includes a fourth input terminal, which is used to receive a status signal of a first state or a status signal of a second state. The status signal of the first state indicates that the unit is in a coordinated automatic control state, and the status signal of the second state indicates that the unit is not in a coordinated automatic control state.

9. A power grid frequency regulation control system, characterized in that, It includes the frequency control device as described in any one of claims 1-8, and the turbine main control manual controller.

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