voltage divider circuit, negative feedback circuit, and power-on reset circuit

Abstract

The present disclosure relates to a voltage divider circuit, a negative feedback circuit, and a power-on reset circuit. The voltage divider circuit includes a first voltage divider having first and second capacitors and an output node configured to output a divided voltage from between the first and second capacitors, a second voltage divider having third and fourth capacitors and first to third switches, and the second voltage divider being connected in parallel with the first voltage divider, and a fourth switch provided between the output node and a connection node of the third and fourth capacitors. In the voltage divider circuit, the switches are controlled based on control of a time period.

Description

[0001] Cross-reference to related applications

[0002] The disclosure of Japanese Patent Application No. 2021-028126, filed on February 25, 2021 (including the specification, drawings and abstract), is incorporated herein by reference in its entirety. Technical Field

[0003] This invention relates to voltage divider circuits, negative feedback circuits, and power-on reset circuits. Background Technology

[0004] The publicly available technologies are listed below.

[0005] [Patent Document 1] Japanese Unexamined Patent Application Publication No. H08-335059

[0006] [Patent Document 2] Japanese Patent No. 3773718

[0007] [Non-patent document 1] "LP3470 Tiny Power ON Reset Circuit" from *Texas Instruments Incorporated*. [Online]

[0008] http: / / www.tij.co.jp / jp / lit / ds / symlink / lp3470.pdf

[0009] Patent Document 1 discloses a signal amplifier that includes a voltage divider circuit formed in the form of a semiconductor film such as a silicon thin film. As a conventional technique, Figure 21 of Patent Document 1 shows a signal amplifier circuit including a resistive voltage divider circuit.

[0010] Non-Patent Document 1 discloses a typical configuration of a power-on reset circuit using a resistive voltage divider circuit. The standby current of a low-current-consumption microcontroller unit (MCU) is approximately 1A, and it is assumed that about 10% (0.1A) is used to monitor the supply voltage (VDD). In this case, when the supply voltage is set to 3.3V, the required resistance is 33 MOhm, and a large circuit area is required.

[0011] Furthermore, Patent Document 2 discloses a boost circuit including a capacitive voltage divider circuit, and a buck circuit. When using a capacitive voltage divider, there is no stable power consumption, and the circuit area can be reduced compared to using a resistive voltage divider. Since the output voltage of the capacitive voltage divider circuit drifts due to leakage current, in Patent Document 2, the resistive voltage divider circuit is operated intermittently to compensate for the drift. This intermittent operation allows for a small time average current consumption of the resistive voltage divider circuit. Note that although the current consumption is added by the clock used to perform the intermittent operation, it is considered very small.

[0012] Compared to using a resistive voltage divider, the technique disclosed in Patent Document 2 allows for a reduction in circuit area and power consumption. However, the current consumption and circuit area required to achieve a simple voltage divider function are currently insufficient, and further reductions in current consumption and circuit area are desired. Summary of the Invention

[0013] The desired operation is for circuits such as power-on reset circuits and regulators for memory retention, operating in the MCU's standby state, with a current consumption of approximately 10nA. These circuits require voltage divider circuits to monitor signals or generate feedback signals. In conventional techniques using resistive voltage dividers, achieving approximately 10nA of current consumption involves sacrificing circuit area or using special optional processes.

[0014] On the other hand, the technology disclosed in Patent Document 2 mainly achieves low current consumption and miniaturization by using a capacitive voltage divider circuit that does not have stable current consumption. However, since this technology uses an intermittently operating resistive voltage divider circuit to compensate for the drift generated in the capacitive voltage divider circuit, there is still a problem that a large circuit area is required to achieve a current consumption of approximately 10 nA.

[0015] In addition, in patent document 2 Figure 1 In the boost circuit shown, leakage current from the capacitor mainly occurs at switch SW2. When the resistive voltage divider circuit is not operating, leakage current generation is unavoidable because the voltage between the terminals of switch SW2 is equal to the divided voltage. Therefore, according to the technology disclosed in Patent Document 2, it is necessary to increase the operating frequency of the resistive voltage divider circuit to compensate for the drift caused by leakage current, or to increase the capacitance values ​​of capacitors C1 and C2 to minimize the drift caused by leakage. However, the former leads to an increase in current consumption, while the latter leads to an increase in circuit area.

[0016] Other objects and novel features will become clear from the description in this specification and the accompanying drawings.

[0017] According to one embodiment, a voltage divider circuit includes: a first voltage divider comprising: a first capacitor and a second capacitor connected in series between an input potential and a reference potential, and an output node configured to output a divided voltage from between the first capacitor and the second capacitor; a second voltage divider comprising: a third capacitor and a fourth capacitor having a capacitance ratio substantially the same as that of the first capacitor and the second capacitor; a first switch; a second switch connected in parallel with the third capacitor; and a third switch connected in parallel with the fourth capacitor, wherein the third capacitor, the fourth capacitor, and the first switch are connected in series and in parallel with the first voltage divider; and a fourth switch disposed between the output node and the connection node of the third capacitor and the fourth capacitor. In a first time period, the first switch is controlled to be in a non-conducting state, the second and third switches are controlled to be in a conducting state, and the fourth switch is controlled to be in a non-conducting state. In a second time period following the first time period, the first switch is controlled to be in a conducting state, the second and third switches are controlled to be in a non-conducting state, and the fourth switch is controlled to be in a non-conducting state. In the third period following the second period, the first switch is controlled to be in the ON state, the second and third switches are controlled to be in the OFF state, and the fourth switch is controlled to be in the ON state. In the fourth period following the third period, the first switch is controlled to be in the ON state, the second and third switches are controlled to be in the OFF state, and the fourth switch is controlled to be in the OFF state.

[0018] According to one embodiment, the voltage divider circuit can be miniaturized or have low current consumption. Attached Figure Description

[0019] Figure 1 This is a diagram showing the configuration of the voltage divider circuit according to the first embodiment.

[0020] Figure 2 This is a diagram showing the control signals input to the voltage divider circuit.

[0021] Figure 3 This is a diagram illustrating a configuration example of a voltage divider circuit according to a first modified example of the first embodiment.

[0022] Figure 4 This is a diagram illustrating a configuration example of a voltage divider circuit according to a first modified example of the first embodiment.

[0023] Figure 5 This is a diagram illustrating a configuration example of a voltage divider circuit according to a second modified example of the first embodiment.

[0024] Figure 6 This is a diagram illustrating a configuration example of a voltage divider circuit according to a fourth modified example of the first embodiment.

[0025] Figure 7 This is a diagram illustrating a configuration example of a voltage divider circuit according to a fourth modified example of the first embodiment.

[0026] Figure 8 This is a diagram illustrating a configuration example of a voltage divider circuit according to a fifth modified example of the first embodiment.

[0027] Figure 9 This is a diagram illustrating a configuration example of a voltage divider circuit according to a fifth modified example of the first embodiment.

[0028] Figure 10 This is a diagram illustrating a configuration example of a voltage divider circuit according to a sixth modified example of the first embodiment.

[0029] Figure 11 This is a diagram illustrating a configuration example of a voltage divider circuit according to a seventh modified example of the first embodiment.

[0030] Figure 12 This is a diagram illustrating a configuration example of a voltage divider circuit according to a seventh modified example of the first embodiment.

[0031] Figure 13 This is a diagram illustrating a configuration example of a voltage divider circuit according to a seventh modified example of the first embodiment.

[0032] Figure 14 This is a diagram illustrating a configuration example of a voltage divider circuit according to an eighth modified example of the first embodiment.

[0033] Figure 15 This is a diagram illustrating an example configuration of the negative feedback circuit of the second embodiment.

[0034] Figure 16 This is a diagram showing the control signals input to the voltage divider circuit.

[0035] Figure 17 This is a diagram illustrating an example configuration of the negative feedback circuit of the second embodiment.

[0036] Figure 18 This is a diagram showing the configuration of the power-on reset circuit according to the third embodiment. Detailed Implementation

[0037] The following description and figures contain omissions or simplifications for clarity. Furthermore, each element described in the figures as a functional block performing various processes can be configured in hardware such as a CPU, memory, or any other circuitry, and in software such as a program loaded in memory. Therefore, those skilled in the art will understand that such functional blocks can be implemented in various ways, including but not limited to separate hardware, separate software, or combinations thereof. Additionally, in the figures, the same reference numerals denote the same elements, and redundant descriptions are appropriately omitted.

[0038] Furthermore, the aforementioned program can be stored in various types of non-transitory computer-readable media for provision to a computer. Non-transitory computer-readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic storage media (such as floppy disks, magnetic tapes, or hard disk drives), magneto-optical storage media (such as magneto-optical disks), CD-ROMs (Read-Only Memory), CD-Rs, CD-R / Ws, and semiconductor memories (such as mask ROMs, PROMs (Programmable ROMs), EPROMs (Erasable PROMs), flash memory ROMs, or RAMs (Random Access Memory). In addition, the program can be provisioned to a computer via various types of transient computer-readable media. Examples of transient computer-readable media include electrical signals, optical signals, and electromagnetic waves. Transient computer-readable media can provide the program to a computer via wired or wireless communication channels such as electrical wires or optical fibers.

[0039] (First Embodiment)

[0040] In the following text, reference will be made to Figure 1 The configuration of the voltage divider circuit according to the first embodiment is described. Figure 1 This diagram illustrates the configuration of a voltage divider circuit 10. The voltage divider circuit 10 includes: a first voltage divider 11, including capacitors C1 and C2 and a voltage node "output"; a second voltage divider 12, including capacitors C3 and C4, switches SW1, SW2, and SW3, and switch SW4. The voltage divider circuit 10 may also include a controller configured to control the on / off states of switches SW1, SW2, SW3, and SW4.

[0041] The first voltage divider 11 includes capacitor C1, capacitor C2, and an output node "output". Capacitor C1 is also referred to as the first capacitor. Capacitor C2 is also referred to as the second capacitor. Capacitors C1 and C2 are connected in series between the input potential "input" and the reference potential VSS. The output node "output" outputs a divided voltage from between capacitors C1 and C2. In other words, the voltage divider node "output" outputs a divided voltage obtained by dividing the input potential "input" by the capacitance ratio of capacitors C1 and C2. The capacitances of capacitors C1 and C2 are selected such that a predetermined voltage division ratio can be obtained. Leakage causes the divided voltage to drift over time.

[0042] The second voltage divider 12 includes capacitor C3, capacitor C4, switch SW1, switch SW2, and switch SW3. Switch SW1 is also referred to as the first switch. Switch SW2 is also referred to as the second switch. Switch SW3 is also referred to as the third switch.

[0043] Switch SW2 is connected in parallel with capacitor C3. Switch SW3 is connected in parallel with capacitor C4. When switch SW2 is turned on, the charge accumulated in capacitor C3 is reset (discharged). When switch SW3 is turned on, the charge accumulated in capacitor C4 is reset.

[0044] Capacitors C3 and C4 and switch SW1 are connected in series and in parallel with the first voltage divider 11 (i.e., capacitors C1 and C2). Figure 1 As shown, switch SW1 can be positioned between capacitor C3 and capacitor C4. Furthermore, switch SW1 can be positioned between the input potential "input" and capacitor C3, or between the reference potential VSS and capacitor C4.

[0045] The capacitance ratio of capacitors C3 and C4 is substantially the same as that of capacitors C1 and C2. However, the capacitance ratios do not need to be exactly the same. After switches SW2 and SW3 are controlled to the non-conducting state, capacitors C3 and C4 are charged when switch SW1 is controlled to the conducting state. Then, the potential of the connection node between capacitors C3 and C4 becomes substantially the same as the potential of the output node "output" of the first voltage divider 11.

[0046] Switch SW4 is positioned between the output node "output" of the first voltage divider 11 and the connection node between capacitors C3 and C4 of the second voltage divider 12. When switch SW4 is controlled to be in the on state, the second voltage divider 12 can be used to compensate for the output voltage of the first voltage divider 11.

[0047] Control the conduction states of switches SW1, SW2, SW3, and SW4 to repeat the following time periods T1, T2, T3, and T4. Time period T1 is also referred to as the first time period, time period T2 as the second time period, time period T3 as the third time period, and time period T4 as the fourth time period.

[0048] Figure 2 This diagram shows the timing of the control signals φ1, φ2, and φ3 for switches SW1, SW2, SW3, and SW4. Control signal φ1 is used to control switch SW1. Control signal φ2 is used to control switches SW2 and SW3. Control signal φ3 is used to control switch SW4.

[0049] Control signals φ1, φ2, and φ3 control switches SW1, SW2, and SW3 to be on when they are high, and to be off when they are low. The operation chart includes time periods T1, T2, T3, and T4.

[0050] During time period T1, control signal φ1 is low, control signal φ2 is high, and control signal φ3 is low. Therefore, switch SW1 is controlled to be in a non-conducting state, switches SW2 and SW3 are controlled to be in a conducting state, and switch SW4 is controlled to be in a non-conducting state. During time period T1, the charge on capacitors C3 and C4 of the second voltage divider 12 is discharged.

[0051] During time period T2 following time period T1, control signal φ1 is high, control signal φ2 is low, and control signal φ3 is low. Therefore, switch SW1 is controlled to be on, switches SW2 and SW3 are controlled to be off, and switch SW4 is controlled to be off. As a result, capacitors C3 and C4 are charged, and the second voltage divider 12 generates a divided voltage.

[0052] During time period T3 following time period T2, control signal φ1 is high, control signal φ2 is low, and control signal φ3 is high. Therefore, switch SW1 is controlled to be on, switches SW2 and SW3 are controlled to be off, and switch SW4 is controlled to be on. As a result, the voltage divider generated during time period T2 compensates for the output voltage of the first voltage divider 11.

[0053] During time period T4, following time period T3, control signal φ1 is high, control signal φ2 is low, and control signal φ3 is low. Therefore, switch SW1 is controlled to be on, switches SW2 and SW3 are controlled to be off, and switch SW4 is controlled to be off. As a result, the voltage divided by the first voltage divider 11 and the voltage divided by the second voltage divider 12 remain independent of each other. After time period T4, the state of the voltage divider circuit 10 returns to the state in time period T1.

[0054] The voltage divider circuit according to the first embodiment can achieve low power consumption and miniaturization. The reasons for achieving these effects will be described below from two perspectives.

[0055] The first reason for achieving this effect is the low current consumption in reset switches SW2 and SW3. Here, the product of the waste charge associated with the reset of capacitors C3 and C4 and the reset frequency (frequency) is the current consumption associated with the voltage divider operation. In the following text, we will consider the case where the area of ​​capacitors C3 and C4 is sufficiently small and the capacitance is 0.2pF. Assuming VDD is 3.3V and the reset frequency is 1kHz, the current consumption will be a sufficiently small value, (0.2pF / / 0.2pF)*3.3V*1kHz = 0.33nA. Therefore, according to the voltage divider circuit 10, miniaturization and low power consumption of the circuit can be achieved.

[0056] The second reason for this effect is the small leakage current of the first voltage divider 11, which is composed of capacitors C1 and C2. The period T4 during which the first voltage divider 11 and the second voltage divider 12 independently maintain the voltage accounts for a large proportion of an operating cycle (periods T1 to T4). During period T4, there is only a small potential difference between the voltages divided by the first voltage divider 11 and the second voltage divider 12, caused only by leakage differences. Therefore, the leakage current of the switch SW4, which is controlled to be in a non-conducting state during period T4, is suppressed to a small extent, and the charge of capacitors C1 and C2 can be maintained for a longer period. By using this to reduce the voltage drift compensation frequency, the current consumption in the voltage divider circuit 10 can be reduced. Furthermore, by using smaller capacitors C1, C2, C3, and C4, and by setting the compensation frequency to meet the required voltage drift criteria, circuit miniaturization and low current consumption can be achieved.

[0057] (First Modification Example)

[0058] In the following text, reference will be made to Figure 3 and Figure 4A voltage divider circuit according to a first modified example of the first embodiment is described. In the voltage divider circuit 10 according to the first modified example, capacitors C1 and C2 are MOS (metal-oxide-semiconductor) capacitors with a very small area. MOS capacitors are capacitors composed of MOS transistors. Additionally, in the voltage divider circuit of the first modified example, capacitors C3 and C4 are MOM (metal-oxide-semiconductor) capacitors with good precision and low bias dependence.

[0059] Capacitors C1 and C2 can both be nMOS capacitors, such as Figure 3 As shown, they could all be pMOS capacitors, such as Figure 4 As shown. In Figure 3 In this configuration, capacitor C1 is composed of nMOS transistor MN1, and capacitor C2 is composed of nMOS transistor MN2. Figure 4 In the diagram, capacitor C1 is composed of pMOS transistor MP2, and capacitor C2 is composed of pMOS transistor MP1.

[0060] By compensating with capacitors C3 and C4, the error in the voltage division ratio caused by changes in the capacitance ratio of capacitors C1 and C2 is suppressed. On the other hand, changes in the capacitance ratio of capacitors C3 and C4 directly affect the accuracy of the voltage division ratio, so small changes are desirable. Furthermore, since charging begins from the reset state, the bias dependence of the capacitor values ​​is required to be small.

[0061] In the voltage divider circuit 10 according to the first modified example, capacitors C1 and C2 are MOS capacitors, and capacitors C3 and C4 are MOM capacitors. Therefore, the circuit area can be reduced while maintaining the accuracy of the voltage division ratio.

[0062] (Second Modification Example)

[0063] In the following text, reference will be made to Figure 5 A voltage divider circuit according to a second modified example of the first embodiment is described. The voltage divider circuit 10 according to the second modified example has a configuration according to the first modified example, wherein one MOS capacitor is an nMOS capacitor and the other MOS capacitor is a pMOS capacitor. Figure 5 As shown, capacitor C1 is a pMOS capacitor composed of pMOS transistor MP1, while capacitor C2 is an nMOS capacitor composed of nMOS transistor MN1. The output node "output" is the node connecting the gate of pMOS transistor MP1 and the gate of nMOS transistor MN1.

[0064] In the voltage divider circuit according to the second modified example, the output node "output" is not connected to the diffusion layer of the MOS transistor, thereby suppressing charge leakage in the MOS capacitor. Since the capacitance value can be reduced by suppressing leakage, or since the compensation frequency can be reduced, low power consumption and miniaturization of the circuit can be achieved in the voltage divider circuit 10.

[0065] (Third Modification Example)

[0066] The voltage divider circuit 10 according to the third modified example has a configuration according to the first and second modified examples, wherein the MOS capacitor and the MOM capacitor are overlapped and arranged on the chip. As a result, the circuit area of ​​the voltage divider circuit 10 can be reduced.

[0067] Specifically, for example, in the wiring layers of the chip, wiring related to MOS capacitors is formed in the first and second layers counting from the bottom. Then, wiring related to MOM capacitors is formed in the third and higher layers. The layers in which wiring related to MOS capacitors is formed overlap with the layers in which wiring related to MOM capacitors is formed. As a result, the circuit area of ​​the voltage divider circuit 10 can be reduced.

[0068] (Fourth modification example)

[0069] In the following text, reference will be made to Figure 6 and Figure 7 A voltage divider circuit according to a fourth modified example of the first embodiment is described. The voltage divider circuit 10 according to the fourth modified example has a configuration in which switches SW1 to SW4 are implemented by MOS transistors as in the second modified example.

[0070] Given the operating potential and component characteristics, the configuration of each switch can be determined. Figure 6 and Figure 7 In this circuit, switch SW1 is composed of pMOS transistor MP3, switch SW2 is composed of pMOS transistor MP4, and switch SW3 is composed of nMOS transistor MN4. Figure 6 The intermediate switch SW4 is composed of a pMOS transistor MP5, and in Figure 7 It consists of a pMOS transistor MP5 and an nMOS transistor MN5 connected in parallel.

[0071] When the switch is an nMOS transistor Figure 2 The corresponding signals among the control signals φ1 to φ3 shown are input to the gate of the transistor constituting each switch. When the switch is a pMOS transistor, the corresponding signals among φ1B to φ3B, which are complementary to the control signals φ1 to φ3, are input to the gate of the transistor.

[0072] (Fifth revision example)

[0073] In the following text, reference will be made to Figure 8 and Figure 9 A voltage divider circuit according to a fifth modified example of the first embodiment is described. The voltage divider circuit 10 according to the fifth modified example is based on... Figure 1 The configuration shown, the configuration of the first modified example, and the configuration of the second modified example, and having a configuration in which each of the capacitors C1 and C2 is divided into two capacitors and a switch SW5 is arranged between the divided capacitors. Figure 8 The configuration shown is based on Figure 1 The configuration shown. Figure 9 The configuration shown is based on the configuration of the second modified example. Control signal φ3 is used to control switch SW5.

[0074] Capacitors C3 and C4 have switches SW2 or SW3 connected in parallel to reset the charge. Therefore, capacitors C11 and C21, which are not connected to switches, have less charge leakage compared to capacitors C3 and C4. During the aforementioned period T4, the voltage difference between the connection points of capacitors C11 and C21 and the connection points of capacitors C12 and C22 is applied only between the terminals of switch SW5, which is controlled to be in the off state. Therefore, the charge leakage in capacitors C12 and C22 is less, and the voltage divider circuit 10 can reduce the drift of the output divided voltage.

[0075] (Sixth Modification Example)

[0076] In the following text, reference will be made to Figure 10 A voltage divider circuit according to a sixth modified example of the first embodiment is described. The voltage divider circuit according to the sixth modified example is based on... Figure 1 The configuration shown, the configuration of the first modified example, and the configuration of the second modified example, and have a configuration in which capacitor C1 is divided into n capacitors C11 to C1n, capacitor C2 is divided into n capacitors C21 to C2n, and switches SW5 to SW(n+3) are arranged between capacitors with adjacent numbers. Switches SW5 to SW(n+3) are controlled using a control signal φ3. Each capacitor in C1 and C2 consists of n capacitors (where n is a two or larger integer) connected in parallel.

[0077] Figure 10The diagram shows each of capacitors C1 and C2 divided into four parts. Capacitors C11, C12, C13, and C14 are obtained by dividing capacitor C1 into four parts, and are respectively composed of pMOS transistors MP8, MP7, MP6, and MP1. Capacitors C21, C22, C23, and C24 are obtained by dividing capacitor C2 into four parts, and are respectively composed of nMOS transistors MN8, MN7, MN6, and MN1.

[0078] Each node connecting capacitors C11 to C14 and capacitors C21 to C24 is connected to the adjacent node via switch SW5, SW6, or SW7. Switches SW5 to SW7 are controlled to be in the same conducting state as switch SW4.

[0079] Choosing the optimal number of n allows the voltage divider circuit based on the sixth modified example to further enhance the effects described in the fifth modified example.

[0080] (Seventh Modification Example)

[0081] In the following description, a voltage divider circuit according to a seventh modified example of the first embodiment will be used with reference to the description. The voltage divider circuit according to the seventh modified example has a configuration in which the placement (insertion) point of switch SW1 and the connection point of switch SW4 on the capacitor C3 and C4 sides are... Figure 1 The configuration changes shown are significant. Insertion points and connection points have some flexibility and are design considerations.

[0082] Switch SW1 can be positioned between the input potential "input" and capacitor C3, such as... Figure 11 As shown, or it can be arranged between capacitor C4 and reference potential VSS, as shown. Figure 12 As shown, or it can be arranged between capacitors C3 and C4, as shown. Figure 13 As shown in the diagram. One end of switch SW4 can be connected to the capacitor C4 side, as shown in the diagram. Figure 1 As shown in the diagram, or it can be connected to the capacitor C3 side, as shown in the diagram. Figure 13 As shown in the image.

[0083] (Eighth Modified Example)

[0084] In the following text, reference will be made to Figure 14 A voltage divider circuit according to an eighth modified example of the first embodiment is described. Although Figure 1 The modified example shows a configuration in which the voltage divider circuit 10 operates with VSS as a reference, but the voltage divider circuit 10 can also operate with VDD as a reference. Alternatively, the voltage divider circuit 10 can also operate with a fixed potential other than VDD or VSS as a reference. Figure 14 This is a diagram showing a voltage divider circuit operating with VDD as a reference.

[0085] (Second Embodiment)

[0086] Figure 15 This is a configuration diagram showing the negative feedback circuit 100 using the voltage divider circuit according to the first embodiment. In the description of the second embodiment, those components equivalent to those in the first embodiment are designated by the same reference numerals, and redundant descriptions are omitted as appropriate. The negative feedback circuit 100 according to the second embodiment includes the voltage divider circuit 10, the controller 20, and the operational amplifier 30 according to the first embodiment. The operational amplifier 30 is also referred to as a comparator amplifier.

[0087] The output "Output 1" of operational amplifier 30 is input to voltage divider circuit 10 as the input potential (input voltage) "Input". Voltage divider circuit 10 divides the input voltage. Then, the voltage divided by voltage divider circuit 10 is input (feedback) to the negative input terminal (negative input) of operational amplifier 30. Controller 20 generates the aforementioned control signals φ1, φ2, and φ3 according to the clock generated by clock source 40.

[0088] Figure 16 This is a timing diagram showing an example of the waveforms of clock CLK and control signals φ1 to φ3. 32 cycles of clock CLK correspond to one operating cycle. The numbers 1 to 32 shown for clock CLK represent clock numbers. Clock 1 corresponds to the aforementioned time period T1. Clock 4 corresponds to the aforementioned time period T2. Clock 5 corresponds to the aforementioned time period T3. Clocks 6 to 32 correspond to the aforementioned time period T4.

[0089] exist Figure 16 Dead time (clock 3 and clock 1) is provided between time period T1 and time period T2, and between time period T4 and time period T1, respectively, to prevent through current caused by simultaneous switching of multiple switches.

[0090] Other examples of negative feedback circuit 100 include LDO (low dropout) and regulators. For example, clock source 40 could be a 32kHz LOCO (low-speed on-chip oscillator).

[0091] Figure 17 It shows Figure 15 The example configuration shown is modified by adding an LPF (low-pass filter) 50. Because the voltage divider circuit 10 intermittently compensates for the drift of the divided voltage, oscillations in the output voltage synchronized with it are unavoidable. The output "output" of the voltage divider circuit 10 is input to the negative input of the operational amplifier 30 via the LPF 50. As a result, the negative feedback circuit 100 can reduce the oscillations in the output voltage synchronized with the compensation.

[0092] Similar to the voltage divider circuit according to the first embodiment, low power consumption and miniaturization can be achieved in the negative feedback circuit according to the second embodiment.

[0093] (Third Embodiment)

[0094] Figure 18 This is a configuration diagram showing the arrangement of a power-on reset circuit 100a using a voltage divider circuit 10. In the description of the third embodiment, components equivalent to those in the first and second embodiments are designated by the same reference numerals, and redundant descriptions are omitted where appropriate. The power-on reset circuit 100a according to the third embodiment includes a voltage divider circuit 10, a controller 20, and a comparator 60.

[0095] Voltage divider circuit 10 divides the power supply voltage VDD and inputs the divided voltage to comparator 60. Comparator 60 compares the divided voltage input from voltage divider circuit 10 with a reference voltage and generates a reset signal RSTB based on the comparison result.

[0096] Because the voltage divider circuit 10 intermittently compensates for the drift of the capacitor voltage, oscillations in the output voltage of the synchronous power-on reset circuit 100a are unavoidable. The comparator 60 can have a hysteresis characteristic to prevent jitter in the reset signal RSTB caused by this oscillation.

[0097] Similar to the voltage divider circuit according to the first embodiment, the power-on reset circuit according to the third embodiment can achieve low power consumption and miniaturization of the circuit.

[0098] The invention has been specifically described above based on embodiments. However, it goes without saying that the invention is not limited to the foregoing embodiments, and various modifications and alterations can be made within the scope of the invention.

[0099] For example, the voltage divider circuit according to the above embodiment may have a configuration in which the semiconductor substrate, semiconductor layer, diffusion layer (diffusion region), etc., have opposite conductivity types (p-type or n-type). Therefore, when the first conductivity type is one of n-type and p-type and the second conductivity type is the other of n-type and p-type, the first conductivity type may be p-type and the second conductivity type may be n-type, or conversely, the first conductivity type may be n-type and the second conductivity type may be p-type.

Claims

1. A voltage divider circuit, comprising: A first voltage divider includes: a first capacitor and a second capacitor connected in series between an input potential and a reference potential; and an output node configured to output a divided voltage from between the first capacitor and the second capacitor. The second voltage divider includes: a third capacitor and a fourth capacitor having substantially the same capacitance ratio as the first capacitor and the second capacitor; a first switch; a second switch connected in parallel with the third capacitor; and a third switch connected in parallel with the fourth capacitor, wherein the third capacitor, the fourth capacitor, and the first switch are connected in series and in parallel with the first voltage divider; and A fourth switch is disposed between the output node and the connection node of the third and fourth capacitors. During the first time period, the first switch is controlled to be in a non-conducting state, the second and third switches are controlled to be in a conducting state, and the fourth switch is controlled to be in a non-conducting state. During the second time period following the first time period, the first switch is controlled to be in the on state, the second and third switches are controlled to be in the off state, and the fourth switch is controlled to be in the off state. In the third period following the second period, the first switch is controlled to be in the ON state, the second and third switches are controlled to be in the OFF state, and the fourth switch is controlled to be in the ON state. In the fourth period following the third period, the first switch is controlled to be in the on state, the second and third switches are controlled to be in the off state, and the fourth switch is controlled to be in the off state.

2. The voltage divider circuit according to claim 1, Each of the first and second capacitors consists of n capacitors connected in parallel, where n is an integer of two or greater. Each of the n nodes of the n capacitors constituting the first capacitor and the n capacitors constituting the second capacitor is connected to an adjacent node via a switch, and The switch is controlled to be in the same conducting state as the fourth switch.

3. The voltage divider circuit according to claim 1, The first capacitor and the second capacitor are MOS capacitors, which are composed of MOS metal oxide semiconductor transistors.

4. The voltage divider circuit according to claim 3, The first capacitor is a MOS capacitor composed of MOS transistors of a first conductivity type, and the second capacitor is a MOS capacitor composed of MOS transistors of a second conductivity type, the second conductivity type being opposite to the first conductivity type. The output node is a node in which the gate of the MOS transistor of the first conductivity type and the gate of the MOS transistor of the second conductivity type are connected.

5. The voltage divider circuit according to claim 3, The third capacitor and the fourth capacitor are MOM metal oxide capacitors.

6. A negative feedback circuit, comprising the voltage divider circuit and operational amplifier according to claim 1, The output voltage of the operational amplifier is input to the voltage divider circuit as the input potential, and the voltage divided by the voltage divider circuit is input to the negative input terminal of the operational amplifier.

7. A power-on reset circuit, comprising the voltage divider circuit and comparator according to claim 1, The voltage divider circuit is configured to divide the power supply voltage and output it as the divided voltage. The comparator is configured to compare the divided voltage with a reference voltage and generate a reset signal based on the comparison result.

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