Feedforward current compensation for CMOS signal paths

Abstract

An integrated circuit has a CMOS signal path coupled to receive a data signal. A compensation circuit is coupled to a power supply rail of the CMOS signal path to inject a compensation current into the power supply rail. The compensation circuit can be a charge pump that operates in response to the data signal to inject the compensation current into the power supply rail at each data signal transition. The compensation circuit can be a replica CMOS signal path to inject the compensation current into the power supply rail at each data signal transition. The compensation circuit can be a voltage regulator and a current mirror that includes an input coupled to the voltage regulator. The replica CMOS signal path receives an operating potential from the voltage regulator. An output of the current mirror injects the compensation current into the power supply rail at each data signal transition.

Description

[0001] This invention is a divisional application filed on August 18, 2020, with application number 202010830321.X and entitled "Feedforward Current Compensation for CMOS Signal Paths". The parent application claims priority to US Patent and Trademark Office application number 16 / 560,583, filed on September 4, 2019. Technical Field

[0002] This invention relates generally to a CMOS IC, and more specifically to a feedforward current compensation scheme for a CMOS signal path. Background Technology

[0003] In complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) that process high-speed serial data, it is effective to use CMOS logic circuit elements (such as inverters and logic gates) in the high-speed serial data signal path. The supply current of CMOS logic circuits changes rapidly in response to logic transitions in the input data.

[0004] Figure 1 A conventional CMOS signal path 50 for propagating high-speed serial differential data via an IC is shown. A voltage regulator 52 includes an amplifier 54 that receives a reference voltage VREF at its inverting input. The output of amplifier 54 is coupled to the gate of transistor 56. The drain of transistor 56 is coupled to a power supply conductor 58 operating at a positive potential VDD, and the source of transistor 56 is coupled to node 60. The non-inverting input of amplifier 54 is coupled to node 60, which serves as a power rail to maintain the regulated output voltage VREG. The CMOS signal path 50 receives the input data signal DATAIN at terminal 70 and the complement of DATAIN at terminal 72. DATAIN is propagated via a series coupling of an inverter or buffer 80 that receives a positive operating potential from VREG and a ground operating potential from the power supply conductor 82. The complement of DATA IN is propagated through a series-coupled inverter or buffer 84, which receives a positive operating potential from V REG and a ground operating potential from the power supply conductor 82. The effective load capacitor 90 is seen at output terminal 92, and the effective load capacitor 94 is seen at output terminal 96. Capacitor 98 is coupled between node 60 and power supply conductor 82.

[0005] The voltage regulator 52, supplying power to series inverters 80 and 84, struggles to handle large and transient demands for charge from its loads. The limited bandwidth of a typical regulator, along with the limited size of the on-chip decoupling capacitors, can prevent the regulator from maintaining a constant supply voltage under rapidly changing current demands, manifesting as variations in the regulated supply voltage, also known as ripple. Ripple in the power rails increases jitter in the output data signal at terminals 92 and 96 because it modulates the propagation delay of the CMOS logic circuitry. Low jitter is critical, especially at high data rates. For the high-speed serial data signal path 50 using CMOS logic circuitry, reducing ripple in the VREG is desirable to reduce jitter in the output signal.

[0006] For signal paths with considerable load capacitance, many stages, and / or operating at high data rates, the absolute supply current ISUP can be large, and therefore the absolute peak-to-peak variation in short-term supply current consumption can also be large. The voltage regulator 52 that generates VREG for power rail 60 can be located inside a CMOS IC, particularly when the IC contains multiple functions operating at various supply voltages, or in applications requiring dedicated power supplies for noise isolation. If the voltage regulator 52 does not respond immediately to changes in its load current, the regulated voltage VREG will deviate from its nominal value. Therefore, short-term variations in the data signal content can cause ripple on the supply voltage.

[0007] A characteristic of CMOS logic circuits is that their propagation delay varies with the supply voltage. Therefore, if the instantaneous value of the supply voltage changes according to the data content, the propagation delay of the CMOS signal path will continuously change, manifesting as timing jitter at the output terminals 92 and 96 of CMOS signal path 50. For systems processing high-speed serial data signals, jitter is critical to performance. Therefore, ripple on the supply voltage of CMOS signal path 50 is undesirable. Summary of the Invention

[0008] According to one aspect of the present invention, an integrated circuit is provided, comprising: a CMOS signal path coupled for receiving a data signal, wherein the CMOS signal path receives an operating potential from a power rail; and a compensation circuit coupled to the power rail for injecting a compensation current into the power rail each time the data signal is converted.

[0009] According to another aspect of the present invention, an integrated circuit is provided, comprising: a CMOS signal path coupled for receiving a data signal; and a compensation circuit coupled to a power rail of the CMOS signal path for injecting a compensation current into the power rail.

[0010] According to another aspect of the present invention, a method for manufacturing an integrated circuit is provided, comprising: providing a CMOS signal path coupled for receiving a data signal; and providing a compensation circuit for a power rail coupled to the CMOS signal path, for injecting a compensation current into the power rail. Attached Figure Description

[0011] Figure 1 This illustrates a typical CMOS signal path with a voltage regulator;

[0012] Figure 2 A CMOS signal path with a charge pump is shown, which provides compensating current to the power rail;

[0013] Figure 3 A CMOS signal path with an additional compensation circuit is shown, which provides compensation current to the power rail; and

[0014] Figure 4 A CMOS signal path with an additional compensation circuit is shown, which provides compensation current to the power rail. Detailed Implementation

[0015] In the following description, the invention is described in one or more embodiments with reference to the accompanying drawings, in which the same numerals denote the same or similar elements. Although the invention has been described in the best manner for carrying out its objectives, those skilled in the art will understand that this description is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims and the equivalents of the claims supported by the following disclosure and the accompanying drawings.

[0016] CMOS ICs, such as optical drivers, can process high-speed serial data. In terms of IC area and power consumption, an efficient and effective way to process serial data signals involves using CMOS logic circuit elements, such as inverters and logic gates. Serial data signals can propagate unmodified, for example, through chains of progressively larger buffers or inverters designed to amplify the data signal's drive strength and drive ultimately large capacitive loads, such as the output stage of an optical driver or line driver. Signal processing may also involve other operations such as gating, configurable polarity inversion, multiplexing between primary and secondary inputs, circuitry for adjusting or manipulating edge timing, data analysis or activity detection, and many other possible functions.

[0017] A CMOS signal path includes CMOS logic circuitry through which the primary high-speed serial data input is transmitted to one or more outputs or internal loads in the IC's normal operating mode. In one embodiment, the inputs of the signal path are typically in the form of differential pairs of complementary signals. In this case, the signal path may contain two substantially identical parallel paths, each transmitting half of the complementary pair. Differential paths improve the symmetry of the overall circuitry's response to the rising and falling edges of the input data signals.

[0018] Figure 2 A CMOS signal path 100 is shown that propagates high-speed (e.g., 10 Gb / s or higher) serial differential data via an IC. A voltage regulator 122 may be internal to the CMOS IC and includes an amplifier 124 that receives a reference voltage VREF at its non-inverting input. The output of amplifier 124 is coupled to the gate of transistor 126. The drain of transistor 126 is coupled to a power supply conductor 128 operating at a positive potential VDD, and the source of transistor 126 is coupled to node 130. The inverting input of amplifier 124 is coupled to node 130 to maintain a regulated output voltage VREG at node 130, which serves as the power rail for inverters 134 and 146, for example, 1-2 volts. The CMOS signal path 100 receives the input data signal DATAIN at terminal 132 and the complement of DATAIN at terminal 140. DATA IN propagates through a series-coupled inverter or buffer 134, which receives a positive operating potential from VREG and a ground operating potential from the power conductor or power rail 138. The complement of DATA IN propagates through a series-coupled inverter or buffer 146, which receives a positive operating potential from VREG and a ground operating potential from the power conductor 138. An effective load capacitor 137 is seen at output terminal 136, and an effective load capacitor 148 is seen at output terminal 144. A capacitor 149 is coupled between node 130 and power conductor 138.

[0019] CMOS signal path 100 exhibits a demand for rapidly changing current from the power rail (i.e., node 130). The operation of CMOS signal path 100 involves a charge burst from the power rail (i.e., node 130) when bit transitions of DATA IN and its complement DATA IN occur. For example, when an input changes the state from logic 0 to logic 1, a supply current I SUP is drawn from the power rail (i.e., node 130) to charge the capacitive load, especially when inverters 134 and 146 are driving a large capacitive load. If the transition is not instantaneous (which is often the case), a large shoot-through current also flows from the power rail (i.e., node 130) for the duration during which the NMOS and PMOS transistors of inverters 134 and 146 are simultaneously on. For larger chains of inverters and logic circuits, each intermediate node along the signal path also switches its state at each transition of the data input. The supply current I SUP demand of the signal path circuitry can be approximated as a packet of charge Q at each transition of the input data state. For symmetrical complementary signal paths, the charge Q drawn from the power supply is essentially the same in both directions of the input logic state transition. The charge Q drawn from the power rail (i.e., node 130) is the integral of the power supply current ISUP over time.

[0020] In practice, the duration of the current pulse will be related to the propagation delay of the signal path. For high data rates and signal paths containing multiple stages, the propagation delay may exceed the bit period, and the power supply current pulses due to consecutive data transitions may overlap. However, the total charge drawn from the power rail (i.e., node 130) through the signal path and, consequently, the average current, remains substantially proportional to the number of data transitions occurring within any reasonable time period. For typical serial data signals with a degree of randomness, short-term transition density can vary significantly. There are also time periods containing many transitions (e.g., 01010101), and other time periods containing multiple consecutive identical bit values ​​(CID) (e.g., 11111111) with few or no transitions. Therefore, the power supply current ISUP drawn by the CMOS signal path 100 can exhibit significant short-term variations.

[0021] For a CMOS signal path 100 with primary data inputs that the circuit must transmit, its power supply current requirement can be approximated as the charge packet drawn from node 130 at each transition of the input data value. The continuously changing data content causes short-term variations in the power supply current requirement, resulting in power supply voltage ripple due to the finite AC impedance of node 130.

[0022] The supply current ISUP provided by voltage regulator 122 is decoupled through energy storage capacitor 149. Voltage regulator 122 is a linear voltage regulator with a negative feedback loop that continuously monitors its output voltage and controls transfer transistor 126 to maintain the desired value VREG. The feedback loop has a limited bandwidth, and voltage regulator 122 cannot respond instantly to rapid changes in load current. The output of voltage regulator 122 is stabilized through a large decoupling capacitor or energy storage capacitor 149, which helps to smooth short-term changes in load current.

[0023] In the case of high-speed serial data signals, the nominal response time of voltage regulator 122 can be many times longer than the data bit period. Therefore, if the data content suddenly demands a significant increase in the supply current ISUP, the nominal response time of voltage regulator 122 may be many bit periods before the voltage regulator responds noticeably. Meanwhile, the supply current ISUP is primarily supplied by the energy storage capacitor 149. The reduction in charge stored on capacitor 149 causes a momentary drop in the supply voltage VREG. Conversely, if a long sequence of CIDs follows a period of frequent data transitions, voltage regulator 122 can continue to supply excess current for a short period. The energy storage capacitor 149 absorbs excessive current, causing VREG to exceed its nominal value.

[0024] A common solution to reduce power supply voltage ripple is to increase the value of the energy storage capacitor. Unfortunately, if located inside the IC, a larger energy storage capacitor can consume a larger area of ​​the chip. Ripple can also be reduced by increasing the bandwidth of the regulator feedback loop, but this typically increases power consumption. Either way, the original advantage of using CMOS logic circuitry to implement high-speed serial data signal paths is diminished.

[0025] As described herein, the proposed solution reduces the ripple on the power rail (i.e., node 130) by supplying a charge packet to the power rail (i.e., node 130) at each DATA IN transition, i.e., feedforward compensation. The introduced charge packet should be approximately equal to the charge Q consumed by the CMOS signal path 100. The feedforward compensation system for the varying load current on the power rail (i.e., node 130) works in conjunction with feedback compensation provided by the voltage regulator 122. The feedforward system is able to compensate for the varying supply current of the CMOS signal path 100 faster than the voltage regulator 122 alone because the feedforward system anticipates the arrival of load current spikes in response to DATA IN, whereas a conventional voltage regulator can only respond retrospectively. The magnitude of the charge supplied by the feedforward system roughly matches the charge drawn from the signal path. Any errors in the feedforward current are corrected by the voltage regulator 122. As long as the feedforward compensation is reasonably accurate, the net charge flowing into and out of the energy storage capacitor 149 and supplied by the voltage regulator 122 is significantly reduced. It also reduces voltage ripple on the power rail (i.e., node 130), thereby providing a corresponding improvement in the jitter performance of the CMOS signal path 100.

[0026] The precise timing and shape of the waveform supplied by the feedforward compensation circuit are also not critical, because the energy storage capacitor can easily provide or absorb any temporary under- or over-charge that occurs during the very short time it takes for data conversion to propagate through the signal path. Unlike systems with only conventional voltage regulators, this under- or over-charge will not accumulate over multiple bit cycles.

[0027] In one embodiment, to achieve feedforward compensation and provide a charge packet to compensate for changes in power supply current during high-speed operation and varying loads, charge pump circuit 150 injects a compensation current ICOMP into node 130 in response to a transition on DATA IN. Charge pump circuit 150 includes a first unit having switching circuits 156 and 160 and a capacitor 158. Terminal 156a of switching circuit 156 is coupled to a first terminal of capacitor 158. Terminal 156b of switching circuit 156 is coupled to a power supply conductor 152 operating at a positive potential VA. Terminal 156c of switching circuit 156 is coupled to node 130. Terminal 160a of switching circuit 160 is coupled to a second terminal of capacitor 158. Terminal 160b of switching circuit 160 is coupled to power supply conductor 138. Terminal 160c of switching circuit 160 is coupled to power supply conductor 152. The power supply VA for the charge pump may be provided by a separate voltage regulator (not shown). The ripple size on VA is less important than the ripple size on VREG, so VA can be generated by a simpler voltage regulator with a relatively small decoupling capacitor.

[0028] The charge pump circuit 150 also includes a second unit having switching circuits 164 and 170 and a capacitor 166. Terminal 164a of switching circuit 164 is coupled to a first terminal of capacitor 166. Terminal 164b of switching circuit 164 is coupled to power conductor 152. Terminal 164c of switching circuit 156 is coupled to node 130. Terminal 170a of switching circuit 170 is coupled to a second terminal of capacitor 166. Terminal 170b of switching circuit 170 is coupled to power conductor 138. Terminal 170c of switching circuit 170 is coupled to power conductor 152. The power supply VA for the charge pump can be provided by a separate voltage regulator (not shown).

[0029] Charge pump 150 delivers a defined amount of charge to the power rail (i.e., node 130) at each transition of DATA IN and its complement. When DATA IN is logic 1, terminal 156a is connected to terminal 156b, and terminal 160a is connected to terminal 160b. Capacitor 158 (C 158) is charged through VA to Q = C 158. VA. In the opposite phase, when DATA IN is logic 0, terminal 156a is connected to terminal 156c, and terminal 160a is connected to terminal 160c. Capacitor 158 is coupled between VA and node 130. The voltage across capacitor 158 becomes (V REG - VA), providing ΔQ = C158 to node 130. (2VA - VREG) is used as the current pulse ICOM. In one embodiment, VA = VREG and ΔQ = C158 VA. The first charge pump unit and the second charge pump unit are locked in opposite phases of DATA IN and are added together to generate pulses of current I COMP at the rising and falling edges of the data signal.

[0030] The values ​​of capacitors 158 and 166, as well as VA, are chosen such that the compensation for the packet of charge ΔQ delivered by charge pump 150 is approximately equal to the charge consumed by the CMOS signal path 100 from the power rail (i.e., node 130) during each data transition. This reduces the net charge flowing into and out of energy storage capacitor 149, and the voltage regulator 122 requires a relatively small current to overcome any mismatch between the average values ​​of ISUP and ICOMP. The value of energy storage capacitor 149 is significantly larger than the values ​​of capacitors 158 and 166, thus ensuring minimal interference to VREG caused by any temporary mismatch between the charge consumed by the CMOS signal path 100 and the charge delivered by charge pump 150. Feedforward compensation with charge pump 150 significantly reduces power supply ripple and jitter in the CMOS signal path 100 without requiring a large area increase in energy storage capacitor 149.

[0031] Figure 2 The simplified conceptual voltage regulator 122 depicted can only supply current to its load and cannot sink current, thus it can correct for a mismatch in polarity between ISUP and ICOMP. Therefore, capacitors 158 and 166 can be selected so that ICOMP is always on average less than ISUP. Alternatively, a constant current sink can be applied to the output of the voltage regulator 122. In another embodiment, the voltage regulator 122 uses a push-pull output stage, which is also capable of supplying or sinking output current and correcting for mismatches in ICOMP and ISUP of either polarity.

[0032] Figure 3 Another implementation of feedforward compensation is shown. For example... Figure 2 The CMOS signal path 100 is provided. Components with the same reference numerals perform similar functions. DATA IN and its complement are coupled to the input of level shifter 190. The output of level shifter 190 is coupled to the inputs of series inverters or buffers 192 and 194 as part of compensation circuit 195. Compensation circuit 195 is effectively stacked on the CMOS signal path 100 such that current from the negative power supply of compensation circuit 195 flows directly into the positive power supply of CMOS signal path 100. Level shifter 190 converts the logic levels of DATA IN and its complement into switching between VB and VREG of series inverters 192 and 194. For example, if inverters 134 and 146 operate at 0 volts for logic 0 and 1 volt for logic 1, then level shifter 190 causes inverters 192 and 194 to operate at 1 volt for logic 0 and 2 volts for logic 1. Inverters 192 and 194 operate at approximately equal to 2 volts. The power conductor 196 under VB of V REG receives the operating potential. The series inverters 192 and 194 contain sufficient logic stages and sufficient load capacitance to match their power current requirements with those of the CMOS signal path 100.

[0033] The compensation circuit 195 is effectively a copy of the CMOS signal path 100 because it mimics the dynamic power supply current consumption of the CMOS signal path 100 and provides a charge packet to node 130 at each DATA IN and its complement transition. The amount of charge consumed by the compensation circuit 195 at each data transition is substantially the same as that of the CMOS signal path 100. The charge is initially drawn from the VB rail and rectified to the power rail (i.e., node 130) to compensate for the same amount of charge drawn by the CMOS signal path 100. The net load current on the voltage regulator 122 and the ripple size on VREG are both significantly reduced.

[0034] One advantage of the compensation circuit 195 is that it uses logic elements similar to those of the CMOS signal path 100. The dependence of the supply current on temperature and other variables tends to mirror the dependence of the CMOS signal path 100 on temperature and other variables. This improves compensation accuracy over variations in operating conditions and manufacturing processes. By adjusting the relative load capacitance and transistor size in the logic elements of the compensation circuit 195, the tracking accuracy can be optimized to control the relative contribution of the capacitive charge pump effect and the CMOS logic pass-through current to the total compensation current.

[0035] Figure 4 Another implementation of feedforward compensation is shown. For example... Figure 2 The CMOS signal path 100 is provided. Components with the same reference numerals perform similar functions. Voltage regulator 212 includes amplifier 214, which receives a reference voltage VREF at its non-inverting input. The output of amplifier 214 is coupled to the gate of transistor 216. The source of transistor 216 is coupled to the inverting input of amplifier 214 at node 218. The drain of transistor 216 is coupled to PMOS transistors 220 and 226, which are arranged as a 1:n current mirror. The drain of transistor 226 is coupled to node 130 to provide a compensation current ICOM to node 130, which serves as the power rail for inverters 134 and 146, for example, 1-2 volts.

[0036] DATA IN is coupled to the input of series inverter or buffer 236, and the complement of DATA IN is coupled to the input of series inverter or buffer 240 as part of compensation circuit 230. Inverters 236 and 240 receive operating potential from node 218. Compensation circuit 230 may include load capacitors 238 and 242 at the outputs of series inverters 236 and 240. Series inverters 236 and 240, each with its own load capacitor, represent a scaled-down copy of CMOS signal path 100 in terms of their dynamic supply current, and the sizes of series inverters 236 and 240 are adjusted so that their supply current requirement (ICOMP / n) is 1 / n of the supply current requirement of CMOS signal path 100.

[0037] Compensation circuit 230 uses a separate voltage regulator 212. It senses the supply current ICOMP / n of the scaled replica signal path and rescales it at a 1:n ratio via current mirrors 220-226 to generate ICOMP to node 130. Compensation circuit 230 simulates the dynamic supply current consumption of the CMOS signal path 100 and provides a charge packet to node 130 at each transition of DATA IN and its complement. The net load current on voltage regulator 122 and the ripple size on VREG are significantly reduced.

[0038] In short, it has already Figure 2-4 Various embodiments illustrate a compensation circuit to generate ICOM to match the transient behavior of ISUP and reduce interference and ripple on the regulated power supply VREG. This compensation reduces jitter on the output of the CMOS signal path 100 and maintains a constant, stable, isolated, and dedicated power supply voltage for the series inverters 134 and 146.

[0039] While one or more embodiments of the invention have been shown in detail, those skilled in the art will understand that modifications and adaptations can be made to those embodiments without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device, comprising: A CMOS signal path, the CMOS signal path including an input terminal coupled to receive data signals from a data terminal; as well as A replica CMOS signal path includes an input coupled to receive the data signal, wherein the output of the replica CMOS signal path, in response to the data signal, provides a feedforward compensation current to a first power rail of the CMOS signal path at each transition of the data signal, as the dynamic power supply current of the CMOS signal path is consumed, and a charge packet provides the feedforward compensation current equal to and opposite to the expected change in the power supply current of the CMOS signal path at each transition of the data signal, such that the replica CMOS signal path consumes substantially the same amount of charge as the CMOS signal path.

2. The semiconductor device of claim 1, further comprising a voltage regulator coupled to the power rail of the CMOS signal path to provide a balance of power supply current, the balance including any mismatch between the power supply current of the CMOS signal path and the feedforward compensation current.

3. The semiconductor device according to claim 1, wherein, The CMOS signal path and the replica CMOS signal path each include multiple series-coupled buffers or inverters.

4. The semiconductor device of claim 1, further comprising a level shifter coupled between the data terminal and the input terminal of the replica CMOS signal path.

5. A semiconductor device, comprising: A CMOS signal path, the CMOS signal path including an input terminal coupled for receiving data signals from a data terminal; as well as A compensation circuit having an output terminal coupled to a power rail of the CMOS signal path and, in response to the data signal, injecting a feedforward compensation current into the power rail at each transition of the data signal, wherein a charge packet provides the feedforward compensation current equal to and opposite to the expected change in the power supply current of the CMOS signal path at each transition of the data signal, such that the compensation circuit consumes substantially the same amount of charge as the CMOS signal path.

6. The semiconductor device of claim 5, further comprising a voltage regulator coupled to the power rail of the CMOS signal path to provide a balance of power supply current, the balance including any mismatch between the power supply current of the CMOS signal path and the feedforward compensation current.

7. The semiconductor device according to claim 5, wherein, The compensation circuit includes a replica CMOS signal path, which includes a plurality of series-coupled buffers or inverters having inputs coupled to receive the data signal and outputs that provide the feedforward compensation current to the power rail of the CMOS signal path at each conversion of the data signal.

8. The semiconductor device of claim 7, further comprising a level shifter coupled between the data terminal and the input terminal of the replica CMOS signal path.

9. The semiconductor device according to claim 5, wherein, The compensation circuit includes: A replica CMOS signal path, the replica CMOS signal path including an input coupled for receiving the data signal; A first voltage regulator, the first voltage regulator including an output terminal coupled to a power rail of the replicated CMOS signal path, wherein the first voltage regulator includes a transistor having a first conductive terminal coupled to the output terminal of the first voltage regulator; and The current mirror includes an input terminal coupled to a second conductive terminal of the transistor and an output terminal that injects the feedforward compensation current into the power rail of the CMOS signal path at each conversion of the data signal.

10. A method for manufacturing an integrated circuit, comprising: A CMOS signal path is provided, the CMOS signal path including an input coupled for receiving data signals from a data terminal; as well as A compensation circuit is provided, the compensation circuit having an output terminal coupled to a power rail of the CMOS signal path, and responsive to the data signal, for injecting a feedforward compensation current into the power rail at each transition of the data signal, wherein the charge packet provides the feedforward compensation current in response to each transition of the data signal, which is equal to and opposite to the expected change in the power supply current of the CMOS signal path, such that the compensation circuit consumes substantially the same amount of charge as the CMOS signal path.

11. The method of claim 10, further comprising providing a voltage regulator coupled to the power rail of the CMOS signal path to provide a balance of power supply current, the balance including any mismatch between the power supply current of the CMOS signal path and the feedforward compensation current.

12. The method according to claim 10, wherein, The compensation circuit includes providing a replica CMOS signal path, the replica CMOS signal path including an input coupled to receive the data signal and an output that provides the feedforward compensation current to the power rail of the CMOS signal path at each conversion of the data signal.

13. The method according to claim 12, wherein, Providing the replica CMOS signal path includes providing multiple series-coupled buffers or inverters.

14. The method of claim 12, further comprising providing a level shifter coupled between the data terminal and the input terminal of the replica CMOS signal path.

15. The method according to claim 10, wherein, The compensation circuit includes: A replica CMOS signal path is provided, the replica CMOS signal path including an input coupled for receiving the data signal; A first voltage regulator is provided, the first voltage regulator including an output terminal coupled to a power rail of the replicated CMOS signal path, wherein the first voltage regulator includes a transistor having a first conductive terminal coupled to the output terminal of the first voltage regulator; and A current mirror is provided, the current mirror including an input terminal coupled to a second conductive terminal of the transistor and an output terminal that injects the feedforward compensation current into the power rail of the CMOS signal path at each conversion of the data signal.

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