MiPi rffe address allocation method and miPi rffe device

Abstract

Various embodiments of the present disclosure disclose MIPI RFFE address allocation methods and MIPI RFFE devices. The method includes detecting a voltage at a configuration terminal of the MIPI RFFE device using a timing based on a MIPI RFFE signal received by the MIPI RFFE device, and setting an address of the MIPI RFFE device based on the detected voltage.

Description

Technical Field

[0001] This application relates to a method for MIPI RFFE address allocation and a corresponding MIPI RFFE device. Background Technology

[0002] The MIPI (Mobile Industrial Processor Interface) RFFE (Radio Frequency Front-End Control Interface) is a standardized interface widely used for controlling radio frequency front-end systems, including mobile phones. A MIPI RFFE system can include up to 15 slave devices and up to 4 master devices coupled to a bus instance, including power amplifiers, low-noise amplifiers, filters, and switches. Each component coupled to the bus instance requires a unique address, called a USID, for communication via the bus instance.

[0003] The USID can be set by the manufacturer of a radio frequency device. However, this can cause problems if two devices deployed on a single bus instance are configured with the same USID, for example, when two different devices of the same type with the same USID are used, or if two different devices happen to have the same USID.

[0004] One way to solve this problem is to use multiple address pins to set the address, a separate fuse chip to set a specific address, or to manufacture the same device with different addresses. All of these methods increase the device cost, which is undesirable. Summary of the Invention

[0005] The apparatus as defined in claim 1 and the method as defined in claim 14 are provided. The dependent claims define further embodiments.

[0006] According to one embodiment, a method for address allocation for a MIPI RFFE device is provided, the method comprising:

[0007] By utilizing the timing of the MIPI signal received by the MIPI RFFE device, the voltage at the configuration terminal of the MIPI RFFE device is detected, and...

[0008] Set the address of the MIPI RFFE device based on the detected voltage.

[0009] According to another embodiment, a MIPI RFFE device including a sensing circuit device is provided, the sensing circuit device being configured as follows:

[0010] By utilizing the timing of the MIPI RFFE signal received by the MIPI RFFE device, the voltage at the configuration terminal of the MIPI device is determined.

[0011] Set the address of the MIPI RFFE device based on the detected voltage.

[0012] The above description of the invention is merely a brief overview of some embodiments and should not be construed as limiting. Attached Figure Description

[0013] Figure 1 This is a block diagram of a device according to one embodiment.

[0014] Figure 2 This is a flowchart illustrating a method according to some embodiments.

[0015] Figure 3 This is a schematic diagram illustrating the format of an example MIPI RFFE signal.

[0016] Figure 4 This diagram illustrates the signals of the MIPI RFFE system during startup.

[0017] Figures 5 to 7 It is a diagram illustrating the sensing timing according to various embodiments.

[0018] Figure 8 This is a circuit diagram of a MIPI RFFE device according to one embodiment. Detailed Implementation

[0019] In the following, various embodiments will be described in detail with reference to the accompanying drawings. These embodiments are given by way of example only and should not be construed as limiting. For example, while an embodiment may be described as including multiple features (e.g., components, elements, actions, events, steps, etc.), in other embodiments, some of these features may be omitted and / or replaced by alternative features. Additional features may be provided in addition to those explicitly shown and described. For example, the embodiments discussed herein relate to address allocation for a MIPI RFFE device. Besides the described address allocation, the MIPI RFFE device may be implemented in a conventional manner, for example, for communication after address allocation and for performing various functions typically performed using MIPI devices, such as power amplifiers, low-noise amplifiers, antenna tuners, filters, switches, or any other radio frequency devices in the case of a MIPI RFFE device.

[0020] Features from different embodiments can be combined to form other embodiments. Unless otherwise stated, variations or modifications described in one embodiment can also be applied to other embodiments.

[0021] Unless otherwise stated, the connections or couplings described herein refer to electrical connections or couplings. Such connections or couplings may be modified, for example, by adding or removing components, provided that the general function of the connection or coupling (e.g., providing some information, transmitting voltage and / or current, etc.) remains substantially unchanged.

[0022] Figure 1 This is a block diagram illustrating a MIPI device 10 according to one embodiment. Components of the MIPI device 10 may be integrated on a single chip, or may be provided, for example, in different chips included in the same package.

[0023] The MIPI device 10 includes a first terminal 13A configured to receive a supply voltage VIO, a fifth terminal 13E configured to receive VSS (or ground) (VIO is the supply voltage relative to VSS), a second terminal 13B configured to receive a MIPI RFFE clock signal SCLK, and a third terminal 13C configured to receive a MIPI RFFE data signal SDATA. Signals SDATA and SCLK are examples of MIPI RFFE signals used herein.

[0024] The supply voltage VIO powers the components of device 10. Clock signal SCLK and data signal SDATA are used for MIPI data communication with the MIPI core 11 of device 10. MIPI core 11 can receive and transmit data signals via terminal 13C, for example, receiving commands timed by clock signal SCLK and performing any function using device 10, such as the functions described above, such as amplifier functions, tuning functions, switching functions, etc. This can be implemented in any conventional manner. Although MIPI core 11 is coupled to three terminals 13A-13C, more terminals can be provided in device 10 depending on the function, such as terminals to be coupled to an antenna for tuning, terminals coupled to the internal switches of MIPI core 11, terminals for receiving signals and outputting amplified signals, etc.

[0025] Furthermore, device 10 includes a fourth terminal 13D, which is used for address configuration during MIPI RFFE device 10 startup. In this embodiment, a voltage VSENSE is applied to the fourth terminal 13D and detected by sensing circuitry 12 to determine the device 10 address (USID) to be used. In this embodiment, as explained in more detail below, VSENSE can take more than two different levels, for example, four different levels, to allow four different addresses to be set via a single terminal (i.e., the fourth terminal 13D).

[0026] The external parasitic capacitance Cpar and internal parasitic capacitance Cpad associated with terminal 13D may affect the degree to which VSENSE reaches a sufficiently stable state at sensing circuit device 12 to allow reliable sensing. The time until VSENSE is sufficiently stable may also be related to the rate at which the supply voltage VIO rises during startup. On the other hand, during startup, according to the MIPI RFFE standard, device 10 should be able to receive the MIPI RFFE signal 120 ns after the supply voltage VIO has reached a predefined threshold at startup, necessitating rapid address setting of device 10. The embodiments described below allow for reliable detection and measurement of VSENSE during device startup.

[0027] In this embodiment, the timing for detecting the voltage VSENSE is based on MIPI RFFE signals, such as the first MIPI RFFE signal received at terminal 13C after startup and / or the clock signal SCLK received at terminal SCLK. For this timing, MIPI core 11 can provide information about the MIPI RFFE signals (at terminals 13B and / or 13C) to the sensing circuitry 12, allowing the sensing circuitry 12 to sense based on its timing.

[0028] For example, the start or end of the sensing period for detecting VSENSE can be based on the MIPI RFFE signal. The "start of the sensing period" can refer to the point in time when the internal node of the sensing circuit device 12 is charged to the threshold voltage for detecting VSENSE, and the internal sensing node is charged to VSENSE. For example, in the case where the voltage at the internal sensing node is compared with the threshold voltage, and the address to be set is determined based on this comparison, the end of the sensing period can refer to the point in time when the actual detection occurs. Various examples of this timing based on the MIPI RFFE signal received by the MIPI RFFE device 10 or other devices according to embodiments will be further discussed below.

[0029] Figure 2 This is a flowchart of a method for address allocation to a MIPI RFFE device according to one embodiment. The method can be implemented, for example, in the device of FIG10, but can also be implemented independently of the device of FIG10. To avoid repetition, reference will be made to the above... Figure 1 To describe Figure 2 The method.

[0030] At point 20, the method includes detecting the voltage at the configuration terminal using sensing timing based on the received MIPI RFFE signal, such as... Figure 1 VSENSE at terminal 13D.

[0031] At point 21, the method includes, based on the detected voltage, such as the voltage level based on VSENSE, targeting... Figure 1 Device 10 is similar to a MIPI RFFE device in that it sets the address. For example, at 21, an address can be selected from a group of more than two addresses (e.g., four addresses) based on the detected VSENSE.

[0032] Next, we will refer to Figures 3 to 7 This describes the detection of VSENSE based on the sensing timing of the MIPI RFFE signal according to various embodiments. Figure 3 It is an example MIPI RFFE signal that can be received by, for example, device 10 at the third terminal 13C. Figure 3 Each box in the table can represent one bit of data. The first bit is marked SSC, can be sent on the bus data line and received at I3C, and indicates that the command will be sent as SDATA along with the clock signal SCLK. After this pause, the address bit SA follows. <3> to SA <0> It consists of a code bit, seven data bits, and a parity bit.

[0033] Figure 4 The diagram illustrates the signals of the MIPI RFFE device during startup. Curve 40 illustrates the supply voltage VIO. During startup, the voltage VIO rises until it reaches a predefined minimum threshold VIOmin at the time point indicated by line 43. At a time point at least 120 ns later, as shown by vertical line 42, the MIPI RFFE signal can begin according to curve 41, where curve 41 illustrates the alternating 0 and 1 values ​​of the MIPI RFFE clock signal SCLK, which can be correlated with... Figure 3 The data signals shown are transmitted simultaneously. In other words, at the time point indicated by line 42, the first bit of the MIPI RFFE data signal (as shown) is transmitted simultaneously. Figure 3 (As shown) SSC may occur.

[0034] Now refer to Figures 5 to 7 To explain the sensing timing based on the MIPI RFFE signal including SCLK, as shown in curve 41, according to different embodiments. Figures 5 to 7 The elements shown (already referenced) Figure 4 (The ones explained) have the same reference numerals as those in the accompanying drawings and will not be described again. Except... Figure 4 Outside of curves 40 and 41, Figures 5 to 7 Each of them will be like Figure 1 The voltage VSENSE at the configuration terminal of the fourth terminal 13D is illustrated by curve 52. It can be seen that VSENSE rises at startup and then remains at a substantially constant value over time, which is related to the voltage externally applied to terminal 13D. (See later...) Figure 8Explain an example of such a voltage. The time it takes for the voltage VSENSE to reach a basically stable level depends, among other things, on the capacitance coupled to the terminals (e.g., ...). Figure 1 The implementation of Cpar and Cpad may also be related to other factors, such as the rate at which the supply voltage VIO rises.

[0035] Figure 5 The illustration shows a first sensing timing sequence available in an embodiment. Figure 5 In this context, the sensing period for detecting the voltage VSENSE begins at the start of the MIPI RFFE signal, for example... Figure 3 The SSC bit, in Figure 5 The example corresponds to the time marked by line 42. The sensing period ends at a predefined clock of the MIPI RFFE clock signal SCLK. In other words, the sensing period ends at the nth clock of the MIPI RFFE clock signal. n can be chosen based on the implementation. For example, in some MIPI RFFE implementations, the device to be addressed (e.g., device 10) must be assigned its address after the first MIPI RFFE signal, such that if it is commanded to be addressed (e.g., if bit SA...). <3> to SA <0> (Addressing the corresponding device), it can execute command transmission. In some implementations, the shortest MIPI RFFE signal can include 12 clock signal segments. In this case, n is chosen to be less than 12, for example, n=8, to ensure that address allocation is completed when needed. Figure 5 In this context, vertical line 51 indicates that the sensing period begins at the time indicated by line 42, which corresponds to the start of the MIPI RFFE signal, and ends at the nth clock cycle indicated by vertical line 51. It can be seen that at the time indicated by vertical line 51, VSENSE according to curve 42 has approximately reached its stable value, which allows for reliable sensing.

[0036] Therefore, in Figure 5 In one embodiment, the sensing period begins with a characteristic of the MIPI RFFE signal (in this case, the first SSC or the first clock of the MIPI RFFE data signal) and ends with a characteristic of the MIPI RFFE data signal (in this case, the nth clock of the MIPI RFFE clock signal). Instead of starting with an SSC bit, in other embodiments, the sensing period may also begin with a different characteristic (e.g., the second clock of the MIPI RFFE clock signal).

[0037] The second sensing timing that can be used in the embodiments is Figure 6 As shown in the image. Figure 5In this example, the sensing period begins at the start of the MIPI RFFE signal, corresponding to vertical line 42. After the start, as shown by vertical line 60, sensing stops after a predefined delay indicated by arrow 61. Also in this case, VIO is almost stable and VSENSE almost reaches its stable value. In the example above, the predefined delay indicated by arrow 61 is chosen to be less than 12 clock cycles, such that in this case, the address is also allocated before the MIPI RFFE command ends.

[0038] exist Figure 6 In the middle, the sensing period is characterized by the MIPI RFFE signal (in Figure 6 In the example, it starts at the beginning and ends at a predefined time after that feature. Similarly, here, instead of the SSC bit, another feature, such as a second clock, can be used.

[0039] In some embodiments, the third sensing timing may be as follows: Figure 7 As shown in the diagram. Here, as indicated by vertical line 70, the start of the sensing period can be some point during the rise of VIO, such as when VIO reaches a certain threshold. In some embodiments, the start may coincide with VIO reaching a certain threshold. min (That is, vertical line 43) coincides. In other words, in this case, the start of sensing is unrelated to the MIPI RFFE signal. Figure 5 In the case of and Figure 7 China also utilizes, such as Figure 5 The vertical line 51 shown indicates the end of the sensing period, which occurs at the nth clock cycle of the MIPIRFFE signal. The end of the sensing period ensures that VSENSE has approached a stable value.

[0040] exist Figure 7 In this example, the sensing time begins according to the slope but ends with the characteristics of the MIPI RFFE signal, which is the nth clock.

[0041] In the implementation method, the above discussion is based on Figures 5 to 7 The sensing timing of the MIPI RFFE signal ensures that the voltage VSENSE to be sensed for address allocation is essentially stable, and VIO has also reached a substantially stable value. In the implementation, sensing begins at a certain point during the rise of VIO (similar to...). Figure 7 Compared to the method of ending with a predefined delay after line 70, this allows for more reliable sensing because the start and end of sensing are both related to the slope of VIO and the rate at which the voltage VIO rises. The stable values ​​of VSENSE and VIO may not be reached during sensing, which could lead to inaccurate sensing.

[0042] Figure 8This is a circuit diagram illustrating a sensing circuit device for address allocation according to one embodiment and its application with different voltage VSENSE. The sensing circuit device can be used, for example, as... Figure 1 The sensing circuit device 12.

[0043] Figure 8 Line 82 separates the off-chip circuitry 83 for applying voltage VSENSE from the on-chip circuitry 84, which includes sensing circuitry devices that may be included in... Figure 1 Among the devices 10 similar to those in the equipment category.

[0044] Figure 8 The implementation supports four different address settings. To achieve this, it can be used with... Figure 1 The configuration node 811 corresponding to the fourth terminal 13D can be directly coupled to the supply voltage VIO to set a first address, can be connected to VIO via a resistor RE to set a second address, can be floated to set a third address, or can be coupled to ground VSS to set a fourth address. In other embodiments, more than four or fewer different couplings of the configuration node 811 can be used to generate the voltage VSENSE to be sensed. In yet another embodiment, the voltage used to set the address can be directly applied to the configuration node 811 from a voltage source independent of VIO and VSS.

[0045] Figure 8 The on-chip portion includes ESD protection circuitry 81, which protects the chip from electrostatic discharge (ESD) events at configuration node 811. Any conventional ESD protection circuitry, such as diodes or other circuit elements, can be used, which conduct when there is a voltage at configuration node 811, thereby shunting the voltage to ground VSS or the positive supply voltage VIO (depending on the sign of the voltage). Such a high voltage could be due to an ESD event, for example.

[0046] For example, due to the capacitance of diodes or other components used in the ESD protection circuit, the ESD protection circuit 81 may also contribute to the capacitance Cpad.

[0047] Aside from potentially providing parasitic capacitance, the ESD protection circuit 81 substantially does not affect the behavior of the illustrated device during normal operation, i.e., outside of ESD or other high-voltage components.

[0048] exist Figure 8 In the device, when turned on, once VIO is high enough (e.g., once VIO reaches...), Figure 4 The value VIO shown minTransistors 85A and 85B are then turned on to conduct between the corresponding source and drain terminals (in the case of a field-effect transistor) or collector and emitter terminals (in the case of a bipolar transistor or an insulated-gate bipolar transistor). This connects the internal sensing node 85 to VIO via resistor 86A and to VSS via resistor 86B. Thus, the internal sensing node 87 is charged using the voltage VSENSE. In other embodiments, the voltage to be sensed can be applied directly to the internal sensing node 87. Resistors 86A and 86B are selected to allow charging fast enough that VSENSE stabilizes substantially at the internal sensing node 87 at the end of the sensing period. The values ​​are related to the allowed or expected parasitic capacitance Cpar. The higher the Cpar, the greater the current required through resistors 86A and 86B, therefore smaller values ​​for resistors 86A and 86B must be chosen. Example values ​​are Cpar less than 5 pF and current less than 10 μA, but this is implementation-dependent.

[0049] At this time, transistors 88A and 88B are still turned off.

[0050] As the sensing period begins (e.g., as Figure 5 and Figure 6 The SSD bit shown in line 42 is either Figure 7 At the time point indicated by the slope of line 70 in the diagram, transistors 88A and 88B are turned on. This generates threshold voltages VTHU, VTHM, and VTHL through a resistive voltage divider formed by resistors 89A, 89B, 89C, and 89D. These threshold voltages are selected such that they fall between four different possible input voltages (VIO, VSS, floating, or VIO via resistor RE) at configuration node 811 as described above. In the case of a sensing period starting from the SSD bit, the SSD bit can trigger counter 813, which then outputs the signal TH_EN, causing transistors 88A and 88B to turn on. Figure 7 In this case, instead of the signal SSD, the counter can be started by VIO exceeding a predefined threshold.

[0051] The voltage at the internal sensing node 87 is provided to the first inputs of comparators 810A, 810B, and 810C. The second inputs of comparators 810A, 810B, and 810C are respectively provided with threshold voltages VTHU, VTHM, and VTHL. At the end of the sensing period (e.g., at...) Figure 5 and Figure 7In the case of clock n (or after a predefined delay of 61), comparators 810A, 810B, and 810C are enabled to perform a comparison between the voltage at the internal sensing node 87 and the corresponding threshold voltages VTHU, VTHM, and VTHL, and output the result to the decoding / latch circuit 812. When using clock n, counter 810 starts counting from SSD (or VIO exceeding the threshold) based on SCKL and, after reaching clock n, outputs a comparator enable signal to COMP_EN to enable comparators 810A, 810B, and 810C. Figure 6 In the case of the simulated delay shown, the counter can be replaced by an simulated delay circuit triggered by the SSD or another feature of the MIPI RFFE signal.

[0052] The decoding / latch circuit 812 receives the outputs from comparators 810A, 810B, and 810C and outputs an ID value, in this case a 2-bit value, indicating one of four addresses to be used. A first value of ID is output when the voltage at the internal sensing node 87 exceeds VTHU; a second value is output if the voltage is between VTHU and VTHM (e.g., corresponding to VIO applied via RE); a third value is output when the voltage at the internal sensing node 87 is between VTHM and VTHL (e.g., configuration node 811 is floating); and a fourth value is output when the voltage is below VTHL (e.g., corresponding to configuration node 811 coupled to VSS). In this embodiment, the value is latched, i.e., it remains output regardless of any changes at configuration node 811. Based on the signal ID, in this case, one of the four predefined addresses is used. Figure 1 The MIPI RFFE device 10. After the address determination process, the sensing circuitry is turned off, for example, transistors 85A, 85B, 88A, and 88B, and comparators 810A, 810B, and 810C are turned off. Therefore, in this embodiment, after the address is set, the sensing circuitry does not contribute to the device's current consumption, except for a possible small leakage current.

[0053] Figure 8 The configuration with three parallel comparators is merely an example configuration, and any configuration capable of sensing VSENSE at the internal sensing node 87 can be used, such as an interleaved comparator configuration, a multi-stage comparator, etc. Therefore, Figure 8 The specific circuit shown should not be interpreted as limiting in any way.

[0054] Some embodiments are defined by the following examples:

[0055] Example 1. A method for address allocation in a MIPI RFFE device, comprising:

[0056] By utilizing the timing of the MIPI RFFE signal received by the MIPI RFFE device, the voltage at the configuration terminal of the MIPI RFFE device is detected, and...

[0057] The address of the MIPI RFFE device is set based on the detected voltage.

[0058] Example 2. The method according to Example 1, wherein the timing detection of the voltage based on the MIPI RFFE signal includes starting a sensing period for detecting the voltage based on features of the MIPI RFFE signal.

[0059] Example 3. The method according to Example 2, wherein the feature is the SSC bit of the MIPI RFFE signal.

[0060] Example 4. The method according to Example 2 or 3, wherein the sensing period ends based on another characteristic of the MIPI RFFE signal.

[0061] Example 5. The method according to Example 4, wherein the other feature is the nth clock of the MIPI RFFE clock signal.

[0062] Example 6. The method described in Example 5, where n is less than the minimum length of the MIPI RFFE signal.

[0063] Example 7. The method according to Example 3 or 4, wherein the sensing period ends at a predefined time after the feature.

[0064] Example 8. The method according to Example 1 or 2, wherein the timing detection of the voltage based on the MIPI RFFE signal includes detecting the voltage during a sensing period, wherein the sensing period ends at a characteristic of the MIPI RFFE signal.

[0065] Example 9. The method according to Example 8, wherein the feature is the nth clock cycle of the MIPI RFFE signal.

[0066] Example 10. The method described in Example 9, where n is less than the minimum length of the MIPI RFFE signal.

[0067] Example 11. The method according to any one of Examples 8 to 10, wherein the start of the sensing period is based on the rise of the supply voltage when the MIPI RFFE device is started.

[0068] Example 12. The method according to any one of Examples 2 to 11, wherein the method includes activating a comparator threshold at the beginning of the sensing period and enabling a comparator arrangement configured to compare the voltage with the comparator threshold at the end of the sensing period, wherein setting the address based on the detected voltage includes setting the address based on one or more outputs of the comparator arrangement.

[0069] Example 13. The method according to any one of Examples 1 to 12, wherein the MIPI RFFE signal is the first MIPI RFFE signal after the MIPI RFFE device is started.

[0070] Example 14. A MIPI RFFE device including a sensing circuit, the sensing circuit being configured to:

[0071] By utilizing the timing of the MIPI RFFE signal received by the MIPI RFFE device, the voltage at the configuration terminal of the MIPI RFFE device is detected, and...

[0072] The address of the MIPI RFFE device is set based on the detected voltage.

[0073] Example 15. The device according to Example 14, wherein the device is configured to perform the method according to any one of Examples 1 to 13.

[0074] Example 16. The device according to Example 14 or 15, wherein the sensing circuitry is configured to initiate a sensing period for detecting the voltage based on the characteristics of the MIPI RFFE, in order to detect the voltage using timing based on the MIPI RFFE signal.

[0075] Example 17. The device according to Example 16, wherein the feature is the SSC bit of the MIPI RFFE signal.

[0076] Example 18. The device according to Example 16 or 17, wherein the sensing circuitry is configured to terminate the sensing period based on another characteristic of the MIPI RFFE signal.

[0077] Example 19. The device according to Example 18, wherein the other feature is the nth clock of the MIPI RFFE clock signal.

[0078] Example 20. The device according to Example 19, where n is less than the minimum length of the MIPI RFFE signal.

[0079] Example 21. The device according to Example 16 or 17, wherein the sensing circuitry is configured to end the sensing period at a predefined time following the feature.

[0080] Example 22. The device according to any one of Examples 14 to 16, wherein the sensing circuitry is configured to detect the voltage during a sensing period using timing based on the MIPI RFFE signal, wherein the sensing period ends at a characteristic of the MIPI RFFE signal.

[0081] Example 23. The device according to Example 22, wherein the feature is the nth clock cycle of the MIPI RFFE signal.

[0082] Example 24. The device according to Example 23, where n is less than the minimum length of the MIPI RFFE signal.

[0083] Example 25. The device according to any one of Examples 22 to 24, wherein the sensing circuitry is configured to initiate the sensing period based on a rise in the supply voltage when the MIPI RFFE device is started.

[0084] Example 26. The device according to any one of Examples 16 to 25, wherein the sensing circuit means includes a comparator arrangement configured to compare the voltage with a plurality of comparator thresholds, wherein the sensing circuit means is configured to activate the comparator thresholds at the beginning of the sensing period, enable the comparator arrangement at the end of the sensing period, and set the address based on one or more outputs of the comparator arrangement.

[0085] Example 27. The device according to any one of Examples 14 to 26, wherein the MIPI RFFE signal is the first MIPI RFFE signal after the MIPI RFFE device is started.

[0086] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that various alternative and / or equivalent implementations can be used instead of the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any modifications or variations of the specific embodiments discussed herein. Therefore, the invention is intended to be limited only by the claims and their equivalents.

Claims

1. A method for address allocation for a MIPI RFFE device (10), comprising: Using the timing of the MIPI RFFE signals (SDATA, SCLK) received by the MIPI RFFE device (10), the voltage (VSENSE) at the configuration terminals (13D, 811) of the MIPI RFFE device (10) is detected, and Based on the detected voltage (VSENSE), the address of the MIPI RFFE device (10) is set. The timing detection of the voltage (VSENSE) based on the MIPI RFFE signal (SDATA, SCLK) includes: detecting the voltage (VSENSE) during a sensing period, wherein the sensing period begins based on the rise of the supply voltage (VIO) when the MIPI RFFE device (10) is started, and the sensing period ends at the nth clock cycle of the MIPI RFFE signal (SDATA, SCLK).

2. The method according to claim 1, wherein n is less than the minimum length of the MIPI RFFE signal (SDATA, SCLK).

3. The method according to claim 1 or 2, wherein the sensing period begins when the supply voltage (VIO) of the MIPI RFFE device (10) reaches a predetermined threshold upon startup.

4. The method of claim 3, wherein the start of the sensing period is earlier than the SSC bit of the MIPI RFFE signal.

5. The method of claim 1 or 2, wherein the method includes activating comparator thresholds (VTHU, VTHM, VTHL) at the beginning of the sensing period and enabling comparator arrangements (810A, 810B, 810C) configured to compare the voltage (VSENSE) with the comparator thresholds at the end of the sensing period, wherein setting the address based on the detected voltage (VSENSE) includes: The address is set based on one or more outputs of the comparator arrangement.

6. The method according to claim 1 or 2, wherein the MIPI RFFE signal (SDATA, SCLK) is the first MIPI RFFE signal (SDATA, SCLK) after the MIPI RFFE device (10) is started.

7. A MIPI RFFE device (10) includes a sensing circuit device configured to: Using the timing of the MIPI RFFE signals (SDATA, SCLK) received by the MIPI RFFE device (10), the voltage (VSENSE) at the configuration terminals (13D, 811) of the MIPI RFFE device (10) is detected, and Based on the detected voltage (VSENSE), the address of the MIPI RFFE device (10) is set. The timing detection of the voltage (VSENSE) based on the MIPI RFFE signals (SDATA, SCLK) includes: The voltage (VSENSE) is detected during a sensing period, wherein the sensing period begins based on the rise of the supply voltage (VIO) when the MIPI RFFE device (10) is started, and the sensing period ends at the nth clock cycle of the MIPI RFFE signal (SDATA, SCLK).

8. The apparatus of claim 7, wherein the apparatus is configured to perform the method of any one of claims 2 to 6.

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