Performing media management operations based on changing write patterns of data blocks in a cache

Abstract

A garbage collection operation can be performed on one or more data blocks of a memory sub-system, where data is stored at the one or more data blocks using a first write mode. In response to determining that the garbage collection operation satisfies a performance condition, a determination is made as to whether a data block of a cache region of the memory sub-system satisfies a durability condition, where data is stored at the data block of the cache region using a second write mode. A write mode for the data block of the cache region is changed from the second write mode to the first write mode in response to determining that the data block satisfies the durability condition. The data block of the cache region is then used in the garbage collection operation.

Description

Technical Field

[0001] This disclosure generally relates to a memory subsystem, and more specifically, to performing media management operations based on changing the write mode of data blocks in a cache used by the memory subsystem. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. These memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can use the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Attached Figure Description

[0003] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof.

[0004] Figure 1 An example computing system including a memory subsystem is shown according to some embodiments of the present disclosure.

[0005] Figure 2 This is a flowchart of an instance method for performing garbage collection operations based on changing the write mode of data blocks in the cache used by the memory subsystem.

[0006] Figures 3A-3B Examples of data configuration of a memory subsystem when performing garbage collection operations based on changes in the write mode of data blocks in the cache, according to some embodiments of the present disclosure, are shown.

[0007] Figure 4 This is a flowchart of an instance method for restoring the write mode of cached data blocks after performing a garbage collection operation based on changing the write mode used for the memory subsystem.

[0008] Figure 5 This is a block diagram of an example computer system in which embodiments of this disclosure may operate. Detailed Implementation

[0009] This disclosure relates to performing media management operations based on changing the write mode of data blocks in a cache used by a memory subsystem. The memory subsystem may be a storage device, a memory module, or a mixture of both. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Typically, a host system may use a memory subsystem that includes one or more components such as a memory device for storing data. The host system can provide data that will be stored in the memory subsystem and can request data that will be retrieved from the memory subsystem.

[0010] Memory devices can be non-volatile memory devices. A non-volatile memory device is a package of one or more dies. Each die can consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells storing data bits. For some memory devices, such as NAND devices, a block is the smallest erasable area, and pages within a block cannot be erased individually. For such devices, erase operations are performed one block at a time.

[0011] Pages within a block may contain valid data, invalid data, or no data. Invalid data is data marked as obsolete because a newer version of that data is stored on the memory device. Invalid data includes data previously written but no longer associated with a valid logical address (e.g., a logical address referenced by the host system in a physical-to-logical (P2L) mapping table). Valid data is the latest version of such data currently stored on the memory device. The memory subsystem may mark data as invalid based on information received, for example, from the operating system. Pages without data contain pages that have been previously erased and have not yet been written to.

[0012] The memory subsystem controller can perform operations for media management algorithms, such as wear leveling, refresh, garbage collection, and erasure. A block may have some pages containing valid data and some pages containing invalid data. To avoid waiting for all pages in a block to have invalid data before erasing and reusing the block, an algorithm, hereinafter referred to as "garbage collection," can be invoked to allow the block to be erased and freed as a free block for subsequent write operations. Garbage collection is a set of media management operations that include, for example: selecting a block containing valid and invalid data; selecting pages in the block containing valid data; copying the valid data to a new location (e.g., a free page in another block); marking data in the previously selected pages as invalid; and erasing the selected block.

[0013] The term "garbage collection" in the following text refers to selecting blocks; rewriting valid data from the selected blocks to another block; and erasing all invalid and valid data stored in the selected blocks. Valid data from multiple selected blocks can be copied to a smaller number of other blocks, and then the selected blocks can be erased. Therefore, the number of erased blocks can be increased, making more blocks available to store subsequent data from the host system.

[0014] The memory subsystem may perform garbage collection operations to maintain or generate a continuous supply of free data blocks to the host application for storing data. Garbage collection is the operation of copying valid data from one data block to another. The source data block (e.g., the data block from which valid data is copied) can then be erased and released as a free block for subsequent host writes. This additional rewriting of valid data in a data block during garbage collection causes write amplification. Write amplification can shorten operational lifetime and impact the performance of the memory subsystem. The memory subsystem may contain some amount of extra blocks beyond the logical size of the memory device exposed as user space. This extra space is often referred to as over-provisioning or OP. The efficiency of garbage collection operations can typically vary with the OP of the memory subsystem. During garbage collection, the extra space from the OP helps reduce write amplification. A larger amount of OP can reduce write amplification by reducing the number of times garbage collection rewrites valid data within the memory subsystem to free up data blocks. For example, for a memory device with an exposed user space size of 128 gigabytes (Gb), if the physical size is 140 Gb, the OP is 12 Gb. In this scenario, the efficiency of garbage collection operations may become lower than that of a device with the same user space size but a larger OP size, because the smaller OP space provides less extra space that can be used during garbage collection to reduce the amplified effects of writes when clearing data blocks that do not need data.

[0015] Memory devices may include one or more arrays of memory cells, such as single-level cell (SLC) memory, multi-level cell (MLC) memory, three-level cell (TLC) memory, or four-level cell (QLC) memory. Each type may have a different data density, which corresponds to the amount of data (e.g., data bits) that can be stored per memory cell of the memory device. Taking flash-based memory as an example, a three-level cell (TLC) can store three bits of data, while a single-level cell (SLC) can store one bit of data. Accordingly, a memory device containing TLC memory cells will have a higher data density than a memory device containing SLC memory cells. Furthermore, each type of memory cell may have different durability for storing data. The durability of a memory device refers to the number of write operations or program / erase operations performed on the memory cells of the memory device before data can no longer be reliably stored at the memory cell. For example, an SLC memory cell with a lower data density may have a higher durability threshold compared to a TLC memory cell with a higher data density. In some cases, the endurance threshold of an SLC memory cell may be 3 to 40 times higher than that of a TLC memory cell. Therefore, an SLC memory cell can store less total data but can be used for a longer period of time, while a TLC memory cell can store more total data but can be used for a shorter period of time.

[0016] The conventional memory subsystem can be further configured to allow a portion of the OP (Operational Program) space to be reserved for other purposes. For example, a portion of the OP can be reserved to store firmware-related information. Similarly, a portion of the OP space can be configured as a static cache to provide improved I / O performance. The remainder of the OP after the reserved area is allocated is generally referred to as operational OP. Accordingly, increasing the size of the cache region reduces operational OP. Blocks reserved for static cache regions can be configured as memory cells with lower data density to provide a higher endurance threshold for writing user data to the memory device. For example, blocks that can be configured as QLC (Quick Logic Cache) can be configured as memory cells with lower data density, such as SLC, MLC, or TLC. Similarly, blocks that can be configured as TLC can be configured as memory cells with lower data density, such as SLC or MLC. Once configured, blocks reserved for static cache are typically configured in this manner for the lifetime of the device and are not subsequently reconfigured as memory cells with higher data density.

[0017] A conventional memory subsystem configured in this way can provide long-term performance advantages for host I / O operations because the cache allocates memory cells with high durability due to lower data density. However, these configurations can have lower random write performance for write-intensive workloads due to the reduced operational operations (OPs) available during garbage collection. During such periods of write-intensive workloads, the operational OPs across the entire user space and memory device can become full, potentially triggering garbage collection to maintain free block balance. This condition is often referred to as a "steady-state" condition, where garbage collection occurs in the foreground or simultaneously with host data writes. A conventional memory subsystem does not provide access to static cache regions for garbage collection operations. Therefore, the reduced operational OPs significantly increase the degree of write amplification, resulting in reduced random write performance for write-intensive workloads under steady-state conditions.

[0018] This disclosure addresses the above and other shortcomings by performing garbage collection operations based on changes in the write patterns of data blocks in the cache used by the memory subsystem. The cache manager can monitor workload activity (e.g., observed write amplification) and can enable the use of a static cache region to supplement operational operations during periods of steady-state conditions until the steady-state conditions subside. For example, during steady-state conditions when garbage collection operations are performed, the current workload conditions of the memory device can be evaluated based on write amplification. If, during steady-state workload, the measured write amplification rises to a level sufficient to satisfy a threshold performance condition, the cache manager can determine whether to use a static cache region to supplement operational operations. Furthermore, in some embodiments, the cache manager can evaluate the durability of data blocks in the state cache to determine whether to use a static cache region to supplement operational operations. In this case, a static cache durability threshold can be used, which is a function of the ratio of cell degradation in higher data density modes to cell degradation in lower data density modes. In some implementations, the cache manager can temporarily change the write mode of data blocks in the cache region from SLC to a mode that provides higher data density (e.g., MLC, TLC, QLC, etc.) and make the cache region available for garbage collection operations during steady-state conditions. When the steady-state conditions subside (e.g., when write amplification decreases), and / or when data blocks in the static cache region no longer meet durability conditions, the cache manager can change the write mode of the cache region back to SLC and restore the restriction that prevents garbage collection operations from using the cache region under normal operating workloads.

[0019] The advantages of this disclosure include, but are not limited to, increased write performance during periods of write-intensive workloads and increased foreground garbage collection efficiency. Switching the write mode of data blocks in the cache to a higher data density mode provides increased operation time (OP) for garbage collection during periods of write-intensive workloads, thereby reducing write amplification during those periods. Furthermore, by monitoring write amplification under workloads to intelligently enable static caching for use with garbage collection, any additional durability impact on cache region blocks can be minimized by limiting mode switching to those periods of greatest performance degradation. Additionally, by utilizing cache regions to supplement operation OP, the number of blocks intentionally allocated to the cache can be increased over the lifetime of the memory subsystem. Therefore, the benefits of increasing cache size (e.g., improved write performance under normal working workload conditions) can be realized throughout the entire lifetime of the memory subsystem, while still achieving the benefits of larger operation OPs for write-intensive workloads in the early years of the memory subsystem's lifespan.

[0020] Figure 1Example computing system 100 including memory subsystem 110 according to some embodiments of the present disclosure is illustrated. Memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0021] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0022] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0023] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 An example of a host system 120 coupled to a memory subsystem 110 is shown. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without intermediate components or devices), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0024] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and to read data from memory subsystem 110.

[0025] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Dual Data Rate (DDR) memory bus, Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), Open NAND Flash Interface (ONFI), Dual Data Rate (DDR), Low Power Dual Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further use an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is shown as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0026] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0027] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND type flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory allows for in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0028] Each memory device 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), stores one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC), store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion, and an MLC portion, a TLC portion, or a QLC portion of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. In the case of some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0029] While non-volatile memory devices, such as 3D cross-point non-volatile memory cell arrays and NAND flash memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0030] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading, writing, or erasing data at the memory device 130, and other such operations (e.g., in response to commands scheduled on the command bus by controller 116). The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include digital circuitry with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0031] The memory subsystem controller 115 may include a processing means 117 (processor) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0032] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although... Figure 1 The instance memory subsystem 110 is shown to include a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0033] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and translates these commands or operations into instructions or appropriate commands to enable desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry translates commands received from the host system into commands for accessing memory devices 130 and / or 140, and translates responses associated with memory devices 130 and / or 140 into information for the host system 120.

[0034] In some implementations, the memory subsystem 110 may use a striping scheme, in which each data payload (e.g., user data) utilizes multiple dies of the memory device 130 (e.g., a NAND flash memory device), such that the payload is distributed across a subset of the dies, while the remaining one or more dies are used to store error correction information (e.g., parity bits). Therefore, a set of blocks distributed across a set of dies of a memory device using a striping scheme is referred to herein as a “superblock”.

[0035] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., a row decoder and a column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0036] In some embodiments, memory device 130 includes a local media controller 135, which operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0037] The memory subsystem 110 includes a cache manager component 113 that can perform media management operations, such as garbage collection, based on changes in the write mode of data blocks in the cache for data blocks stored at memory device 130. In some embodiments, the controller 115 includes at least a portion of the cache manager component 113. For example, the controller 115 may include a processor 117 (processing device) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the cache manager component 113 is part of the host system 120, an application, or an operating system.

[0038] Cache manager component 113 monitors the workload conditions of memory subsystem 110 (e.g., observed write amplification) and whether the performance of garbage collection operations meets performance conditions (e.g., whether observed write amplification indicates that memory subsystem 110 is operating under steady-state conditions). Cache manager component 113 determines whether blocks in the cache region of memory device 130 meet durability conditions. If both conditions are met, cache manager component 113 can change the write mode of data blocks in the cache region from a low data density mode (e.g., SLC) to a higher data density write mode (e.g., MLC, TLC, QLC, etc., hereinafter collectively referred to as XLC) and use the data blocks in garbage collection operations. Furthermore, once the workload conditions indicate that steady-state performance conditions no longer exist, cache manager component 113 can switch the write mode of subsequent data blocks in the cache region back to their original data density (e.g., return to SLC). Further details regarding the operation of cache manager component 113 are described below.

[0039] Figure 2 This is a flowchart of an example method 200 for performing garbage collection operations based on changing the write mode of data blocks in the cache used by the memory subsystem. Method 200 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 200 is performed by… Figure 1 The cache manager component 113 executes. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0040] like Figure 2As shown, at operation 205, the processing logic performs a garbage collection operation on one or more data blocks of the memory subsystem. Data can be stored in one or more blocks of the memory subsystem using a write mode that stores data using a specific number of bits per memory cell of the data block. In some embodiments, a write mode with a higher data density than blocks stored in the cache region of the memory subsystem can be used to store data. In one illustrative example, data may be stored in blocks configured with QLC memory cells, while blocks stored in the cache region may be configured with SLC, MLC, or TLC memory cells (because the data density per memory cell is lower than that of a QLC memory cell). In another illustrative example, data may be stored in blocks configured with TLC memory cells, while blocks stored in the cache region may be configured with SLC or MLC memory cells (because the data density per memory cell is lower than that of a TLC memory cell).

[0041] At operation 210, the processing logic determines whether the garbage collection operation meets a performance condition. In some embodiments, the performance condition may be based on the number of write operations used in the garbage collection operation to write a certain amount of data to one or more new data blocks (e.g., write amplification observed during garbage collection). In other words, the performance condition may be based on the number of additional writes that occur during garbage collection to copy valid data from one block to another. The processing logic may monitor the workload conditions of the memory subsystem to determine whether a steady-state condition exists based on the observed write amplification. As described above, the memory subsystem may be in a steady state during periods of high data write volume when the garbage collection operation becomes necessary to clear data blocks that do not require data, in parallel with writing new host data. For example, if the measured write amplification observed during the garbage collection operation meets a threshold, the performance condition is met. If at operation 210 the processing logic determines that the performance condition is met, the processing continues to operation 215. Otherwise, the processing proceeds to operation 230.

[0042] At operation 215, the processing logic determines whether a data block in the cache region of the memory subsystem meets a durability condition. As described above, in some embodiments, a second write mode with a lower data density than the data density of a data block accessed by a garbage collection operation can be used to store data in the data block of the cache region. In other words, the second write mode can use several bits per memory cell of the data block to store data, the number of bits being less than the number of bits of the block written using the first write mode specified at operation 205. For example, if the first write mode is QLC, the second write mode can be SLC, MLC, or TLC, because each mode has a lower data density than QLC. At operation 215, the processing logic may determine whether a data block allocated to the cache region of the memory subsystem has a durability value that satisfies a threshold associated with one of the higher data density write modes. For example, in cases where the processing logic may compare the durability of the cache data block with a high threshold durability value for a TLC memory cell. If the observed durability of a cached data block is less than the TLC durability threshold, the processing logic determines that the cached data block meets the durability condition and can be used in TLC mode. If the processing logic determines that the data block does indeed meet the durability condition, the processing continues to operation 220. Otherwise, the processing proceeds to operation 230.

[0043] At operation 220, the processing logic changes the write mode of the data blocks in the cache region from a second write mode to a first write mode. For example, if at operation 215, the processing logic determines that the data blocks in the cache region have observed durability less than the maximum durability threshold associated with a higher data density write mode, the processing logic may change the write mode of the data blocks in the cache region from its current write mode (e.g., SLC) to a write mode with a higher data density (e.g., MLC, TLC, etc.). At operation 225, the processing logic uses the data blocks in the cache region during a garbage collection operation. In other words, the processing logic can now use a new higher data density write mode (e.g., one of the XLC modes) to write data to the data blocks in the cache region during a garbage collection operation.

[0044] If at operation 210, the processing logic determines that the garbage collection operation does not meet performance conditions (e.g., the memory subsystem is not experiencing steady-state workload conditions), then processing proceeds to block 230, where the garbage collection operation uses data blocks from outside the cache region (e.g., the garbage collection operation does not use data blocks from the cache region). Similarly, if at operation 215, the processing logic determines that any data block in the cache region does not meet durability conditions (e.g., each data block in the cache has an observed durability value exceeding a threshold associated with the higher data density write pattern used by the memory subsystem), then processing proceeds to block 230, where the garbage collection operation uses data blocks from outside the cache region.

[0045] The following is combined with Figure 3A and Figure 3B Describe further details regarding the above operations.

[0046] Figures 3A-3B Examples of data configuration of a memory subsystem when performing a garbage collection operation based on changes in the write pattern of data blocks in the cache, according to some embodiments of the present disclosure, are illustrated. In some embodiments, the garbage collection operation may be performed by... Figure 1 The cache manager component 113 executes, as described above regarding... Figure 2 And the following text about Figure 4 As described.

[0047] like Figure 3A As shown, data configuration 300 may include user data block 301, firmware reserved data block 302, cache data block 303, and operation OP data block 304. In some embodiments, the entire OP area of ​​data configuration 300 may include firmware reserved data block 302, cache data block 303, and operation OP data block 304 (e.g., data blocks not allocated to user data block 301). As described above, firmware reserved data block 302 and cache data block 303 may be allocated from the entire OP area of ​​data configuration 300, thereby reducing the operation OP area 305 to contain only operation OP data block 304. Furthermore, as described above, data blocks allocated to cache data block 303 (e.g., data block 306) may be configured to be written using a low-density write mode (e.g., SLC).

[0048] As described above, when the memory subsystem receives host data to be written, it first writes the host data to cache data block 303, and then moves it to a data block in user data block 301. As data continues to be written to the memory subsystem, cache data block 303 may begin to fill up, causing subsequent received host data to be written directly to user data block 301. As writes continue, available space decreases, thus requiring garbage collection to clear data blocks containing unnecessary data. As described above, during periods of high write activity, the memory subsystem may experience a steady-state condition where garbage collection and new data writing occur simultaneously.

[0049] As mentioned above Figure 2 During garbage collection operations, the workload performance of the memory subsystem (e.g., observed write amplification) is monitored to assess the presence of steady-state conditions (e.g., whether performance conditions are met). If the write amplification of a data block during a garbage collection operation meets or exceeds a threshold, the garbage collection operation meets the performance conditions. As mentioned above, write amplification is based on the number of write operations used in the garbage collection operation to write a certain amount of data to one or more new data blocks. For example, to write 1Gb of host data to the memory subsystem, garbage collection may sometimes involve multiple write or rewrite operations, resulting in the amount of host data written far exceeding 1Gb. Therefore, effectively writing a total of 2Gb of data during garbage collection to process 1Gb of host data can produce a write amplification value of 2. During steady-state conditions, the number of write operations may be a large multiple of the amount of host data to be written.

[0050] If the garbage collection operation meets performance conditions (e.g., if steady-state conditions are observed based on garbage collection write amplification), cache block 303 can be analyzed to determine whether any block can be used to supplement the operation OP region 305. The cache manager can then select block 306 from cache block 303 to determine if the block meets the durability condition for XLC write mode. In some embodiments, the durability condition corresponds to a threshold number of write operations that have been performed on block 306 using XLC write mode. In other words, the durability condition may represent the maximum number of program / erase cycles available for XLC write mode before the memory cells of the block become unreliable.

[0051] For example, if user data block 301 and operation OP data block 304 are configured to use TLC write mode, the cache manager can compare the observed durability value of data block 306 with the durability threshold of the TLC write mode. Similarly, if the memory subsystem uses other higher data density write modes (e.g., MLC, QLC, etc.), the cache manager can use the durability threshold of the write mode being used. Therefore, durability conditions ensure that data blocks in the cache are suitable for the write mode before switching to a higher density write mode.

[0052] In some implementations, the cache manager can determine whether data block 306 meets the durability condition by first determining whether the average durability value of all data blocks in cache data block 303 meets the durability condition. If the average durability of the entire cache data block 303 meets the durability condition, the cache manager can then select data block 306. If the average durability value does not meet the durability condition, this indicates that there are no data blocks in cache data block 303 that support XLC write mode. In this case, cache data block 303 can be used only for cache operations, and any write mode switching for any subsequent garbage collection operations can be disabled or bypassed.

[0053] If the cache manager determines that the garbage collection operation meets performance conditions (e.g., write amplification has been met or exceeded during steady-state garbage collection), and at least one data block in cache data block 303 meets durability conditions (e.g., data block 306 can support XLC write mode), the cache manager can perform a change write mode 340 to change the write mode of data block 306 (e.g., increase the data density of data block 306 to support XLC write mode).

[0054] By changing the write mode 340, you can then modify the data configuration 300 to obtain... Figure 3B The data configuration is 350. For example... Figure 3BAs shown, data configuration 350 may include user data block 351, firmware reserved data block 352, cache data block 353, and operation OP data block 354. Similar to data configuration 300, the entire OP area of ​​data configuration 350 may include firmware reserved data block 352, cache data block 353, and operation OP data block 354 (e.g., data blocks not allocated to user data block 351). However, performing a change-of-write-mode 340 may increase the operation OP area to include some or all of the cache data block 353 (e.g., as shown in temporary operation OP area 355). Furthermore, due to performing a change-of-write-mode 340, data blocks allocated to cache data block 353 (e.g., data block 356) may be configured to be written using a higher-density write mode (e.g., XLC). In some implementations, some data blocks in cache data block 353 may not meet durability conditions (e.g., some blocks may have durability values ​​exceeding the XLC threshold). In this case, these blocks may be restricted from garbage collection in XLC mode.

[0055] As garbage collection continues, the cache manager can continue to monitor the ongoing workload conditions of the memory subsystem (e.g., observed write amplification) to determine when steady-state conditions have ceased. If the cache manager determines that subsequent garbage collection operations do not meet the established performance conditions (e.g., observed write amplification has fallen below a threshold during steady-state garbage collection), write mode recovery 360 can be performed to switch the write mode of the data blocks in cache data block 353 back to its previous state (e.g., restoring the write mode configuration to SLC mode). Therefore, data blocks in the cache can be used in XLC mode during steady-state conditions but revert to SLC mode when those conditions cease. The following is about... Figure 4 The description further details the restoration of the write mode of the cached data blocks to their original configuration.

[0056] Note that, for illustrative purposes, Figures 3A-3B The document describes switching the write mode of cache data block 306 from SLC write mode to XLC write mode. In various embodiments, aspects of this disclosure can be implemented using other write modes. For example, in some embodiments, cache data block 306 may initially be configured to have MLC memory cells and subsequently switched to TLC or QLC memory cells.

[0057] Figure 4This is a flowchart of an example method 400 for restoring the write mode of cache data blocks after performing a garbage collection operation based on a change in the write mode of a memory subsystem, according to some embodiments of the present disclosure. Method 400 may be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1 The cache manager component 113 executes. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0058] like Figure 4 As shown, at operation 405, by changing the number of bits stored at the data block from a first number to a second number, the processing logic determines that a garbage collection operation on a set of data blocks associated with the memory device has used data blocks in the cache region associated with the memory device, where the first number is less than the second number. (As mentioned above regarding...) Figure 2 and Figures 3A-3B In some implementations, garbage collection operations can utilize data blocks in the cache region by switching the write mode of data blocks from a low data density mode (storing fewer bits at the data block) to a higher data density mode (storing more bits at the data block). For example, the write mode of a data block configured with SLC memory cells can be switched to one of the XLC write modes. Similarly, the write mode of a data block configured with MLC memory cells can be switched to TLC or QLC write modes.

[0059] At operation 410, the processing logic determines that the garbage collection operation has met performance requirements. In some implementations, performance requirements may be based on the number of write operations used in the garbage collection operation to write a certain amount of data to one or more new data blocks (e.g., write amplification observed during garbage collection). The processing logic may monitor the workload conditions of the memory subsystem to determine when steady-state conditions no longer exist based on the observed write amplification. For example, if the measured write amplification observed during the garbage collection operation is below a high threshold, the performance requirements are met.

[0060] At operation 415, in response to determining that the garbage collection operation has met performance requirements, the processing logic stores subsequent data at the data block as cached data by changing the number of bits stored at the data block from a second number (e.g., the number of bits for a higher data density write mode) to a first number (the number of bits for a lower data density write mode). As described above, the processing logic can restore the write mode of the data block to the original write mode that existed before encountering steady-state workload conditions. For example, if a data block in the cache region was initially configured with SLC memory cells and subsequently switched to XLC write mode, the processing logic can change the write mode of the data block in the cache region of the memory subsystem from XLC write mode back to its originally configured SLC write mode.

[0061] Figure 5 An example machine of computer system 500 is shown, within which an instruction set is executable to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 500 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110), or may be used to perform controller operations (e.g., to execute an operating system, thereby executing commands corresponding to...). Figure 1 (Operation of the cache manager component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, with the capabilities of a server or client machine in a client-server network environment.

[0062] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch or bridge, or non-digital circuit system, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is shown, it should also be understood that the term "machine" includes any set of machines that individually or jointly execute a set (or sets of sets) of instructions to perform any or more of the methods discussed herein.

[0063] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518 that communicates with each other via a bus 530.

[0064] Processing device 502 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets or combinations of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 for communication via network 520.

[0065] Data storage system 518 may include machine-readable storage medium 524 (also referred to as computer-readable medium) on which one or more sets of instructions 526 or software embodying any one or more of the methods or functions described herein are stored. Instructions 526 may also reside wholly or at least partially within main memory 504 and / or processing device 502 during execution by computer system 500, which also constitute machine-readable storage medium. Machine-readable storage medium 524, data storage system 518, and / or main memory 504 may correspond to... Figure 1 The memory subsystem 110.

[0066] In one embodiment, instruction 526 includes implementing a component corresponding to a cache manager (e.g., Figure 1 The cache manager component 113) contains functional instructions. Although the machine-readable storage medium 524 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. The term "machine-readable storage medium" may include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0067] Some parts of the foregoing detailed description have been presented based on algorithms and symbolic representations of operations on data bits within computer memory. These algorithms are described and represented as a way for those skilled in the art of data processing to most effectively communicate the essence of their work to others skilled in the art. Algorithms are, and generally are, considered as a self-consistent sequence of operations that produce the desired result. These operations are those that require physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0068] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient notations applied to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0069] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions and each coupled to a computer system bus.

[0070] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may be convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0071] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0072] In the foregoing description, embodiments of this disclosure have been described with reference to specific examples thereof. It will be apparent that various modifications can be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A method for performing memory operations, comprising: Garbage collection is performed on one or more data blocks of a memory device in a memory subsystem, wherein the one or more data blocks of the memory device store first data, wherein the first data is stored in the one or more data blocks of the memory device using a first write mode. Determine whether the waste collection operation meets the performance requirements; In response to determining that the garbage collection operation meets the performance conditions, it is determined whether the cache data block of the cache region of the memory subsystem meets the durability conditions, wherein the cache data block stores second data, wherein the second data is stored in the cache data block using a second write mode; In response to determining that the cache data block meets the durability condition, the processing device changes the write mode for the cache data block from the second write mode to the first write mode; as well as The cached data block is used in the garbage collection operation. The performance conditions are based on the number of write operations used in the garbage collection operation to write a certain amount of data to one or more new data blocks.

2. The method of claim 1, wherein the first write mode stores the first data in a first number of bits per memory cell, and wherein the second write mode stores the second data in a second number of bits per memory cell, less than the first number of bits per memory cell.

3. The method of claim 1, wherein the durability condition corresponds to a threshold number of write operations that have been performed on the cache data block using the first write mode.

4. The method of claim 1, wherein the first write mode includes at least one of the following: multi-level cell (MLC) mode, three-level cell (TLC) mode, and four-level cell (QLC) mode, and wherein the second write mode includes single-level cell (SLC) mode.

5. The method of claim 1, wherein determining whether the cached data block satisfies the durability condition further comprises: Determine whether the average durability value of the cache region meets the durability condition; as well as In response to determining that the average durability value of the cache region satisfies the durability condition, the cache data block is selected from a plurality of additional data blocks associated with the cache region.

6. The method of claim 5, wherein the average durability value corresponds to the average number of write operations that have been performed on the plurality of additional data blocks using the first write mode.

7. A memory system comprising: Memory components; as well as A processing device operatively coupled to the memory component to perform the following operations: By changing the number of bits stored in the cache data block from a first number to a second number, it is determined that garbage collection operations on multiple data blocks of the memory device associated with the memory component have used the cache data blocks of the cache region associated with the memory component. Determine that the garbage collection operation has met the performance requirements, wherein the performance requirements are based on the number of write operations used in the garbage collection operation to write a certain amount of data to one or more new data blocks; as well as In response to determining that the garbage collection operation has met the performance requirements, subsequent data stored in the cache block is stored as cache data by changing the number of bits stored in the cache data block from the second number to the first number.

8. The memory system of claim 7, wherein the first number is less than the second number.

9. The memory system of claim 7, wherein the first number is associated with a first write mode and the second number is associated with a second write mode.

10. The memory system of claim 9, wherein the first write mode comprises a single-level cell (SLC) mode, and wherein the second write mode comprises at least one of the following: a multi-level cell (MLC) mode, a three-level cell (TLC) mode, and a four-level cell (QLC) mode.

11. The memory system of claim 7, wherein, in order to determine that the garbage collection operation has met performance requirements, the processing device further: It is determined that the number of write operations used in the garbage collection operation to write the certain amount of data is below a high threshold.

12. A non-transitory computer-readable medium comprising instructions that, when executed by a processing means, cause the processing means to perform operations including: Garbage collection is performed on one or more data blocks of a memory device in a memory subsystem, wherein the one or more data blocks of the memory device store first data, wherein the first data is stored in the one or more data blocks using a first write mode. Determine whether the waste collection operation meets the performance requirements; In response to determining that the garbage collection operation meets the performance conditions, it is determined whether the cache data block of the cache region of the memory subsystem meets the durability conditions, wherein the cache data block stores second data, wherein the second data is stored in the cache data block of the cache region using a second write mode; In response to determining that the cache data block meets the durability condition, the write mode of the cache data block used for the cache region is changed from the second write mode to the first write mode; as well as The cached data block is used in the garbage collection operation. The performance conditions are based on the number of write operations used in the garbage collection operation to write a certain amount of data to one or more new data blocks.

13. The non-transitory computer-readable medium of claim 12, wherein the first write mode stores the first data in a first number of bits per memory cell, and wherein the second write mode stores the second data in a second number of bits per memory cell, less than the first number of bits per memory cell.

14. The non-transitory computer-readable medium of claim 12, wherein the durability condition corresponds to a threshold number of write operations that have been performed on the cached data block using the first write mode.

15. The non-transitory computer-readable medium of claim 12, wherein the first write mode includes at least one of the following: a multi-level cell (MLC) mode, a three-level cell (TLC) mode, and a four-level cell (QLC) mode, and wherein the second write mode includes a single-level cell (SLC) mode.

16. The non-transitory computer-readable medium of claim 12, wherein, in order to determine whether the cached data block satisfies the durability condition, the operation further comprises: Determine whether the average durability value of the cache region meets the durability condition; as well as In response to determining that the average durability value of the cache region satisfies the durability condition, the cache data block is selected from a plurality of additional data blocks associated with the cache region.

17. The non-transitory computer-readable medium of claim 16, wherein the average durability value corresponds to the average number of write operations that have been performed on the plurality of additional data blocks using the first write mode.

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