Display substrate, preparation method thereof and display device

Abstract

A display substrate, a manufacturing method thereof and a display device, the display substrate comprising a display area, a first transition area located in the display area, a second transition area located in the first transition area, and a void area located in the second transition area, the first transition area comprising a substrate, a buffer layer arranged on the substrate, an insulating layer arranged on the buffer layer, and a plurality of isolation dams arranged on the insulating layer, the second transition area comprising a substrate, a buffer layer arranged on the substrate, and a plurality of isolation columns arranged on the buffer layer, the plurality of isolation dams and the plurality of isolation columns are arranged around the void area.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and particularly to a display substrate, a method for preparing the same, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, and extremely fast response speed. With the continuous development of display technology, OLED technology is increasingly being used in various display devices, especially in smart terminal products such as mobile phones and tablets.

[0003] For smart terminal products, most manufacturers are pursuing higher screen-to-body ratios, such as full-screen and borderless screens, in order to bring users a more stunning visual experience. Since smart terminal products typically require hardware such as front-facing cameras and light sensors, the solution of creating mounting holes in the effective display area of ​​the OLED screen to house these devices is receiving significant attention within the industry. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] An exemplary embodiment of this disclosure provides a display substrate, including a display area, a first transition area located in the display area, a second transition area located in the first transition area, and a void area located in the second transition area, wherein: the first transition area includes a substrate, a buffer layer disposed on the substrate, an insulating layer disposed on the buffer layer, and a plurality of isolation dams disposed on the insulating layer; the second transition area includes a substrate, a buffer layer disposed on the substrate, and a plurality of isolation pillars disposed on the buffer layer; the plurality of isolation dams and the plurality of isolation pillars are all disposed around the void area.

[0006] In an exemplary embodiment, the display area includes a substrate, a driving structure layer disposed on the substrate, a planarization layer disposed on the driving structure layer, and a pixel definition layer defining a pixel opening area;

[0007] The driving structure layer includes a buffer layer on the substrate, an active layer on the buffer layer, a first insulating layer covering the active layer, a first gate electrode layer on the first insulating layer, a second insulating layer covering the first gate electrode layer, a second gate electrode layer on the second insulating layer, a third insulating layer covering the second gate electrode layer, and a first source / drain electrode layer on the third insulating layer.

[0008] The insulating layer includes a first insulating layer located on the buffer layer, a second insulating layer located on the first insulating layer, and a third insulating layer located on the second insulating layer.

[0009] In an exemplary embodiment, the plurality of isolation dams includes a plurality of first isolation dams and a plurality of second isolation dams. The first isolation dam includes a first dam foundation and a first protrusion, and the second isolation dam includes a second protrusion. The nearest distance between the first isolation dam and the vacant area is greater than the nearest distance between the second isolation dam and the vacant area, wherein:

[0010] The first dam foundation is disposed on the same layer as the planarization layer, and the first protrusion and the second protrusion are disposed on the same layer as the pixel.

[0011] In an exemplary embodiment, in a plane perpendicular to the substrate, the height of the end of the first isolation dam away from the substrate is greater than or equal to the height of the end of the second isolation dam away from the substrate.

[0012] In an exemplary embodiment, in a plane perpendicular to the substrate, the distance between the end of the second isolation dam near the substrate and the end of the isolation column near the substrate is 5 micrometers to 40 micrometers, and the distance between the end of the first isolation dam near the substrate and the end of the second isolation dam near the substrate is 10 micrometers to 40 micrometers.

[0013] In an exemplary embodiment, the isolation column includes a second dam foundation and a third protrusion, wherein:

[0014] The second dam foundation is disposed on the same layer as the planarization layer, and the third protrusion is disposed on the same layer as the pixel.

[0015] In an exemplary embodiment, in a plane perpendicular to the base, the distance from the end of the isolation dam away from the base is greater than or equal to the distance from the end of the isolation column away from the base.

[0016] In an exemplary embodiment, in a plane perpendicular to the base, the width of the isolation post at the end furthest from the base is smaller than the width of the isolation post at the end closest to the base.

[0017] In an exemplary embodiment, the closest distance between the end of the isolation column away from the substrate and the void area is 10 to 20 micrometers; the closest distance between the end of the isolation column near the substrate and the void area is 1 to 5 micrometers.

[0018] In an exemplary embodiment, in a plane perpendicular to the base, the width of the isolation dam at the end furthest from the base is smaller than the width of the isolation dam at the end closest to the base.

[0019] In an exemplary embodiment, the display area further includes a light-emitting structure layer disposed on the planarization layer and an encapsulation layer disposed on the light-emitting structure layer. The encapsulation layer includes a first inorganic layer, a second inorganic layer, and an organic encapsulation layer disposed between the first inorganic layer and the second inorganic layer. The first inorganic layer and the second inorganic layer both extend to the first transition region and the second transition region and cover the plurality of isolation dams and the plurality of isolation pillars.

[0020] In an exemplary embodiment, the display substrate further includes a polarizer located on the encapsulation layer. The orthographic projection of the contact area between the second inorganic layer and the polarizer in the second transition region onto the substrate is located within the range of the orthographic projection of the isolation pillar onto the substrate. In a plane parallel to the substrate, the area of ​​the contact area between the second inorganic layer and the polarizer in the second transition region is greater than or equal to the area of ​​the end of the isolation pillar away from the substrate.

[0021] An exemplary embodiment of this disclosure also provides a display device including the aforementioned display substrate, wherein the empty area is used for mounting hardware structures.

[0022] An exemplary embodiment of this disclosure also provides a method for fabricating a display substrate, the display substrate including a display area, a first transition area located in the display area, a second transition area located in the first transition area, and a void area located in the second transition area, the fabrication method including:

[0023] Forming a buffer layer covering the substrate;

[0024] An insulating layer covering the buffer layer is formed in the first transition region, the second transition region, and the empty region. A patterning process is performed on the insulating layer of the second transition region and the empty region to form a first groove that exposes the buffer layer. The orthographic projection of the first groove on the substrate covers the orthographic projection of the second transition region and the empty region on the substrate.

[0025] Multiple isolation dams are formed on the insulating layer, and multiple isolation pillars are formed in the first groove. The multiple isolation dams and the multiple isolation pillars are arranged around the empty area.

[0026] In an exemplary embodiment, the isolation dam and the isolation column are arranged in the same layer, made of the same material, and formed by the same process; or, the isolation dam and the isolation column are not arranged in the same layer.

[0027] In an exemplary embodiment, the fabrication method further includes: forming a driving structure layer disposed on the substrate, a planarization layer disposed on the driving structure layer, and a pixel definition layer defining a pixel opening region in the display area;

[0028] The driving structure layer includes a buffer layer on the substrate, an active layer on the buffer layer, a first insulating layer covering the active layer, a first gate electrode layer on the first insulating layer, a second insulating layer covering the first gate electrode layer, a second gate electrode layer on the second insulating layer, a third insulating layer covering the second gate electrode layer, and a first source / drain electrode layer on the third insulating layer.

[0029] The insulating layer includes a first insulating layer located on the buffer layer, a second insulating layer located on the first insulating layer, and a third insulating layer located on the second insulating layer.

[0030] In an exemplary embodiment, the plurality of isolation dams includes a plurality of first isolation dams and a plurality of second isolation dams. The first isolation dam includes a first dam foundation and a first protrusion, and the second isolation dam includes a second protrusion. The nearest distance between the first isolation dam and the vacant area is greater than the nearest distance between the second isolation dam and the vacant area.

[0031] The first dam foundation is disposed on the same layer as the planarization layer, and the first protrusion and the second protrusion are disposed on the same layer as the pixel.

[0032] In an exemplary embodiment, the isolation column includes a second dam foundation and a third protrusion, wherein:

[0033] The second dam foundation is disposed on the same layer as the planarization layer, and the third protrusion is disposed on the same layer as the pixel.

[0034] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood. Attached Figure Description

[0035] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0036] Figure 1 This is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0037] Figure 2 for Figure 1 Sectional view along the middle AA direction;

[0038] Figure 3 A schematic diagram of a display substrate after forming an active layer pattern according to an exemplary embodiment of the present disclosure;

[0039] Figure 4 This is a schematic diagram of a display substrate after the gate electrode pattern has been formed, as per an exemplary embodiment of the present disclosure.

[0040] Figure 5 This is a schematic diagram of a display substrate after forming a capacitor electrode pattern according to an exemplary embodiment of the present disclosure;

[0041] Figure 6 A schematic diagram of a display substrate after forming a third insulating layer pattern according to an exemplary embodiment of the present disclosure;

[0042] Figure 7 A schematic diagram of a display substrate after forming source and drain electrode patterns according to an exemplary embodiment of the present disclosure;

[0043] Figure 8 A schematic diagram of a display substrate after a planarization layer pattern has been formed, as shown in an exemplary embodiment of this disclosure;

[0044] Figure 9 This is a schematic diagram of a display substrate after an anode pattern has been formed, as per an exemplary embodiment of the present disclosure.

[0045] Figure 10 A schematic diagram of a display substrate after forming a pixel definition layer pattern according to an exemplary embodiment of the present disclosure;

[0046] Figure 11 A schematic diagram of a display substrate after forming an organic light-emitting layer and a cathode pattern, as shown in an exemplary embodiment of the present disclosure;

[0047] Figure 12 This is a schematic diagram of a display substrate after forming an encapsulation layer pattern according to an exemplary embodiment of the present disclosure;

[0048] Figure 13 This is a schematic flowchart illustrating a method for fabricating a display substrate, which is an exemplary embodiment of this disclosure. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0050] In the accompanying drawings, the size of the constituent elements, the thickness of the layers, or the area are sometimes exaggerated for clarity. Therefore, one aspect of this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0051] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0052] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0053] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0054] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0055] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0056] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0057] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0058] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0059] OLED displays are self-emissive display devices that offer significant advantages over traditional LCD displays, including high brightness, high contrast, high color saturation, and high response time, and have gradually become the mainstream product in the display field. In practical applications, to achieve a larger effective display area and reduce bezels, some terminal manufacturers have begun to place the mounting holes, originally intended for pre-installed front-facing cameras and other hardware, within the active area (AA) of the display panel.

[0060] Flexible display products are generally susceptible to the effects of external light when used directly in natural environments, which can affect their normal use. Therefore, a polarizing film needs to be attached to the surface of the flexible display product to prevent natural light from affecting the display device. At the same time, the polarizing film can also achieve a seamless black effect for the display device.

[0061] The main component of the polarizer is polyvinyl acetate, which adsorbs dyeing substances (iodine compounds). Before the polarizer is bonded to the display device, both the upper and lower layers of the polarizer are covered with protective films. These protective films are used to prevent the polarizer from being damaged during transportation and affecting its use. Therefore, when bonding the polarizer to the display device, the lower protective film needs to be removed first. After bonding the polarizer, the mounting hole (AA hole) area is cut into a through hole using a laser. Then, the upper protective film of the polarizer is removed, and the subsequent cover plate bonding work is carried out.

[0062] Laser cutting utilizes a focused, high-power-density laser beam to irradiate a workpiece, causing the irradiated material to rapidly melt, vaporize, ablate, or reach its ignition point. Simultaneously, a high-speed airflow coaxial with the laser beam removes the molten material, thus cutting the workpiece. However, display substrates are composed of multiple layers of materials with different coefficients of thermal expansion. Under the influence of heat, varying degrees of splitting occur between the upper and lower stacked layers in the AA-hole area. Furthermore, the existing structural design results in a relatively large cutting angle for the inorganic encapsulation layer at the edge of the AA hole, easily leading to stress concentration. Additionally, the edge of the AA hole is not easily wetted by ink. Therefore, during the subsequent film peeling process, the adhesive force of the film further increases the degree of splitting in the AA hole, thereby damaging the encapsulation structure of the AA hole area. This results in the phenomenon of growing black spots (GDS) on the display screen, severely impacting product yield and display quality.

[0063] This disclosure provides a display substrate and its fabrication method, as well as a display device. Without altering the existing process flow, by arranging multiple isolation pillars around the empty area and shrinking the stacked structure of the empty area before cutting, interlayer splitting caused by thermal expansion of the film layer due to heat conduction at the cutting edge is avoided. This solves the problem of edge structure cracking caused by adhesive stress during subsequent film removal. On the other hand, it also increases the contact area between the inorganic encapsulation layer and the polarizer, reduces the angle formed by the AA hole edge cutting, and reduces stress concentration at the AA hole cutting edge, thereby avoiding the GDS problem caused by edge structure cracking due to adhesive stress during subsequent film removal.

[0064] Figure 1 This is a schematic diagram of the structure of a display substrate according to an embodiment of the present disclosure. Figure 2 for Figure 1 The cross-sectional view along line AA illustrates the structure of the display area, the first transition area, the second transition area, and the empty area on a plane perpendicular to the display substrate. Figure 1 As shown, on a plane parallel to the display substrate, the main structure of the display substrate includes a display area 100, a first transition area 200, a second transition area 300, and a void area 400. The first transition area 200 is located within the display area 100, the second transition area 300 is located within the first transition area 200, and the void area 400 is located within the second transition area 300. That is, the first transition area 200 is an annular region surrounding the second transition area 300, and the second transition area 300 is an annular region surrounding the void area 400. The position and shape of the void area 400 within the display area 100 are not limited; it can be any shape. Figure 1 The circle shown can also be an ellipse, a square, a rhombus, or other polygons.

[0065] like Figure 2 As shown, on a plane perpendicular to the display substrate, the main structure of the display area 100 includes multiple light-emitting units arranged in an array. Each light-emitting unit includes a driving structure layer and a light-emitting structure layer disposed on the substrate 10. The driving structure layer includes multiple thin-film transistors. Figure 2 The illustration uses only two light-emitting units and two thin-film transistors as an example. Specifically, the driving structure layer mainly includes a buffer layer 11 disposed on the substrate 10 and a thin-film transistor 101 disposed on the buffer layer 11. The light-emitting structure layer mainly includes an anode 31 connected to the drain electrode of the thin-film transistor 101, a pixel definition layer 32 defining a pixel opening region, an organic light-emitting layer 33 formed in the pixel opening region and on the pixel definition layer 32, a cathode 34 formed on the organic light-emitting layer 33, and an encapsulation layer. The encapsulation layer includes a first inorganic layer 35, an organic encapsulation layer 36, and a second inorganic layer 37 stacked together.

[0066] like Figure 2 As shown, on a plane perpendicular to the display substrate, the main structure of the first transition region 200 includes a buffer layer 11 disposed on the substrate 10, an insulating layer 201 disposed on the buffer layer 11, a plurality of isolation dams 202 disposed on the insulating layer 201, an organic light-emitting layer 33 and a cathode 34 disposed on the plurality of isolation dams 202, and a first inorganic layer 35 and a second inorganic layer 37 covering the above structure. The insulating layer 201 disposed on the substrate 10 includes a first insulating layer, a second insulating layer, and a third insulating layer formed simultaneously with the driving structure layer.

[0067] On a plane perpendicular to the display substrate, the main structure of the second transition region 300 includes a buffer layer 11 disposed on the substrate 10, a plurality of isolation pillars 203 disposed on the buffer layer 11, an organic light-emitting layer 33 and a cathode 34 disposed on the plurality of isolation pillars 203, and a first inorganic layer 35 and a second inorganic layer 37 covering the above structure. The plurality of isolation dams 202 and the plurality of isolation pillars 203 are all disposed around the empty region 400. The plurality of isolation dams 202 are disposed between the isolation pillars 203 and the display region 100. The orthographic projection of the isolation pillars 203 on the substrate 10 does not overlap with the orthographic projection of the empty region 400 on the substrate 10.

[0068] In one exemplary embodiment, in a plane perpendicular to the substrate 10, the width of the end of the isolation pillar 203 away from the substrate 10 is smaller than the width of the end of the isolation pillar 203 near the substrate 10. By setting the width of the end of the isolation pillar 203 away from the substrate 10 to be smaller than the width of the end of the isolation pillar 203 near the substrate 10, the stacked structure near the empty area is further recessed, thereby reducing heat conduction at the cut edge.

[0069] In one exemplary embodiment, in a plane perpendicular to the substrate 10, the width of the isolation dam 202 at the end away from the substrate 10 is smaller than the width of the isolation dam 202 at the end near the substrate 10. Exemplarily, in a plane perpendicular to the substrate 10, the cross-sectional shape of each isolation dam 202 is a trapezoid. When the ramping capability of the organic encapsulation layer 36 between the first inorganic layer 35 and the second inorganic layer 37 is weak, the width of the isolation dam 202 at the end away from the substrate 10 can be set to be smaller than the width of the isolation dam 202 at the end near the substrate 10. In this case, the process is simpler, and the organic encapsulation layer 36 is less likely to cross the isolation dam 202, avoiding encapsulation failure.

[0070] In another exemplary embodiment, in a plane perpendicular to the substrate 10, the width of the isolation dam 202 at the end away from the substrate 10 is greater than the width of the isolation dam 202 at the end near the substrate 10. Exemplarily, in a plane perpendicular to the substrate 10, the cross-sectional shape of each isolation dam 202 is an inverted trapezoid. When the climbing ability of the organic encapsulation layer 36 between the first inorganic layer 35 and the second inorganic layer 37 is strong, the width of the isolation dam 202 at the end away from the substrate 10 can be set to be greater than the width of the isolation dam 202 at the end near the substrate 10. In this case, the isolation dam 202 can be used to disconnect the subsequently deposited organic light-emitting layer 33 and cathode 34 in the transition region 200, blocking the water and oxygen intrusion path from the vacant region 400 to the display region 100.

[0071] In one exemplary embodiment, in a plane perpendicular to the base 10, the height of the end of the isolation dam 202 away from the base 10 is greater than or equal to the height of the end of the isolation column 203 away from the base 10.

[0072] Since the bottom of the isolation dam 202 is provided with an insulating layer 201 and a buffer layer 11, and the isolation column 203 is only formed on the buffer layer 11, the height of the end of the isolation dam 202 away from the base 10 is greater than or equal to the height of the end of the isolation column 203 away from the base 10. This can reduce the thickness of the laser cutting in the mounting hole area.

[0073] In one exemplary embodiment, the encapsulation layer includes a first inorganic layer 35, an organic encapsulation layer 36, and a second inorganic layer 37 stacked together. In a plane perpendicular to the substrate 10, the height of the end of the isolation dam 202 away from the substrate 10 is greater than the height of the end of the first inorganic layer 35 away from the substrate 10. This prevents the organic encapsulation layer 36 from leaking to the other side of the isolation dam 202.

[0074] In one exemplary embodiment, the plurality of isolation dams include a first isolation dam 202a and a second isolation dam 202b, the first isolation dam 202a and the second isolation dam 202b being arranged at intervals around the empty zone 400, and the closest distance between the first isolation dam 202a and the empty zone 400 being greater than the closest distance between the second isolation dam 202b and the empty zone 400.

[0075] In one exemplary embodiment, the first isolation dam 202a includes a first dam base and a first protrusion, and the second isolation dam 202b includes a second protrusion. The first dam base is disposed on the same layer as the planarization layer, and the first and second protrusions are defined on the same layer as the pixels.

[0076] In one exemplary embodiment, the isolation column 203 includes a second dam base and a third protrusion, wherein the second dam base is disposed on the same layer as the planarization layer, and the third protrusion is disposed on the same layer as the pixel.

[0077] In one exemplary embodiment, in a plane perpendicular to the substrate 10, the height of the end of the first isolation dam 202a away from the substrate 10 is greater than or equal to the height of the end of the second isolation dam 202b away from the substrate 10. When the height of the end of the first isolation dam 202a away from the substrate 10 is greater than the height of the end of the second isolation dam 202b away from the substrate 10, the height difference between the two can be 1 to 15 micrometers.

[0078] like Figure 2 As shown, on a plane perpendicular to the display substrate, the empty area 400 is a through hole, and each structural film layer and substrate in the through hole is removed by laser cutting.

[0079] The structure of the display substrate disclosed herein is illustrated below through an example of the fabrication process of the display substrate. The "patterning process" mentioned in this disclosure includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping. Deposition can be performed using any one or more methods selected from sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more methods selected from spraying and spin coating; and etching can be performed using any one or more methods selected from dry etching and wet etching. A "thin film" refers to a thin film of a certain material fabricated on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." When the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are set in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection range of A, or the orthographic projection of A covers the orthographic projection of B.

[0080] In some exemplary embodiments, Figure 2 The fabrication process of the display substrate may include the following steps:

[0081] (1) Forming an active layer pattern on a substrate. Forming an active layer pattern on a substrate includes: firstly depositing a buffer film on a substrate 10 to form a buffer layer 11 pattern covering the entire substrate 10. Subsequently, depositing an active layer film, and patterning the active layer film using a patterning process to form an active layer 12 pattern disposed on the buffer layer 11 in the display area 100, such as... Figure 3 As shown. The active layer 12 pattern is formed only in the display area 100, while the first transition region 200, second transition region 300, and empty region 400 only have a buffer layer 11. The substrate can be a flexible substrate, using materials such as polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer soft films. The buffer film can be made of silicon nitride (SiNx) or silicon oxide (SiOx), and can be a single layer or a multilayer structure of silicon nitride / silicon oxide.

[0082] (2) Forming a gate electrode pattern. Forming the gate electrode pattern includes: sequentially depositing a first insulating film and a first metal film on the substrate 10 on which the above structure is formed; patterning the first metal film using a patterning process to form a first insulating layer 13 covering the active layer 12 and the buffer layer 11; a first gate electrode 14, a second gate electrode 15 disposed on the first insulating layer 13; and a gate line (not shown) pattern, such as... Figure 4 As shown. In this case, the first gate electrode 14, the second gate electrode 15 and the gate line are only formed in the display area 100. At this time, the first transition area 200, the second transition area 300 and the empty area 400 are formed with a buffer layer 11 and a first insulating layer 13.

[0083] (3) Forming a capacitor electrode pattern. Forming the capacitor electrode pattern includes: sequentially depositing a second insulating film and a second metal film on the substrate 10 where the above structure is formed; patterning the second metal film using a patterning process to form a second insulating layer 16 covering the first gate electrode 14, the second gate electrode 15, and the first insulating layer 13, and a capacitor electrode 17 pattern disposed on the second insulating layer 16. The positions of the capacitor electrodes 17 correspond to the positions of the second gate electrode 15, and the capacitor electrodes 17 and the second gate electrode 15 constitute a capacitor. Figure 5 As shown. In this case, the capacitor electrode 17 is formed only in the display area 100, and the first transition area 200, the second transition area 300 and the empty area 400 are formed with a buffer layer 11, a first insulating layer 13 and a second insulating layer 16.

[0084] (4) Forming a third insulating layer pattern with vias and grooves. Forming the third insulating layer pattern includes: depositing a third insulating film on the substrate 10 on which the above structure is formed; patterning the third insulating film using a patterning process to form a third insulating layer 18 pattern; the third insulating layer 18 has at least two first vias K1 in the display area 100; the third insulating layer 18, the second insulating layer 16, and the first insulating layer 13 in the two first vias K1 are etched away to expose the active layer 12; the third insulating layer 18 also has a first groove K2; the orthographic projection of the first groove K2 on the substrate covers the orthographic projection of the second transition area 300 and the empty area 400 on the substrate; the third insulating layer 18, the second insulating layer 16, and the first insulating layer 13 in the first groove K2 are etched away to expose the buffer layer 11, such as... Figure 6 As shown. That is, the two first vias are formed only in the display area 100, and the first groove K2 is formed in the second transition area 300 and the empty area 400. At this time, the first transition area 200 is formed with a buffer layer 11, a first insulating layer 13, a second insulating layer 16 and a third insulating layer 18.

[0085] (5) Forming source and drain electrode patterns. Forming source and drain electrode patterns includes: depositing a third metal thin film on the substrate 10 on which the above structure is formed; patterning the third metal thin film using a patterning process; and forming source electrode 19, drain electrode 20, and data line (not shown) patterns in the display area 100. Source electrode 19 and drain electrode 20 are respectively connected to the active layer 12 through two first vias, as shown below. Figure 7 As shown. In this case, the source electrode 19, the drain electrode 20 and the data line are only formed in the display area 100. At this time, the second transition area 300 and the empty area 400 are formed with a buffer layer 11 and a first groove K2. The first transition area 200 is formed with a buffer layer 11, a first insulating layer 13, a second insulating layer 16 and a third insulating layer 18.

[0086] Through the above process, the driving structure layer located in the display area 100, the insulating layer located in the first transition region 200, and the buffer layer located in the second transition region 300 and the empty region 400 are fabricated on the substrate 10. The driving structure layer located in the display area 100 includes an active layer 12, a first gate electrode 14, a second gate electrode 15, a capacitor electrode 17, a source electrode 19, a drain electrode 20, gate lines, and data lines. The gate lines and data lines perpendicularly intersect to define a sub-pixel. A thin-film transistor composed of the active layer 12, the first gate electrode 14, the source electrode 19, and the drain electrode 20 is disposed within the sub-pixel. The insulating layer located in the first transition region 200 includes a first insulating layer 13, a second insulating layer 16, and a third insulating layer 18. The first and second insulating layers are also referred to as gate insulating layers (GI), and the third insulating layer is also referred to as an interlayer insulating layer (ILD).

[0087] (6) Forming a planarization layer pattern. Forming a planarization layer pattern includes: coating a fourth insulating film on a substrate on which the aforementioned pattern is formed; and forming a fourth insulating layer 21 pattern covering the source electrode 19 and the drain electrode 20 in the display area 100 by a photolithography process involving mask exposure and development. The fourth insulating layer 21 has a second via K3, which exposes the drain electrode 20. Figure 8 As shown. A fourth insulating layer 21 is formed in the display area 100, the first transition area 200, and the second transition area 300. The orthographic projection of the fourth insulating layer 21 in the first transition area 200 overlaps with the orthographic projection of the subsequently formed first isolation dam 202a on the substrate. That is, the fourth insulating layer 21 formed in the first transition area 200 serves as the base of the subsequently formed first isolation dam 202a. The orthographic projection of the fourth insulating layer 21 in the second transition area 300 overlaps with the orthographic projection of the subsequently formed isolation pillar 203 on the substrate. That is, the fourth insulating layer 21 formed in the second transition area 300 serves as the base of the subsequently formed isolation pillar 203. The fourth insulating film in other areas is developed away, and a buffer layer 11 is formed in the empty area 400. The fourth insulating layer is also called a planarization layer (PLN).

[0088] (7) Forming an anode pattern. Forming the anode pattern includes: depositing a transparent conductive film on a substrate on which the aforementioned pattern is formed, patterning the transparent conductive film using a patterning process, forming an anode 31 pattern in the display area 100, and connecting the anode 31 to the drain electrode 20 through a second via, such as... Figure 9 As shown. In this configuration, the anode 31 is formed only in the display area 100. The transparent conductive films of the first transition region 200, the second transition region 300, and the empty region 400 are etched away. At this time, the first transition region 200 has a buffer layer 11, a first insulating layer 13, a second insulating layer 16, a third insulating layer 18, and a fourth insulating layer 21 disposed on the third insulating layer 18. The second transition region 300 has a buffer layer 11 and a fourth insulating layer 21 disposed on the buffer layer 11. The empty region 400 has a buffer layer 11. The transparent conductive film can be indium tin oxide (ITO) or indium zinc oxide (IZO).

[0089] (8) Forming a pixel definition layer pattern. Forming a pixel definition layer pattern includes: coating a pixel definition film on the substrate on which the aforementioned pattern is formed, and forming a pixel definition layer (Pixel Define Layer) 32 pattern by photolithography. The pixel definition layer 32 pattern can be located in the display area 100, the first transition area 200, and the second transition area 300. The pixel definition layer 32 pattern in the display area 100 defines a pixel opening area for exposing the anode 31 in each sub-pixel. A portion of the pixel definition layer 32 pattern in the first transition area 200 is disposed on the fourth insulating layer 21 to form a protruding portion of the first isolation dam 202a, and another portion is disposed on the third insulating layer 18 to form a protruding portion of the second isolation dam 202b. The pixel definition layer 32 pattern in the second transition area 300 is disposed on the fourth insulating layer 21 to form a protruding portion of the isolation pillar 203, such as... Figure 10 As shown. In this case, the empty area 400 has a buffer layer 11. The pixel definition layer can be made of polyimide, acrylic, or polyethylene terephthalate, etc.

[0090] In one exemplary embodiment, such as Figure 10 As shown, in the second transition zone 300, isolation pillars 203 are spaced apart around the empty zone 400, and isolation dams 202 are disposed between the isolation pillars 203 and the display area 100. In this embodiment, the isolation dams 202 are formed in the first transition zone 200, and the isolation pillars 203 are formed in the second transition zone 300. In this embodiment, multiple isolation dams 202 and multiple isolation pillars 203 are used to block the intrusion of water and oxygen and the crack propagation path from the empty zone 400 to the display area 100.

[0091] In one exemplary embodiment, such as Figure 10 As shown, in a plane perpendicular to the base 10, the cross-sectional shape of each isolation post 203 has the characteristic of being narrower at the top and wider at the bottom, that is, the width a1 of the isolation post 203 at the end away from the base 10 (the upper end) is smaller than the width b1 of the isolation post 203 at the end closer to the base 10 (the lower end). For example, in a plane perpendicular to the base 10, the cross-sectional shape of each isolation post 203 can be a regular trapezoid.

[0092] In one exemplary embodiment, such as Figure 10As shown, in a plane perpendicular to the substrate 10, the closest distance between the end of the isolation pillar 203 furthest from the substrate 10 (upper end) and the empty area 400 is between 2 and 6 times the closest distance between the end of the isolation pillar 203 closest to the substrate 10 (lower end) and the empty area 400. For example, the closest distance between the end of the isolation pillar 203 furthest from the substrate 10 (upper end) and the empty area 400 can be 10 to 20 micrometers to prevent thermal expansion failure of the encapsulation layer during laser cutting of the empty area 400. The closest distance between the end of the isolation pillar 203 closest to the substrate 10 (lower end) and the empty area 400 can be 1 to 5 micrometers to prevent the transition area 200 from being too wide and affecting the display effect.

[0093] In one exemplary embodiment, such as Figure 10 As shown, in a plane perpendicular to the base 10, the cross-sectional shape of each isolation dam 202 is narrower at the top and wider at the bottom; that is, the width a2 or a3 of the isolation dam 202 at the end away from the base 10 (upper end) is smaller than the width b2 or b3 of the isolation dam 202 at the end closer to the base 10 (lower end). For example, in a plane perpendicular to the base 10, the cross-sectional shape of each isolation column 203 can be a regular trapezoid.

[0094] In another exemplary embodiment, on a plane perpendicular to the base 10, the cross-sectional shape of each isolation dam 202 has a wider top and narrower bottom, that is, the width a2 or a3 of the isolation dam 202 at the end away from the base 10 (upper end) is greater than the width b2 or b3 of the isolation dam 202 at the end closer to the base 10 (lower end). For example, on a plane perpendicular to the base 10, the cross-sectional shape of each isolation column 203 can be an inverted trapezoid.

[0095] In one exemplary embodiment, on a plane perpendicular to the base 10, the height h2 or h3 of the isolation dam 202 away from the base 10 is greater than or equal to the height h1 of the isolation column 203 away from the base 10.

[0096] In one exemplary embodiment, the cross-sectional shape of each isolation pillar 203 on a plane parallel to the base 10 can be rectangular, circular, or elliptical, etc.

[0097] In one exemplary embodiment, the plurality of isolation dams 202 include a plurality of first isolation dams 202a and a plurality of second isolation dams 202b, the plurality of first isolation dams 202a and the plurality of second isolation dams 202b being respectively arranged around the isolation column 203, and the closest distance between the first isolation dam 202a and the isolation column 203 is greater than the closest distance between the second isolation dam 202b and the isolation column 203.

[0098] In one exemplary embodiment, such as Figure 11As shown, in a plane perpendicular to the base 10, the distance between the end of the second isolation dam 202b near the base 10 (lower end) and the end of the isolation column 203 near the base 10 (lower end) can be 5 to 40 micrometers.

[0099] In one exemplary embodiment, such as Figure 11 As shown, in a plane perpendicular to the substrate 10, the distance between the end of the first isolation dam 202a near the substrate 10 (lower end) and the end of the second isolation dam 202b near the substrate 10 (lower end) can be 10 to 40 micrometers to prevent the organic encapsulation layer 36 from climbing over the first isolation dam 202a and causing display defects.

[0100] In one exemplary embodiment, the isolation dam 202 and the isolation pillar 203 can be formed in the same layer or in different layers. This disclosure does not limit the materials used for the isolation dam 202 and the isolation pillar 203, nor does it limit which specific layer of the display substrate the isolation dam 202 and the isolation pillar 203 are formed on.

[0101] In one exemplary embodiment, the isolation dam 202 can be formed by one or more layers of a planarization layer, a pixel definition layer, or a support pillar layer (not shown in the figure), and the isolation pillar 203 can also be formed by one or more layers of a planarization layer, a pixel definition layer, or a support pillar layer. The support pillar layer of the display area 100 is used to maintain the distance between the display substrate and the cover plate (not shown in the figure) to prevent scratches on the OLED film layer or the formation of Newton's rings.

[0102] In one exemplary embodiment, the display substrate further includes at least one crack dam (not shown) to prevent the insulation layer 201 of the first transition region 200 from cracking due to laser cutting of the mounting hole, thereby damaging the driving structure layer structure of the display area 100. The crack dam can be formed between the isolation pillar 203 and the isolation dam 202b. The crack dam can include any one or more of the following: a first crack dam fabricated in the same layer as the source / drain electrode layer, a second crack dam fabricated in the same layer as the first gate electrode layer, and a third crack dam fabricated in the same layer as the second gate electrode layer. In this embodiment, since the dam base of the isolation pillar 203 is disposed on the buffer layer 11, the step of fabricating the crack dam can be omitted. When the mounting hole is laser cut, the isolation pillar 203 can simultaneously protect the structure of the driving structure layer and the light-emitting layer of the display area 100.

[0103] (9) Forming an organic light-emitting layer and a cathode pattern. Forming the organic light-emitting layer and the cathode pattern includes: sequentially depositing an organic light-emitting material and a cathode metal thin film on a substrate on which the aforementioned pattern is formed, to form an organic light-emitting layer 33 and a cathode 34 pattern. In the display area 100, the organic light-emitting layer 33 is connected to the anode 31 in the pixel opening area defined by the pixel definition layer 32, and the cathode 34 is disposed on the organic light-emitting layer 33. In the transition area 200, the organic light-emitting layer 33 and the cathode 34 are formed on a support pillar layer; in the first transition area 200, the organic light-emitting layer 33 and the cathode 34 are formed on an isolation dam 202; in the second transition area 300, the organic light-emitting layer 33 and the cathode 34 are formed on an isolation pillar 203; in the vacant area 400, the organic light-emitting layer 33 and the cathode 34 are formed on a buffer layer 11, such as... Figure 11 As shown. The organic light-emitting layer 33 mainly includes an emissive layer (EML). In actual implementation, the organic light-emitting layer may include a hole injection layer, a hole transport layer, an emissive layer, an electron transport layer, and an electron injection layer arranged sequentially to improve the efficiency of electron and hole injection into the emissive layer. The cathode can be one of the following metal materials: magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), lithium (Li), or an alloy of the above metals.

[0104] (10) Forming an encapsulation layer pattern. Forming the encapsulation layer pattern includes: firstly depositing a first inorganic thin film on the substrate on which the aforementioned pattern is formed, the first inorganic thin film covering the display area 100, the first transition area 200, the second transition area 300, and the vacant area 400, to form a first inorganic layer 35 pattern. Subsequently, an organic encapsulation layer 36 is formed on the display area 100 using inkjet printing. Subsequently, a second inorganic thin film is deposited, the second inorganic thin film covering the display area 100, the first transition area 200, the second transition area 300, and the vacant area 400, to form a second inorganic layer 37 pattern, such as... Figure 12 As shown. The encapsulation layer is a three-layer structure of inorganic / organic / inorganic. The middle organic layer is formed only in the display area 100, and the upper and lower inorganic layers cover the display area 100, the first transition area 200, the second transition area 300 and the empty area 400, thus completing the encapsulation of the display substrate.

[0105] Through the above process, the light-emitting structure layer located in the display area 100, the isolation dam 202 located in the first transition region 200, and the isolation pillar 203 located in the second transition region 300 are fabricated. Among them, the light-emitting structure layer located in the display area 100 includes an anode 31, a pixel definition layer 32, an organic light-emitting layer 33, a cathode 34, and an encapsulation layer.

[0106] (11) Finally, the module stage process is performed. After the polarizer 38 is bonded, the various structural film layers and substrate of the empty area 400 are etched away using laser and other related processes to form the OLED display substrate with mounting holes in this embodiment of the present disclosure, such as... Figure 2As shown. In actual implementation, all structural film layers and substrates of the empty area 400 can be etched away to form through holes, or part of the structural film layers of the empty area 400 can be etched away to form blind holes, depending on actual needs. This disclosure does not impose specific limitations on the embodiments.

[0107] As can be seen from the structure and fabrication process of the display substrate disclosed herein, the display substrate provided herein, without changing the existing process flow, avoids interlayer splitting caused by thermal expansion of the film layer due to heat conduction at the cutting edge by spaced isolation pillars 203 around the empty area 400 and shrinking the stacked structure of the empty area 400 before cutting. This solves the problem of edge structure cracking caused by adhesive stress during the subsequent film peeling process. On the other hand, it also increases the contact area between the inorganic encapsulation layer and the polarizer (e.g., Figure 2 As shown, although there are gaps between the polarizer 38 and the second isolation dam 202b, as well as between the polarizer 38 and the isolation pillar 203, the polarizer 38 and the display substrate are actually fully bonded together by using a roller bonding method. This reduces the angle formed by the AA hole edge cutting, lowers the stress concentration at the AA hole cutting edge, and thus avoids the edge structure cracking caused by adhesive stress during the subsequent film peeling process, resulting in GDS problems.

[0108] Meanwhile, since the preparation process of this embodiment can be achieved using existing mature preparation equipment without changing the existing process flow, the process is simple to implement, easy to carry out, and has high production efficiency. It has the advantages of easy process implementation, low production cost and high yield, and has good application prospects.

[0109] The structure and fabrication process of the display substrate disclosed herein are merely illustrative examples. In actual implementation, the corresponding structure and patterning processes can be modified and added or reduced according to actual needs. For example, the OLED display substrate can be either a top-emitting structure or a bottom-emitting structure. Similarly, the thin-film transistor can be either a top-gate structure or a bottom-gate structure, and either a dual-gate structure or a single-gate structure. Furthermore, the thin-film transistor can be an amorphous silicon (a-Si) thin-film transistor, a low-temperature polycrystalline silicon (LTPS) thin-film transistor, or an oxide thin-film transistor. Other electrodes, leads, and structural films can also be disposed in the driving structure layer and the light-emitting structure layer; the embodiments disclosed herein do not impose specific limitations.

[0110] This disclosure also provides a method for fabricating a display substrate, the display substrate including a display area, a first transition region located in the display area, a second transition region located in the first transition region, and a void region located in the second transition region. Figure 13 As shown, the method for fabricating the display substrate disclosed herein includes:

[0111] S1, forming a buffer layer covering the substrate;

[0112] S2. An insulating layer covering the buffer layer is formed in the first transition zone, the second transition zone and the empty zone, and a patterning process is performed on the insulating layer in the second transition zone and the empty zone to form a first groove that exposes the buffer layer. The orthographic projection of the first groove on the substrate covers the orthographic projection of the second transition zone and the empty zone on the substrate.

[0113] S3. Multiple isolation dams are formed on the insulating layer, and multiple isolation pillars are formed in the first groove. The multiple isolation dams and multiple isolation pillars are arranged around the empty area.

[0114] In an exemplary embodiment, the isolation dam and the isolation column are arranged in the same layer, made of the same material, and formed by the same process; or, the isolation dam and the isolation column are not arranged in the same layer.

[0115] In an exemplary embodiment, the fabrication method further includes: forming a driving structure layer disposed on a substrate, a planarization layer disposed on the driving structure layer, and a pixel definition layer defining a pixel opening region in the display area;

[0116] The driving structure layer includes a buffer layer on a flexible substrate, an active layer on the buffer layer, a first insulating layer covering the active layer, a first gate electrode layer on the first insulating layer, a second insulating layer covering the first gate electrode layer, a second gate electrode layer on the second insulating layer, a third insulating layer covering the second gate electrode layer, and a first source / drain electrode layer on the third insulating layer.

[0117] The insulating layer includes a first insulating layer located on the buffer layer, a second insulating layer located on the first insulating layer, and a third insulating layer located on the second insulating layer.

[0118] In an exemplary embodiment, the plurality of isolation dams includes a plurality of first isolation dams and a plurality of second isolation dams. The first isolation dam includes a first dam foundation and a first protrusion, and the second isolation dam includes a second protrusion. The nearest distance between the first isolation dam and the vacant area is greater than the nearest distance between the second isolation dam and the vacant area.

[0119] The first dam foundation is set on the same layer as the flattening layer, and the first and second protrusions are defined on the same layer as the pixels.

[0120] In an exemplary embodiment, the isolation column includes a second dam base and a third protrusion, wherein the second dam base is disposed on the same layer as the planarization layer, and the third protrusion is disposed on the same layer as the pixel.

[0121] In an exemplary embodiment, the fabrication method further includes: forming a support pillar layer on the pixel definition layer; the isolation dam can be fabricated in the same layer as any one or more of the planarization layer, pixel definition layer and support pillar layer, and the isolation pillar can be fabricated in the same layer as any one or more of the planarization layer, pixel definition layer and support pillar layer.

[0122] This disclosure provides a method for fabricating a display substrate. By spaced the isolation pillars around the empty area and shrinking the stacked structure of the empty area before cutting, the interlayer splitting caused by thermal expansion of the film layer due to heat conduction at the cutting edge is avoided. This solves the problem of edge structure cracking caused by adhesive stress during subsequent film removal. On the other hand, it also increases the contact area between the inorganic encapsulation layer and the polarizer, reduces the angle formed by the cutting of the AA hole edge, and reduces the stress concentration at the cutting edge of the AA hole, thereby avoiding the edge structure cracking and GDS problem caused by adhesive stress during subsequent film removal. The fabrication process of this disclosure can be realized using existing mature fabrication equipment without changing the existing process flow. The process is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield.

[0123] This disclosure also provides a display device, including the display substrate of the foregoing embodiments, wherein the empty area of ​​the foregoing embodiments is used for mounting hardware structures, exemplarily including structures such as cameras. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0124] The accompanying drawings in this disclosure only illustrate the structures relevant to this disclosure; other structures can be referenced to common designs. Unless otherwise specified, embodiments of this disclosure, i.e., features within the embodiments, can be combined with each other to obtain new embodiments.

[0125] Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions disclosed herein without departing from the spirit and scope of the technical solutions disclosed herein, and all such modifications and substitutions should be covered within the scope of the claims of this disclosure.

Claims

1. A display substrate, comprising a display area, a first transition area located in the display area, a second transition area located in the first transition area, and an empty area located in the second transition area, wherein: The first transition region includes a substrate, a buffer layer disposed on the substrate, an insulating layer disposed on the buffer layer, a plurality of isolation dams disposed on the insulating layer, and an organic light-emitting layer and an encapsulation layer disposed on the plurality of isolation dams; The second transition region includes a substrate, a buffer layer disposed on the substrate, a plurality of isolation pillars disposed on the buffer layer, and an organic light-emitting layer and an encapsulation layer disposed on the plurality of isolation pillars; The plurality of isolation dams and the plurality of isolation pillars are all arranged around the void area. In a plane perpendicular to the substrate, the closest distance from the end of the isolation pillar away from the substrate to the void area is L1, and the closest distance from the end of the isolation pillar near the substrate to the void area is L2, where L1 > L2 > 0. The plurality of isolation dams includes a plurality of first isolation dams and a plurality of second isolation dams. The closest distance between the first isolation dam and the void area is greater than the closest distance between the second isolation dam and the void area. The first isolation dam includes a first dam base and a first protrusion, and the second isolation dam includes a second protrusion. The isolation pillar includes a second dam base and a third protrusion. The height of the end of the first isolation dam away from the substrate is greater than the height of the end of the second isolation dam away from the substrate, and the height of the end of the second isolation dam away from the substrate is greater than the height of the end of the isolation pillar away from the substrate. The lowest height of the organic light-emitting layer in the first transition area and the second transition area is greater than the height of the end of the isolation pillar near the substrate. The display substrate further includes a polarizer. In the first transition region, the polarizer is bonded to an encapsulation layer on the surface of the isolation dam away from the substrate. In the second transition region, the polarizer is bonded to an encapsulation layer on the surface of the isolation pillar away from the substrate.

2. The display substrate according to claim 1, wherein the display area includes a substrate, a driving structure layer disposed on the substrate, a planarization layer disposed on the driving structure layer, and a pixel definition layer defining a pixel opening area; The driving structure layer includes a buffer layer on the substrate, an active layer on the buffer layer, a first insulating layer covering the active layer, a first gate electrode layer on the first insulating layer, a second insulating layer covering the first gate electrode layer, a second gate electrode layer on the second insulating layer, a third insulating layer covering the second gate electrode layer, and a first source / drain electrode layer on the third insulating layer. The insulating layer includes a first insulating layer located on the buffer layer, a second insulating layer located on the first insulating layer, and a third insulating layer located on the second insulating layer. 3.The display substrate of claim 2, wherein, The first dam foundation is disposed on the same layer as the planarization layer, and the first protrusion and the second protrusion are disposed on the same layer as the pixel.

4. The display substrate according to claim 3, wherein, In a plane perpendicular to the substrate, the distance between the end of the second isolation dam near the substrate and the end of the isolation column near the substrate is 5 micrometers to 40 micrometers, and the distance between the end of the first isolation dam near the substrate and the end of the second isolation dam near the substrate is 10 micrometers to 40 micrometers.

5. The display substrate according to claim 2, wherein, The second dam foundation is disposed on the same layer as the planarization layer, and the third protrusion is disposed on the same layer as the pixel.

6. The display substrate according to any one of claims 1 to 5, wherein, In a plane perpendicular to the base, the width of the isolation post at the end furthest from the base is smaller than the width of the isolation post at the end closest to the base.

7. The display substrate according to claim 6, wherein, The closest distance between the end of the isolation column away from the substrate and the vacant area is 10 to 20 micrometers; the closest distance between the end of the isolation column near the substrate and the vacant area is 1 to 5 micrometers.

8. The display substrate according to any one of claims 1 to 5, wherein, In a plane perpendicular to the base, the width of the isolation dam at the end furthest from the base is smaller than the width of the isolation dam at the end closest to the base.

9. The display substrate according to claim 2, wherein the display area further includes a light-emitting structure layer disposed on the planarization layer and an encapsulation layer disposed on the light-emitting structure layer, the encapsulation layer including a first inorganic layer, a second inorganic layer and an organic encapsulation layer disposed between the first inorganic layer and the second inorganic layer, the first inorganic layer and the second inorganic layer both extending to the first transition region and the second transition region, and covering the plurality of isolation dams and the plurality of isolation pillars.

10. The display substrate according to claim 9, wherein the orthographic projection of the contact area between the second inorganic layer and the polarizer in the second transition region on the substrate is located within the range of the orthographic projection of the isolation pillar on the substrate, and in a plane parallel to the substrate, the area of ​​the contact area between the second inorganic layer and the polarizer in the second transition region is greater than or equal to the area of ​​the end of the isolation pillar away from the substrate.

11. A display device comprising a display substrate as described in any one of claims 1 to 10, wherein, The empty area is used for installing hardware structures.

12. A method for fabricating a display substrate, the display substrate comprising a display area, a first transition area located in the display area, a second transition area located in the first transition area, and a void area located in the second transition area, the fabrication method comprising: Forming a buffer layer covering the substrate; An insulating layer covering the buffer layer is formed in the first transition region, the second transition region, and the empty region. A patterning process is performed on the insulating layer of the second transition region and the empty region to form a first groove that exposes the buffer layer. The orthographic projection of the first groove on the substrate covers the orthographic projection of the second transition region and the empty region on the substrate. Multiple isolation dams are formed on the insulating layer, and multiple isolation pillars are formed in the first groove. The multiple isolation dams and multiple isolation pillars are arranged around the void area. In a plane perpendicular to the substrate, the closest distance between the end of the isolation pillar away from the substrate and the void area is L1, and the closest distance between the end of the isolation pillar near the substrate and the void area is L2, where L1 > L2 > 0. The multiple isolation dams include multiple first isolation dams and multiple second isolation dams. The closest distance between the first isolation dam and the void area is greater than the closest distance between the second isolation dam and the void area. The first isolation dam includes a first dam base and a first protrusion, the second isolation dam includes a second protrusion, and the isolation pillar includes a second dam base and a third protrusion. The height of the end of the first isolation dam away from the substrate from the substrate is greater than the height of the end of the second isolation dam away from the substrate from the substrate, and the height of the end of the second isolation dam away from the substrate from the substrate is greater than the height of the end of the isolation pillar away from the substrate from the substrate. An organic light-emitting layer and an encapsulation layer are formed on the isolation dam and the isolation pillar; the lowest height of the organic light-emitting layer in the first transition region and the second transition region is greater than the height of the isolation pillar near the substrate from the substrate. The polarizer is bonded in the first transition zone, where it is bonded to the encapsulation layer on the surface of the isolation dam away from the substrate, and in the second transition zone, it is bonded to the encapsulation layer on the surface of the isolation pillar away from the substrate.

13. The preparation method according to claim 12, further comprising: A driving structure layer, a planarization layer, and a pixel definition layer defining a pixel opening area are formed on the substrate in the display area. The driving structure layer includes a buffer layer on the substrate, an active layer on the buffer layer, a first insulating layer covering the active layer, a first gate electrode layer on the first insulating layer, a second insulating layer covering the first gate electrode layer, a second gate electrode layer on the second insulating layer, a third insulating layer covering the second gate electrode layer, and a first source / drain electrode layer on the third insulating layer. The insulating layer includes a first insulating layer located on the buffer layer, a second insulating layer located on the first insulating layer, and a third insulating layer located on the second insulating layer.

14. The preparation method according to claim 13, wherein, The first dam foundation is disposed on the same layer as the planarization layer, and the first protrusion and the second protrusion are disposed on the same layer as the pixel.

15. The preparation method according to claim 13, wherein, The second dam foundation is disposed on the same layer as the planarization layer, and the third protrusion is disposed on the same layer as the pixel.

Images