Multi-chip device

Abstract

Some examples described herein relate to a multi-chip device. In one example, the multi-chip device includes first and second chips (102, 104). The first chip (102) includes a power supply circuit (508) and a logic circuit (506). The first and second chips are coupled together. The second chip (104) is configured to receive a power supply from the power supply circuit (508). The second chip includes a programmable circuit (510), a pull-up circuit (PL), and a detection circuit (504). The detection circuit is configured to detect a presence of a power supply voltage on the second chip (104) and responsively output a presence signal (534-1). The power supply voltage on the second chip is based on the power supply from the power supply circuit. The logic circuit (506) is configured to generate a pull-up signal (540) based on the presence signal. The pull-up circuit is configured to receive the pull-up signal and configured to pull up a voltage of a node of the programmable circuit in response to the pull-up signal.

Description

Technical Field

[0001] Examples of this disclosure generally relate to multi-chip devices, and more specifically, to techniques for reducing contention current during power outages in multi-chip devices. Background Technology

[0002] Devices comprising multiple integrated circuit chips, including modules and / or packages, have been developed. These devices take many forms. By forming such devices, electronic devices can integrate multiple chips to form a device, where each chip can be manufactured using standard semiconductor processes, and then assembled and packaged to form a larger, more versatile device. By using different chips, semiconductor processes that are difficult to integrate can be separated in certain situations, such as when parts of one chip require high-temperature processing while parts of another chip cannot withstand high temperatures.

[0003] On the other hand, it allows for the construction of devices with different functionalities (e.g., some are field-programmable gate array (FPGA) chips while others are memory chips) into the same device with a smaller device size, more functionality, and lower power consumption. Semiconductor processes used for the chips can then be more focused on providing greater advantages to the device, such as improved chip performance, reduced costs, and increased manufacturing yield. Such devices can achieve other benefits as well. Summary of the Invention

[0004] Some of the examples described in this article generally involve multi-chip devices. More specifically, the examples described in this article involve techniques for reducing contention current during power-down of multi-chip devices.

[0005] The example described herein is a multi-chip device. The multi-chip device includes a first chip and a second chip. The first chip includes power supply circuitry and logic circuitry. The second chip is coupled to the first chip. The second chip is configured to receive power from the power supply circuitry. The second chip includes programmable circuitry, pull-up circuitry, and detection circuitry. The detection circuitry is configured to detect the presence of a power supply voltage on the second chip and output a presence signal in response. The power supply voltage on the second chip is based on the power supply from the power supply circuitry. The logic circuitry is configured to generate a pull-up signal based on the presence signal. The pull-up circuitry is configured to receive the pull-up signal and is configured to pull up the voltage of a node of the programmable circuitry in response to the pull-up signal.

[0006] Another example described in this paper is a method for operating a multi-chip device. Based on the detection of the presence of a power supply voltage on a first chip, a presence signal is generated by a detection circuit on the first chip. The power supply voltage on the first chip is based on a power supply circuit on a second chip. Logic circuitry on the second chip generates a pull-up signal in response to the presence signal. The voltage of a node in the programmable circuitry on the first chip is pulled up by the pull-up circuitry on the first chip in response to the pull-up signal.

[0007] Another example described herein is a multi-chip device. The multi-chip device includes a chip stack comprising multiple chips. The multiple chips include a first chip and a second chip. The first chip includes a power management module. The power management module includes power circuitry and logic circuitry. The power circuitry is configured to output power. The second chip includes a configurable interconnect network, configuration memory cells, detection circuitry, and pull-up circuitry. Each configuration memory cell has a memory node connected to a corresponding configurable element of the configurable interconnect network. The configuration memory cell is connected to the first power node. A first power supply voltage at the first power node is a power supply output based on the power supply circuitry. The detection circuitry is connected to the first power node and configured to detect the presence of the first power supply voltage at the first power node and output a presence signal in response. The logic circuitry is connected to the detection circuitry and configured to generate a pull-up signal at the pull-up node based on the presence signal. The pull-up circuitry is connected to the pull-up node and configured to pull up a link node of the configurable interconnect network to a second power supply voltage at the second power node in response to the pull-up signal. Each link node is connected between two or more configurable elements of the configurable interconnect network.

[0008] These and other aspects can be understood by referring to the following detailed explanation. Attached Figure Description

[0009] To gain a more detailed understanding of the features listed above, a more specific description of the brief overview can be obtained by referring to the example implementations, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only illustrate typical exemplary implementations and should not be considered as limiting the scope of the work.

[0010] Figure 1 It is based on the structure of some example multi-chip devices;

[0011] Figure 2 It is a description based on some examples. Figure 1 A block diagram illustrating the circuit diagram of an integrated circuit (IC) for a multi-chip device;

[0012] Figure 3 It is a simplified circuit diagram of configurable interconnect elements of a configurable interconnect network based on some examples;

[0013] Figure 4 The illustration shows an example configuration of a static random access memory (CRAM) cell based on some examples;

[0014] Figure 5 and 6 It is a chart that shows the signals and timings when the base chip and the structure chip are characterized at different process corners;

[0015] Figure 7It describes based on some examples. Figure 2 A block diagram of the circuit schematic for other details of the multi-chip device IC;

[0016] Figure 8 This is an explanation based on some examples. Figure 7 In the context of the circuit diagram, the base chip and the structural chip are characterized as signal and timing diagrams in fast-fast (FF) and slow-slow (SS) modes;

[0017] Figure 9 It is a circuit diagram based on at least a portion of a detection circuit from some examples;

[0018] Figure 10 It is a flowchart of a method for operating a multi-chip device based on some examples;

[0019] For ease of understanding, the same reference numerals are used where possible to denote common elements in the figures. It is anticipated that elements of one example can be beneficially incorporated into other examples. Detailed Implementation

[0020] Some of the examples described in this article typically involve multi-chip devices. More specifically, the examples described in this article relate to techniques for reducing contention current during power-down of multi-chip devices.

[0021] Typically, in some examples, one or more chips in a multi-chip device include a configurable interconnect network (e.g., which may be included in a field-gate programmable array (FPGA) or other programmable integrated circuit), configuration memory cells (e.g., configuration static random access memory (CRAM) cells), pull-up circuits, and one or more detection circuits. On each of the one or more chips, the configuration memory cell has a memory node connected to a corresponding configurable circuit or element of the configurable interconnect network. The configuration memory cell can be written to or programmed to configure the configurable circuit or element of the configurable interconnect network. The configuration memory cell is connected to a memory power node for powering the configuration memory cell. The pull-up circuit may include a transistor having source / drain terminals connected to the interconnect power node and a node of the configurable interconnect network (e.g., a node connected between two or more configurable circuits or elements). The transistor may have a gate connected to the pull-up node. The pull-up circuit is configured to pull up the voltage of the node of the configurable interconnect network to the voltage of the interconnect power supply. A first detection circuit is connected to the memory power node and configured to detect the presence of a memory power supply voltage on the memory power node. A second detection circuit may be connected to the interconnect power node and configured to detect the presence of an interconnect power supply voltage on the interconnect power node. The first and second detection circuits can be configured to detect the corresponding power supply voltage when the corresponding power supply voltage is higher than the trip voltage of the chip of the first and second detection circuits. The first and second detection circuits can be configured to output a memory power supply voltage presence signal and an interconnect power supply voltage presence signal, respectively. These signals can be logic low values ​​when the respective power supply voltage is lower than the chip's trip voltage, and can be logic high values ​​when the corresponding power supply voltage is higher than the chip's trip voltage.

[0022] Another chip in the multi-chip device includes a power management module, which includes power circuitry, one or more detection circuits, and logic circuitry. The power circuitry can generate power for one or more different power domains distributed across the chips of the multi-chip device. In some examples, the power circuitry generates interconnect power voltages applied to interconnect power nodes and memory power voltages applied to memory power nodes. In some examples, the power circuitry generates interconnect power voltages applied to interconnect power nodes and generates an intermediate auxiliary power voltage from which the memory power voltage applied to the memory power nodes is generated. The memory power voltage can be a regulated voltage generated from the intermediate auxiliary power voltage on each of one or more chips having a configurable interconnect network or on a chip having power circuitry. A first detection circuit is connected to, for example, the intermediate auxiliary power node and / or the memory power node, and is configured to detect the presence of power supply voltages on the intermediate auxiliary power node and / or the memory power node. A second detection circuit can be connected to the interconnect power node and is configured to detect the presence of interconnect power voltages on the interconnect power node. The first and second detection circuits can be configured to detect the corresponding power voltage when the corresponding power voltage is higher than the chip's trip voltage. The first and second detection circuits can be configured to output an intermediate auxiliary and / or memory power supply voltage presence signal and an interconnect power supply voltage presence signal, respectively, which can be logic low values ​​when the corresponding power supply voltage is lower than the chip's trip voltage and logic high values ​​when the corresponding power supply voltage is higher than the chip's trip voltage.

[0023] Logic circuitry is connected to various detection circuits and configured to receive various power supply voltage presence signals. The logic circuitry is configured to generate pull-up signals based on one or more of the power supply voltage presence signals. For example, the logic circuitry may include an AND gate (or similar logic) that performs a bitwise AND operation (or similar logic function) on the power supply voltage presence signals to generate pull-up signals. The pull-up signals are output to pull-up nodes on the architecture chip. The pull-up circuitry on the architecture chip can pull up the voltage of each node of the configurable interconnect network to the interconnect power supply voltage based on the pull-up signals.

[0024] As illustrated in the detailed example below, pull-up signals can be implemented using complementary interconnect power-on reset signals, and the logic circuitry can operate during a power-down sequence in a multi-chip device. During a power-down sequence, when any chip reaches its trip voltage, the pull-up signal (e.g., a complementary interconnect power-on reset signal) can align the nodes of the respective configurable interconnect network (e.g., by pulling up the node voltage). By aligning the nodes when any chip reaches its trip voltage, contention current in the configurable interconnect network can be reduced or avoided.

[0025] These and other examples are described below. As will be readily understood by one of ordinary skill in the art upon reading this disclosure, additional or other benefits may be obtained through various examples. The examples described below are set in a chip-stacked environment. Other examples can be implemented in any multi-chip device, such as where each chip is connected to an interposer via, for example, microbumps. Furthermore, although aspects are described in various circuit settings, other examples may be implemented in or in multiple different programmable circuits (e.g., different programmable integrated circuits). The examples provided herein are merely for the purpose of clearly understanding the aspects.

[0026] Various features are described below with reference to the accompanying drawings. It should be noted that the drawings may or may not be drawn to scale, and elements with similar structures or functions are indicated by similar reference numerals in all the drawings. It should be noted that the drawings are intended only to facilitate the description of features. They are not intended as an exhaustive description of the claimed invention or as a limitation on the scope of the claimed invention. Furthermore, the illustrated examples do not need to possess all the aspects or advantages shown. Aspects or advantages described in conjunction with a particular example are not necessarily limited to that example and can be practiced in any other example, even if not so stated or explicitly described. Moreover, the methods described herein may be described in a particular order of operations, but other methods according to other examples may be implemented in various other orders with more or fewer operations (e.g., including different sequential or parallel executions of various operations).

[0027] Figure 1 It is based on the structure of some example multi-chip devices. Figure 1 Multi-chip devices comprise chip stacks, including a base chip 102 and structural chips 104, 106, and 108. Various other multi-chip devices can have different structures, different numbers of chips, additional components, etc. Figure 1 In this configuration, chips 102-108 are stacked to form a chip stack in a multi-chip device. In some examples, chips 102-108 are stacked to form an active-on-chip (AoA) device. In some examples, such as those described below, more or fewer chips may be included in the chip stack. For example, one or more of the structural chips 104-108 may be removed from the chip stack or added to it.

[0028] Each of chips 102-108 includes a corresponding semiconductor substrate 112, 114, 116, 118 and a corresponding front-side dielectric layer 122, 124, 126, 128 on the front side of the corresponding semiconductor substrate 112-118. The front-side dielectric layers 122-128 include metallization layers (e.g., metal lines and / or vias) formed therein (illustrated but not specifically numbered), which can electrically connect various components in the integrated circuit. Each of chips 102-106 includes a back-side dielectric layer 132, 134, 136 on the back side of the corresponding semiconductor substrate 112-116. The back-side dielectric layers 132-136 include metallization layers (e.g., metal lines and / or vias) formed therein (illustrated but not specifically numbered), which can electrically connect various components in the integrated circuit. Each semiconductor substrate 112-118 of chips 102-108 includes, for example, transistors 142, 144, 146, 148 formed on and / or in the front surface of the respective semiconductor substrate 112-118. Transistors 142-148 and any other components may be connected to the metallization layer in the front dielectric layer 122-128. Each semiconductor substrate 112-116 of each chip 102-106 has a through back substrate via (TSV) 162, 164, 166 that can electrically connect the metallization layer in the front dielectric layer 122-126 to the metallization layer in the back dielectric layer 132-136 of the respective chip 102-106.

[0029] Front pads 152, 154, 156, 158 (e.g., metal (e.g., Cu) pads) are formed in the corresponding front dielectric layers 122-128 of chips 102-108, at the outer surface remote from the corresponding semiconductor substrates 112-118. The front pads 152-158 may be in an arrangement forming the corresponding chip-to-chip interface. The front pads 152-158 are connected to the metallization layer in the corresponding front dielectric layers 122-128. Back pads 174, 176 (e.g., metal (e.g., Cu) pads) are formed in the corresponding back dielectric layers 134, 136 of structure chips 104, 106, at the outer surface remote from the corresponding semiconductor substrates 114, 116. The back pads 174, 176 may be in an arrangement forming the corresponding chip-to-chip interface. The back pads 174, 176 are connected to the metallization layer in the corresponding back dielectric layers 134, 136.

[0030] External connector back pads 172 (e.g., metal (e.g., aluminum) pads) are formed in the back dielectric layer 132 of the base chip 102, on the outer surface of the semiconductor substrate 112, away from the base chip 102. The external connector back pads 172 are connected to a metallization layer in the back dielectric layer 132 of the base chip 102. A passivation layer 180 is formed on the outer surface of the semiconductor substrate 112, away from the base chip 102, having corresponding openings through which the external connector back pads 172 are exposed. External connectors 182 (e.g., controlled collapse chip connections (C4), microbumps, etc.) are formed on the respective external connector back pads 172 through openings in the passivation layer 180.

[0031] External connector 182 can be attached to the package substrate. The package substrate can be further bonded to, for example, a printed circuit board (PCB) to bond the package substrate (and therefore the multi-chip device) to the PCB. Various other components may be included in the multi-chip device. For example, interposers, sealants (e.g., molding compounds (MUFs), etc.) may be included in the multi-chip device. Various modifications that can be made to the multi-chip device will be readily apparent to those skilled in the art.

[0032] Chips 102-108 are bonded together (e.g., by using a hybrid bonding method of metal-to-metal and oxide-to-oxide bonding) to form a chip stack. Reference Figure 1 The base chip 102 is bonded to the structure chip 104 from front to front, such that the front bonding pad 152 and the outer surface of the front dielectric layer 122 of the base chip 102 are bonded to the front bonding pad 154 and the outer surface of the front dielectric layer 124 of the structure chip 104. The structure chip 104 is bonded to the structure chip 106 from back to front, such that the outer surface of the back bonding pad 174 and the back dielectric layer 134 of the structure chip 104 are bonded to the outer surface of the front bonding pad 156 and the front dielectric layer 126 of the structure chip 106. The structure chip 106 is bonded to the structure chip 108 from back to front, such that the outer surface of the back bonding pad 176 and the back dielectric layer 136 of the structure chip 106 are bonded to the front bonding pad 158 and the front dielectric layer 128 of the outer surface structure chip 108.

[0033] Other bonding methods can also be implemented. Various arrangements of front-to-back, front-to-front, and back-to-back bonding are possible. In other examples, chips 102-108 can be attached together using external connectors (e.g., microbumps, solder, etc.). In some examples, some of chips 102-108 can be attached together using external connectors, while others can be bonded together without using external connectors. Any arrangement of external connector bonding and use is possible.

[0034] In some examples, chips 102-108 are manufactured on different wafers and through different processes. For example, base chip 102 is manufactured on a base wafer along with multiple other base chips, and each structural chip 104-108 is manufactured on a corresponding structural wafer along with other structural chips. For example, the base wafer can be manufactured using a device (e.g., a transistor) having a thick oxide layer included in the gate dielectric, and the structural wafer can be manufactured using a device (e.g., a transistor) having a thin oxide layer included in the gate dielectric. The base wafer is bonded to a first structural wafer such that base chip 102 is aligned with and bonded to structural chip 104. The first structural wafer is bonded to a second structural wafer such that structural chip 106 is bonded to structural chip 108. The second structural wafer is bonded to a third structural wafer such that structural chip 106 is bonded to structural chip 108. Bonding can be performed in any suitable order.

[0035] Because chips 102-108 undergo different processing steps, they can be characterized at different process corners. For example, for a given chip, each advantage of n-type and p-type transistors can be characterized as fast (F), typical (T), and slow (S), allowing each chip to be characterized by such advantages. For instance, a chip characterized as "FF" is a chip with very fast n-type and p-type transistors (overall), or a chip characterized as "TS" is a chip with typical (or nominal) speed n-type transistors (overall) and very slow speed p-type transistors (overall). As described in more detail below, chips integrated into multi-chip devices at different process corners can lead to contention for current.

[0036] Figure 2 It describes based on some examples, Figure 1 A block diagram illustrating the circuit diagram of a multi-chip device, a stacked integrated circuit (IC). In the example shown, the multi-chip device is a multi-chip programmable device. Various components of the IC, chips 102-108, are... Figure 1 As shown in the text, and regarding Figure 1 The other components of chips 102-108 are shown in the following figures and described with respect to them.

[0037] In the example shown, base chip 102 includes a base IC on base chip 102, which can be a SoC. Structure chips 104-108 each include a programmable logic (PL) IC 220, which is the same IC. Other ICs (e.g., with other hard IP blocks) can be implemented in the chip. More generally, although structure chips 104-108 are illustrated and described as having PL IC 220, other examples besides or in lieu of structure chips 104-108 can implement one or more different chips, wherein such one or more chips have any programmable IC.

[0038] The basic IC on the base chip 102 includes a processing system 202, input / output (I / O) circuitry 204, IP core circuitry 206, on-chip network (NoC) 210, and Z-interface 216. The processing system 202 can be or includes any of a variety of different processor types and processor core numbers. For example, the processing system 202 can be implemented as a single processor, such as a single core capable of executing program instruction code. In another example, the processing system 202 can be implemented as a multi-core processor. The processing system 202 can be implemented using any of a variety of different architectures. Example architectures that can be used to implement the processing system 202 include ARM processor architecture, x86 processor architecture, graphics processing unit (GPU) architecture, mobile processor architecture, reduced instruction set computer (RISC) architecture (e.g., RISC-V), or other suitable architectures capable of executing computer-readable program instruction code.

[0039] Input / output circuitry 204 may include extreme performance input / output (XPIO), multi-gigabit transceivers (MGT), high-bandwidth memory (HBM) interfaces, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), or any other input / output modules. Input / output circuitry 204 may be configured to receive and / or transmit signals to circuitry external to the multi-chip device. IP core circuitry 206 may include memory controllers (e.g., Double Data Rate (DDR) memory controllers, High-Bandwidth Memory (HBM) memory controllers, etc.), peripheral component interconnect fast (PCIe) interfaces, cached coherent interconnect (CCIX) interfaces for accelerators, Ethernet cores (e.g., media address controllers (MACs), etc.), forward error correction (FEC) blocks, and / or any other hardened circuitry. Any input / output circuitry 204 and / or IP core circuitry 206 may be programmable.

[0040] NoC 210 includes a programmable network 212 and NoC peripheral interconnects (NPIs) 214. The programmable network 212 communicatively couples the subsystems of the base IC on the base chip 102 with any other circuitry. The programmable network 212 includes NoC packet switches and interconnects connecting the NoC packet switches. Each NoC packet switch performs NoC packet switching within the programmable network 212. The programmable network 212 has interface circuitry at its edges. The interface circuitry includes NoC master units (NMUs) and NoC slave units (NSUs). Each NMU is an entry circuit connecting master circuitry to the programmable network 212, and each NSU is an exit circuit connecting the programmable network 212 to slave endpoint circuitry. The NMUs are communicatively coupled to the NSUs via the NoC packet switches and interconnects of the programmable network 212. The NoC packet switches are interconnected and connected to the NMUs and NSUs via interconnects to implement multiple physical channels 212 within the programmable network. NoC packet switches, NMUs, and NSUs include register blocks that determine the operation of the respective NoC packet switch, NMU, or NSU.

[0041] NPI 214 includes circuitry for writing register blocks that determine the functionality of the NMU, NSU, and NoC packet switches. NPI 214 includes peripheral interconnects coupled to the register blocks for programming them to configure their functionality. The register blocks in the NMU, NSU, and NoC packet switches of programmable network 212 support interrupts, Quality of Service (QoS), error handling and reporting, transaction control, power management, and address mapping control. NPI 214 may include an NPI root node residing on processing system 202 (e.g., the Platform Management Controller (PMC) of processing system 202), interconnect NPI switches connected to the NPI root node, and protocol block switches and corresponding register blocks connected to the interconnect NPIs. NPI 214 can be used to program any programmable circuitry of the underlying IC on base chip 102. For example, NPI 214 can be used to program any programmable input / output circuitry 204 and / or IP core circuitry 206.

[0042] Z-interface 216 may be a passive interconnect or may include active circuitry, such as a buffer for drive signals. Z-interface 216 provides the NoC 210's processing system 202, input / output circuitry 204, IP core circuitry 206, and programmable network 212 with an interface to a chip overlaid on the base chip 102, including through-hole metal lines and through-holes 102 in the metallization layer.

[0043] The various subsystems and circuits of the base IC on base chip 102 are communicatively coupled. As shown, processing system 202, input / output circuitry 204, and IP core circuitry 206 are connected to NoC 210 (e.g., to programmable network 212) and are therefore communicatively coupled to each other. Processing system 202 is also connected to NPI 214 for transferring configuration data to various programmable components on base chip 102. Processing system 202 is also connected to programmable network 212 of NoC 210 for transferring configuration data to chips on base chip 102. Programmable network 212 of NoC 210 is connected to Z-interface 216, allowing data such as transaction data and configuration data to be transferred to another chip via Z-interface 216. Each of processing system 202, input / output circuitry 204, and IP core circuitry 206 is connected to Z-interface 216 for direct communication with programmable logic in PL IC 220, for example, in overlay structure chips 104-108. It can enable other communication mechanisms between various subsystems and circuits, such as direct connections.

[0044] Each PL IC 220 on each of the structure chips 104-108 includes one or more programmable logic regions. A programmable logic region is a logic circuit that can be programmed to perform a specified function. A programmable logic region can include any number or arrangement of programmable blocks. As an example, a programmable logic region can be implemented as an FPGA structure. For example, a programmable logic region can include any number of configurable logic blocks (CLBs), lookup tables (LUTs), digital signal processing blocks (DSPs), random access memory blocks (BRAMs), etc. Each programmable block (e.g., CLB, LUT, DSP, BRAM, etc.) can include one or more programmable interconnect elements. For example, various corresponding types of programmable blocks can be arranged in rows and / or columns, and associated programmable interconnect elements can be connected to adjacent programmable logic elements in the same column and row. Programmable interconnect elements can be interconnected to form a configurable interconnect network for the programmable logic region. Any logic and connections can be implemented by the programmable logic region through programming or configuring any programmable blocks within the programmable logic region.

[0045] Each PL IC 220 may also include a configuration interconnect that includes a configuration frame (CFRAME) driver. The CFRAME driver may be or include control logic to transmit configuration data (e.g., a bitstream) to configure the programmable logic. Each programmable logic region can be configured or programmed via configuration data received via Z interface 216. For example, processing system 202 (e.g., the PMC of processing system 202) can transmit configuration data via programmable network 212 of NoC 210. In some examples, the configuration interconnect (e.g., including a CFRAME driver) can direct configuration data to the appropriate programmable block and control the configuration of such programmable blocks.

[0046] PL IC 220 and / or structure chips 104-108 may include communication paths for transmitting signals between lower and upper layer chips. For example, the communication path may be a passive communication path, such as a metallization layer and a TSV (Transmission Signal Vessel) through a given chip. In some examples, active circuitry, such as buffers or drivers, may be included in the communication path. In some examples, the active circuitry may be programmable to configure, for example, the directionality of signal communication, such as through a tri-state buffer.

[0047] In the various circuits described below, reference identifiers can be added to nodes and / or signals on those nodes. Those skilled in the art will readily understand this interchangeability of reference identifiers and will understand from the context whether such a reference identifier refers to a node or a signal. Furthermore, references to low or high signals refer to signals having logic low or logic high values, respectively.

[0048] Figure 3 This is a simplified circuit diagram of configurable interconnect elements (e.g., for each PL IC220) based on some examples of configurable interconnect networks. The configurable interconnect network can be or be included in programmable circuitry, such as an FPGA, a complex programmable logic device (CPLD), a programmable logic array (PLA), etc. The configurable interconnect network described above as part of the PL IC220 can be or include an FPGA. Figure 3 A first interconnect node 302-1, a second interconnect node 302-2, and a multiplexer node 304 are shown. The circuitry within the first interconnect node 302-1 and the second interconnect node 302-2 is generally identical; therefore, a generic interconnect node is described herein. Components typically described but appended with "-1" in the figures (or described below) are for the first interconnect node 302-1, and components appended with "-2" in the figures (or described below) are for the second interconnect node 302-2. The first interconnect node 302-1 and the second interconnect node 302-2 are generally referred to individually or collectively as interconnect node 302.

[0049] Interconnect node 302 includes transmission gates 312, 314, 316, and 318. Each transmission gate 312-318 includes n-type and p-type transistors connected in parallel. Each transmission gate 312-318 has an input / output node connected to link node 310. Each transmission gate 312-316 also has another input / output node connected to another (e.g., adjacent) interconnect node 302 or multiplexer node 304. Transmission gate 318 has another input / output node connected to a logic node LOGIC of a programmable logic element, such as a configurable logic element (CLE), a BRAM logic element (BRL), a DSP logic element (DSPL), or an input / output logic element (IOL). The gate of each transmission gate 312-318 is connected to a complementary memory node of a corresponding configurable static random access memory (CRAM) cell of interconnect node 302. The gate of the n-type transistor of transmission gate 312 is connected to memory node Q0 of CRAM cell C0, and the gate of the p-type transistor of transmission gate 312 is connected to complementary memory node Q0B of CRAM cell C0. The gate of the n-type transistor of transmission gate 314 is connected to memory node Q1 of CRAM cell C1, and the gate of the p-type transistor of transmission gate 314 is connected to complementary memory node Q1B of CRAM cell C1. The gate of the n-type transistor of transmission gate 316 is connected to memory node Q2 of CRAM cell C2, and the gate of the p-type transistor of transmission gate 316 is connected to complementary memory node Q2B of CRAM cell C2. The gate of the n-type transistor of transmission gate 318 is connected to memory node Q3 of CRAM cell C3, and the gate of the p-type transistor of transmission gate 318 is connected to complementary memory node Q3B of CRAM cell C3.

[0050] Multiplexer node 304 includes transmission gates 322, 324, 326, 328, p-type transistors 330, 340, 342, 344, 346, and inverters 350, 352. Each transmission gate 312-318 includes n-type and p-type transistors connected in parallel. Each transmission gate 322-328 has an input / output node connected to link node 320. Each transmission gate 322-328 also has another input / output node connected to another (e.g., adjacent) interconnect node 302 or multiplexer node 304. The gate of each of transmission gates 322-328 is connected to the complementary memory node of the corresponding CRAM cell of multiplexer node 304. The gate of the n-type transistor of transmission gate 322 is connected to memory node Q0 of CRAM cell C0, and the gate of the p-type transistor of transmission gate 322 is connected to complementary memory node Q0B of CRAM cell C0. The gate of the n-type transistor in transmission gate 324 is connected to memory node Q1 of CRAM cell C1, and the gate of the p-type transistor in transmission gate 324 is connected to the complementary memory node Q1B of CRAM cell C1. The gate of the n-type transistor in transmission gate 326 is connected to memory node Q2 of CRAM cell C2, and the gate of the p-type transistor in transmission gate 326 is connected to the complementary memory node Q2B of CRAM cell C2. The gate of the n-type transistor in transmission gate 328 is connected to memory node Q3 of CRAM cell C3, and the gate of the p-type transistor in transmission gate 328 is connected to the complementary memory node Q3B of CRAM cell C3.

[0051] The source of p-type transistor 330 is connected to the interconnect power node VCC_INT, and the drain of p-type transistor 330 is connected to the link node 320. The gate of p-type transistor 330 is connected to the complementary interconnect power-on reset node POR_INT_B. P-type transistors 340-346 are connected in series. The source of p-type transistor 340 is connected to the interconnect power node VCC_INT. The drain of p-type transistor 340 is connected to the source of p-type transistor 342. The drain of p-type transistor 342 is connected to the source of p-type transistor 344. The drain of p-type transistor 344 is connected to the source of p-type transistor 346. The drain of p-type transistor 346 is connected to the link node 320. The gates of p-type transistors 340-346 are connected to the complementary memory nodes Q0B-Q3B of the CRAM cells C0-C3 of the multiplexer node 304. Inverters 350 and 352 are connected in series. The input node of inverter 350 is connected to link node 320, and the output node of inverter 350 is connected to the input node of inverter 352.

[0052] Interconnect nodes 302 and multiplexer nodes 304 are shown to illustrate aspects of the examples herein. A plurality of interconnect nodes 302 are typically included in a configurable interconnect network of a PL IC. The connection between link node 310-1 of the first interconnect node 302-1 and the input / output node of transmission gate 316-2 of the second interconnect node 302-2 illustrates a number of connections that can be implemented between adjacent interconnect nodes 302. Multiple multiplexer nodes 304 may be interleaved within the interconnect nodes 302 in the configurable interconnect network. Multiplexer nodes 304 may be connected to adjacent interconnect nodes 302, as shown in the connection between link node 310-2 of the second interconnect node 302-2 and the input / output node of transmission gate 328. Furthermore, multiplexer nodes 304 may be connected to provide feedback to interconnect nodes 302, as shown in the connection between the output node of inverter 352 of multiplexer node 304 and the input / output node of transmission gate 314-2 of the second interconnect node 302-2. For the sake of simplicity and clarity, many details of the various interconnect nodes 302 and multiplexer nodes 304 have been omitted.

[0053] Figure 4 Example CRAM cell 400 is illustrated. CRAM cell 400 illustrates a CRAM cell for interconnect node 302 and multiplexer node 304. CRAM cell 400 includes cross-coupled inverters 410 and 412 and transmission gate transistors 414 and 416. The input node of inverter 410 and the output node of inverter 412 are connected together to form a memory node QX. The output node of inverter 410 and the input node of inverter 412 are connected together to form a complementary memory node QXB. Inverters 410 and 412 are connected to the CRAM power node VCC_RAM for power supply.

[0054] The source / drain of transmission gate transistor 414 is connected to the data line node DX, and the other source / drain of transmission gate transistor 414 is connected to the memory node QX. The source / drain of transmission gate transistor 416 is connected to the complementary data line node DXB, and the other source / drain of transmission gate transistor 416 is connected to the complementary memory node QXB. The gates of transmission gate transistors 414 and 416 are connected to the address node A.

[0055] The complementary interconnect power-on reset signal POR_INT_B can be generated on the base chip 102 (e.g., via a power management module (PMM)). This complementary interconnect power-on reset signal POR_INT_B then propagates from the base chip 102 to the structure chips 104-108 and is assigned to the complementary interconnect power-on reset node POR_INT_B of the multiplexer node 304 in the configurable interconnect network. When the complementary interconnect power-on reset signal POR_INT_B is low during the power-on and power-off sequences, it can cause link nodes 310 (via feedback) and 320 to be pulled up to the interconnect power supply voltage VCC_INT. For example, a low complementary interconnect power-on reset signal POR_INT_B can cause p-type transistor 330 to become closed or on, thereby pulling link node 320 up to the interconnect power supply voltage VCC_INT, which can be fed back to other link nodes 310 via inverters 350 and 352. Therefore, p-type transistor 330 can be referred to as a pull-up circuit. It can also be used to implement other pull-up circuits.

[0056] By pulling link nodes 310 and 320 up to the interconnect power supply voltage VCC_INT, the voltage drop between link nodes 310 and 320, which would cause high contention current through the connected transmission gate, can be reduced or eliminated. For example, without pulling link nodes 310 and 320 up to the interconnect power supply voltage VCC_INT, contention current would occur when (i) the logic node LOGIC to which interconnect node 302 is connected is at a different voltage and (ii) the CRAM power node VCC_RAM drops below the trip voltage of the corresponding chip during a power-down sequence, so that the signal of the complementary memory node QXB becomes low enough to allow the p-type transistor of the transmission gate to be turned on.

[0057] If the complementary interconnect power-on reset signal POR_INT_B is generated solely based on conditions detected on the base chip 102, then in some cases, the complementary interconnect power-on reset signal POR_INT_B may not be low when link nodes 310, 320 should be pulled up to the interconnect power supply voltage VCC_INT. This typically occurs when the base chip 102 is characterized by a faster process corner than any of the structure chips 104-108.

[0058] Figure 5 and 6 It displays the signals and timings when the characteristics of the base chip and any chip architecture lie at different process corners. Figure 5 The basic chip is characterized by slow-slow (SS), while the structural chip is characterized by fast-fast (FF). Figure 6In the above examples, the base chip is characterized as fast-fast (FF), and the structure chip is characterized as slow-slow (SS). In these examples, the power-on reset signal POR and the complementary interconnect power-on reset signal POR_INT_B are generated solely based on conditions detected on the base chip.

[0059] Figure 5 and Figure 6 The diagram illustrates the rise of the supply voltage VCC during the power-on sequence and its fall during the power-off sequence. As VCC rises during power-on, it delivers a fast trip voltage VTRIPF (e.g., 0.25V) at time T1, followed by a slow trip voltage VTRIPS (e.g., 0.53V) at time T2. As VCC falls during power-off, it delivers a slow trip voltage VTRIPS at time T3, followed by a fast trip voltage VTRIPF at time T4. Typically, transistors in chips classified as fast have a lower threshold voltage Vt than transistors in chips classified as slow. t Therefore, chips classified as fast will start operating at a lower voltage when powered on and will trip at a lower voltage when powered off. Conversely, chips classified as slow will trip at a higher voltage when powered on and will trip at a higher voltage when powered off.

[0060] Figure 5 and 6 The presence signal BAS_VCC_X_PRES of the universal supply voltage for the base chip during the power-on and power-off sequences is shown when the base chip is characterized as slow-slow (SS) and fast-fast (FF), respectively. The universal supply voltage presence signal BAS_VCC_X_PRES is universal for any supply voltage on the base chip and is typically used to illustrate various aspects of the power-on and power-off sequences. Figure 5 The presence of the general power supply voltage signal BAS_VCC_X_PRES on the base chip indicates that the power supply voltage VCC is high enough to turn on the base chip during power-on at time T2, and low enough to trip the base chip during power-off at time T3. Figure 5 The underlying chip in the circuit switches on / off at a relatively high, slow trip voltage VTRIPS because the underlying chip is characterized by a slow-slow switching behavior. Figure 6 The presence of the general power supply voltage signal BAS_VCC_X_PRES indicates that the power supply voltage VCC is high enough to turn on the base chip during the power-on period at time T1, and low enough to turn off the base chip during the power-off period at time T4. Figure 6 The underlying chip is turned on / off at a relatively low fast trip voltage VTRIPF because the underlying chip is characterized by fast-fast switching.

[0061] Figure 5 and 6 The presence signal FAB_VCC_X_PRES of the general supply voltage for the structure chip during the power-on and power-off sequences is shown when the structure chip is characterized as fast-fast (FF) and slow-slow (SS), respectively. The general supply voltage presence signal FAB_VCC_X_PRES is universal for any supply voltage on the structure chip and is typically used to describe various aspects of the power-on and power-off sequences. Figure 5 The presence of the general power supply voltage signal FAB_VCC_X_PRES on the structure chip indicates that the power supply voltage VCC is high enough to enable the structure chip during power-on at time T1 and low enough to disable the structure chip during power-off at time T4. Figure 5 The chip in the structure is turned on / off with a relatively low fast trip voltage VTRIPF because the structure chip is characterized by fast-fast switching. Figure 6 The general power supply voltage presence signal FAB_VCC_X_PRES for the structure chip indicates that the power supply voltage VCC is high enough to turn on the structure chip during the power-on period at time T2, and low enough to turn off the structure chip during the power-off period at time T3. Figure 6 The structure chip in the middle is turned on / off at a higher slow trip voltage VTRIPS because the structure chip is characterized by slow-slow.

[0062] Figure 5 and 6 The power-on reset signal POR is also shown. In these diagrams, the power-on reset signal POR is detected and / or generated only at the base chip. The power-on reset signal POR typically tracks the supply voltage VCC until VCC exceeds the trip voltage of the base chip, at which point the power-on reset signal POR goes low. Figure 5 As shown, the power-on reset signal POR tracks the power supply voltage VCC until time T2 when the base chip is triggered (as indicated by the base chip general power supply voltage presence signal BAS_VCC_X_PRES). It remains low from time T2 to time T3, and at time T3, as the base chip is turned off (as indicated by the base chip general power supply voltage presence signal BAS_VCC_X_PRES), it switches to track the power supply voltage VCC. Figure 6 As shown, the power-on reset signal POR tracks the power supply voltage VCC until time T1 when the base chip is triggered (as indicated by the base chip general power supply voltage presence signal BAS_VCC_X_PRES). It remains low from time T1 to time T4, and at time T4, as the base chip is turned off (as indicated by the base chip general power supply voltage presence signal BAS_VCC_X_PRES), it switches to track the power supply voltage VCC.

[0063] Figure 5 and 6 The complementary interconnect power-on reset signal POR_INT_B is further illustrated. During the power-on sequence, the complementary interconnect power-on reset signal POR_INT_B is generated based on a specified sequence of a state machine that controls the sequence of boosting different power domains to the supply voltage. During this power-on sequence, the complementary interconnect power-on reset signal POR_INT_B is typically low. It is assumed that the complementary interconnect power-on reset signal POR_INT_B is provided in... Figure 3 At the complementary interconnect power-on reset node POR_INT_B, when the complementary interconnect power-on reset signal POR_INT_B is low, the link nodes 310 and 320 in the configurable interconnect network are pulled up to the voltage of the interconnect power supply node VCC_INT. At the end of the power-on sequence, the complementary interconnect power-on reset signal POR_INT_B is released and transitions to a high level (between time T2 and time T3). Typically, the timing of the power-on sequence can indicate the timing of the transition of the complementary interconnect power-on reset signal POR_INT_B between time T2 and time T3.

[0064] exist Figure 5 and 6 During the power-down sequence, the complementary interconnect power-on reset signal POR_INT_B tracks the presence of the base chip's general-purpose power supply voltage signal BAS_VCC_X_PRES. Therefore, in Figure 5 In the process, the complementary interconnect power-on reset signal POR_INT_B transitions to a low level at time T3 (e.g., when the base chip trips during a power-off period), and... Figure 6 In this process, the complementary interconnect power-on reset signal POR_INT_B transitions to a low level at time T4 (e.g., when the base chip trips during a power outage).

[0065] exist Figure 5 In the scenario shown, high contention current may not occur in the configurable interconnect network. Note that immediately before power-off, it is assumed that the configurable interconnect network is configured to operate (e.g., according to the user design), and there is no contention current in the configurable interconnect network. Because the structure chip is characterized by fast-fast behavior and its transistors typically have low threshold voltages, the interconnect chip can maintain its operating state and configuration after time T3, at which point the base chip generates a low complementary interconnect power-on reset signal POR_INT_B. Figure 5The low complementary interconnect power-on reset signal POR_INT_B at time T3 causes link nodes 310 and 320 in the configurable interconnect network to be pulled up to the interconnect power node VCC_INT via transistor 330 and feedback. This prevents or reduces voltage drops between different link nodes 310 and 320. Reduced or no voltage drops between different link nodes 310 and 320 avoid high contention currents through the transmission gates connected between these link nodes.

[0066] exist Figure 6 In the scenario shown, high contention currents may occur in the configurable interconnect network. In this case, the configurable interconnect network of the structure chip may lose its configuration before the complementary interconnect power-on reset signal POR_INT_B goes low. Because the base chip is characterized by fast-fast behavior and its transistors typically have low threshold voltages, the base chip will not transition the complementary interconnect power-on reset signal POR_INT_B low until the supply voltage VCC is at a low fast-trip voltage VTRIPF at time T4. However, because the structure chip is characterized by slow-slow behavior and its transistors typically have high threshold voltages, the signals on the complementary memory nodes QX and QXB of the CRAM cell may drop below the threshold voltage of the corresponding transmission gate transistor, and after time T3 (therefore, the structure chip trips at time T3, as indicated by the structure chip general supply voltage presence signal FAB_VCC_X_PRES). When the signals on the complementary memory nodes QX and QXB drop below the threshold voltage of the transmission gate transistor, the p-type transistor of the transmission gate may be in the on state. If the voltage at the logic node LOGIC of the transmission gate 318 connected to interconnect node 302 is different (e.g., due to the continuous voltage from the aforementioned configuration of the programmable logic element), a voltage drop may exist between the nodes to which one or more transmission gates are connected. This voltage drop can cause high contention current to flow through the intermediate transmission gates, which can burn out these gates and damage the chip structure. Such contention current may occur between time T3 when the complementary interconnect power-on reset signal POR_INT_B is high and time T4 when the complementary interconnect power-on reset signal POR_INT_B transitions to low and link nodes 310, 310 are pulled up by p-type transistor 330.

[0067] Figure 7 It describes based on some examples. Figure 2A block diagram illustrating the circuit schematic of the multi-chip device's stacked ICs. The base chip 102 includes a power management module (PMM) 502. The PMM 502 may be included in the processing system 202 in some examples, and outside the processing system in others. The PMM 502 includes detection circuitry 504, logic circuitry 506, and power supply circuitry 508. The PL ICs 220 of the structure chips 104-108 each include detection circuitry 504 and interconnect networks and programmable logic (INT / PL) 510 (e.g., structure).

[0068] Power supply circuit 508 is used to output electrical power to chips 102-108. Power supply circuit 508 is also configured to generate and regulate the power supply voltage of one or more power domains of the chip stack. Power supply circuit 508 distributes this power throughout the chip stack through metal layers and / or TSVs in the various chips 102-108. Figure 7 A power supply circuit 508 is shown, connected via a first power node 520 and a second power node 522 to the detection circuit 504 in the INT / PL 510 and PMM 502 of the structure chips 104-108. In some examples, the power supply circuit 508 may allocate an interconnect power supply voltage VCC_INT on the first power node 520 and a CRAM power supply voltage VCC_RAM on the second power node 522. In such an example, the first power node 520 may be the interconnect power node VCC_INT, and the second power node 522 may be the CRAM power node VCC_RAM. In other examples, the power supply circuit 508 may allocate an interconnect power supply voltage VCC_INT on the first power node 520 and an auxiliary power supply voltage VCC_AUX on the second power node 522. In such an example, the first power node 520 may be the interconnect power node VCC_INT, and the second power node 522 may be the auxiliary power node VCC_AUX. Each architecture chip 104-108 may include power conversion circuitry to generate a regulated CRAM power supply voltage VCC_RAM from the auxiliary power supply voltage VCC_AUX and to distribute the CRAM power supply voltage VCC_RAM to the CRAM power node VCC_RAM on the corresponding architecture chip 104-108. When powered on and operating, the CRAM power supply voltage VCC_RAM may be greater than the interconnect power supply voltage VCC_INT and / or the auxiliary power supply voltage VCC_AUX. The interconnect power node VCC_INT and the CRAM power node VCC_RAM are connected to the configurable interconnect network of the INT / PL 510, such as... Figure 3 and 4 As shown.

[0069] The detection circuit 504 on each of the structure chips 104-108 is connected to the interconnect power node VCC_INT and the CRAM power node VCC_RAM on their respective chips 102-108 to detect when the interconnect power voltage VCC_INT and the CRAM power voltage VCC_RAM are high enough to enable the corresponding structure chip 104-108 to operate. The detection circuit 504 on the base chip 102 is connected to the first power node 520 (e.g., the interconnect power node VCC_INT) and the second power node 522 (e.g., the CRAM power node VCC_RAM or the auxiliary power node VCC_AUX). The detection circuit 504 detects when the corresponding chip 102-108 is turned on and off. The detection circuit 504 of the base chip 102 is connected to the logic circuit 506 via the first power voltage presence node VCC_X_PRES 530 and the second power voltage presence node VCC_X_PRES 532. Each detection circuit 504 of the structure chips 104-108 is connected to the logic circuit 506 of the PMM 502 via corresponding interconnect power supply voltage presence nodes VCC_INT_PRES 534-1, 534-2, 534-3 and corresponding CRAM power supply voltage presence nodes VCC_RAM_PRES 536-1, 536-2, 536-3. The detection circuit 504 of the base chip 102 outputs corresponding first power supply voltage presentation signals VCC_X_PRES and second power supply voltage presentation signals VCC_X_PRES at the first power supply voltage presentation node VCC_X_PRES 530 and the second power supply voltage presentation node VCC_X_PRES 532, respectively. Each detection circuit 504 of the structure chips 104-108 outputs the corresponding interconnect power supply voltage presentation signal VCC_INT_PRES and CRAM power supply voltage presentation signal VCC_RAM_PRES at the interconnect power supply voltage present nodes VCC_INT_PRES 534-1, 534-2, 534-3 and the CRAM power supply voltage present nodes VCC_RAM_PRES 536-1, 536-2, 536-3.

[0070] Logic circuit 506 is connected to each power supply voltage presence node 530, 532, 534, 536. Logic circuit 506 may include NAND gates or similar logic circuitry to perform NAND operations on the power supply voltage presence signals VCC_X_PRES, VCC_INT_PRES, and VCC_RAM_PRES generated on chips 102-108 to generate a global power-on reset signal POR. The global power-on reset signal POR is output by logic circuit 506 at the global power-on reset node POR 540, which is connected to each INT / PL 510 of the structure chips 104-108. Logic circuit 506 may also include a logic state machine configured to implement power-on sequences and / or power-off sequences. In the power-on sequence, the logic state machine can generate a globally complementary interconnect power-on reset signal POR_INT_B based on the global power-on reset signal POR and any conditions of the state machine. In the power-down sequence, the logic state machine can generate a global complementary interconnect power-down reset signal POR_INT_B by inverting the global power-on reset signal POR. In some examples, the logic circuitry may include AND gates or similar logic circuitry to perform an AND operation on the power supply voltage presence signals VCC_X_PRES, VCC_INT_PRES, and VCC_RAM_PRES generated on chips 102-108 to generate the global complementary interconnect power-on reset signal POR_INT_B. The global complementary interconnect power-on reset signal POR_INT_B is output by logic circuitry 506 at the global complementary interconnect power-on reset node POR_INT_B 542, which is connected to each INT / PL510 of the structure chips 104-108. The complementary interconnect power-on reset node POR_INT_B 542 is connected to the gate of the p-type transistor 330 in the multiplexer node 304 of the configurable interconnect network of the INT / PL510. Therefore, the pull-up circuit of the configurable interconnect network can pull up the voltage of link nodes 310 and 320 in response to the complementary interconnect power-on reset signal POR_INT_B on the global complementary interconnect power-on reset node POR_INT_B 542.

[0071] Figure 8 It is based on some examples to illustrate that Figure 7 In the context of the circuit diagram, the basic chip and the structural chip are characterized as signal and timing diagrams in fast-fast (FF) and slow-slow (SS) modes. Figure 8In the diagram, the general power supply voltage presence signal FAB_VCC_X_PRES of the structural chips refers to any interconnect power supply voltage presence signal VCC_INT_PRES and / or CRAM power supply voltage presence signal VCC_RAM_PRES generated by any structural chips 104-108, and the general power supply voltage presence signal BAS_VCC_X_PRES of the base chips refers to either the first or second power supply voltage presence signal VCC_X_PRES generated by the base chip 102. Figure 8 As shown, in the power-down sequence, the global power-on reset signal POR has a transition aligned with the slowest chip, which is the structure chip indicated by the general power supply presence signal FAB_VCC_X_PRES of the structure chip that trips at the slow trip voltage VTRIPS. The power-on reset signal POR is generated by performing a NAND operation on the structure chip general power supply voltage presence signal FAB_VCC_X_PRES and the base chip general power supply voltage presence signal BAS_VCC_X_PRES to align the power-on reset signal POR with the slowest chip. Furthermore, in the power-down sequence, the global complementary interconnect power-on reset signal POR_INT_B has a transition aligned with the slowest chip. The global complementary interconnect power-on reset signal POR_INT_B is generated by inverting the global power-on reset signal POR or by performing an AND operation on the structure chip general power supply voltage presence signal FAB_VCC_X_PRES and the base chip general power supply voltage presence signal BAS_VCC_X_PRES during the power-down sequence. In a power-on sequence, the timing of the state machine controlling the power-on sequence can cause the global complementary interconnect power-on reset signal POR_INT_B to transition from low to high at the point where contention current can be eliminated by the previous state and / or timing of the power-on sequence.

[0072] Based on the foregoing description, by aligning the low-level transition of the global complementary interconnect power-on reset signal POR_INT_B during a power-down period with the tripping of the slowest chip, link nodes 310 and 320 in the configurable interconnect network are pulled up to the interconnect power node VCC_INT by p-type transistor 330 before or at the tripping of each structure chip 104-108. This prevents or reduces contention current through the transmission gates of the configurable interconnect network.

[0073] Figure 9This is a circuit diagram of at least a portion of a detection circuit 504 according to some examples. The detection circuit 504 can be implemented in any chip 102-108 to detect the presence of any power supply voltage. The detection circuit 504 is generally described relative to any power domain, which is indicated by the symbol "X". The detection circuit 504 can be implemented on the respective chip for each power domain whose power supply is to be detected. The detection circuit 504 includes resistors 602, n-type transistors 604, 606, 612, 614, 618, 620, p-type transistors 608, 610, 616, 622, and inverters 624, 626. The detection circuit is connected to the universal power supply node VCC_X and the universal power supply voltage presence node VCC_X_PRES. For one detection circuit on structure chips 104-108, the general-purpose power node VCC_X can be the interconnect power node VCC_INT on structure chips 104-108, and the general-purpose power supply voltage presence node VCC_X_PRES can be the presence node VCC_INT_PRES of the interconnect power supply voltage on structure chips 104-108. For another detection circuit on structure chips 104-108, the general-purpose power node VCC_X can be the CRAM power node VCC_RAM on structure chips 104-108, and the general-purpose power supply voltage presence node VCC_X_PRES can be the presence node VCC_RAM_PRES of the CRAM power supply voltage on structure chips 104-108. Both detection circuits can be part of detection circuit 504 on structure chips 104-108. Similarly, for one detection circuit on the base chip 102, the general-purpose power node VCC_X can be the first power node 520 on the base chip 102, and the general-purpose power supply voltage presentation node VCC_X_PRES can be the first power supply voltage presentation signal VCC_X_PRES on the base chip 102. For another detection circuit on the base chip 102, the general-purpose power node VCC_X can be the second power node 522 on the base chip 102, and the general-purpose power supply voltage presence node VCC_X_PRES can be the second power supply voltage presence signal VCC_X_PRES on the base chip 102. Both detection circuits can be part of the detection circuit 504 on the base chip 102.

[0074] Resistor 602 has a first terminal connected to the universal power node VCC_X, and a second terminal connected to the drain of n-type transistor 604 and the respective gates of transistors 608, 610, 612, and 614. The drains of n-type transistors 604 and 606 are connected, and the source of n-type transistor 606 is connected to the ground node GND. The gates of n-type transistors 604 and 606 are connected to the universal power node VCC_X.

[0075] The source of p-type transistor 608 is connected to the universal power node VCC_X, and the drain of p-type transistor 608 is connected to the corresponding sources of p-type transistors 610 and 616. The drain of p-type transistor 610 is connected to the drain of n-type transistor 612, the gate of p-type transistor 616, the gate of n-type transistor 620, and the input node of inverter 624. The source of n-type transistor 612 is connected to the drain of n-type transistor 614, and the source of n-type transistor 614 is connected to the ground node GND. The drain of p-type transistor 616 is connected to the drain of n-type transistor 618, and the source of n-type transistor 618 is connected to the ground node GND. The gate of n-type transistor 618 is connected to the universal power node VCC_X. The drain of n-type transistor 620 is connected to the drain of p-type transistor 622, and the source of p-type transistor 622 is connected to the universal power node VCC_X. The gate of p-type transistor 622 is connected to the ground node GND. The output node of inverter 624 is connected to the input node of inverter 626, and the output node of inverter 626 is the universal power supply voltage present node VCC_X_PRES.

[0076] Those skilled in the art will readily understand the detailed operation of the detection circuit 504. Generally, the detection circuit 504 detects when the general power supply voltage VCC_X at the general power node VCC_X is higher than the trip voltage of the chip that sets the detection circuit 504. When the general power supply voltage VCC_X is lower than the trip voltage, the signal on the general power supply voltage presence node VCC_X_PRES is low; when the general power supply voltage VCC_X is higher than the trip voltage, the signal VCC_X_PRES on the current general power supply voltage node tracks the general power supply voltage VCC_X (e.g., logic high). Therefore, the detection circuit 504 is configured to detect the presence of the general power supply voltage VCC_X and output the general power supply voltage presence node VCC_X_PRES accordingly.

[0077] Figure 10This is a flowchart of a method 700 for operating a multi-chip device according to some examples. The multi-chip device can be as described above. In block 702, detection circuitry on each chip generates one or more presence signals based on the detection of the corresponding presence of the power supply voltage of the respective chip. For example, the power supply voltage of the structure chips 104-108 can be the CRAM power supply voltage VCC_RAM and / or the interconnect power supply voltage VCC_INT, and detecting the presence (e.g., above or below the chip's trip voltage) of the CRAM power supply voltage VCC_RAM and / or the interconnect power supply voltage VCC_INT can respectively result in the generation of the CRAM power supply voltage presence signal VCC_RAM_PRES and / or the interconnect power supply voltage presence signal VCC_INT_PRES. The CRAM power supply voltage VCC_RAM and the interconnect power supply voltage VCC_INT can be applied to the CRAM power nodes VCC_RAM and VCC_INT in the configurable interconnect network of the structure chips 104-102, as shown below. Figure 3 and 4 As shown. The power supply voltage of the base chip 102 can be a first power supply voltage and / or a second power supply voltage at the first power node 520 and the second power node 522, respectively. The detection of the presence of the first power supply voltage and / or the second power supply voltage (e.g., higher or lower than the chip's trip voltage) can respectively cause the generation of the first power supply voltage presence signal VCC_X_PRES and / or the second power supply voltage presence signal VCC_X_PRES. The power supply applied to chips 102-108 can be output by the power supply circuit 508 on the base chip 102, and the power supply voltage that detects its presence can be based on the power supply output by the power supply circuit 508, as described above.

[0078] In block 704, pull-up signals are generated by logic circuitry on the base chip based on one or more presence signals. For example, the complementary interconnect power-on reset signal POR_INT_B can be generated by logic circuitry 506 on base chip 102 based on the CRAM power supply voltage presence signal VCC_RAM_PRES, the interconnect power supply voltage presence signal VCC_INT_PRES, the first power supply voltage presence signal VCC_X_PRES, and the second power supply voltage presence signal VCC_X_PRES.

[0079] In block 706, the corresponding pull-up circuits on the structure chip, responding to the pull-up signal, pull up the corresponding voltages of the nodes of the configurable interconnect network of the programmable IC on the structure chip. For example, when the complementary interconnect power-on reset signal POR_INT_B is low, the p-type transistor 330 pulls up the voltages of the link nodes 320 and 310 of the configurable interconnect network as described above. The configurable interconnect network can be as described above regarding... Figure 3 and 4 As described.

[0080] While the foregoing is directed to specific examples, other and further examples may be devised without departing from its basic scope, the scope of which is determined by the appended claims.

Claims

1. A multi-chip device, characterized in that, The multi-chip device includes: First chip and second chip, The first chip includes: A power supply circuit, configured to supply power to the first chip and the second chip, A first detection circuit is configured to disable the first voltage presence signal during a power-off sequence when the first voltage of the first chip is lower than the trip voltage of the first chip; and Logic circuits; and The second chip includes: Programmable circuits Storage unit, A first pull-up circuit, configured to pull up the output of the memory cell according to a pull-up signal, and A second detection circuit is configured to disable the second voltage presence signal during a power-off sequence when the second voltage of the second chip is lower than the trip voltage of the second chip, wherein the trip voltage of the first chip and the trip voltage of the second chip are different from each other. The logic circuitry of the first chip is configured to activate the pull-up signal during a power-down sequence if the second voltage presence signal has been disabled before the first voltage presence signal is disabled, in order to reduce contention between the outputs of the memory cells.

2. The multi-chip device according to claim 1, characterized in that, The storage unit includes a configuration memory for configuring the programmable circuit, the configuration memory being connected to a power supply node of the second voltage of the second chip.

3. The multi-chip device according to claim 1, characterized in that, The first pull-up circuit includes a transistor connected between a node of the programmable circuit and the output of a memory cell, the transistor having a gate configured to receive the pull-up signal.

4. The multi-chip device according to claim 1, characterized in that: The second detection circuit is configured to output a logic low value as a signal that the second voltage exists when the second voltage is lower than the trip voltage of the second chip, and to output a logic high value as a signal that the second voltage exists when the second voltage is higher than the trip voltage of the second chip. and The logic circuit is configured to output the logic low value as the pull-up signal when the second voltage signal is logic low.

5. The multi-chip device according to claim 1, characterized in that, The multi-chip device also includes a third chip configured to be identical to the second chip, wherein the logic circuitry is configured to enable the pull-up signal during a power-down sequence if the second voltage presence signal or a third voltage presence signal from the third chip has been disabled before the first voltage presence signal is disabled.

6. The multi-chip device according to claim 1, characterized in that: The programmable circuit includes a configurable interconnect network and a storage unit. The storage unit includes a configuration storage unit for configuring the programmable circuit. Each configuration storage unit is connected to a first power node, wherein a second voltage is applied to the first power node. Each configuration storage unit includes a storage node connected to a corresponding configurable circuit of the configurable interconnect network. The second detection circuit is connected to the first power node and is configured to output a logic low value as a signal that the second voltage exists when the second voltage on the first power node is lower than the trip voltage of the second chip, and to output a logic high value as a signal that the second voltage exists when the second voltage on the first power node is higher than the trip voltage of the second chip. The logic circuit is configured to generate the logic low value as the pull-up signal when the second voltage signal is logic low. and The first pull-up circuit includes a transistor connected between a second power node and a corresponding node interconnected between two or more of the configurable circuits in the configurable interconnect network. Each transistor is configured to pull the corresponding node up to the voltage of the second power node when the pull-up signal is a logic low value.

7. A method for operating a multi-chip device, characterized in that, The method includes: During the power-off sequence, when the first voltage of the first chip is lower than the trip voltage of the first chip, the first detection circuit on the first chip disables the first voltage presence signal of the first chip; and During the power-off sequence, when the second voltage of the second chip is lower than the trip voltage of the second chip, the second detection circuit on the second chip disables the second voltage presence signal, wherein the trip voltage of the first chip and the trip voltage of the second chip are different from each other; If the second voltage presence signal is disabled before the first voltage presence signal is disabled, the pull-up signal is activated by the logic circuitry on the first chip during the power-down sequence; and During the power-down sequence, the pull-up circuit on the second chip pulls up the nodes of the memory cells based on the pull-up signal to reduce contention between the outputs of the memory cells.

8. The method according to claim 7, characterized in that: Generating a signal to disable the presence of the second voltage includes: When the second voltage is lower than the trip voltage of the second chip, a logic low value is generated as a signal that the second voltage exists; Enabling the pull-up signal includes generating a logic low value as the pull-up signal.

9. The method according to claim 7, characterized in that, The method further includes: During the power-off sequence, when the third voltage on the third chip is lower than the trip voltage on the third chip, the third detection circuit on the third chip disables the third voltage presence signal; and The second pull-up circuit on the third chip pulls up the node of the memory cell of the third chip based on the pull-up signal.

10. The method according to claim 7, characterized in that: The second voltage presence signal is generated based on the detection of the presence of a second voltage on the first power node of the second chip. The second detection circuit is connected to the first power node. When the second voltage on the first power node is lower than the trip voltage of the second chip, a logic low value is generated as the first voltage presence signal. When the second voltage on the first power node is higher than the trip voltage of the second chip, a logic high value is generated as the second voltage presence signal. When the first voltage signal is a logic low value, the logic low value is used as the pull-up signal. The second chip includes a configurable interconnect network, which includes interconnect nodes and multiplexers. The interconnect node includes a storage unit. The storage unit includes a configuration storage unit for configuring programmable circuitry. The multiplexer is configured to connect interconnect nodes to nodes of programmable circuitry; and The pull-up circuit pulls up the interconnect node.

11. A multi-chip device, characterized in that, include: A chip stack, comprising multiple chips, the multiple chips including: A first chip, the first chip including a power management module, the power management module including a power circuit and a logic circuit, the power circuit being configured to output power; and The second chip includes a first configurable interconnect network, a first configuration memory unit, a first detection circuit, and a first pull-up circuit. Each first configuration memory unit has a memory node connected to a corresponding first configurable element of the first configurable interconnect network. The first configuration memory unit is connected to a first power node. A first power supply voltage on the first power node is based on a power supply output by the power supply circuit. The first detection circuit is connected to the first power node and configured to detect the presence of the first power supply voltage on the first power node and output a first presence signal in response. The logic circuit is connected to the first detection circuit and configured to generate a pull-up signal on the pull-up node based on the first presence signal. The first pull-up circuit is connected to the pull-up node and configured to pull up a first link node of the first configurable interconnect network to a second power supply voltage on a second power supply node in response to the pull-up signal. Each first link node is connected between two or more first configurable elements of the first configurable interconnect network.

12. The multi-chip device according to claim 11, characterized in that, The first chip further includes a second detection circuit, which is connected to a third power node and configured to detect the presence of a third power supply voltage at the third power node and output a second presence signal in response. The logic circuit is connected to the second detection circuit and configured to generate a pull-up signal based on the first presence signal and the second presence signal.

13. The multi-chip device according to claim 11, characterized in that, The plurality of chips further includes a third chip, which includes a second configurable interconnect network, a second configuration memory unit, a second detection circuit, and a second pull-up circuit. Each second configuration memory unit has a memory node connected to a corresponding second configurable element of the second configurable interconnect network. The second configuration memory unit is connected to a third power node, and a third power supply voltage on the third power node is based on the power output of the power circuit. The second detection circuit is connected to the third power node and configured to detect the presence of the third power supply voltage on the third power node and output a second presence signal in response. The logic circuit is connected to the second detection circuit and configured to generate the pull-up signal at the pull-up node based on the first presence signal and the second presence signal. The second pull-up circuit is connected to the pull-up node and configured to pull up a second link node of the second configurable interconnect network to the fourth power supply voltage on the fourth power node in response to the pull-up signal. Each second link node is connected between two or more second configurable elements of the second configurable interconnect network. The first chip, the second chip, and the third chip are coupled together.

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