Memory and its operation method, memory system, calibration circuit

Abstract

This disclosure provides a memory and its operation method, a memory system, and a calibration circuit. The operation method of the memory includes: acquiring calibration parameters; adjusting a measurement value used to characterize the failure bit count of the memory according to the calibration parameters, so as to calibrate the failure bit count of the memory; the first value adopts a thermometer encoding method.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory and its operation method, a memory system, and a calibration circuit. Background Technology

[0002] Memory, such as 3D NAND memory, may include a memory cell array and peripheral circuitry. The memory cell array may include multiple blocks, each block may include multiple pages, and each page may include multiple memory cells. Each memory cell can be programmed to store one or more bits of data. A memory page is the smallest unit of a write (i.e., programming) operation. In some embodiments, after data is written to a memory page, write verification is performed on the memory cell to count the number of memory cells that failed to write or had errors; this process is called Fail Bit Count (FBC). In practical applications, FBC can be measured using an FBC measurement circuit.

[0003] However, the FBC measurement circuit in the related technology has the problem of inaccurate counting when measuring FBC. Summary of the Invention

[0004] To address one or more of the related technical problems, embodiments of this disclosure provide a memory and its operation method, a memory system, and a calibration circuit.

[0005] This disclosure provides a method for operating a memory, including:

[0006] Obtain calibration parameters;

[0007] According to the calibration parameters, the measurement value used to characterize the failure bit count of the memory is subjected to bit adjustment processing to achieve calibration of the failure bit count of the memory; the measurement value adopts a thermometer encoding method.

[0008] In the above scheme, the bit adjustment process includes: adjusting the most significant bit of the measurement value towards the highest bit of the thermometer code or towards the lowest bit of the thermometer code by at least one bit.

[0009] In the above scheme, the calibration parameters include N calibration coefficients; the N calibration coefficients correspond to N groups of the thermometer code bits; and N is a positive integer greater than 1.

[0010] The method further includes:

[0011] Determine the group to which the measured value belongs;

[0012] The step of performing bit adjustment processing on the measurement value used to characterize the failure bit count result of the memory according to the calibration parameters includes:

[0013] The measurement value is adjusted according to the calibration coefficient corresponding to the group in which it belongs.

[0014] In the above scheme, the calibration parameters include three calibration coefficients; the three calibration coefficients correspond to the first group, the second group, and the third group of the thermometer code from the least significant bit to the most significant bit, respectively;

[0015] Determining the group to which the measurement value belongs includes:

[0016] The measured value is determined to be in the first group; all values ​​in the first group are greater than the actual failure bit count of the memory.

[0017] The measured value is determined to be in the second group; all values ​​in the second group are equal to the actual failure bit count of the memory.

[0018] The measured value is determined to be in the third group; all values ​​in the third group are less than the actual failure bit count of the memory.

[0019] In the above scheme, the step of performing position adjustment processing on the measurement value according to the calibration coefficient corresponding to the group to which the measurement value belongs includes:

[0020] Based on the calibration coefficients corresponding to the first group, the most significant bit of the measurement value is shifted by at least one bit in a direction lower than the most significant bit.

[0021] According to the calibration coefficients corresponding to the second group, the most significant bit of the measurement value is not shifted;

[0022] Based on the calibration coefficients corresponding to the third group, the most significant bit of the measurement value is shifted by at least one bit in a direction higher than the most significant bit.

[0023] In the above scheme, obtaining calibration parameters includes:

[0024] The calibration parameters are obtained from the registers in the memory.

[0025] The above scheme, the method further includes:

[0026] Establish the calibration parameters and save the established calibration parameters in the register.

[0027] In the above scheme, establishing the calibration parameters includes:

[0028] The reference failure bit count is obtained from the memory latch using an adder calculation method.

[0029] The measurement value is obtained from the latch by using the current quantization unit of the memory;

[0030] Compare the measured value with the reference failure bit count;

[0031] The calibration parameters are established based on the comparison results.

[0032] In the above scheme, the calibration parameters are initialized before comparing the measured value with the reference failure bit count;

[0033] The process of establishing the calibration parameters using the comparison results includes:

[0034] Based on the comparison results, adjust the calibration parameters after initialization;

[0035] The measurement value is adjusted using the adjusted calibration parameters.

[0036] Compare the bit-adjusted measurement value with the reference failure bit count;

[0037] When the measured value after the bit adjustment process is the same as the reference failure bit count, the adjusted calibration parameters are saved.

[0038] The calibration parameters are established using the saved adjusted calibration parameters.

[0039] In the above scheme, the calibration parameters include N calibration coefficients; the N calibration coefficients correspond to N groups of the thermometer code bits; and N is a positive integer greater than 1.

[0040] The process of establishing the calibration parameters using the comparison results includes:

[0041] Based on the comparison results, the calibration coefficients for the corresponding groups of the measurement values ​​are obtained;

[0042] Multiple calibration coefficients corresponding to different groups of the thermometer code are obtained sequentially;

[0043] The calibration parameters are established based on the obtained multiple calibration coefficients.

[0044] This disclosure also provides a failure bit count calibration circuit for a memory, including:

[0045] Multiple first input ports are used to receive metering values ​​output by multiple current quantization units; the metering values ​​are used to characterize the failure bit count result of the memory, and the metering values ​​are encoded using a thermometer encoding method;

[0046] The second input port is used to receive calibration parameters;

[0047] Multiple output ports are used to output calibration values ​​after bit adjustment processing of the measurement values; the calibration values ​​are made based on the calibration parameters.

[0048] In the above scheme, the calibration circuit includes multiple data shifters;

[0049] The multiple first input ports of each of the data shifters are respectively connected to the output terminals of multiple adjacent current quantization units in the multiple current quantization units;

[0050] The second input port of each of the data shifters is used to receive calibration parameters;

[0051] The output port of each of the data shifters is used to output a calibration value corresponding to the output value of the first current quantization unit; the first current quantization unit is a current quantization unit located in the middle position among the plurality of adjacent current quantization units; the calibration value is one of the output values ​​of the plurality of adjacent current quantization units; the number of data shifters corresponds to the number of current quantization units.

[0052] In the above scheme, the number of current quantization units includes M, and the M current quantization units are divided into N groups; the calibration parameters include N calibration coefficients; the N calibration coefficients correspond to the N groups of current quantization units respectively; M and N are both positive integers greater than 1;

[0053] For each of the N groups of current quantization units, the second input of the corresponding data shifter of the corresponding group of current quantization units is used to receive the calibration coefficient corresponding to the corresponding group of current quantization units.

[0054] In the above scheme, the three first input ports of each data shifter are respectively connected to the output terminals of three adjacent current quantization units;

[0055] The second input port of each data shifter is used to receive the calibration parameters corresponding to the group of the current quantization unit in the middle position among the three adjacent current quantization units.

[0056] The output port of each data shifter is used to output the calibration value of the current quantization unit output value in the middle position.

[0057] This disclosure also provides a memory, including:

[0058] Storage cell array;

[0059] Peripheral circuitry, coupled to the memory cell array, is used to control the storage operations of the memory cell array; wherein, the peripheral circuitry includes:

[0060] The programming operation circuit is used to perform programming pulse application operation, verification operation and failure bit counting operation on the memory cell array;

[0061] A latch is used to store the failure bit count result of the memory;

[0062] Multiple current quantization units, connected to the latch, are used to obtain, via current measurement, a metric value characterizing the failure bit count of the memory from the latch; and

[0063] The failure bit counting calibration circuit described in the above scheme is used to output a calibration value after bit adjustment processing of the measurement value using calibration parameters.

[0064] This disclosure also provides a memory, including:

[0065] Storage cell array;

[0066] Peripheral circuitry, coupled to the memory cell array, is used to control the storage operations of the memory cell array; wherein, the peripheral circuitry includes:

[0067] The programming operation circuit is used to perform programming pulse application operation, verification operation and failure bit counting operation on the memory cell array;

[0068] A latch is used to store the failure bit count result of the memory;

[0069] Multiple current quantization units, connected to the latch, are used to obtain, via current measurement, a metric value characterizing the failure bit count of the memory from the latch; and

[0070] The control logic is used to output a calibration value after bit adjustment processing of the measurement value using calibration parameters.

[0071] In the above scheme, the peripheral circuit also includes a register for storing the calibration parameters.

[0072] In the above scheme, the memory includes a three-dimensional NAND type memory.

[0073] This disclosure also provides a memory system, including: the memory described in the above scheme; and a memory controller coupled to the memory and controlling the memory.

[0074] This disclosure provides a memory, its operation method, a memory system, and a calibration circuit. The operation method of the memory includes: acquiring calibration parameters; and performing bit adjustment processing on a measurement value representing the failure bit count of the memory based on the calibration parameters to calibrate the failure bit count of the memory. The first value is encoded using a thermometer encoding method. In this disclosure, the failure bit count of the memory is represented by a thermometer encoding method. After obtaining the preliminary measurement result, the thermometer encoding value is shifted using the calibration parameters, i.e., bit adjustment processing is performed on the thermometer encoding value based on the characteristics of the thermometer encoding. This bit adjustment processing achieves calibration of the failure bit count of the memory, thereby improving the accuracy of the failure bit count result of the memory. Attached Figure Description

[0075] Figure 1 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0076] Figure 2a This is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0077] Figure 2b This is a schematic diagram of an exemplary solid-state drive with a memory system according to an embodiment of the present disclosure;

[0078] Figure 3a This is a schematic diagram showing the distribution of storage cells in a three-dimensional NAND type memory according to an embodiment of the present disclosure;

[0079] Figure 3b This is a schematic diagram of an exemplary memory including peripheral circuitry according to an embodiment of the present disclosure;

[0080] Figure 4 This is a schematic cross-sectional view of a memory cell array including NAND memory strings according to an embodiment of the present disclosure;

[0081] Figure 5 This is a schematic diagram of an exemplary memory including a memory cell array and peripheral circuitry according to an embodiment of the present disclosure;

[0082] Figure 6a This is a schematic diagram of the connection structure between a page cache region and a peripheral circuit region in a related technology.

[0083] Figure 6b This is a schematic diagram of the encoding result of a thermometer in a related technology.

[0084] Figure 7 A schematic flowchart of a failure bit count calibration method for a memory provided in this disclosure embodiment;

[0085] Figure 8 A schematic diagram of the logic flow of a failure bit count calibration method for a memory provided in this embodiment of the present disclosure;

[0086] Figure 9 A schematic diagram illustrating an example of failure bit count calibration for a memory provided in an embodiment of this disclosure;

[0087] Figure 10 A schematic diagram illustrating an example of failure bit count calibration for another memory provided in this disclosure embodiment;

[0088] Figure 11 This is a schematic diagram of a failure bit counting group structure provided in an embodiment of the present disclosure;

[0089] Figure 12 This is a schematic diagram of a failure bit count calibration circuit for a memory provided in an embodiment of the present disclosure. Detailed Implementation

[0090] To make the technical solutions and advantages of the embodiments of this disclosure clearer, the specific technical solutions of the invention will be further described in detail below with reference to the accompanying drawings of the embodiments of this disclosure. The following embodiments are used to illustrate this disclosure, but are not intended to limit the scope of this disclosure.

[0091] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise scale, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0092] The memory in the embodiments of this disclosure includes, but is not limited to, three-dimensional NAND memory. For ease of understanding, a three-dimensional NAND memory is used as an example for explanation. However, it should be understood that the embodiments of this disclosure are not limited to this configuration, but can also be applied to two-dimensional NAND memory. In addition, without departing from the scope of this disclosure, this disclosure can be applied to other non-volatile memory devices, such as electrically erasable programmable read-only memory (EEPROM), NOR flash memory, phase-change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), ferroelectric random access memory (FRAM), etc.

[0093] Figure 1 A block diagram of an exemplary system 100 having memory according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memories 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory 104.

[0094] According to some embodiments, memory controller 106 is coupled to memory 104 and host 108 and is configured to control memory 104. Memory controller 106 can manage data stored in memory 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs) used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0095] The memory controller 106 can be configured to control the operation of the memory 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions related to data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Devices (IDE) protocol, Firewire protocol, etc.

[0096] The memory controller 106 and one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2aIn one example shown, the memory controller 106 and a single memory 104 can be integrated into the memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 can also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2b In another example shown, the memory controller 106 and multiple memories 104 can be integrated into the SSD 206. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0097] Figure 3a An exemplary schematic diagram of a storage cell array for a three-dimensional NAND flash memory is provided, such as... Figure 3a As shown, the memory cell array of a three-dimensional NAND flash memory consists of several rows of parallel, staggered memory cell rows parallel to the gate isolation structure. Each two rows of memory cell rows are separated by a gate isolation structure and an up-select gate isolation structure. Each memory cell row includes multiple memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory cell array into multiple memory blocks. Multiple second gate isolation structures can divide the memory blocks into multiple finger memory regions. An up-select gate isolation structure located in the middle of each finger memory region can divide the finger memory region into two parts, thereby dividing the finger memory region into two memory chips. Figure 3a The memory block shown contains 6 memory chips; however, in practical applications, the number of memory chips in a memory block is not limited to this. A memory cell in a memory block coupled to a word line can be called a memory page.

[0098] It should be noted that, Figure 3a The number of cell rows between the gate isolation structure and the top-select gate isolation structure given is merely an exemplary example and is not intended to limit the number of cell rows contained in a single memory region of the three-dimensional NAND memory in this disclosure. In practical applications, the number of cell rows contained in a single memory region can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0099] Figure 3b A schematic circuit diagram of an exemplary memory 300, including peripheral circuitry, is shown according to some aspects of this disclosure. The memory 300 may be... Figure 1 An example of memory 104 is provided. Memory 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 is illustrated as a three-dimensional NAND-type memory cell array, wherein the memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0100] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erase state.

[0101] like Figure 3bAs shown, each NAND memory string 308 may include a lower select gate (BSG) 310 at its source end and an upper select gate (TSG) 312 at its drain end. BSG 310 and TSG 312 can be configured to activate the selected NAND memory string 308 during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same memory block 304 are coupled via a common source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 312) or a deselection voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 310) or a deselection voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0102] like Figure 3bAs shown, NAND memory strings 308 can be organized into multiple memory blocks 304, each of which may have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block 304a, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source line 314 of the selected memory block 304a and the unselected memory block 304b on the same face as the selected memory block 304a. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some implementations, each word line 318 is coupled to a page 320 of memory cell 306, where page 320 is the basic data unit used for programming operations. The size of a page 320, in bits, can be related to the number of NAND memory strings 308 coupled by word lines 318 in a memory block 304. Each word line 318 may include multiple control gates (gate electrodes) at each memory cell 306 in the corresponding page 320, as well as gate lines coupling the control gates. (This is in conjunction with the preceding...) Figure 3a A page 320 contains multiple memory cells 306, which are separated by an up-select gate isolation structure and a gate isolation structure. The memory cells between the up-select gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows, each of which is parallel to the gate isolation structure and the up-select gate isolation structure. The memory cells in the memory chip that share the same word line form a programmable (read / write) page.

[0103] Figure 4 A schematic cross-sectional view of an exemplary memory cell array 301 including NAND memory strings 308 is shown, according to some aspects of this disclosure. Figure 4 As shown, the NAND memory string 308 may include a stacked structure 410, which includes multiple gate layers 411 and multiple insulating layers 412 stacked alternately in sequence, and a memory string 308 perpendicularly penetrating the gate layers 411 and insulating layers 412. The gate layers 411 and insulating layers 412 may be stacked alternately, with adjacent gate layers 411 separated by an insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410 determines the number of memory cells included in the memory cell array 301.

[0104] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line layer.

[0105] In some embodiments, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0106] In some embodiments, the NAND memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel holes filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0107] Return to reference Figure 3bThe peripheral circuitry 302 can be coupled to the memory cell array 301 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, an FBC measurement circuit 507, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0108] Page buffer / sensor amplifier 504 can be configured to read data from and program (write) data to memory cell array 301 according to control signals from control logic 512. In one example, page buffer / sensor amplifier 504 can store a page of programming data (write data) to be programmed into a page 320 of memory cell array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0109] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSG lines 315 and TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0110] In some specific embodiments, the programming operation may include multiple steps. For example, the programming operation may include a bit line setting step, a programming execution step, and a programming recovery step. After the programming operation, a programming verification operation is also required; after the programming verification operation, a programming verification recovery operation is also required. During the bit line setting step of the programming operation, the voltage for unselected word lines can be maintained at ground (GND). During the programming execution step of the programming operation, a pass voltage (Vpass) can be applied to the unselected word lines, and a programming voltage (Vpgm) can be applied to the selected word lines. Therefore, the memory cells connected to the selected word lines can be programmed. During the programming recovery step of the programming operation, the voltage applied to all word lines can be reduced to ground (GND).

[0111] Control logic 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 512, as well as to buffer status information received from control logic 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bit line driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 301.

[0112] The memory cell array is connected to the page buffer via bit lines, and the page buffer is connected to the FBC circuit. The memory cell array includes multiple memory cells. After programming, the page buffer 504 outputs a current signal to the FBC measurement circuit 507. If the memory cell passes programming verification, the current signal is 0; if the memory cell fails programming verification, the page buffer of the corresponding bit line branch will output a corresponding current signal. The FBC measurement circuit 507 counts these current signals to determine the number of memory cells that failed programming verification and outputs this number. The FBC measurement circuit typically includes multiple current quantization units.

[0113] For example, refer to Figure 6a As shown, the FBC circuit can include 14 current quantization units. The comparators in each current quantization unit compare the current Verok_q generated by a memory cell whose programming verification failed from the page cache with different reference currents, thereby obtaining the comparison result Ver_cont<0:13>, which is the FBC result. Here, the FBC result measured by the current quantization units can also be called the Current Counting Scheme (CCS) result, or the FBC result obtained through simulation. Furthermore, the number of current quantization units can be set according to actual needs, and is not limited to the 14 shown in the example. For instance, the number of current quantization units can be set according to the memory's error correction capability; for example, the number of current quantization units can be greater than the maximum number that the memory's error checking and correction (ECC) circuit can correct. Understandably, the location of the page buffer (page buffer region) differs from the location of the FBC circuit (peripheral region). Differences in manufacturing processes in these different regions will cause variations in the sensed current and reference current. The page buffer region is far from the peripheral region, requiring the sensed current to travel a long distance from the page buffer to the peripheral region, resulting in a significant voltage drop and thus variations in the sensed current. Furthermore, the reference current will also vary depending on the manufacturing process of different products. These variations may lead to undercounting or overcounting by the comparator, resulting in undercounting or overcounting when performing data failure bit counting. In other words, obtaining FBC results through simulation has measurement errors due to distance and other factors. However, since obtaining FBC results through simulation is based on hardware measurement, it is faster and has better real-time performance.

[0114] In some embodiments, the number of storage units that failed the programming verification is locked. Figure 6aIn the left-hand page buffer, firmware (FW) can be used, such as a digital adder, to accumulate the results from multiple latches and read the accumulated result as the FBC result. This method of obtaining the FBC result through addition can be called obtaining the FBC result digitally. It's understandable that obtaining the FBC result digitally takes longer because it involves the addition calculation, but the result is less affected by environmental factors and is more accurate.

[0115] Because FBC results obtained through simulation offer better real-time performance, memory systems often use this method. Of course, calibrating the simulated FBC results can achieve both speed and accuracy. Clearly, since digitally obtained FBC results are more accurate, they can serve as a calibration reference.

[0116] In one specific embodiment, the FBC results obtained through simulation are typically output in a thermometer-encoded format. For ease of understanding, Figure 6b The example shown is only the thermometer code Ver_cont<0:5> corresponding to the 6 current quantization units. The current output by each current quantization unit is one unit, and the current output by the current quantization units is cumulative. When the failure bit current Verok_q includes several units of current, the corresponding thermometer code bits will be set to 1.

[0117] The thermometer code is characterized by the following: the positions of 1s are arranged continuously from the least significant bit to the most significant bit, without any 0s interspersed. The number of 1s represents the value of the thermometer code. Considering the characteristics of the thermometer code, the FBC result obtained through analog means can be easily calibrated by adjusting the bits towards the higher or lower bits. Based on this, in the various embodiments of this disclosure, the failure bit count result of the memory is characterized by a thermometer code. After obtaining the preliminary measurement result, the thermometer code value is bit-adjusted using compensation parameters. This bit adjustment process calibrates the failure bit count of the memory, thereby improving the accuracy of the failure bit count result of the memory.

[0118] Understandably, shifting doesn't require many resources to implement and allows for flexible application of different calibration rules to the bits between the most and least significant bits of the thermometer code. These different calibration rules will be described in detail later.

[0119] The embodiments of this disclosure provide a method for calibrating the failure bit count of a memory. Figure 7 This is a schematic diagram illustrating the implementation flow of the failure bit count calibration method for a memory according to an embodiment of this disclosure. Figure 7 As shown, the method includes the following steps:

[0120] Step 701: Obtain calibration parameters;

[0121] Step 702: According to the calibration parameters, the measurement value used to characterize the failure bit count of the memory is shifted to achieve calibration of the failure bit count of the memory; the first value adopts the thermometer encoding method.

[0122] In some embodiments, the bit adjustment process includes adjusting the most significant bit of the measurement value towards either the most significant bit of the thermometer code or the least significant bit of the thermometer code by at least one bit. It should be understood that... Figure 7 The operations shown are not exclusive; other operations may be performed before, after, or between any of the operations shown.

[0123] In practical applications, calibration parameters can be established before performing step 701 to facilitate the acquisition of subsequent calibration parameters.

[0124] In some embodiments, establishing the calibration parameters includes:

[0125] The reference failure bit count is obtained from the memory latch using an adder calculation method.

[0126] The measurement value is obtained from the latch by using the current quantization unit of the memory;

[0127] Compare the measured value with the reference failure bit count;

[0128] The calibration parameters are established based on the comparison results.

[0129] As previously mentioned, obtaining FBC results through simulation offers better real-time performance. However, this method also suffers from the aforementioned measurement errors caused by factors such as distance. Here, the FBC result obtained by the current quantization unit in the simulation is referred to as the metrological value, which is encoded using a thermometer.

[0130] Based on the differences between the two methods of obtaining FBC results, FBC results can be obtained in a special state, such as a test state, using the two different methods. The FBC results obtained digitally are compared with the first value of the FBC results obtained analogically. After multiple comparisons, the offset of the current quantization unit in the FBC circuit is obtained, thereby establishing the calibration parameters that need to be accurately adjusted corresponding to the offset.

[0131] In some embodiments, the calibration parameters are initialized before comparing the measurement value with the reference failure bit count;

[0132] The process of establishing the calibration parameters using the comparison results includes:

[0133] Based on the comparison results, adjust the calibration parameters after initialization;

[0134] The calibration value is adjusted using the adjusted calibration parameters;

[0135] Compare the bit-adjusted measurement value with the reference failure bit count;

[0136] When the measured value after the bit adjustment process is the same as the reference failure bit count, the adjusted calibration parameters are saved.

[0137] The calibration parameters are established using the saved adjusted calibration parameters.

[0138] Here, the FBC result obtained through the aforementioned numerical method is defined as Nd; meanwhile, the FBC result obtained through the aforementioned simulation method is named Na.

[0139] In practical applications, such as Figure 8 As shown, in the process of establishing the calibration parameters, such as in step 801, the calibration parameters are first initialized. After initialization, the value of the calibration parameters can be a value that indicates no shifting, such as 0.

[0140] After initialization is complete, step 802 is executed, and the control logic obtains Nd digitally.

[0141] While performing step 802, step 803 is also performed to obtain the FBC result through simulation.

[0142] After completing step 803, step 804 is executed, and the control logic obtains the measurement result Na of the current quantization unit.

[0143] Next, step 805 is executed, where the control logic compares the acquired Nd with the Na acquired by the FW, that is, it determines whether the sizes of Nd and Na are equal.

[0144] When Na=Nd, it means that the FBC result obtained by simulation is accurate and no correction is needed. Execute step 807 to end the calibration parameter establishment process. The output calibration parameters are the initialized values.

[0145] When Na≠Nd, it means that the FBC result obtained by simulation is inaccurate and needs to be corrected. Execute step 806 to determine whether Na is less than Nd.

[0146] When Na < Nd, it indicates that the FBC result obtained through simulation is too small. The most significant bit in Na needs to be adjusted by one bit towards the most significant bit direction for correction. In this case, step 808 is executed, and the calibration parameter is reduced by 1. In practical applications, after adjusting the most significant bit in Na by one bit towards the most significant bit direction, steps 803, 804, and 805 are executed again. Then, the comparison continues downwards according to step 805 until Na = Nd. The calibration parameter at this point is saved and output.

[0147] When Na > Nd, it indicates that the FBC result obtained through simulation is too large. The most significant bit in Na needs to be adjusted by one bit towards the least significant bit for correction. In this case, step 809 is executed, incrementing the calibration parameter by 1. In practical applications, after adjusting the most significant bit in Na by one bit towards the least significant bit, steps 803, 804, and 805 are executed again. The comparison continues downwards according to step 805 until Na = Nd. The calibration parameter at this point is then saved and output.

[0148] For a calibration parameter of -1, for example, such as Figure 9 As shown, when Nd=3, meaning there are 3 failure bits, the measured code in the failure bit count result Ver_cont<0:5> output by the current quantization unit in the FBC circuit is 000011, indicating a short count. In this case, the most significant bit in the failure bit count result needs to be adjusted by one bit towards the highest bit of the thermometer code, so that the correction code is 000111. It should be noted that after the bit adjustment, the most significant bit of the measurement value is shifted one bit higher, while the measurement value still conforms to the characteristics of the thermometer code.

[0149] For a calibration parameter of +1, for example, such as Figure 10 As shown, when Nd=3, meaning there are 3 failure bits, the measured code in the failure bit count result Ver_cont<0:5> output by the current quantization unit in the FBC circuit is 001111, indicating an overcount. In this case, the most significant bit in the failure bit count result needs to be adjusted by one bit towards the least significant bit of the thermometer code, so that the correction code is 000111. It should be noted that after the bit adjustment, the most significant bit of the measurement value is shifted one bit towards the least significant bit, while the measurement value still conforms to the characteristics of the thermometer code.

[0150] It should be noted that in practical applications, when the calibration parameter is -k or +k (where k is a positive integer greater than 1), i.e., when more bits need to be calibrated, the example above can be used as a reference. The most significant bit in the failure bit count result can be adjusted k bits towards the highest bit of the thermometer code; or, the most significant bit in the failure bit count result can be shifted k bits towards the lowest bit of the thermometer code. It should be noted that after the bit adjustment process, the most significant bit of the measurement value is shifted k bits towards the higher or lower bits, while the measurement value after the bit adjustment process still conforms to the characteristics of the thermometer code.

[0151] In some specific embodiments, the calibration parameter can be established for the first time when the memory leaves the factory, or it can be re-established according to the needs of the product in actual application, such as when the performance of the product drifts after long-term use.

[0152] In some embodiments, the method further includes: storing the established calibration parameters in the register.

[0153] In other words, in practical applications, once the calibration parameters are established, they can be used for the normal operation of the memory. In practical applications, step 701 mainly involves obtaining the calibration parameters.

[0154] Here, the calibration parameter is used to indicate the specific execution of the shifting process in subsequent step 702. In some specific embodiments, the sign of the calibration parameter can indicate the direction of bit adjustment in subsequent step 702, and the magnitude of the calibration parameter can indicate the number of bits adjusted in subsequent step 702. It should be noted that in other specific embodiments, other different properties of the calibration parameter can also be used to indicate the direction of bit adjustment and the specific number of bits adjusted.

[0155] Here, when the FBC measurement circuit is enabled, calibration parameters indicating how much shift to perform on the first value are first obtained. In practical applications, these parameters can be obtained from memory registers or from other non-volatile memory elements.

[0156] In some embodiments, obtaining the calibration parameters includes:

[0157] The calibration parameters are obtained from the registers in the memory.

[0158] As we can understand it, registers are small storage areas within memory used to temporarily store data involved in calculations and their results. A register can also be understood as a commonly used sequential logic circuit, but this type of sequential logic circuit only contains storage circuitry. The storage circuitry of a register can include latches or flip-flops.

[0159] In practical applications, calibration parameters can be obtained from the register when the memory is powered on and temporarily stored; or they can be obtained from the register when the FBC measurement circuit needs to be started.

[0160] In step 702, the main task is to perform bit adjustment on the failure bit count, that is, to adjust the most significant bit of the measurement value towards the highest bit of the thermometer code or towards the lowest bit of the thermometer code by at least one bit.

[0161] Here, the measured value can be understood as a thermometer-coded value, which can be used to characterize the result of the failure bit count. It is understood that the first value, i.e., the thermometer-coded value, can include multiple bits. As mentioned above, when the FBC circuit includes 14 current quantization units, the first value, i.e., the thermometer-coded value, can include 14 bits, i.e., Ver_cont<0:13>.

[0162] Here, the bit being adjusted is the most significant bit in the measurement value. For example, when the first value is 00... 1 When the result is 111, the most significant bit is the one indicated by the underline. The shifting of the first bit among the multiple bits of the first value by at least one bit to the left or right can be understood as adjusting the most significant bit of the measurement value towards the highest bit of the thermometer code by one or more bits; or adjusting the most significant bit of the measurement value towards the lowest bit of the thermometer code by one or more bits. In other words, the most significant bit of the measurement value changes after the bit adjustment process, but the measurement value after the bit adjustment process still satisfies the characteristics of the thermometer code.

[0163] In some specific examples, the sign indicator bit of the calibration parameter can be used to adjust the direction of processing, and the magnitude indicator bit of the calibration parameter can be used to adjust the number of shift bits performed during processing. Specifically, when the sign of the calibration parameter is negative, it can be defined as a risk of undercounting in the measurement value, in which case the most significant bit in the measurement value can be adjusted towards the highest bit of the thermometer code; when the sign of the calibration parameter is zero, the most significant bit in the measurement value does not need to be shifted; when the sign of the calibration parameter is positive, it can be defined as a risk of overcounting in the measurement value, in which case the most significant bit in the measurement value can be adjusted towards the lowest bit of the thermometer code. When the magnitude of the calibration parameter is 1, it indicates an adjustment of 1 bit; when the magnitude of the calibration parameter is k, it indicates an adjustment of k bits.

[0164] For example, when the calibration parameter is -1, the most significant bit in the measurement value is adjusted by 1 bit towards the most significant bit of the thermometer code, according to the calibration parameter.

[0165] For example, when the calibration parameter is +k, the most significant bit in the measurement value is adjusted by k bits towards the least significant bit of the thermometer code, according to the calibration parameter. It is understood that in this embodiment of the disclosure, the thermometer code is used to characterize the result of the failure bit count, making it easy to correct the calibration result during the bit adjustment process without requiring significant resources.

[0166] In some specific embodiments, considering the different distances of different current quantization units from the page buffer, the degree to which voltage drop and other factors affect the CCS result varies. For example, when 14 current quantization units are arranged sequentially, the corresponding Ver_cont... <0> To Ver_cont <13> As the distance from the page buffer increases, the influence of the resistance on the connection line becomes more significant. This is reflected in Ver_cont<0:13> as the number of bits increases, leading to a gradual increase in voltage drop and a more pronounced undercount problem in the CCS result. At this point, applying the same calibration strategy to all bits in the CCS result may not effectively correct the inaccuracy. Therefore, in this embodiment, group correction is introduced, where different correction strategies are applied to the N groups of thermometer encoding bits.

[0167] For group calibration, the calibration parameters need to be obtained separately according to the group. Therefore, when establishing the calibration parameters, the calibration coefficients corresponding to each group also need to be established separately according to the group.

[0168] In some embodiments, the calibration parameters include N calibration coefficients; the N calibration coefficients correspond to N groups of thermometer code bits; and N is a positive integer greater than 1.

[0169] The process of establishing the calibration parameters using the comparison results includes:

[0170] Using the comparison results, the calibration coefficients for the corresponding groups of the measurement values ​​are obtained;

[0171] Multiple calibration coefficients corresponding to different groups of the thermometer code are obtained sequentially;

[0172] The calibration parameters are established based on the obtained multiple calibration coefficients.

[0173] In practical applications, the calibration parameters are divided into N calibration coefficients; each calibration coefficient can be used to characterize the shift of the same group of failure bit counts. Here, N can be determined according to the actual situation, such as the grouping pattern summarized when establishing calibration coefficients for multiple products in a batch. In practical applications, the calibration coefficients of each group can be established with reference to the method described above when establishing a calibration parameter. The established calibration coefficients can also be stored in a register for subsequent calibration during normal operation of the memory. In some embodiments, the calibration parameters include N calibration coefficients; the N calibration coefficients correspond to N groups of thermometer code bits; N is a positive integer greater than 1.

[0174] The method further includes:

[0175] Determine the group to which the measured value belongs;

[0176] The step of performing bit adjustment processing on the measurement value used to characterize the failure bit count result of the memory according to the calibration parameters includes:

[0177] The measurement value is adjusted according to the calibration coefficient corresponding to the group in which it belongs.

[0178] In other words, when performing thermometer encoding operation on the failure bit count of the same set of data, the failure bit count of the same set of data is divided into N groups. Here, the grouping is based on the fact that the bit adjustment processing rules of the failure bit count of the same group are the same, that is, the failure bit count of the same group is adjusted towards the least bit of the thermometer encoding or towards the most bit of the thermometer encoding by one or more bits.

[0179] In some specific examples, the group to which the measurement value belongs can be determined first; then, based on the calibration coefficient corresponding to the group to which the measurement value belongs, the position adjustment of the measurement value can be determined.

[0180] In some specific examples, grouping typically involves grouping the thermometer-encoded bits corresponding to current quantization units with similar calibration requirements into one group. For instance, the lower bits might be grouped based on the distance of the current quantization unit from the page buffer region; the middle bits might be grouped together; and the higher bits might be grouped together.

[0181] In some embodiments, the calibration parameters include three calibration coefficients; the three calibration coefficients correspond to the first group, the second group, and the third group of the thermometer code from the least significant bit to the most significant bit, respectively;

[0182] The method further includes:

[0183] Determining the group to which the measurement value belongs includes:

[0184] The measured value is determined to be in the first group; all values ​​in the first group are greater than the actual failure bit count of the memory.

[0185] The measured value is determined to be in the second group; all values ​​in the second group are equal to the actual failure bit count of the memory.

[0186] The measured value is determined to be in the third group; all values ​​in the third group are less than the actual failure bit count of the memory.

[0187] In some embodiments, the step of performing bit adjustment processing on the measurement value according to the calibration coefficient corresponding to the group to which the measurement value belongs includes:

[0188] Based on the calibration coefficients corresponding to the first group, the most significant bit of the measurement value is adjusted by at least one bit in a direction lower than the most significant bit.

[0189] Based on the calibration coefficients corresponding to the second group, the most significant bit of the measurement value is not adjusted;

[0190] Based on the calibration coefficients corresponding to the third group, the most significant bit of the measurement value is adjusted by at least one bit in a direction higher than the most significant bit. Here, the first group may include a lower bit group, where each measurement value in the first group is greater than the actual failure bit count of the memory; the second group may include a middle bit group, where each measurement value in the second group is equal to the actual failure bit count of the memory; and the third group may include a higher bit group, where each measurement value in the third group is less than the actual failure bit count of the memory.

[0191] For example, refer to Figure 11 Here, the failure bit count includes 11 bits, i.e., 1 bit, 2 bits...11 bits; and each corresponds to one of the 11 failure bit count results, i.e., Ver_cont <0> Ver_cont <1> …Ver_cont <10> Among them, Ver_cont<1:3> is in the lower bit group, which has an overcount problem. According to the calibration coefficient corresponding to the first group, the highest valid bit of the measurement value is adjusted by at least one bit towards the lowest bit of the thermometer code; Ver_cont<4:6> is in the middle bit group, which does not need to be corrected, and none of the bits of the measurement value are moved; Ver_cont<7:9> is in the higher bit group, which has an undercount problem. According to the calibration coefficient corresponding to the third group, the highest valid bit of the measurement value is adjusted by at least one bit towards the highest bit of the thermometer code.

[0192] It should be noted that Ver_cont <0> As the least significant bit of the first value, it cannot be corrected towards lower bits; Ver_cont <10> As the highest digit of the measurement value, it cannot be corrected towards higher digits. Therefore, in this embodiment, the correction for Ver_cont is omitted. <0> and Ver_cont <10> The correction. It should be noted that Ver_cont <3> As the boundary bit between the lower and higher bit groups, Ver_cont <7> As the boundary between the median group and the higher-order group, there may be overlap due to the shifting process.

[0193] In this way, during the calibration process of the same set of failure bit counts, failure bit counts with different shift rules can be shifted differently according to actual needs, thereby further enhancing the accuracy of failure bit count correction.

[0194] In some specific examples, the bit adjustment processing of the aforementioned thermometer-encoded measurement value can be implemented using software, such as firmware. In the software implementation, the bit adjustment processing can be implemented in code.

[0195] In some specific examples, the shifting of the aforementioned thermometer-encoded value can also be achieved through hardware, such as a data shifting circuit.

[0196] Another aspect of this disclosure provides a failure bit count calibration circuit for a memory, including:

[0197] Multiple first input ports are used to receive metering values ​​output by multiple current quantization units; the metering values ​​are used to characterize the failure bit count result of the memory, and the metering values ​​are encoded using a thermometer encoding method;

[0198] The second input port is used to receive calibration parameters;

[0199] Multiple output ports are used to output calibration values ​​after bit adjustment processing of the measurement values; the calibration values ​​are made based on the calibration parameters.

[0200] In some embodiments, the calibration circuit includes multiple data shifters;

[0201] The multiple first input ports of each of the data shifters are respectively connected to the output terminals of multiple adjacent current quantization units in the multiple current quantization units;

[0202] The second input port of each of the data shifters is used to receive calibration parameters;

[0203] The output port of each of the data shifters is used to output a calibration value corresponding to the output value of the first current quantization unit; the first current quantization unit is a current quantization unit located in the middle position among the plurality of adjacent current quantization units; the calibration value is one of the output values ​​of the plurality of adjacent current quantization units; the number of data shifters corresponds to the number of current quantization units.

[0204] The current quantization unit is used to measure the current output on the page buffer and output it in a thermometer-encoded manner; the output value of one current quantization unit corresponds to one thermometer-encoded bit.

[0205] Here, a data shifter can be connected to the output ports of multiple current quantization units, which can be bit-adjacent current quantization units. The number of adjacent current quantization units can be determined according to the actual situation. For example, when it is determined that a bit shift to the left or right is required, the number of adjacent current quantization units can include three.

[0206] In some embodiments, the number of current quantization units includes M, and the M current quantization units are divided into N groups; the calibration parameters include N calibration coefficients; the N calibration coefficients correspond to the N groups of current quantization units respectively; and M and N are both positive integers greater than 1.

[0207] For each of the N groups of current quantization units, the second input of the corresponding data shifter of the corresponding group of current quantization units is used to receive the calibration coefficient corresponding to the corresponding group of current quantization units.

[0208] Here, the second input port of each data shifter is connected to the calibration parameters; the calibration parameters include N calibration coefficients; the N calibration coefficients correspond to the N groups of the thermometer encoding bits. Here, the first input port of each of the multiple data shifters is connected to the output of multiple adjacent current quantization units; these multiple current quantization units can be divided into N groups. The N calibration coefficients of the calibration parameters correspond one-to-one with the N groups of current quantization units.

[0209] In other words, the multiple second input ports of the multiple data shifters corresponding to each group of current quantization units are connected together and connected to the calibration coefficients corresponding to the corresponding groups, thereby enabling group calibration.

[0210] In some embodiments, the three first input ports of each data shifter are respectively connected to the outputs of three adjacent current quantization units;

[0211] The second input port of each data shifter is used to receive the calibration parameters corresponding to the group of the current quantization unit in the middle position among the three adjacent current quantization units.

[0212] The output port of each data shifter is used to output the calibration value of the current quantization unit output value in the middle position.

[0213] For example, such as Figure 12 As shown, the calibration circuit includes 12 data shifters, each with its first input connected to the outputs of three adjacent current quantization units. Specifically, the first shifter outputs the calibration value of the middle current quantization unit among the three current quantization units Ver_cont<0:2>, i.e., the current quantization unit Ver_cont. <1> The calibration value Ver_cont_d <1> The output of the second shifter is the calibration value of the middle current quantization unit among the three current quantization units Ver_cont<1:3>, i.e., the current quantization unit Ver_cont. <2> The calibration value Ver_cont_d <2> Similarly, the output of the twelfth shifter outputs the calibration value of the middle current quantization unit among the three current quantization units Ver_cont<11:13>, i.e., the current quantization unit Ver_cont. <12> The calibration value Ver_cont_d <12> .

[0214] Understandably, Ver_cont <1> The calibration value Ver_cont_d <1> Ver_cont can be easily output <0> or Ver_cont <2> This is equivalent to using Ver_cont as the most significant bit. <1> One bit was adjusted towards either the lowest or highest bit of the thermometer code.

[0215] It should be noted that the above only describes the hardware implementation of the aforementioned shifting process for the thermometer encoding value.

[0216] Based on the above embodiments, this disclosure further provides a memory, including:

[0217] Storage cell array;

[0218] Peripheral circuitry, coupled to the memory cell array, is used to control the storage operations of the memory cell array;

[0219] The peripheral circuit is configured to include:

[0220] The programming operation circuit is used to perform programming pulse application operation, verification operation and failure bit counting operation on the memory cell array;

[0221] A latch is used to store the failure bit count result of the memory;

[0222] Multiple current quantization units, connected to the latch, are used to obtain, via current measurement, a metric value characterizing the failure bit count of the memory from the latch; and

[0223] The failure bit counting calibration circuit described in the embodiments of this disclosure is used to output a calibration value after bit adjustment processing of the measurement value using calibration parameters.

[0224] Based on the above-described embodiment of the error bit counting calibration circuit, this disclosure further provides a memory, including:

[0225] Storage cell array;

[0226] Peripheral circuitry, coupled to the memory cell array, is used to control the storage operations of the memory cell array; wherein, the peripheral circuitry includes:

[0227] The programming operation circuit is used to perform programming pulse application operation, verification operation and failure bit counting operation on the memory cell array;

[0228] A latch is used to store the failure bit count result of the memory;

[0229] Multiple current quantization units, connected to the latch, are used to obtain, via current measurement, a metric value characterizing the failure bit count of the memory from the latch; and

[0230] The control logic is used to output a calibration value after bit adjustment processing of the measurement value using calibration parameters.

[0231] Specifically, calibration can be achieved through the execution of code in the control logic. In some embodiments, the peripheral circuitry also includes registers for storing the calibration parameters.

[0232] In some embodiments, the memory includes a three-dimensional NAN-type memory.

[0233] This disclosure also provides a memory system, the memory system comprising:

[0234] One or more memories as described in any of the above embodiments; and

[0235] A memory controller, which is coupled to the memory device and controls the memory.

[0236] Here, the specific structure and composition of the memory system can be referred to the foregoing. Figure 1 , Figure 2a , Figure 2b The relevant structure and composition of the memory system 102 are described below. For the sake of brevity, they will not be elaborated here.

[0237] It should be noted that terms such as "first" and "second" are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0238] Furthermore, the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0239] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

Claims

1. A method for operating a memory, characterized in that, include: Obtain calibration parameters; According to the calibration parameters, the measurement value used to characterize the failure bit count result of the memory is subjected to bit adjustment processing to achieve calibration of the failure bit count of the memory. The measurement value adopts a thermometer encoding method; wherein, the bit adjustment process includes: adjusting the most significant bit of the measurement value towards the highest bit of the thermometer encoding or towards the lowest bit of the thermometer encoding by at least one bit.

2. The method according to claim 1, characterized in that, The calibration parameters include N calibration coefficients; the N calibration coefficients correspond to N groups of the thermometer code bits; and N is a positive integer greater than 1. The method further includes: Determine the group to which the measured value belongs; The step of performing bit adjustment processing on the measurement value used to characterize the failure bit count result of the memory according to the calibration parameters includes: The measurement value is adjusted according to the calibration coefficient corresponding to the group in which it belongs.

3. The method according to claim 2, characterized in that, The calibration parameters include three calibration coefficients; the three calibration coefficients correspond to the first, second and third groups of the thermometer code from the least significant bit to the most significant bit; Determining the group to which the measurement value belongs includes: The measured value is determined to be in the first group; all values ​​in the first group are greater than the actual failure bit count of the memory. The measured value is determined to be in the second group; all values ​​in the second group are equal to the actual failure bit count of the memory. The measured value is determined to be in the third group; all values ​​in the third group are less than the actual failure bit count of the memory.

4. The method according to claim 3, characterized in that, The step of adjusting the measurement value according to the calibration coefficient corresponding to the group to which the measurement value belongs includes: Based on the calibration coefficients corresponding to the first group, the most significant bit of the measurement value is adjusted by at least one bit in a direction lower than the most significant bit. Based on the calibration coefficients corresponding to the second group, the most significant bit of the measurement value is not adjusted; Based on the calibration coefficients corresponding to the third group, the most significant bit of the measurement value is adjusted by at least one bit in a direction higher than the most significant bit.

5. The method according to claim 1, characterized in that, The acquisition of calibration parameters includes: The calibration parameters are obtained from the registers in the memory.

6. The method according to claim 5, characterized in that, The method further includes: Establish the calibration parameters and save the established calibration parameters in the register.

7. The method according to claim 6, characterized in that, The establishment of the calibration parameters includes: The reference failure bit count is obtained from the memory latch using an adder calculation method. The measurement value is obtained from the latch by using the current quantization unit of the memory; Compare the measured value with the reference failure bit count; The calibration parameters are established based on the comparison results.

8. The method according to claim 7, characterized in that, The calibration parameters are initialized before comparing the measured value with the reference failure bit count; The process of establishing the calibration parameters using the comparison results includes: Based on the comparison results, adjust the calibration parameters after initialization; The measurement value is adjusted using the adjusted calibration parameters. Compare the bit-adjusted measurement value with the reference failure bit count; When the measured value after the bit adjustment process is the same as the reference failure bit count, the adjusted calibration parameters are saved. The calibration parameters are established using the saved adjusted calibration parameters.

9. The method according to claim 8, characterized in that, The calibration parameters include N calibration coefficients; the N calibration coefficients correspond to N groups of the thermometer code bits; and N is a positive integer greater than 1. The process of establishing the calibration parameters using the comparison results includes: Using the comparison results, the calibration coefficients for the corresponding groups of the measurement values ​​are obtained; Multiple calibration coefficients corresponding to different groups of the thermometer code are obtained sequentially; The calibration parameters are established based on the obtained multiple calibration coefficients.

10. A failure bit count calibration circuit for a memory, characterized in that, include: Multiple first input ports are used to receive metering values ​​output by multiple current quantization units; The measurement value is used to characterize the failure bit count result of the memory, and the measurement value adopts a thermometer encoding method; The second input port is used to receive calibration parameters; Multiple output ports are used to output the calibration value after bit adjustment processing of the measurement value; The calibration value is made based on the calibration parameters; wherein the bit adjustment process includes: adjusting the most significant bit of the measurement value towards the highest bit of the thermometer code or towards the lowest bit of the thermometer code by at least one bit.

11. The failure bit counting calibration circuit according to claim 10, characterized in that, The calibration circuit includes multiple data shifters; The multiple first input ports of each of the data shifters are respectively connected to the output terminals of multiple adjacent current quantization units in the multiple current quantization units; The second input port of each of the data shifters is used to receive calibration parameters; The output port of each of the data shifters is used to output a calibration value corresponding to the output value of the first current quantization unit; the first current quantization unit is a current quantization unit located in the middle position among the plurality of adjacent current quantization units; the calibration value is one of the output values ​​of the plurality of adjacent current quantization units; the number of data shifters corresponds to the number of current quantization units.

12. The failure bit counting calibration circuit according to claim 11, characterized in that, The number of current quantization units includes M units, and the M current quantization units are divided into N groups; the calibration parameters include N calibration coefficients; the N calibration coefficients correspond to the N groups of current quantization units respectively; M and N are both positive integers greater than 1; For each of the N groups of current quantization units, the second input of the corresponding data shifter of the corresponding group of current quantization units is used to receive the calibration coefficient corresponding to the corresponding group of current quantization units.

13. The failure bit counting calibration circuit according to claim 11, characterized in that, The three first input ports of each data shifter are connected to the outputs of three adjacent current quantization units, respectively. The second input port of each data shifter is used to receive the calibration parameters corresponding to the group of the current quantization unit in the middle position among the three adjacent current quantization units. The output port of each data shifter is used to output the calibration value of the current quantization unit output value in the middle position.

14. A memory, characterized in that, include: Storage cell array; Peripheral circuitry, coupled to the memory cell array, is used to control the storage operations of the memory cell array; wherein, the peripheral circuitry includes: The programming operation circuit is used to perform programming pulse application operation, verification operation and failure bit counting operation on the memory cell array; A latch is used to store the failure bit count result of the memory; Multiple current quantization units, connected to the latch, are used to obtain, via current measurement, a metric value characterizing the failure bit count of the memory from the latch; and The failure bit counting calibration circuit as described in any one of claims 10-13 is used to output a calibration value after bit adjustment processing of the measurement value using calibration parameters.

15. A memory, characterized in that, include: Storage cell array; Peripheral circuitry, coupled to the memory cell array, is used to control the storage operations of the memory cell array; wherein, the peripheral circuitry includes: The programming operation circuit is used to perform programming pulse application operation, verification operation and failure bit counting operation on the memory cell array; A latch is used to store the failure bit count result of the memory; Multiple current quantization units, connected to the latch, are used to obtain, via current measurement, a metric value characterizing the failure bit count of the memory from the latch; and Control logic is used to perform bit adjustment processing on the measurement value used to characterize the failure bit count result of the memory using calibration parameters; and output a calibration value after bit adjustment processing of the measurement value; wherein the measurement value adopts a thermometer encoding method; the bit adjustment processing includes: adjusting the most significant bit of the measurement value towards the highest bit of the thermometer encoding or towards the least significant bit of the thermometer encoding by at least one bit.

16. The memory according to claim 14 or 15, characterized in that, The peripheral circuitry also includes a register for storing the calibration parameters.

17. The memory according to claim 14 or 15, characterized in that, The memory includes a three-dimensional NAND type memory.

18. A memory system, characterized in that, include: One or more memories as described in claim 14 or 15; as well as A memory controller, which is coupled to the memory and controls the memory.

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