A method, apparatus, device, and readable medium for injecting fault signals into an NVMESSD interface.

Abstract

The application provides a method, device, equipment and readable medium for NVME SSD interface fault signal injection, the method comprising: setting a signal simulation switch between a host interface and a device interface connected to a disk; connecting an output end of a control system to an enable end of the signal simulation switch to control opening or closing of the signal simulation switch; in response to receiving an instruction to test the NVME SSD interface, calculating a control signal of the signal simulation switch according to the instruction; and outputting the control signal to the enable end of the signal simulation switch to simulate a fault of the NVME SSD interface. Through use of the scheme of the application, hot plug control testing of each signal can be accurately performed, a wide variety of test cases can be supported, and problems in product design and production processing can be quickly found during research and development and production, thereby improving research and development and production testing efficiency.

Description

Technical Field

[0001] This invention relates to the field of computers, and more specifically to a method, apparatus, device, and readable medium for injecting fault signals into an NVMe SSD interface. Background Technology

[0002] During R&D and production testing, hot-swap tests are required for NVMe SSD interfaces to verify product reliability and stability, exposing design and manufacturing defects as quickly as possible. Manual hot-swap testing is time-consuming, labor-intensive, and inefficient. Repeated hot-swap tests cause wear and tear on the interface connections, significantly shortening the lifespan of test fixtures. Furthermore, it cannot simulate single or multiple signal failures that could lead to disk loss, resulting in incomplete test case coverage, limited testing methods, few test scenarios, and low testing efficiency. Summary of the Invention

[0003] In view of this, the purpose of this invention is to provide a method, apparatus, device and readable medium for injecting fault signals into an NVMe SSD interface. By using the technical solution of this invention, hot-plug control testing of each signal can be accurately performed, and a wide variety of test cases can be supported. This facilitates the rapid discovery of problems in the design and manufacturing processes of products during research and development and production, thereby improving the efficiency of research and development and production testing.

[0004] To achieve the above objectives, one aspect of the present invention provides a method for injecting a fault signal into an NVMe SSD interface, comprising the following steps:

[0005] A signal analog switch is installed between the host-side interface and the device-side interface connected to the disk;

[0006] Connect the output of the control system to the enable terminal of the analog signal switch to control the opening or closing of the analog signal switch;

[0007] In response to receiving a command to test the NVMe SSD interface, the control signal for the signal simulation switch is calculated based on the command.

[0008] The control signal is output to the enable terminal of the signal simulation switch to simulate a fault in the NVMe SSD interface.

[0009] According to one embodiment of the present invention, setting a signal analog switch between the host-side interface and the device-side interface connected to the disk includes:

[0010] A PCIe high-speed signal analog switch, a PCIe out-of-band signal analog switch, an interface detection analog switch, and a power switch are respectively installed between the host-side interface and the device-side interface connected to the disk.

[0011] According to one embodiment of the present invention, connecting the output terminal of the control system to the enable terminal of the signal analog switch to control the opening or closing of the signal analog switch includes:

[0012] Connect the output of the control system to the enable terminal of the PCIe high-speed signal analog switch, the enable terminal of the PCIe out-of-band signal analog switch, the enable terminal of the interface detection analog switch, and the control terminal of the power switch, respectively.

[0013] According to one embodiment of the present invention, in response to receiving an instruction to test the NVMe SSD interface, the control signal of the signal analog switch calculated according to the instruction includes:

[0014] The instructions calculate control signals of different cycles and proportions used to control the opening or closing of the PCIe high-speed signal analog switch;

[0015] The instructions calculate control signals of different cycles and proportions used to control the opening or closing of the PCIe out-of-band signal analog switch.

[0016] The instructions calculate control signals of different cycles and proportions used to control the interface to detect the opening or closing of analog switches;

[0017] The instructions calculate control signals of different cycles and proportions used to control the power switch to turn on or off.

[0018] In another aspect, embodiments of the present invention also provide an apparatus for injecting a fault signal into an NVMe SSD interface, the apparatus comprising:

[0019] The configuration module is configured to set up a signal analog switch between the host-side interface and the device-side interface connected to the disk;

[0020] A connection module is configured to connect the output of the control system to the enable terminal of a signal analog switch to control the opening or closing of the signal analog switch;

[0021] The calculation module is configured to, in response to receiving a command to test the NVMe SSD interface, calculate the control signal of the analog switch based on the command.

[0022] The output module is configured to output control signals to the enable terminal of the signal analog switch to simulate a fault in the NVMESSD interface.

[0023] According to one embodiment of the present invention, the setting module is further configured to:

[0024] A PCIe high-speed signal analog switch, a PCIe out-of-band signal analog switch, an interface detection analog switch, and a power switch are respectively installed between the host-side interface and the device-side interface connected to the disk.

[0025] According to one embodiment of the present invention, the connection module is further configured as follows:

[0026] Connect the output of the control system to the enable terminal of the PCIe high-speed signal analog switch, the enable terminal of the PCIe out-of-band signal analog switch, the enable terminal of the interface detection analog switch, and the control terminal of the power switch, respectively.

[0027] According to one embodiment of the present invention, the computing module is further configured as follows:

[0028] The instructions calculate control signals of different cycles and proportions used to control the opening or closing of the PCIe high-speed signal analog switch;

[0029] The instructions calculate control signals of different cycles and proportions used to control the opening or closing of the PCIe out-of-band signal analog switch.

[0030] The instructions calculate control signals of different cycles and proportions used to control the interface to detect the opening or closing of analog switches;

[0031] The instructions calculate control signals of different cycles and proportions used to control the power switch to turn on or off.

[0032] Another aspect of the embodiments of the present invention also provides a computer device, the computer device comprising:

[0033] At least one processor; and

[0034] The memory stores computer instructions that can be executed by a processor, which, when executed by the processor, implement the steps of any of the methods described above.

[0035] In another aspect, embodiments of the present invention also provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of any of the above methods.

[0036] The present invention has the following beneficial technical effects: The method for injecting NVMe SSD interface fault signals provided in the embodiments of the present invention sets a signal simulation switch between the host-side interface and the device-side interface connected to the disk; connects the output terminal of the control system to the enable terminal of the signal simulation switch to control the opening or closing of the signal simulation switch; in response to receiving an instruction to test the NVMe SSD interface, calculates the control signal of the signal simulation switch according to the instruction; and outputs the control signal to the enable terminal of the signal simulation switch to simulate the fault of the NVMe SSD interface. This technical solution can accurately control and test the hot-plugging of each signal, supports a wide variety of test cases, facilitates the rapid discovery of problems in the design and manufacturing processes of products during R&D and production, and improves the efficiency of R&D and production testing. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0038] Figure 1 A schematic flowchart illustrating a method for injecting fault signals into an NVMe SSD interface according to an embodiment of the present invention;

[0039] Figure 2 This is a schematic diagram of an NVME SSD interface fault signal injection system according to an embodiment of the present invention;

[0040] Figure 3 This is a schematic diagram of an apparatus for injecting fault signals into an NVMe SSD interface according to an embodiment of the present invention;

[0041] Figure 4 This is a schematic diagram of a computer device according to an embodiment of the present invention;

[0042] Figure 5 This is a schematic diagram of a computer-readable storage medium according to an embodiment of the present invention. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0044] Based on the above objectives, a first aspect of the embodiments of the present invention provides an embodiment of a method for injecting fault signals into an NVMe SSD interface. Figure 1 The diagram shown is a schematic flowchart of the method.

[0045] like Figure 1 As shown, the method may include the following steps:

[0046] S1 provides a signal analog switch between the host-side interface and the device-side interface for connecting the disk. The host-side interface is used to connect the disk backplane, and the device-side interface is used to connect the disk. A PCIe high-speed signal analog switch, a PCIe Sideband (out-of-band) signal analog switch, an interface detection analog switch, and a power switch can be provided between the two interfaces using any method in the prior art.

[0047] S2 connects the output of the control system to the enable terminal of the analog signal switch to control the opening or closing of the analog signal switch. For example... Figure 2 As shown, the control system consists of an MCU (Microcontroller Unit) and a CPLD (Field Programmable Gate Array). The output of the control system can output corresponding I / O signals to the enable or control terminals of the aforementioned analog switches to control the opening or closing of the switches. The control system can be embedded between the disk and the disk backplane in a very small physical form without affecting the function and performance of the disk backplane or the disk. It can realize fault injection and hot-swap control and can be flexibly used in various server testing environments. Various test cases can simulate disk hot-swap and fault injection tests.

[0048] In response to a received instruction to test the NVMe SSD interface, the S3 calculates the control signals for the analog switch. The MCU, as the core processor unit of the control system, receives control commands or scripts from the host computer, processes them, and can simulate and generate signal glitch signals with different periods and ratios of PRBS (pseudo-random binary sequences or pseudo-random codes). The CPLD outputs corresponding I / O control signals to control the opening and closing of the analog switch. The analog switch generates glitch signals with different amplitudes at different opening and closing times; the higher the switching frequency, the larger the amplitude of the generated glitch signal, and vice versa. By controlling the switching frequency of the analog switch, signal glitch fault signals with different periods and amplitudes can be superimposed on PCIe high-speed signals, PCIe out-of-band signals, interface detection signals, and power signals, thus injecting fault signals to simulate hot-plug tests under various scenarios. It can also divide each signal into various signal combinations, each of which can support different timing switch controls. It can simulate the contact and disconnection time of connector pins of different lengths online, and perform PIN bounce simulation tests for each or multiple signals at different cycles. It solves the problems of incomplete coverage of NVEM SSD interface hot-plug test cases, single test methods, limited test scenarios, and low test efficiency.

[0049] S4 outputs a control signal to the enable terminal of the signal simulation switch to simulate a fault in the NVMe SSD interface.

[0050] By using the solution of this invention, hot-plug control testing of each signal can be accurately performed, supporting a wide variety of test cases. This facilitates the rapid discovery of problems in product design and manufacturing processes during research and development and production, thereby improving the efficiency of research and development and production testing.

[0051] In a preferred embodiment of the present invention, setting a signal analog switch between the host-side interface and the device-side interface connected to the disk includes:

[0052] Set up a PCIe high-speed signal simulation switch, a PCIe out-of-band signal simulation switch, an interface detection simulation switch, and a power switch between the host-side interface and the device-side interface connected to the disk, respectively. Other simulation switches can be set up according to actual testing needs, and the above method can be used for testing.

[0053] In a preferred embodiment of the present invention, connecting the output terminal of the control system to the enable terminal of the signal analog switch to control the opening or closing of the signal analog switch includes:

[0054] The output terminals of the control system are connected to the enable terminals of the PCIe high-speed signal analog switch, the PCIe out-of-band signal analog switch, the interface detection analog switch, and the power switch, respectively. The output terminals of the control system can output corresponding IO control signals. Connecting the output terminals of the control system to the enable or control terminals of each analog switch can control the opening or closing of the analog switches, thereby simulating various fault signals of the interface.

[0055] In a preferred embodiment of the present invention, in response to receiving an instruction to test the NVMe SSD interface, the control signal for calculating the signal analog switch according to the instruction includes:

[0056] The instructions calculate control signals of different cycles and proportions used to control the opening or closing of the PCIe high-speed signal analog switch;

[0057] The instructions calculate control signals of different cycles and proportions used to control the opening or closing of the PCIe out-of-band signal analog switch.

[0058] The instructions calculate control signals of different cycles and proportions used to control the interface to detect the opening or closing of analog switches;

[0059] The system calculates control signals with different cycles and ratios to control the power switch to turn on or off, based on the instructions. It can also test various combinations of these signals, each supporting different timing switch controls. It can simulate the contact and disconnection times of connector pins (long and short pins) online, and perform PIN bounce simulation tests with different cycles for each or multiple signals.

[0060] This invention has the following characteristics:

[0061] 1) Supports the combination of controlled signals, which can be roughly divided into PCIe signals, clock signals, sideband signals, power control signals and interface detection, etc. Each group can realize the injection of signal Glitch fault signals with different periods and amplitudes.

[0062] 2) Control of the contact and disconnection time of the long and short pins of the analog connector signal. When inserting, the long pin signal of the connector opens earlier than the short pin signal, and when pulling out, the short pin signal closes earlier than the long pin signal. The opening and closing time of the long pin, the opening and closing time of the short pin signal, and the difference between the two time values ​​can all be set.

[0063] 3) The system can support multiple sets of different signal timing settings at the same time. The opening and closing time periods of each control signal can be set according to different test requirements.

[0064] 4) By setting the opening and closing time period of the analog switch through control signals, the bounce test of the connector pins is simulated to achieve a more realistic hot-plug test;

[0065] 5) Fault injection tests can be performed on the host-side signals of PCIe devices independently;

[0066] 6) Fault injection tests can be performed on the Device-side signals of PCIe devices independently;

[0067] 7) It can perform simulation tests on the lane of PCIe devices, such as downgrading from PCIe X4 to PCIe X2.

[0068] This invention uses the on / off timing of MCU control signals to generate glitch injections into the controlled signals, enabling precise hot-plug control testing of each signal. The controlled signals can be configured with different combinations and on / off times, simulating hot-plug testing in various scenarios for PCIe in-band and out-of-band signals, interface detection signals, power signals, etc. It supports a wide variety of test cases, facilitating rapid identification of design and manufacturing issues in R&D and production, thus improving R&D and production testing efficiency.

[0069] It should be noted that those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc. The embodiments of the computer program described above can achieve the same or similar effects as any of the corresponding foregoing method embodiments.

[0070] Furthermore, the method disclosed in the embodiments of the present invention can also be implemented as a computer program executed by a CPU, which may be stored in a computer-readable storage medium. When the computer program is executed by the CPU, it performs the functions defined in the method disclosed in the embodiments of the present invention.

[0071] Based on the above objectives, a second aspect of the embodiments of the present invention provides an apparatus for injecting fault signals into an NVMe SSD interface, such as... Figure 3 As shown, the device 200 includes:

[0072] The configuration module is configured to set up a signal analog switch between the host-side interface and the device-side interface connected to the disk;

[0073] A connection module is configured to connect the output of the control system to the enable terminal of a signal analog switch to control the opening or closing of the signal analog switch;

[0074] The calculation module is configured to, in response to receiving a command to test the NVMe SSD interface, calculate the control signal of the analog switch based on the command.

[0075] The output module is configured to output control signals to the enable terminal of the signal analog switch to simulate a fault in the NVMESSD interface.

[0076] In a preferred embodiment of the present invention, the setting module is further configured as follows:

[0077] A PCIe high-speed signal analog switch, a PCIe out-of-band signal analog switch, an interface detection analog switch, and a power switch are respectively installed between the host-side interface and the device-side interface connected to the disk.

[0078] In a preferred embodiment of the present invention, the connection module is further configured as follows:

[0079] Connect the output of the control system to the enable terminal of the PCIe high-speed signal analog switch, the enable terminal of the PCIe out-of-band signal analog switch, the enable terminal of the interface detection analog switch, and the control terminal of the power switch, respectively.

[0080] In a preferred embodiment of the present invention, the computing module is further configured as follows:

[0081] The instructions calculate control signals of different cycles and proportions used to control the opening or closing of the PCIe high-speed signal analog switch;

[0082] The instructions calculate control signals of different cycles and proportions used to control the opening or closing of the PCIe out-of-band signal analog switch.

[0083] The instructions calculate control signals of different cycles and proportions used to control the interface to detect the opening or closing of analog switches;

[0084] The instructions calculate control signals of different cycles and proportions used to control the power switch to turn on or off.

[0085] In view of the above objectives, a third aspect of the present invention provides a computer device. Figure 4 The diagram shown is a schematic representation of an embodiment of the computer device provided by the present invention. Figure 4 As shown, embodiments of the present invention include the following apparatus: at least one processor 21; and a memory 22 storing computer instructions 23 executable on the processor, which, when executed by the processor, implement the following method:

[0086] A signal analog switch is installed between the host-side interface and the device-side interface connected to the disk;

[0087] Connect the output of the control system to the enable terminal of the analog signal switch to control the opening or closing of the analog signal switch;

[0088] In response to receiving a command to test the NVMe SSD interface, the control signal for the signal simulation switch is calculated based on the command.

[0089] The control signal is output to the enable terminal of the signal simulation switch to simulate a fault in the NVMe SSD interface.

[0090] In a preferred embodiment of the present invention, setting a signal analog switch between the host-side interface and the device-side interface connected to the disk includes:

[0091] A PCIe high-speed signal analog switch, a PCIe out-of-band signal analog switch, an interface detection analog switch, and a power switch are respectively installed between the host-side interface and the device-side interface connected to the disk.

[0092] In a preferred embodiment of the present invention, connecting the output terminal of the control system to the enable terminal of the signal analog switch to control the opening or closing of the signal analog switch includes:

[0093] Connect the output of the control system to the enable terminal of the PCIe high-speed signal analog switch, the enable terminal of the PCIe out-of-band signal analog switch, the enable terminal of the interface detection analog switch, and the control terminal of the power switch, respectively.

[0094] In a preferred embodiment of the present invention, in response to receiving an instruction to test the NVMe SSD interface, the control signal for calculating the signal analog switch according to the instruction includes:

[0095] The instructions calculate control signals of different cycles and proportions used to control the opening or closing of the PCIe high-speed signal analog switch;

[0096] The instructions calculate control signals of different cycles and proportions used to control the opening or closing of the PCIe out-of-band signal analog switch.

[0097] The instructions calculate control signals of different cycles and proportions used to control the interface to detect the opening or closing of analog switches;

[0098] The instructions calculate control signals of different cycles and proportions used to control the power switch to turn on or off.

[0099] In view of the above objectives, a fourth aspect of the present invention provides a computer-readable storage medium. Figure 5The diagram shown is a schematic representation of an embodiment of the computer-readable storage medium provided by the present invention. Figure 5 As shown, the computer-readable storage medium 31 stores a computer program 32 that, when executed by a processor, performs the methods described above.

[0100] Furthermore, the method disclosed in the embodiments of the present invention can also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. When the computer program is executed by the processor, it performs the functions defined in the method disclosed in the embodiments of the present invention.

[0101] Furthermore, the above-described method steps and system units can also be implemented using a controller and a computer-readable storage medium for storing a computer program that enables the controller to perform the functions of the above-described steps or units.

[0102] Those skilled in the art will also understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the functionality of various illustrative components, blocks, modules, circuits, and steps has been generally described. Whether this functionality is implemented as software or as hardware depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art can implement the functionality in various ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the embodiments disclosed herein.

[0103] In one or more exemplary designs, functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, functionality may be stored as one or more instructions or code on or transmitted via a computer-readable medium. Computer-readable media include computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one location to another. Storage media may be any available medium accessible to a general-purpose or special-purpose computer. By way of example, and not limitation, computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage devices, disk storage devices or other magnetic storage devices, or any other medium that may be used to carry or store the required program code in the form of instructions or data structures and is accessible to a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection may be appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the aforementioned coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are all included in the definition of media. As used herein, disks and optical discs include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0104] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0105] It should be understood that, as used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, “and / or” refers to any and all possible combinations of one or more of the associated listed items.

[0106] The embodiment numbers disclosed in the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0107] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0108] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A method for injecting fault signals into an NVMe SSD interface, characterized in that, Includes the following steps: A signal simulation switch is set between the host interface and the device interface connected to the disk, including: a PCIe high-speed signal simulation switch, a PCIe out-of-band signal simulation switch, an interface detection simulation switch, and a power switch respectively between the host interface and the device interface connected to the disk. Connect the output of the control system to the enable terminal of the PCIe high-speed signal analog switch, the enable terminal of the PCIe out-of-band signal analog switch, the enable terminal of the interface detection analog switch, and the control terminal of the power switch to control the opening or closing of the signal analog switch. In response to receiving a command to test the NVMe SSD interface, the system calculates control signals for the signal analog switches according to the command. These signals include: calculating control signals of different periods and proportions for controlling the PCIe high-speed signal analog switch to open or close; calculating control signals of different periods and proportions for controlling the PCIe out-of-band signal analog switch to open or close; calculating control signals of different periods and proportions for controlling the interface detection analog switch to open or close; and calculating control signals of different periods and proportions for controlling the power switch to open or close. Control signals are output to the enable pins of the PCIe high-speed signal simulation switch, the PCIe out-of-band signal simulation switch, the interface detection simulation switch, and the power switch to simulate an NVMe SSD interface failure.

2. A device for injecting fault signals into an NVMe SSD interface, characterized in that, The device includes: The configuration module is configured to set a signal analog switch between the host-side interface and the device-side interface connected to the disk; A connection module is configured to connect the output terminal of the control system to the enable terminal of a signal analog switch to control the opening or closing of the signal analog switch; A computing module configured to, in response to receiving an instruction to test the NVMe SSD interface, calculate a control signal for a signal analog switch based on the instruction. An output module configured to output a control signal to the enable terminal of a signal analog switch to simulate a fault in the NVMESSD interface; The settings module is also configured to: A PCIe high-speed signal analog switch, a PCIe out-of-band signal analog switch, an interface detection analog switch, and a power switch are respectively installed between the host-side interface and the device-side interface connecting the disk. The connection module is also configured to: Connect the output of the control system to the enable terminal of the PCIe high-speed signal analog switch, the enable terminal of the PCIe out-of-band signal analog switch, the enable terminal of the interface detection analog switch, and the control terminal of the power switch, respectively. The computing module is also configured to: The instructions calculate control signals of different cycles and proportions used to control the opening or closing of the PCIe high-speed signal analog switch; The instructions calculate control signals of different cycles and proportions used to control the opening or closing of the PCIe out-of-band signal analog switch. The instructions calculate control signals of different cycles and proportions used to control the interface to detect the opening or closing of analog switches; The instructions calculate control signals of different cycles and proportions used to control the power switch to turn on or off.

3. A computer device, characterized in that, include: At least one processor; as well as A memory storing computer instructions executable on the processor, which, when executed by the processor, implement the steps of the method of claim 1.

4. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method of claim 1.

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