Overcurrent protection circuit and memory
By designing an overcurrent protection circuit to monitor and adjust the programming current in real time, the overprogramming pollution and stability problems of efuse programmable memory are solved, achieving flexible adjustment and low-power programming protection, and improving the reliability of the memory.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SOUTH CHINA UNIV OF TECH
- Filing Date
- 2022-06-20
- Publication Date
- 2026-07-21
AI Technical Summary
Existing efuse programmable memories have the risk of overprogramming pollution and poor stability. Especially under high current fusing conditions, they are prone to thermal trapping effects, which lead to unstable fuse resistance.
An overcurrent protection circuit was designed, including an overcurrent sampling module, a voltage adjustment pre-control module, a voltage adjustment module, and a power selection module. By monitoring the programming current in real time and performing voltage reduction operation, the circuit avoids damage to the circuit caused by excessive current and achieves flexible voltage adjustment to reduce programming power.
It effectively reduces the risk of overprogramming pollution, improves the stability and reliability of the memory, reduces programming power consumption, and the circuit can be embedded in existing array modules to improve the overall reliability of the circuit.
Smart Images
Figure CN114999539B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of memory, and in particular to an overcurrent protection circuit and a memory. Background Technology
[0002] Currently, efuse programmable memories often employ p+poly resistors with silicide to enhance the electromigration capability of the fuse resistors. This allows for programming devices without requiring excessive heat and current, resulting in minimal contamination of the fuse array. While using this device as a fuse reduces the high-temperature heat required by traditional metal high-temperature fuses, high-current fusing conditions are still unavoidable, and the risk of overprogramming contamination remains.
[0003] In addition to the pollution phenomena mentioned above, overprogramming may also cause a heat trapping effect. After a period of time, high-resistance circuits that were determined to be burned out may return to a low-resistance state, which will reduce the stability of the efuse programmable memory.
[0004] Therefore, how to achieve adjustable programming current, improve flexibility, reduce the risk of overprogramming pollution, and improve memory stability has become one of the technical problems that urgently need to be solved by those skilled in the art. Summary of the Invention
[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an overcurrent protection circuit and memory to solve the problems of overprogramming pollution and poor stability of the efuse programmable memory in the prior art.
[0006] To achieve the above and other related objectives, the present invention provides an overcurrent protection circuit, the overcurrent protection circuit comprising at least:
[0007] Overcurrent sampling module, gear pre-control module, gear adjustment module and power selection module;
[0008] The overcurrent sampling module samples the programming current of the memory cell to be programmed based on the word line signal of the memory cell to be programmed, and determines the overcurrent level of the programming current based on the difference between the sampled signal and the reference signal.
[0009] The gear shifting pre-control module is connected to the output terminal of the overcurrent sampling module and generates a corresponding gear shifting control signal based on the overcurrent level;
[0010] The gear shifting module is connected to the output terminal of the gear shifting pre-control module and generates the corresponding gear output voltage based on the gear shifting control signal;
[0011] The power selection module is connected to the output terminal of the tuning module. When in programming mode, it applies the output voltage of the tuning module to the bit line of the memory cell to be programmed.
[0012] Optionally, the overcurrent sampling module includes a monitoring unit and a comparison unit; the monitoring unit is connected to the bit line of the memory cell to be programmed and receives the word line signal of the memory cell to be programmed, and generates a monitoring signal of the programming current based on the word line signal; the comparison unit is connected to the output terminal of the monitoring unit, compares the monitoring signal with the reference signal, and outputs the comparison result.
[0013] Alternatively, the monitoring unit includes a first NMOS transistor and i sampling resistors; the source of the first NMOS transistor is grounded, the gate is connected to the word line of the memory cell to be programmed, and the drain is connected to the bit line of the memory cell to be programmed via each series sampling resistor; the connection node of each sampling resistor outputs the monitoring signal; i is a natural number greater than or equal to 2.
[0014] Alternatively, the comparison unit includes (i-1) comparators, the non-inverting input of each comparator is connected to the connection node of each sampling resistor, the inverting input is connected to the reference signal, and the comparison result is output to represent the overcurrent level.
[0015] Alternatively, the gear shift control signal is i-bit, and only one bit of the i-bit gear shift control signal corresponding to each overcurrent level is valid.
[0016] Alternatively, the gear adjustment module includes i voltage divider resistors and i transmission units; each voltage divider resistor is connected in series to form a resistor string, one end of which is connected to a preset programming voltage and the other end is grounded; the input terminal of each transmission unit is connected to the high-voltage terminal of each voltage divider resistor, the control terminal receives the corresponding gear adjustment control signal, and the output terminals are connected together.
[0017] Optionally, the power selection module includes a level conversion unit, a buffer unit, and a drive unit;
[0018] The power supply terminal of the level conversion unit is connected to the output voltage of the gear adjustment module, and the control terminal receives the programming control signal and the reading control signal respectively, and performs level conversion based on the programming control signal and the reading control signal;
[0019] The buffer unit is connected to the output terminal of the level conversion unit;
[0020] The driving unit is connected to the output terminal of the buffer unit, and the output terminal is connected to the bit line of the memory unit to be programmed; when in read mode, the driving unit outputs a low level, and when in programming mode, the driving unit outputs the output voltage of the tuning module.
[0021] To achieve the above and other related objectives, the present invention also provides a memory, the memory comprising at least: a memory array consisting of N rows and M columns of memory cells, a multi-select data selector, a row selection control circuit, an amplification readout circuit, M readout control circuits, and M of the above-mentioned overcurrent protection circuits; wherein, N and M are natural numbers greater than or equal to 2;
[0022] The row selection control circuit provides word line signals to each memory cell;
[0023] The input of the multiple-choice data selector receives each word line signal and selects one to output the word line signal;
[0024] The input terminals of each overcurrent protection circuit are connected to the output terminals of the multiplexer, and the output terminals are connected to one bit line respectively. In programming mode, overcurrent protection is provided for the storage cells on each bit line.
[0025] Each read control circuit's output terminal is connected to a bit line, providing read voltage to the storage cells on each bit line in read mode;
[0026] The amplification and readout circuit is connected to each bit line to read out the output signal of each column.
[0027] Optionally, the number of rows N in the storage array is greater than the number of columns M.
[0028] Alternatively, the memory cell includes a fuse and a gate transistor, one end of the fuse being connected to a bit line and the other end being connected to the drain of the gate transistor; the gate of the gate transistor receives the corresponding word line signal, and the source is grounded.
[0029] As described above, the overcurrent protection circuit and memory of the present invention have the following beneficial effects:
[0030] 1. The overcurrent protection circuit and memory of the present invention monitor the current of the programming circuit in real time through the overcurrent sampling module and make corresponding circuit control feedback. It can quickly perform voltage reduction operation for excessive current, thereby reducing the current size and finally reducing the programming power of the circuit, thus avoiding overprogramming of the fuse resistor.
[0031] 2. The overcurrent protection circuit and memory of the present invention can be flexibly adjusted according to different circuit specifications, so that the circuit will not immediately shut down when an overcurrent occurs, but will be reduced to a certain level so that the circuit can continue to work normally.
[0032] 3. The overcurrent protection circuit of the present invention is compatible with efuse programmable memory. This circuit can be embedded in existing array modules and integrated into the entire IP design to improve the reliability of the circuit. Attached Figure Description
[0033] Figure 1 The diagram shown is a schematic representation of the overcurrent protection circuit of this invention.
[0034] Figure 2 The diagram shown is a structural schematic of the gear shifting pre-control module of the present invention.
[0035] Figure 3 The diagram shown is a structural schematic of the file adjustment module of the present invention.
[0036] Figure 4 The diagram shown is a structural schematic of the power selection module of the present invention.
[0037] Figure 5 The diagram shown is a structural schematic of the memory of the present invention.
[0038] Component designation explanation
[0039] 1. Overcurrent protection circuit
[0040] 11 Overcurrent Sampling Module
[0041] 111 Monitoring Unit
[0042] 112 Comparison Unit
[0043] 12. Gear shifting pre-control module
[0044] 121-123 First, Second, and Third Inverters
[0045] 124-127 First, Second, Third, Fourth and Doors
[0046] 13 File Adjustment Module
[0047] 131-134 First, Second, Third, and Fourth Transmission Units
[0048] 14 Power Selection Module
[0049] 141 Level Conversion Unit
[0050] 142 buffer units
[0051] 143 drive unit
[0052] 2 storage units
[0053] 2a Programmable memory unit
[0054] 3. Multiple-choice data selector
[0055] 4. Amplification and readout circuit Detailed Implementation
[0056] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content described in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0057] Please see Figures 1-5 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0058] Example 1
[0059] like Figure 1 As shown, this embodiment provides an overcurrent protection circuit 1, which includes:
[0060] The system includes an overcurrent sampling module 11, a gear adjustment pre-control module 12, a gear adjustment module 13, and a power selection module 14.
[0061] like Figure 1 As shown, the overcurrent sampling module 11 samples the programming current of the programmable memory cell 2a based on the word line signal WL of the programmable memory cell 2a, and determines the overcurrent level of the programming current based on the difference between the sampled signal and the reference signal Vref.
[0062] Specifically, in this embodiment, the overcurrent sampling module 11 includes a monitoring unit 111 and a comparison unit 112.
[0063] More specifically, the monitoring unit 111 is connected to the bit line of the programmable memory cell 2a and receives the word line signal WL of the programmable memory cell 2a, generating a monitoring signal for the programming current based on the word line signal WL. In this embodiment, the monitoring unit 111 includes a first NMOS transistor M1 and i sampling resistors, where i is a natural number greater than or equal to 2; the source of the first NMOS transistor M1 is grounded, its gate is connected to the word line of the programmable memory cell 2a, and its drain is connected to the bit line of the programmable memory cell 2a via each series-connected sampling resistor; the connection node of each sampling resistor outputs the monitoring signal. As an example, i is set to 4. The first sampling resistor R1, the second sampling resistor R2, the third sampling resistor R3, and the fourth sampling resistor R4 are connected in series between the drain of the first NMOS transistor M1 and the bit line of the memory cell 2a to be programmed. The connection node of the first sampling resistor R1 and the second sampling resistor R2 outputs the first monitoring signal V1, the connection node of the second sampling resistor R2 and the third sampling resistor R3 outputs the second monitoring signal V2, and the connection node of the third sampling resistor R3 and the fourth sampling resistor R4 outputs the third monitoring signal V3. In actual use, the number of sampling resistors can be set as needed. Theoretically, the more sampling resistors there are, the better, not limited to this embodiment.
[0064] More specifically, the comparison unit 112 is connected to the output terminal of the monitoring unit 111, compares the monitoring signal with the reference signal Vref, and outputs the comparison result. In this embodiment, the comparison unit 112 includes (i-1) comparators, the non-inverting input terminal of each comparator is connected to the connection node of each sampling resistor, and the inverting input terminal is connected to the reference signal Vref (as an example, the reference signal Vref is provided by a bandgap reference circuit), and outputs the comparison result, which is used to represent the overcurrent level. As an example, the comparison unit 112 includes 3 comparators, each comparator compares the 3 monitoring signals output by the monitoring unit 111 with the reference signal Vref respectively to obtain 3 corresponding comparison results, denoted as the first comparison result A. <0> Second comparison result A <1> and the third comparison result A <2> The three comparison results form a set of 3-bit data A<2:0>; in actual use, the number of comparators can be set as needed.
[0065] More specifically, such as Figure 1As shown, the first NMOS transistor M1 generates a current in the monitoring unit 111 that has a certain proportional relationship with the programming current of the memory cell 2a to be programmed, based on the word line signal WL, thereby realizing real-time monitoring of the programming current; the current ratio can be adjusted by setting the width-to-length ratio of the first NMOS transistor M1, which will not be elaborated here. As shown in Table 1, if the programming current is normal (i.e., no overcurrent), the third monitoring signal V3, the second monitoring signal V2, and the first monitoring signal V1 are all less than the reference signal Vref, then the output signal A<2:0> of the overcurrent sampling module 11 is 000, corresponding to level 0; if the programming current is slightly overcurrent, the third monitoring signal V3 is greater than the reference signal Vref, and the second monitoring signal V2 and the first monitoring signal V1 are all less than the reference signal Vref, then the output signal A<2:0> of the overcurrent sampling module 11 is 100, corresponding to level 1 ... If the programming current is moderately overcurrent, and both the third monitoring signal V3 and the second monitoring signal V2 are greater than the reference signal Vref, while the first monitoring signal V1 is less than the reference signal Vref, then the output signal A<2:0> of the overcurrent sampling module 11 is 110, corresponding to level 2. If the programming current is highly overcurrent, and the third monitoring signal V3, the second monitoring signal V2, and the first monitoring signal V1 are all greater than the reference signal Vref, then the output signal A<2:0> of the overcurrent sampling module 11 is 111, corresponding to level 3. This allows for the classification and determination of overcurrent levels. In practical use, the classification boundaries can be adjusted by setting the resistance values of each sampling resistor and the voltage value of the reference signal; details are omitted here.
[0066]
[0067]
[0068] Table 1
[0069] It should be noted that any circuit structure capable of monitoring the programming current of the programmable memory cell 2a and obtaining the corresponding overcurrent level is applicable to the present invention, and is not limited to this embodiment.
[0070] like Figure 1 As shown, the gear shifting pre-control module 12 is connected to the output terminal of the overcurrent sampling module 11, and generates a corresponding gear shifting control signal based on the overcurrent level.
[0071] Specifically, in this embodiment, the gear shifting pre-control module 12 is implemented using logic gate circuits. These logic gate circuits obtain an i-bit gear shifting control signal based on the overcurrent level, with only one bit of the i-bit gear shifting control signal corresponding to each overcurrent level being valid. For example... Figure 2As shown, as an example, the gear shifting pre-control module 12 includes a first inverter 121, a second inverter 122, a third inverter 123, a first AND gate 124, a second AND gate 125, a third AND gate 126, and a fourth AND gate 127. The input terminal of the first inverter 121 receives the first comparison result A. <0> The input terminal of the second inverter 122 receives the second comparison result A. <1> The input terminal of the third inverter 123 receives the third comparison result A. <2> The input terminals of the first AND gate 124 are respectively connected to the input terminals of the first inverter 121, the second inverter 122, and the third inverter 123, and output the first gear shifting control signal B. <0> The input terminals of the second AND gate 125 are respectively connected to the output terminal of the first inverter 121, the input terminal of the second inverter 122, and the input terminal of the third inverter 123, and output the second gear shifting control signal B. <1> The input terminals of the third AND gate 126 are respectively connected to the output terminals of the first inverter 121, the second inverter 122, and the third inverter 123, and output the third gear control signal B. <2> The input terminals of the fourth AND gate 127 are respectively connected to the output terminals of the first inverter 121, the second inverter 122, and the third inverter 123, and output the fourth gear shifting control signal B. <3> Four gear shift control signals form a 4-bit data group B<3:0>; in actual use, the number of gear shift control signals can be set as needed. In this example, the number of gear shift signals is consistent with the number of gears.
[0072] Specifically, in this embodiment, the gear shift control signal and the overcurrent level satisfy the following relationship:
[0073]
[0074]
[0075]
[0076] B <0> =A<2>A<1>A<0>.
[0077] Further, as shown in Table 1, when A<2:0>=000, B<3:0>=1000; when A<2:0>=100, B<3:0>=0100; when A<2:0>=110, B<3:0>=0010; when A<2:0>=111, B<3:0>=0001.
[0078] It should be noted that the relationship between the gear shift control signal and the overcurrent level can be set as needed, and the specific structure of the gear shift pre-control module 12 can be set according to the relationship between the two, which is not limited to this embodiment.
[0079] like Figure 1 As shown, the gear shifting module 13 is connected to the output terminal of the gear shifting pre-control module 12, and generates the corresponding gear output voltage VQ1 based on the gear shifting control signal.
[0080] Specifically, in this embodiment, the gear adjustment module 13 includes i voltage divider resistors and i transmission units; the voltage divider resistors are connected in series to form a resistor string, one end of which is connected to a preset programming voltage VQ, and the other end is grounded; the input terminal of each transmission unit is connected to the high-voltage terminal of each voltage divider resistor, the control terminal receives the corresponding gear adjustment control signal, and the output terminals are connected together. Figure 3 As shown in the example, the first voltage divider resistor R5, the second voltage divider resistor R6, the third voltage divider resistor R7, and the fourth voltage divider resistor R8 are connected in series between ground and the preset programming voltage VQ. The connection node of the first voltage divider resistor R5 and the second voltage divider resistor R6 is connected to the input terminal of the first transmission unit 131, the connection node of the second voltage divider resistor R6 and the third voltage divider resistor R7 is connected to the input terminal of the second transmission unit 132, the connection node of the third voltage divider resistor R7 and the fourth voltage divider resistor R8 is connected to the input terminal of the third transmission unit 133, and the high-voltage terminal of the fourth voltage divider resistor R8 (i.e., the preset programming voltage VQ) is connected to the input terminal of the fourth transmission unit 134. The output terminals of each transmission unit are connected together. In this example, each transmission unit uses a transmission gate implemented with a parallel PMOS and NMOS structure to obtain better transmission characteristics. The positive phase control terminal of the first transmission unit 131 receives the first gear shifting control signal B. <0> The inverting control terminal receives the inverted signal of the first gear shifting control signal. The non-phase control terminal of the second transmission unit 132 receives the second gear shifting control signal B. <1> The inverting control terminal receives the inverted signal of the second gear shifting control signal. The non-phase control terminal of the third transmission unit 133 receives the third gear shifting control signal B. <2> The inverting control terminal receives the inverted signal of the third gear shifting control signal. The positive phase control terminal of the fourth transmission unit 134 receives the fourth gear shifting control signal B. <3> The inverting control terminal receives the inverted signal of the fourth gear shifting control signal. Only one transmission unit is active at any given time. At position 0, the fourth transmission unit 134 is active, achieving level 0 voltage reduction (i.e., no voltage reduction). At position 1, the third transmission unit 133 is active, achieving level 1 voltage reduction. At position 2, the second transmission unit 132 is active, achieving level 2 voltage reduction. At position 3, the first transmission unit 131 is active, achieving level 3 voltage reduction. From level 0 to level 3 voltage reduction, the output voltage VQ1 decreases sequentially, thereby minimizing programming power consumption.
[0081] It should be noted that any circuit structure that can output the corresponding voltage according to the step-down level is applicable to the present invention, and is not limited to this embodiment.
[0082] like Figure 1 As shown, the power selection module 14 is connected to the output terminal of the tuning module 13. When in programming mode, the output voltage VQ1 of the tuning module 13 is applied to the bit line of the memory cell 2a to be programmed.
[0083] Specifically, in this embodiment, the power selection module 14 includes a level conversion unit 141, a buffer unit 142, and a driving unit 143.
[0084] More specifically, the power supply terminal of the level conversion unit 141 is connected to the output voltage VQ1 of the gear shifting module 13, and the control terminal receives the programming control signal ps_prog and the read control signal ps_read respectively, and performs level conversion based on the programming control signal ps_prog and the read control signal ps_read; when in read mode, the level conversion unit 141 outputs the output voltage VQ1 of the gear shifting module, and when in programming mode, the level conversion unit 141 outputs a low level. Figure 4 As shown in the figure, as an example, the level conversion unit 141 includes a second NMOS transistor N2, a third NMOS transistor N3, a first PMOS transistor P1, and a second PMOS transistor P2. The source of the second NMOS transistor N2 is grounded, its drain is connected to the drain of the first PMOS transistor P1, and its gate receives the programming control signal ps_prog. The source of the first PMOS transistor P1 is connected to the output voltage VQ1 of the tuning module 13, and its gate is connected to the drain of the second PMOS transistor P2. The source of the third NMOS transistor N3 is grounded, its drain is connected to the drain of the second PMOS transistor P2, and its gate receives the read control signal ps_read. The source of the second PMOS transistor P2 is connected to the output voltage VQ1 of the tuning module 13, and its gate is connected to the drain of the first PMOS transistor P1. The third NMOS transistor N3 and the drain of the second PMOS transistor P2 serve as the output terminals of the level conversion unit 141.
[0085] More specifically, the buffer unit 142 is connected to the output terminal of the level conversion unit 141 to increase the circuit's load driving capability. For example... Figure 4As shown, as an example, the buffer unit 142 includes a fourth NMOS transistor N4, a fifth NMOS transistor N5, a third PMOS transistor P3, and a fourth PMOS transistor P4; the source of the fourth NMOS transistor N4 is grounded, and its drain is connected to the drain of the third PMOS transistor P3; the source of the third PMOS transistor P3 is connected to the output voltage VQ1 of the level adjustment module 13; the gates of the fourth NMOS transistor N4 and the third PMOS transistor P3 are connected to the output terminal of the level conversion unit 141; the source of the fifth NMOS transistor N5 is grounded, and its drain is connected to the drain of the fourth PMOS transistor P4; the source of the fourth PMOS transistor P4 is connected to the output voltage VQ1 of the level adjustment module 13; the gates of the fifth NMOS transistor N5 and the fourth PMOS transistor P4 are connected to the drains of the fourth NMOS transistor N4 and the third PMOS transistor P3; the drains of the fifth NMOS transistor N5 and the fourth PMOS transistor P4 serve as the output terminals of the buffer unit 142.
[0086] More specifically, the driving unit 143 is connected to the output terminal of the buffer unit 142, and the output terminal is connected to the bit line of the programmable memory unit 2a; when in read mode, the driving unit 143 outputs a low level, and when in programming mode, the driving unit 143 outputs the output voltage VQ1 of the tuning module. Figure 4 As shown, as an example, the driving unit 143 includes a sixth NMOS transistor N6 and a fifth PMOS transistor P5; the source of the sixth NMOS transistor N6 is grounded, and its drain is connected to the drain of the fifth PMOS transistor P5; the source of the fifth PMOS transistor P5 is connected to the output voltage VQ1 of the tuning module 13; the gates of the sixth NMOS transistor N6 and the fifth PMOS transistor P5 are connected to the output terminal of the buffer unit 142; the drains of the sixth NMOS transistor N6 and the fifth PMOS transistor P5 serve as the output terminals of the driving unit 143, outputting the programming voltage VQPS of the current memory cell.
[0087] More specifically, such as Figure 4As shown, the level conversion unit 141 filters the power signal through the programming control signal ps_prog and the read control signal ps_read. When the memory cell 2a to be programmed is in the programming state, the programming control signal ps_prog is low and the read control signal ps_read is high. The output of the level conversion unit 141 is pulled to the reference ground, and after passing through the buffer unit 142, the fifth PMOS transistor P5 is turned on and the sixth NMOS transistor N6 is turned off. The output voltage VQ1 of the tuning module 13 is provided to the bit line to provide the corresponding programming voltage to realize the programming function. When the memory cell 2a to be programmed is in the read state, the programming control signal ps_prog is high and the read control signal ps_read is low. The level conversion unit 141 outputs the output voltage VQ1 of the tuning module 13, and after passing through the buffer unit 142, the fifth PMOS transistor P5 is turned off and the sixth NMOS transistor N6 is turned on, and no programming voltage is provided.
[0088] It should be noted that in read mode, the overcurrent protection circuit 1 does not provide voltage. At this time, the read control circuit (not shown in the figure) provides VDD voltage to the bit line as the read voltage, which is used to determine whether the fuse in the memory cell has blown, thereby realizing the read function. The focus of this invention is on overcurrent protection in write mode, and does not involve improvements to read mode. Therefore, the circuit structure and method for reading the memory cell will not be described in detail here.
[0089] The overcurrent protection circuit of this invention reduces the programming current by controlling it at multiple levels, thereby reducing power consumption and overprogramming pollution. The control accuracy can be improved by increasing the number of resistors, comparators, and levels, greatly enhancing flexibility. Furthermore, the circuit operates on a fast level control throughout the entire control cycle, with minimal delay from gate delay and negligible wire delay, resulting in better robustness.
[0090] Example 2
[0091] like Figure 5 As shown, this embodiment provides a memory, the memory comprising:
[0092] The storage array consists of N rows and M columns of storage units 2, a multi-select data selector 3, a row selection control circuit, an amplification readout circuit 4, M read control circuits and M overcurrent protection circuits 1; where N and M are natural numbers greater than or equal to 2.
[0093] like Figure 5 As shown, the storage array is formed by arranging N rows and M columns of storage units 2.
[0094] Specifically, in this embodiment, the number of rows of the storage array is N = 2.n The number of columns in the storage array is M = 2 m n and m are integers greater than or equal to 0. In practical use, the number of rows N and columns M of the storage array can be odd, and are not limited to this embodiment. As an example, the number of rows N of the storage array is greater than the number of columns M. Therefore, with the same number of storage cells, the number of overcurrent protection circuits 1 can be reduced, thereby reducing the area and cost of the entire memory.
[0095] Specifically, in this embodiment, the memory cell 2 includes a fuse and a selector M0. One end of the fuse is connected to the bit line BL, and the other end is connected to the drain of the selector M0. The gate of the selector M0 receives the corresponding word line signal WL, and its source is grounded. In actual use, the memory cell 2 may be more complex. Any memory cell structure that requires programming by blowing a fuse is applicable to this invention, and will not be described in detail here.
[0096] like Figure 5 As shown, the row selection control circuit (not shown in the figure) provides word line signals to each memory cell 2. The specific structure will not be described in detail here.
[0097] like Figure 5 As shown, the input terminal of the multiplexer 3 receives each word line signal and selects one to output the word line signal.
[0098] Specifically, when a row is selected for programming operations, the multiple-to-one data selector selects the corresponding bit line signal and outputs it to each overcurrent protection circuit.
[0099] like Figure 5 As shown, the input terminal of each overcurrent protection circuit 1 is connected to the output terminal of the multiplexer 3, and the output terminal is connected to one bit line respectively. In programming mode, overcurrent protection is provided for the storage cells on each bit line.
[0100] Specifically, the number of overcurrent protection circuits 1 is the same as the number of bit lines. The circuit structure and working principle of the overcurrent protection circuit 1 are described in Embodiment 1, and will not be repeated here.
[0101] like Figure 5 As shown, the output terminals of each read control circuit (not shown in the figure) are connected to one bit line respectively, and in read mode, the read voltage VDD is provided to the memory cell on each bit line.
[0102] Specifically, the number of read control circuits is the same as the number of bit lines, and they are used to provide read voltage VDD to the memory cells on each bit line in read mode. The specific structure will not be described in detail here.
[0103] It should be noted that in write mode, the preset programming voltage VQ is used to program the memory cell to be programmed. In read mode, the read voltage VDD is used to read the data in the memory cell. Generally, the read voltage VDD is less than the preset programming voltage VQ. Taking 1.8 / 3.3V CMOS process as an example, the preset programming voltage VQ is generally given a bias of 3.3V, and the read voltage VDD is given a bias of 1.8V.
[0104] like Figure 5 As shown, the amplification and readout circuit 4 is connected to each bit line to read out the output signal of each column.
[0105] Specifically, the amplification and readout circuit 4 is connected to the readout voltage VDD as its operating voltage and processes the output data of the selected row to read the data OUTPUT from each storage cell in the memory row by row. <p:0>P is a natural number greater than or equal to 1, which can be set according to actual needs, and will not be elaborated here.
[0106] The overcurrent protection circuit of this invention is compatible with efuse programmable memory arrays. Each bit line occupies one overcurrent protection circuit, which can improve the reliability of the efuse array and realize the automatic and controllable melting of multiple fuses.
[0107] In summary, this invention provides an overcurrent protection circuit and a memory, comprising: an overcurrent sampling module, a level-adjustment pre-control module, a level-adjustment module, and a power selection module; the overcurrent sampling module samples the programming current of the memory cell to be programmed based on the word line signal of the memory cell to be programmed, and determines the overcurrent level of the programming current based on the difference between the sampled signal and a reference signal; the level-adjustment pre-control module is connected to the output terminal of the overcurrent sampling module and generates a corresponding level-adjustment control signal based on the overcurrent level; the level-adjustment module is connected to the output terminal of the level-adjustment pre-control module and generates an output voltage of a corresponding level based on the level-adjustment control signal; the power selection module is connected to the output terminal of the level-adjustment module and applies the output voltage of the level-adjustment module to the bit line of the memory cell to be programmed when in programming mode. The overcurrent protection circuit and memory of this invention monitor the current magnitude of the programming circuit in real time through an overcurrent sampling module and provide corresponding circuit control feedback. This allows for rapid voltage reduction of excessive current, thereby decreasing the current magnitude and ultimately lowering the circuit's programming power, preventing over-programming of the fuse resistor. Flexible voltage adjustment is possible to meet different circuit specifications, ensuring that the circuit does not immediately shut down upon overcurrent but instead continues to operate normally after the voltage is reduced to a certain level. It is compatible with fuse programmable memory and can be embedded within existing array modules, integrating into the overall IP design to improve circuit reliability. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.
[0108] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. An overcurrent protection circuit applied to an efuse programmable memory, characterized in that, The overcurrent protection circuit includes at least: Overcurrent sampling module, gear pre-control module, gear adjustment module and power selection module; The overcurrent sampling module samples the programming current of the memory cell to be programmed based on the word line signal of the memory cell to be programmed, and determines the overcurrent level of the programming current based on the difference between the sampled signal and the reference signal. The overcurrent sampling module includes a monitoring unit and a comparison unit. The monitoring unit is connected to the bit line of the memory cell to be programmed and receives the word line signal of the memory cell to be programmed, and generates a monitoring signal of the programming current based on the word line signal. The comparison unit is connected to the output terminal of the monitoring unit, compares the monitoring signal with the reference signal, and outputs the comparison result. The monitoring unit includes a first NMOS transistor and i sampling resistors. The source of the first NMOS transistor is grounded, the gate is connected to the word line of the memory cell to be programmed, and the drain is connected to the bit line of the memory cell to be programmed through each series sampling resistor. The connection node of each sampling resistor outputs the monitoring signal. i is a natural number greater than or equal to 2. The gear shifting pre-control module is connected to the output terminal of the overcurrent sampling module and generates a corresponding gear shifting control signal based on the overcurrent level; The gear shifting module is connected to the output terminal of the gear shifting pre-control module and generates the corresponding gear output voltage based on the gear shifting control signal; The power selection module is connected to the output terminal of the tuning module. When in programming mode, the output voltage of the tuning module is applied to the bit line of the memory cell to be programmed to avoid overprogramming.
2. The overcurrent protection circuit according to claim 1, characterized in that: The comparison unit includes (i-1) comparators. The non-inverting input of each comparator is connected to the connection node of each sampling resistor, and the inverting input is connected to the reference signal. The comparison result is output to represent the overcurrent level.
3. The overcurrent protection circuit according to claim 1 or 2, characterized in that: The gear shift control signal is i-bit, and only one bit of the i-bit gear shift control signal corresponding to each overcurrent level is valid.
4. The overcurrent protection circuit according to claim 3, characterized in that: The gear adjustment module includes i voltage divider resistors and i transmission units; each voltage divider resistor is connected in series to form a resistor string, one end of which is connected to a preset programming voltage and the other end is grounded; the input terminal of each transmission unit is connected to the high voltage terminal of each voltage divider resistor, the control terminal receives the corresponding gear adjustment control signal, and the output terminals are connected together.
5. The overcurrent protection circuit according to claim 1, characterized in that: The power selection module includes a level conversion unit, a buffer unit, and a drive unit; The power supply terminal of the level conversion unit is connected to the output voltage of the gear adjustment module, and the control terminal receives the programming control signal and the reading control signal respectively, and performs level conversion based on the programming control signal and the reading control signal; The buffer unit is connected to the output terminal of the level conversion unit; The driving unit is connected to the output terminal of the buffer unit, and the output terminal is connected to the bit line of the memory unit to be programmed; When in read mode, the drive unit outputs a low level; when in programming mode, the drive unit outputs the output voltage of the gear shifting module.
6. A memory, characterized in that, The memory includes at least: a storage array consisting of N rows and M columns of storage cells, a multi-select data selector, a row selection control circuit, an amplification readout circuit, M readout control circuits, and M overcurrent protection circuits as described in any one of claims 1-5; wherein N and M are natural numbers greater than or equal to 2; The row selection control circuit provides word line signals to each memory cell; The input of the multiple-choice data selector receives each word line signal and selects one to output the word line signal; The input terminals of each overcurrent protection circuit are connected to the output terminals of the multiplexer, and the output terminals are each connected to a bit line. In programming mode, overcurrent protection is provided for the memory cells on each bit line. The memory cell includes a fuse and a selector. One end of the fuse is connected to the bit line, and the other end is connected to the drain of the selector. The gate of the selector receives the corresponding word line signal, and the source is grounded. Each read control circuit's output terminal is connected to a bit line, providing read voltage to the storage cells on each bit line in read mode; The amplification and readout circuit is connected to each bit line to read out the output signal of each column.
7. The memory according to claim 6, characterized in that: The number of rows N in the storage array is greater than the number of columns M.