A storage device, control method, and memory system

Abstract

Embodiments of the present application provide a storage device, a control method and a memory system, the storage device comprising: a storage cell array comprising a plurality of storage strings and word lines coupled to the storage strings; a peripheral circuit coupled to the storage cell array, the peripheral circuit configured to perform a program operation on storage cells of a storage string coupled to a selected word line; the program operation comprising coarse programming and fine programming; the peripheral circuit further configured to, during the coarse programming, derive a first voltage parameter according to a first compensation parameter, and apply a first pass voltage to unselected word lines based on the first voltage parameter; during the fine programming, derive a second voltage parameter according to a second compensation parameter, and apply a second pass voltage to the unselected word lines based on the second voltage parameter.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a storage device, control method, and memory system. Background Technology

[0002] Low-power, lightweight, and high-performance non-volatile storage devices, such as NAND flash memory, are widely used in electronic products.

[0003] However, in related technologies, when programming the memory cells in a non-volatile memory device, it is easy to cause the read window of some memory cells in the non-volatile memory device to decrease.

[0004] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Various operations, such as reading, programming (writing), and erasing, can be performed on flash memory devices to change the threshold voltage of each storage cell to a desired level. For NAND flash memory devices, erasure operations can be performed at the block level, and programming or reading operations can be performed at the page level. Summary of the Invention

[0005] This application provides a storage device, a control method, and a memory system.

[0006] In a first aspect, embodiments of this application provide a storage device, the storage device comprising:

[0007] A storage cell array, the storage cell array comprising a plurality of storage strings and word lines coupled to the storage strings;

[0008] Peripheral circuitry coupled to the memory cell array is configured to perform programming operations on memory cells of a memory string coupled to a selected word line; the programming operations include coarse programming and fine programming.

[0009] The peripheral circuitry is further configured to: during the coarse programming phase, obtain a first voltage parameter based on a first compensation parameter, and apply a first pass voltage to the unselected word line based on the first voltage parameter; during the fine programming phase, obtain a second voltage parameter based on a second compensation parameter, and apply a second pass voltage to the unselected word line based on the second voltage parameter.

[0010] In one alternative implementation, the peripheral circuit is specifically configured to: obtain the first voltage parameter based on a first standard through voltage and the first compensation parameter during the coarse programming; and obtain the second voltage parameter based on a second standard through voltage and the second compensation parameter during the fine programming.

[0011] The first standard passes through a different voltage than the second standard.

[0012] In one alternative implementation, the peripheral circuitry is specifically configured to apply the first pass voltage to the unselected word line while simultaneously applying the first standard pass voltage to the selected word line based on the first voltage parameter during the coarse programming.

[0013] In one alternative implementation, the peripheral circuitry is specifically configured to apply the second pass voltage to the unselected word line while simultaneously applying the second standard pass voltage to the selected word line based on the second voltage parameter during the fine programming.

[0014] In one alternative implementation, for the same unselected word line: the first compensation parameter and the second compensation parameter are different; the first voltage parameter and the second voltage parameter are different.

[0015] In one alternative implementation, for different unselected word lines: the first compensation parameter is different for different unselected word lines, and the second compensation parameter is different for different unselected word lines.

[0016] In one alternative implementation, each of the storage units is configured to have 2 x One of the storage states stores x bits of data, where x is an integer greater than 1.

[0017] Secondly, embodiments of this application provide a control method for a storage device, the storage device including a storage cell array, the storage cell array including a plurality of storage strings and word lines coupled to the storage strings, the method including:

[0018] Perform programming operations on the memory cells of the memory string coupled to the selected word line; the programming operations include coarse programming and fine programming;

[0019] During the coarse programming, a first voltage parameter is obtained according to a first compensation parameter, and a first pass voltage is applied to the unselected word line based on the first voltage parameter; during the fine programming, a second voltage parameter is obtained according to a second compensation parameter, and a second pass voltage is applied to the unselected word line based on the second voltage parameter.

[0020] In one optional implementation, obtaining the first voltage parameter based on the first compensation parameter includes:

[0021] The first voltage parameter is obtained based on the first standard through voltage and the first compensation parameter.

[0022] In one optional implementation, obtaining the first voltage parameter based on the first compensation parameter includes:

[0023] The second voltage parameter is obtained according to the second standard through the voltage and the second compensation parameter;

[0024] The first standard passes through a different voltage than the second standard.

[0025] In one alternative implementation, applying a first pass voltage to the unselected word line based on the first voltage parameter includes:

[0026] While applying the first pass voltage to the unselected word line based on the first voltage parameter, the first standard pass voltage is applied to the selected word line.

[0027] In one alternative implementation, applying a second pass voltage to the unselected word line based on the second voltage parameter includes:

[0028] While applying the second pass voltage to the unselected word line based on the second voltage parameter, the second standard pass voltage is applied to the selected word line.

[0029] In one alternative implementation, for the same unselected word line: the first compensation parameter and the second compensation parameter are different; the first voltage parameter and the second voltage parameter are different.

[0030] In one alternative implementation, for different unselected word lines: the first compensation parameter is different for different unselected word lines, and the second compensation parameter is different for different unselected word lines.

[0031] In one alternative implementation, each of the storage units is configured to have 2 x One of the storage states stores x bits of data, where x is an integer greater than 1.

[0032] Thirdly, embodiments of this application provide a memory system, including a controller and the storage device described in the above technical solutions; the controller is coupled to the storage device and is used to control the storage device. Attached Figure Description

[0033] Figure 1 This is a block diagram of a memory system according to an exemplary embodiment of this application;

[0034] Figure 2A This is a schematic diagram illustrating a memory card according to an exemplary embodiment of this application;

[0035] Figure 2BThis is a schematic diagram illustrating a solid-state drive (SSD) according to an exemplary embodiment of this application;

[0036] Figure 3 A schematic diagram of an exemplary storage device including peripheral circuitry provided for embodiments of this application.

[0037] Figure 4 A side view of a cross-section of an exemplary memory cell array including memory strings, provided for an embodiment of this application.

[0038] Figure 5 Block diagram of an exemplary storage device including a storage cell array and peripheral circuitry provided for embodiments of this application;

[0039] Figure 6 The word line priority order for performing coarse programming and fine programming is provided in the embodiments of this application;

[0040] Figure 7 A schematic diagram illustrating the implementation flow of the control method for the storage device provided in the embodiments of this application;

[0041] Figure 8 This is a schematic diagram of the through voltage curves corresponding to different word lines provided in the embodiments of this application;

[0042] Figure 9 A distribution diagram of the threshold voltage of the memory cell in the memory device provided in the embodiments of this application;

[0043] Figure 10 This is a schematic diagram of the structure of a storage device provided in an embodiment of this application. Detailed Implementation

[0044] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0045] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0046] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0047] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0048] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0049] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0050] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0051] refer to Figure 1 , Figure 1 This is a block diagram illustrating a memory system according to an exemplary embodiment of this application. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more storage devices 104 and a controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the storage device 104.

[0052] Storage device 104 may be any storage device disclosed herein. As detailed below, storage device 104 may be (e.g., a NAND flash memory storage device (e.g., a three-dimensional (3D) NAND flash memory storage device)).

[0053] According to some embodiments, controller 106 is coupled to storage device 104 and host 108 and is configured to control storage device 104. Controller 106 can manage data stored in storage device 104 and communicate with host 108. In some embodiments, controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, controller 106 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs), which are used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays. Controller 106 can be configured to control the operation of storage device 104, such as read, erase, and program operations. Controller 106 can also be configured to manage various functions related to data stored or to be stored in storage device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, controller 106 is also configured to process error correction codes (ECC) for data read from or written to storage device 104. Controller 106 may also perform any other suitable functions, such as formatting storage device 104. Controller 106 may communicate with external devices (e.g., host 108) according to specific communication protocols. For example, controller 106 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0054] The controller 106 and one or more storage devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2AIn one example shown, controller 106 and a single storage device 104 can be integrated into memory card 202. Memory card 202 may include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. Memory card 202 may also include a connection between memory card 202 and a host (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2B In another example shown, controller 106 and multiple storage devices 104 may be integrated into SSD 206. SSD 206 may also include a connection between SSD 206 and a host (e.g., Figure 1 The SSD connector 208 is coupled to the host 108 in the host. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0055] Figure 3 A schematic circuit diagram of an exemplary storage device 300, including peripheral circuitry, is shown according to some aspects of this application. The storage device 300 may be... Figure 1 An example of storage device 104 is shown. Storage device 300 may include a storage cell array 301 and peripheral circuitry 302 coupled to the storage cell array 301. The storage cell array 301 may be a NAND flash memory cell array, wherein storage cells 306 are provided in the form of an array of NAND storage strings 308, each extending vertically above a substrate (not shown). In some embodiments, each NAND storage string 308 includes a plurality of storage cells 306 coupled in series and stacked vertically. Each storage cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the storage cell 306. Each storage cell 306 may be a floating-gate storage cell including a floating-gate transistor or a charge-trapping storage cell including a charge-trapping transistor.

[0056] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible storage states (levels) and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a first threshold voltage range, and a second storage state "1" may correspond to a second threshold voltage range. In some implementations, each memory cell 306 is an xLC capable of storing more than a single bit of data in more than or equal to four storage states (levels), such as a multi-level cell (MLC), a three-level cell (TLC), a four-level cell (QLC), etc. Each memory cell can be configured to store more than one bit of data in 2... xOne of the storage states stores x bits of data, where x is an integer greater than 1. 2 x The storage states include erase state and 2. x -1 programming state. In one example, each QLC memory cell can be configured to store 4 bits of data in one of 16 memory states (P0-P15), where P0 is the erase state and P1-P15 are 15 programming states respectively.

[0057] like Figure 3 As shown, each NAND memory string 308 may also include a source-select-gate (SSG) transistor 310 at its source end and a drain-select-gate (DSG) transistor 312 at its drain end. The SSG transistor 310 and DSG transistor 312 can be configured to activate the selected NAND memory string 308 (column of the array) during read and program operations. Figure 3 As shown, NAND memory strings 308 can be organized into multiple memory blocks 304. In some embodiments, the sources of NAND memory strings 308 in the same memory block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the drain of each NAND memory string 308 is coupled to a corresponding bit line 316, from which data can be read or written via an output bus (not shown). In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage or deselect voltage to the gate of a corresponding DSG transistor 312 via one or more DSG lines 313 and / or by applying a select voltage or deselect voltage to the gate of a corresponding SSG transistor 310 via one or more SSG lines 315.

[0058] like Figure 3As shown, each memory block may have, for example, a common source line 314 coupled to the ACS. In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block 304, an erase voltage (Vers) (e.g., a high positive bias (e.g., 20V or greater)) can be used to bias the source line 314 coupled to the selected memory block 304 and the unselected memory blocks 304 in the same plane as the selected memory block 304. Memory cells of adjacent NAND memory strings can be coupled via word lines, which can select which row of memory cells is affected by read and program operations. In some embodiments, each word line 318 is coupled to a memory page 320 of memory cell 306, which is the basic data unit for read and program operations. The size of a memory page 320, in bits, may be related to the number of NAND memory strings 308 coupled by word lines 318 in a memory block 304. Each word line 318 may include multiple control gates (gate electrodes) and gate lines coupled to the control gates at each memory cell 306 in the corresponding memory page 320.

[0059] like Figure 3 As shown, the memory cell array 301 may include an array of memory cells 306 in multiple rows and columns within each memory block 304. According to some embodiments, a row of memory cells 306 corresponds to one or more memory pages 320, and a column of memory cells corresponds to a NAND memory string 308. Multiple rows of memory cells 306 may be coupled to different word lines 318, and multiple columns of memory cells 306 may be coupled to different bit lines 316. Peripheral circuitry 302 may be coupled to the memory cell array 301 via the bit lines 316 and word lines 318.

[0060] Figure 4 A side view of a cross-section of an exemplary memory cell array 301 including NAND memory strings 308 is shown, according to some aspects of this disclosure. Figure 4 As shown, the NAND memory string 308 can extend vertically through the memory stack layer 404 above the substrate 402. The substrate 402 can include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0061] The memory stack 404 may include alternating gate conductive layers 406 and gate-to-gate dielectric layers 408. The number of pairs of gate conductive layers 406 and gate-to-gate dielectric layers 408 in the memory stack 404 determines the number of memory cells 306 in the memory cell array 301. The gate conductive layers 406 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, each gate conductive layer 406 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 406 includes a doped polysilicon layer. Each gate conductive layer 406 may include a control gate surrounding the memory cell 306 and may extend laterally at the top of the memory stack 404 as a DSG line 313, at the bottom of the memory stack 404 as an SSG line 315, or between DSG lines 313 and SSG lines 315 as a word line 318.

[0062] like Figure 4 As shown, the NAND flash memory string 308 includes a channel structure 412 extending vertically through the memory stack layer 404. In some embodiments, the channel structure 412 includes channel vias filled with one or more semiconductor materials (e.g., as semiconductor channel 420) and one or more dielectric materials (e.g., as memory film 418). In some embodiments, the semiconductor channel 420 includes silicon, for example, polysilicon. In some embodiments, the memory film 418 is a composite dielectric layer including a tunneling layer 426, a storage layer 424 (also referred to as a "charge trap / storage layer"), and a barrier layer 422. The channel structure 412 may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel 420, tunneling layer 426, storage layer 424, and barrier layer 422 are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer 426 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 424 may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer 422 may comprise silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film 418 may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0063] According to some implementation methods, such as Figure 4As shown, a well 414 (e.g., a P-well and / or an N-well) is formed in a substrate 402, and the source terminal of the NAND memory string 308 is in contact with the well 414. For example, a source line 314 may be coupled to the well 414 to apply an erase voltage to the well 414 (i.e., the source of the NAND memory string 308) during an erase operation. In some embodiments, the NAND memory string 308 also includes a channel plug 416 at the drain terminal of the NAND memory string 308. It should be understood that, although in Figure 4 Additional components, not shown, but which may form the memory cell array 301, include, but are not limited to, gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0064] Return to reference Figure 3 The peripheral circuitry 302 can be coupled to the memory cell array 301 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic unit 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0065] Page buffer / sensor amplifier 504 can be configured to read data from and program (write) data to memory cell array 301 according to control signals from control logic unit 512. In one example, page buffer / sensor amplifier 504 can store a page of programming data (write data) to be programmed into a memory page 320 of memory cell array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic unit 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0066] The row decoder / word line driver 508 can be configured to be controlled by the control logic unit 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of the memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive SSG lines 315 and DSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform an erase operation on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by the control logic unit 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0067] Control logic unit 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic unit 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic unit 512 and acts as a control buffer to buffer control commands received from a host (not shown) and relay them to control logic unit 512, as well as to buffer status information received from control logic unit 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bit line driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 301.

[0068] Storage devices can store more than one bit of information in each storage cell with multiple storage states, increasing storage capacity and reducing cost per bit. In NAND flash memory devices, the intersection of word lines and storage strings forms multiple storage cells. A storage block includes multiple strings. Each storage string is coupled to a bit line. During programming operations, data can be written to xLC such as MLC, TLC, QLC, etc. For xLC, multiple programming operations can be used to reduce programming time and increase read margin. These multiple programming operations involve coarse programming, which programs the xLC to one of the intermediate stages, and fine programming, which programs the xLC from the intermediate stage to the final stage.

[0069] Figure 6 This shows the word line priority order for performing coarse and fine programming. For example... Figure 6 As shown, the word line priority order includes an order in which memory cells in adjacent fingers of a single line are programmed sequentially (e.g., one after another), and memory cells in adjacent lines are programmed in an interleaved manner. Figure 6 In this text, "Finger 0" to "Finger 5" represent six fingers arranged in the storage device. "WL" represents the word line number. For example, WL0 represents the bottom word line (e.g., word line 0, adjacent to SSG), WL1 represents the word line immediately above word line 0 (e.g., word line 1), WL2 represents the word line immediately above word line 1 (e.g., word line 2), ..., WLm represents the top word line (e.g., word line m, adjacent to DSG). In some embodiments, the word lines are programmed from word line 0 to word line 1. As an example, Figure 6The programming operation for each memory cell shown is a two-stage process involving coarse programming and fine programming. Memory cells in finger sections 0–5 all undergo the corresponding coarse programming and fine programming. Figure 6 In this context, "coarse" represents the coarse programming sequence number, and "fine" represents the fine programming sequence number.

[0070] In some embodiments, coarse programming is achieved by sequentially programming the memory cells in row 0 (i.e., memory cells coupled to the 0th word line) from finger 0 to finger 5, with the programming order of the finger segments shown as numbers 0-5. Then, coarse programming is achieved by sequentially programming the memory cells in row 1 (i.e., memory cells coupled to the 1st word line) from finger 0 to finger 5, with the programming order of the finger segments shown as numbers 6-11. Then, fine programming is achieved by sequentially programming the memory cells in row 0 from finger 0 to finger 5, with the programming order of the finger segments shown as numbers 12-17. Finally, coarse programming is achieved by sequentially programming the memory cells in row 2 (i.e., memory cells coupled to the 2nd word line) from finger 0 to finger 5, with the programming order of the finger segments shown as numbers 18-23. Then, the memory cells in the first row are programmed sequentially from finger 0 to finger 5 to achieve fine programming, with the programming order of the finger segments shown as numbers 24-29. Next, the memory cells in the third row (i.e., the memory cells coupled to the third word line) are programmed sequentially from finger 0 to finger 5 to achieve coarse programming, with the programming order of the finger segments shown as numbers 30-35. Then, the memory cells in the second row are programmed sequentially from finger 0 to finger 5 to achieve fine programming, with the programming order of the finger segments shown as numbers 36-41. As described above, the memory cells coupled to the remaining word lines can be programmed repeatedly according to word line priority until the memory cells coupled to the m-th word line are finely programmed.

[0071] As an example, the second word line can be a selected word line, and in finger sections 0 to 5, the memory cells coupled to the second word line can be memory cells of a selected row. When the memory cells of the selected row are being coarse-programmed, all memory cells in the row coupled to the first word line have been coarse-programmed but not fine-programmed. For example, the memory cells in finger section 0 and coupled to the second word line may first be coarse-programmed (number 18), the memory cells in finger section 1 and coupled to the second word line may then be coarse-programmed (number 19), the memory cells in finger section 0 and coupled to the first word line may then be fine-programmed (number 24), the memory cells in finger section 1 and coupled to the first word line may then be fine-programmed (number 25), the memory cells in finger section 0 and coupled to the second word line may then be fine-programmed (number 36), and the memory cells in finger section 1 and coupled to the second word line may then be fine-programmed (number 37). That is, while the memory cells of the selected row are undergoing coarse programming, the memory cells of the unselected rows immediately below the selected row have not yet undergone fine programming. In other words, between the two programming passes of WLn (coarse programming of WLn and fine programming of WLn), fine programming of WLn-1 and coarse programming of WLn+1 will be inserted.

[0072] During coarse programming of WLn, the memory cells of word lines WLn+1 and above are in an erased state. During fine programming of WLn, the memory cell WLn+1 has already been coarsely programmed (is in a programming state), while the memory cells of word lines WLn+2 and above are in an erased state. Therefore, the channel boosting conditions for each memory cell are not entirely the same, resulting in differences in the boosting conditions for each word line. In other words, when the same memory cell undergoes multiple programming operations, the state of the same word line during coarse programming and fine programming may differ.

[0073] During programming, a pass voltage (Vpass) can be applied to the unselected word line to boost the channel voltage of the unselected memory cell, thereby reducing the potential difference between the programming voltage applied to the selected word line and the boosted voltage in the channel of the unselected memory cell, thus reducing program disturb. If the pass voltage is too low, the potential difference between the programming voltage applied to the selected word line and the boosted voltage in the channel of the unselected memory cell will be too large, leading to increased programming disturb. However, when a pass voltage (Vpass) is applied to the unselected word line, the potential difference between the gate and channel of the unselected memory cell creates an electric field. This electric field strength allows electrons to enter the memory layer with a certain probability, especially when the tunneling layer's isolation performance is poor or degraded (e.g., after many erase / write cycles). If the pass voltage is too high, the electric field strength formed between the gate and channel will be too large, increasing the probability of electrons entering the memory layer. Therefore, unselected memory cells are affected by the pass voltage (Vpass) to some extent, a phenomenon known as pass voltage disturb.

[0074] Therefore, both excessively high and excessively low pass voltages (Vpass) can interfere with unselected memory cells. For example, excessively low pass voltages (Vpass) can cause programming interference, while excessively high pass voltages (Vpass) can cause pass voltage interference. Thus, the pass voltage (Vpass) usually needs to be selected within a specific voltage range, which is called the pass voltage window (Vpasswindow).

[0075] As mentioned earlier, during multiple programming passes, the states of different word lines are different, and the state of the same word line may also differ between coarse and fine programming. This results in inconsistent channel boosting conditions for each memory cell, leading to variations in the boosting conditions for each word line. Consequently, if the same word line voltage is applied to all word lines, interference problems in the memory cells will become more severe, impacting the reliability and performance of the memory device.

[0076] In response, this application proposes the following implementation methods.

[0077] This application provides a method for controlling a storage device. Figure 7 This is a schematic diagram illustrating the implementation flow of the control method for the storage device provided in an embodiment of this application. The storage device includes a storage cell array, which includes multiple storage strings and word lines coupled to the storage strings, such as... Figure 7 As shown, the method includes:

[0078] Step 701: Perform programming operations on the memory cells of the memory string coupled to the selected word line; the programming operations include coarse programming and fine programming;

[0079] Step 702: During the coarse programming, a first voltage parameter is obtained according to a first compensation parameter, and a first pass voltage is applied to the unselected word line based on the first voltage parameter; during the fine programming, a second voltage parameter is obtained according to a second compensation parameter, and a second pass voltage is applied to the unselected word line based on the second voltage parameter.

[0080] In this embodiment, the first compensation parameter and the second compensation parameter can be word line compensation parameters. These word line compensation parameters can be used to generate voltage parameters, thereby allowing different pass voltages to be applied to unselected word lines based on different voltage parameters. Here, the first compensation parameter can be determined based on the number of failure bits in coarse programming, and the second compensation parameter can be determined based on the number of failure bits in fine programming.

[0081] In this embodiment, for the same unselected word line, the first compensation parameter and the second compensation parameter are different. In other words, in this embodiment, the compensation parameters for the same word line are different in coarse programming and fine programming. Thus, compensation can be applied to the same unselected word line in coarse programming and fine programming based on different compensation parameters, thereby reducing programming interference and voltage interference, and improving the reliability of the memory device.

[0082] In this embodiment, for the same unselected word line, the first voltage parameter and the second voltage parameter are different. In other words, in this embodiment, the voltage parameters of the same word line are different in coarse programming and fine programming. Thus, different through voltages can be applied to the same unselected word line in coarse programming and fine programming based on different voltage parameters, thereby reducing programming interference and through voltage interference, and improving the reliability of the memory device.

[0083] In this embodiment, the first compensation parameter and the second compensation parameter are different for different unselected word lines. Because the word line positions differ during multiple programming passes, the degree of programming interference and voltage interference varies for each word line. Therefore, in this embodiment, the compensation parameters for different unselected word lines are different in each programming process to adapt to the different word line states. In this way, different voltage parameters can be obtained based on different compensation parameters, and different through voltages can be applied to different unselected word lines based on these different voltage parameters.

[0084] In this embodiment, unselected word lines can be further classified into ordinary word lines and special word lines (specialWL), with different compensation parameters for different categories to adapt to the states of different categories of unselected word lines. Thus, different voltage parameters can be obtained based on different compensation parameters, and different pass voltages can be applied to different categories of unselected word lines based on these different voltage parameters. Special word lines can be unselected word lines located near the edges of the memory cell array, such as SSG lines and DSG lines. Ordinary word lines are other unselected word lines besides special word lines.

[0085] In the embodiments of this application, the compensation parameters for different word lines in the same programming process, as well as the compensation doping for the same word line in different programming processes, are all different. In other words, the compensation parameters for each word line in the embodiments of this application can change with the changes in different programming processes in multiple programming passes, thereby achieving adaptive compensation for the through voltage of word lines in different states.

[0086] In this embodiment, obtaining the first voltage parameter based on the first compensation parameter includes: obtaining the first voltage parameter based on the first standard pass voltage and the first compensation parameter. Obtaining the first voltage parameter based on the first compensation parameter includes: obtaining the second voltage parameter based on the second standard pass voltage and the second compensation parameter; wherein the first standard pass voltage and the second standard pass voltage are different. Here, the first standard pass voltage can be the reference pass voltage for coarse programming. Compensating the first standard pass voltage based on the first compensation parameter of coarse programming yields the first voltage parameter adapted to the word line states in coarse programming; the second standard pass voltage can be the reference pass voltage for fine programming. Compensating the second standard pass voltage based on the second compensation parameter of fine programming yields the second voltage parameter adapted to the word line states in fine programming.

[0087] In this embodiment, applying a first pass voltage to the unselected word line based on the first voltage parameter includes: simultaneously applying a first pass voltage to the unselected word line based on the first voltage parameter and applying a first standard pass voltage to the selected word line. Here, a coarse-programmed reference pass voltage can be directly applied to the selected word line.

[0088] In this embodiment, applying a second pass voltage to the unselected word line based on the second voltage parameter includes: simultaneously applying a second pass voltage to the unselected word line based on the second voltage parameter and applying a second standard pass voltage to the selected word line. Here, a fine-programming reference pass voltage can be directly applied to the selected word line.

[0089] Figure 8 This is a schematic diagram of the voltage curves corresponding to different word lines provided in the embodiments of this application. It should be noted that... Figure 8The diagram illustrates the voltage curves of memory cells on different word lines of a memory string during fine programming and coarse programming. Figure 8 In the diagram, the horizontal axis represents the first / second through voltage, and the vertical axis represents the E0 window. Figure 9 The distribution diagram of the threshold voltage of the memory cell in the memory device provided in the embodiments of this application is as follows: Figure 9 As shown, Figure 9 The diagram illustrates the distribution of threshold voltages in MLC memory cells. A window distance exists between each memory state, and this window distance is divided into multiple windows. For example, windows E0 and E1 are located between the erase state P0 and the first programming state P1, with window E0 closer to erase state P0 and window E1 closer to first programming state P1. Similarly, the window distance between first programming state P1 and second programming state P2 is divided into windows E2 and E3, and the window distance between second programming state P2 and third programming state P3 is divided into windows E4 and E5. Figure 8 As shown, in the through voltage curves of the memory cells of each word line, the through voltage corresponding to the maximum E0 window is the optimal through voltage, which means that the E0 window is at its maximum under this optimal through voltage.

[0090] according to Figure 8 Analysis shows that: the optimal first pass voltage for WL126 during coarse programming is approximately 5.1V, and the optimal second pass voltage for WL126 during fine programming is approximately 6.5V; for WL80, the optimal first pass voltage during coarse programming is approximately 5.2V, and the optimal second pass voltage for WL80 during fine programming is approximately 3.25V; for WL54, the optimal first pass voltage during coarse programming is approximately 4.6V, and the optimal second pass voltage for WL54 during fine programming is approximately 5V; for WL36, the optimal first pass voltage during coarse programming is approximately 5.5V, and the optimal second pass voltage for WL36 during fine programming is approximately 3V. When performing multiple programming passes, the pass voltage windows for different word lines of the same memory string are different, and the pass voltage windows for the same word line of the same memory string may also be different during coarse and fine programming. Therefore, the optimal pass voltages for different word lines of the same memory string are different, and the optimal pass voltages for the same word line of the same memory string may also be different during coarse and fine programming.

[0091] Because the voltage window for the same word line may differ across different programming operations in multiple programming passes, meaning the optimal voltage may vary, uniformly applying the same voltage parameters based on the same compensation parameters to unselected word lines will cause a mismatch between the voltage for each word line and its current state, resulting in programming interference or voltage interference. For example, during fine programming of WLn, memory cells in WLn+1 have already undergone coarse programming (are in a programming state), thus creating local self-boosting in the WLn+1 region. Meanwhile, memory cells in WLn+2 and above are in an erase state; therefore, the voltage window for memory cells in WLn+2 and above differs between the fine programming and coarse programming processes of WLn. Combined with... Figure 8 Specific examples are analyzed below: For instance, regarding coarse programming, when the first standard pass voltage is 5V and the fixed compensation parameter for coarse programming is 0.3V, the first voltage parameter obtained based on the first standard pass voltage and the fixed compensation parameter for coarse programming is 5V + 0.3V = 5.3V. Therefore, a first pass voltage of 5.3V is applied to the unselected word line according to this first voltage parameter. And combined with... Figure 8 As shown, the 5.3V first pass voltage is not suitable for WL126, WL80, WL54 and WL36, and is even far from the optimal first pass voltage for WL54 and WL36. Both excessively high and excessively low pass voltages will cause interference to unselected memory cells. For example, excessively low pass voltage (Vpass) will cause programming interference, and excessively high pass voltage (Vpass) will cause pass voltage interference.

[0092] Based on this, in the embodiments of this application, during coarse programming and fine programming, a first pass voltage and a second pass voltage are applied to the unselected word lines based on the first voltage parameter and the second voltage parameter, respectively. This method of applying pass voltages to unselected word lines using different voltage parameters during different programming operations in multiple programming passes allows the pass voltage corresponding to each word line to be more compatible with the current state of that word line, thereby reducing programming interference and pass voltage interference, and improving programming efficiency. Combined with... Figure 8Specific examples are analyzed below: For instance, for coarse programming, when the first standard pass voltage is 5V, the first compensation parameter of WL126 is 0.1V, the first compensation parameter of WL80 is 0.2V, the first compensation parameter of WL54 is -0.4V, and the first compensation parameter of WL36 is 0.5V, then the first voltage parameters obtained based on the first standard pass voltage and the first compensation parameter are 5.1V, 5.2V, 4.6V, and 5.5V, respectively. Therefore, the first pass voltage applied to the corresponding unselected word line based on the first voltage parameter all match the optimal first pass voltage for that unselected word line, thereby greatly reducing programming interference and pass voltage interference. Similarly, since the pass voltage window for the same word line in the same memory string may be different during coarse and fine programming, even the compensation parameter corresponding to the same word line may be different during coarse and fine programming. This application applies a pass voltage to the unselected word line during fine programming based on a second compensation parameter that is different from the first compensation parameter during coarse programming, which can reduce programming interference and pass voltage interference and improve the reliability of the memory device.

[0093] In some embodiments, since the memory cell WLn+1 has already been coarsely programmed (is in a programmed state) during fine programming of WLn, local self-boosting occurs in the WLn+1 region, reducing programming interference caused by the through voltage on word lines WLn+2 and above. Based on this, different first compensation parameters can be set for different unselected word lines during coarse programming; while during fine programming, the unselected word lines are simply divided into two categories for separate control, i.e., different second compensation parameters are set for ordinary word lines and special word lines among the unselected word lines. This can reduce device power consumption to some extent.

[0094] Based on the same technical concept as the aforementioned control method for storage devices, embodiments of this application provide a storage device. Figure 10 This is a schematic diagram of the structure of a storage device provided in an embodiment of this application, such as... Figure 10 As shown, the storage device 900 includes:

[0095] A storage cell array 910, the storage cell array including a plurality of storage strings and word lines coupled to the storage strings;

[0096] A peripheral circuit 920 coupled to the memory cell array 910 is configured to perform programming operations on memory cells of a memory string coupled to a selected word line; the programming operations include coarse programming and fine programming.

[0097] The peripheral circuit 920 is further configured to: during the coarse programming, obtain a first voltage parameter based on a first compensation parameter, and apply a first pass voltage to the unselected word line based on the first voltage parameter; during the fine programming, obtain a second voltage parameter based on a second compensation parameter, and apply a second pass voltage to the unselected word line based on the second voltage parameter.

[0098] In some embodiments, the peripheral circuit 920 is specifically configured to: obtain a first voltage parameter based on a first standard through voltage and a first compensation parameter during the coarse programming; and obtain a second voltage parameter based on a second standard through voltage and a second compensation parameter during the fine programming.

[0099] The first standard passes through a different voltage than the second standard.

[0100] In some embodiments, the peripheral circuit 920 is specifically configured to apply the first pass voltage to the unselected word line while applying the first standard pass voltage to the selected word line based on the first voltage parameter during the coarse programming.

[0101] In some embodiments, the peripheral circuit 920 is specifically configured to apply the second pass voltage to the unselected word line while applying the second standard pass voltage to the selected word line based on the second voltage parameter during the fine programming.

[0102] In some embodiments, for the same unselected word line: the first compensation parameter and the second compensation parameter are different; the first voltage parameter and the second voltage parameter are different.

[0103] In some embodiments, for different unselected word lines: the first compensation parameter is different for different unselected word lines, and the second compensation parameter is different for different unselected word lines.

[0104] In some embodiments, each of the storage units is configured to have 2 x One of the storage states stores x bits of data, where x is an integer greater than 1.

[0105] It should be noted that the description of the storage device above is similar to the description of the control method embodiment of the storage device above, and has similar beneficial effects as the control method embodiment of the storage device, therefore, it will not be repeated. For technical details not disclosed in the storage device of this application, please refer to the description of the control method of the storage device in the embodiments of this application for understanding.

[0106] This application embodiment also provides a memory system, including a controller and the storage device described in the above technical solution; the controller is coupled to the storage device and is used to control the storage device.

[0107] In some embodiments, the first compensation parameter and the second compensation parameter can be determined by the controller. Here, the controller can determine the first compensation parameter based on the number of failure bits in coarse programming and the second compensation parameter based on the number of failure bits in fine programming.

[0108] In some embodiments, the first compensation parameter and the second compensation parameter, after being determined by the controller, can be stored in the peripheral circuit and directly called by the peripheral circuit without needing to be sent by the controller.

[0109] In some embodiments, during the storage device fabrication stage, a first standard pass voltage and a second standard pass voltage applicable to each die can be determined and stored in the storage device or controller. Then, when programming the storage device, the first and second standard pass voltages can be used directly.

[0110] In other embodiments, the controller may determine the first standard pass voltage and the second standard pass voltage before programming the storage device and send them to the peripheral circuitry. In some embodiments, after the first standard pass voltage and the second standard pass voltage are determined by the controller, they may be stored in the peripheral circuitry and directly accessed by the peripheral circuitry.

[0111] This application provides a storage device, control method, and memory system. The storage device includes: a memory cell array, the memory cell array including a plurality of memory strings and word lines coupled to the memory strings; and peripheral circuitry coupled to the memory cell array, the peripheral circuitry being configured to: perform programming operations on memory cells of memory strings coupled to selected word lines; the programming operations including coarse programming and fine programming; the peripheral circuitry is further configured to: during coarse programming, obtain a first voltage parameter based on a first compensation parameter, and apply a first through voltage to unselected word lines based on the first voltage parameter; during fine programming, obtain a second voltage parameter based on a second compensation parameter, and apply a second through voltage to the unselected word lines based on the second voltage parameter. In this application embodiment, during coarse programming and fine programming, a first through voltage and a second through voltage are applied to unselected word lines based on the first voltage parameter and the second voltage parameter, respectively. This method of applying through voltage to unselected word lines using different voltage parameters during different programming operations in multiple programming operations allows the through voltage corresponding to each word line to be more adapted to the current state of the word line, thereby reducing programming interference and through voltage interference, and improving the reliability of the storage device.

[0112] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0113] The above description is only a preferred embodiment of this application and does not limit the patent scope of this application. All equivalent structural transformations made based on the inventive concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A storage device, characterized in that, The storage device includes: A storage cell array, the storage cell array comprising a plurality of storage strings and word lines coupled to the storage strings; Peripheral circuitry coupled to the memory cell array is configured to perform programming operations on memory cells of a memory string coupled to a selected word line; the programming operations include coarse programming and fine programming; and programming operations on memory cells of adjacent word lines are inserted between the coarse programming and the fine programming of the memory cells of the memory string coupled to the selected word line. The peripheral circuitry is further configured to: during the coarse programming phase, obtain a first voltage parameter based on a first compensation parameter, and apply a first pass voltage to the unselected word line based on the first voltage parameter; during the fine programming phase, obtain a second voltage parameter based on a second compensation parameter, and apply a second pass voltage to the unselected word line based on the second voltage parameter.

2. The storage device according to claim 1, characterized in that, The peripheral circuit is specifically configured to: during the coarse programming, obtain the first voltage parameter based on the first standard through voltage and the first compensation parameter; during the fine programming, obtain the second voltage parameter based on the second standard through voltage and the second compensation parameter; The first standard passes through a different voltage than the second standard.

3. The storage device according to claim 2, characterized in that, The peripheral circuit is specifically configured to apply the first pass voltage to the unselected word line while applying the first standard pass voltage to the selected word line based on the first voltage parameter during the coarse programming.

4. The storage device according to claim 2, characterized in that, The peripheral circuit is specifically configured to apply the second pass voltage to the unselected word line while applying the second standard pass voltage to the selected word line based on the second voltage parameter during the fine programming.

5. The storage device according to any one of claims 1 to 4, characterized in that, For the same unselected word line: the first compensation parameter and the second compensation parameter are different; the first voltage parameter and the second voltage parameter are different.

6. The storage device according to any one of claims 1 to 4, characterized in that, For different unselected word lines: the first compensation parameter is different for different unselected word lines, and the second compensation parameter is different for different unselected word lines.

7. The storage device according to any one of claims 1 to 4, characterized in that, Each of the storage units is configured to have 2 x One of the storage states stores x bits of data, where x is an integer greater than 1.

8. A method for controlling a storage device, characterized in that, The storage device includes a storage cell array, the storage cell array including a plurality of storage strings and word lines coupled to the storage strings, the method including: Perform programming operations on the memory cells of the memory string coupled to the selected word line; the programming operations include coarse programming and fine programming; Between the coarse programming and the fine programming of the memory cells of the memory string coupled to the selected word line, programming operations on memory cells of adjacent word lines are inserted. During the coarse programming, a first voltage parameter is obtained based on a first compensation parameter, and a first pass voltage is applied to the unselected word line based on the first voltage parameter; during the fine programming, a second voltage parameter is obtained based on a second compensation parameter, and a second pass voltage is applied to the unselected word line based on the second voltage parameter.

9. The control method for the storage device according to claim 8, characterized in that, The step of obtaining the first voltage parameter based on the first compensation parameter includes: The first voltage parameter is obtained based on the first standard through voltage and the first compensation parameter.

10. The control method for the storage device according to claim 9, characterized in that, The step of obtaining the first voltage parameter based on the first compensation parameter includes: The second voltage parameter is obtained according to the second standard through the voltage and the second compensation parameter; The first standard passes through a different voltage than the second standard.

11. The control method for a storage device according to claim 10, characterized in that, Applying a first pass voltage to the unselected word line based on the first voltage parameter includes: While applying the first pass voltage to the unselected word line based on the first voltage parameter, the first standard pass voltage is applied to the selected word line.

12. The control method for the storage device according to claim 10, characterized in that, Applying a second pass voltage to the unselected word line based on the second voltage parameter includes: While applying the second pass voltage to the unselected word line based on the second voltage parameter, the second standard pass voltage is applied to the selected word line.

13. The control method for a storage device according to any one of claims 9 to 12, characterized in that, For the same unselected word line: the first compensation parameter and the second compensation parameter are different; the first voltage parameter and the second voltage parameter are different.

14. The control method for a storage device according to any one of claims 9 to 12, characterized in that, For different unselected word lines: the first compensation parameter is different for different unselected word lines, and the second compensation parameter is different for different unselected word lines.

15. The control method for a storage device according to any one of claims 9 to 12, characterized in that, Each of the storage units is configured to have 2 x One of the storage states stores x bits of data, where x is an integer greater than 1.

16. A memory system, characterized in that, It includes a controller and a storage device according to any one of claims 1 to 7; the controller is coupled to the storage device and is used to control the storage device.

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