Memory and operating method thereof, memory system

Abstract

The present disclosure provides a memory and an operating method thereof, a memory system, the memory comprising a plurality of memory blocks, each of the memory blocks comprising a plurality of memory strings, each of the memory strings having a plurality of memory cells connected in series, the method comprising: after performing an erase operation on the memory block, performing a charge release operation on the memory block, the charge release operation comprising: during a preset period, applying a first voltage to a bit line connected to each memory string in the memory block, applying a ground voltage to a common source connected to each memory string in the memory block, and applying a second voltage to each word line in the memory block, the second voltage being greater than the first voltage.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a memory and its operation method, and a memory system. Background Technology

[0002] With the continuous development of science and technology, the density of semiconductor memory devices is constantly increasing. High data reliability, high access speed, and smaller chip size have become important trends in the development of semiconductor memory. In order to further improve the bit density of memory while reducing the bit cost, three-dimensional (3D) memory technology has been proposed. Among them, 3D NAND memory has become a relatively advanced and highly promising three-dimensional memory.

[0003] In 3D NAND flash memory, each cell includes a non-volatile charge-trapping transistor that is programmed or erased by biasing a voltage of appropriate polarity, amplitude, and duration between its control gate and its substrate. Programming (also known as write) interference is an unintended and harmful change caused by residual charge in the cell. Programming interference can worsen the threshold voltage distribution of the cell, resulting in a smaller read window and reduced reliability of the stored data. Summary of the Invention

[0004] In view of the above, embodiments of the present disclosure provide a memory and a method for operating the same, as well as a memory system.

[0005] In a first aspect, embodiments of this disclosure provide a method for operating a memory, the memory comprising a plurality of memory blocks, each memory block comprising a plurality of memory strings, each memory string having a plurality of memory cells connected in series, the method comprising:

[0006] After performing an erase operation on the memory block, a charge release operation is performed on the memory block, the charge release operation including:

[0007] Within a preset time period, a first voltage is applied to the bit lines connected to each memory string in the memory block, a ground voltage is applied to the common source of each memory string connected to the memory block, and a second voltage is applied to each word line in the memory block, wherein the second voltage is greater than the first voltage.

[0008] In some embodiments, the first voltage is greater than the ground voltage, and the second voltage is greater than the threshold voltage of the memory cell.

[0009] In some embodiments, the memory string further includes a top select transistor and a bottom select transistor, and the charge release operation further includes:

[0010] During the preset time period, a third voltage is applied to the top select gate of the memory string coupling and a second voltage is applied to the bottom select gate of the memory string coupling to turn on the top select transistor and the bottom select transistor.

[0011] In some embodiments, the charge release operation further includes:

[0012] During the preset time period, the second voltage is applied to the virtual word line coupled to the memory string.

[0013] In some embodiments, the method further includes:

[0014] After performing the charge release operation on the storage block, an erase verification operation is performed on the storage block;

[0015] If the erase verification operation fails, the erase operation and the charge release operation continue to be performed on the storage block until the erase verification operation passes.

[0016] In some embodiments, the method further includes:

[0017] If the erase verification operation passes, the storage block is marked as a programmable block.

[0018] In some embodiments, the method further includes: performing the erase operation on the memory block; wherein, after performing the erase operation, residual charge remains in the oxide layer or tunneling layer between each word line in the memory block and the channel layer of the memory string.

[0019] Secondly, embodiments of this disclosure also provide a memory, including:

[0020] A storage cell array includes several storage blocks, each storage block including several storage strings, and each storage string having multiple storage cells connected in series.

[0021] A peripheral circuit coupled to the memory cell array is configured to perform a charge release operation on the memory block after performing an erase operation on the memory block. The charge release operation includes: applying a first voltage to the bit lines connected to each memory string in the memory block, applying a ground voltage to the common source of each memory string connected to the memory block, and applying a second voltage to each word line in the memory block, wherein the second voltage is greater than the first voltage, within a preset time period.

[0022] In some embodiments, the first voltage is greater than the ground voltage, and the second voltage is greater than the threshold voltage of the memory cell.

[0023] In some embodiments, the peripheral circuitry includes:

[0024] The control logic is configured to issue a first instruction after the erase operation is performed on the storage block;

[0025] A voltage generator configured to generate the first voltage and the second voltage during the preset time period in response to the first instruction;

[0026] A column driver configured to apply the first voltage to the bit lines connecting each memory string in the memory block during the preset time period in response to the first instruction;

[0027] A row driver configured to apply the second voltage to each word line in the memory block during the preset time period in response to the first instruction.

[0028] In some embodiments, the control logic is further configured to:

[0029] In response to the first instruction, the common source of each memory string connected in the memory block is grounded during the preset time period.

[0030] In some embodiments, the memory string further includes a top select transistor and a bottom select transistor;

[0031] The voltage generator is further configured to generate a third voltage during the preset time period in response to the first instruction;

[0032] The row driver is further configured to: in response to the first instruction, apply the third voltage to the top select gate of the memory string coupled with the second voltage to the bottom select gate of the memory string coupled with the second voltage during the preset time period, so as to turn on the top select transistor and the bottom select transistor.

[0033] In some embodiments, the row driver is further configured to apply the second voltage to the virtual word line coupled to the memory string during the preset time period in response to the first instruction.

[0034] In some embodiments, the peripheral circuit is further configured as follows:

[0035] After performing the charge release operation on the storage block, an erase verification operation is performed on the storage block;

[0036] If the erase verification operation fails, the erase operation and the charge release operation continue to be performed on the storage block until the erase verification operation passes.

[0037] In some embodiments, the peripheral circuit is further configured as follows:

[0038] If the erase verification operation passes, the storage block is marked as a programmable block.

[0039] Thirdly, embodiments of this disclosure provide a memory system, including:

[0040] A memory, at least used to perform the operation methods described in any of the above embodiments;

[0041] A memory controller, which is coupled to the memory.

[0042] In the memory operation method provided in this embodiment, after performing an erase operation on the memory block, a first voltage is applied to the bit lines connecting each memory string in the memory block, a ground voltage is applied to the common source terminal connecting each memory string in the memory block, and a second voltage, greater than the first voltage, is applied to each word line in the memory block. In this way, an electric field can be formed between the word lines and the channel layer of the memory strings to accelerate the movement of residual charges in the memory cells towards the channel layer and timely discharge through the channel structure, thereby reducing programming interference after the erase operation and improving the reliability of the stored data. Attached Figure Description

[0043] Figure 1 A schematic diagram of the structure of a memory provided in an embodiment of this disclosure;

[0044] Figure 2 A schematic diagram illustrating the threshold voltage offset of a memory cell in an embodiment of this disclosure;

[0045] Figure 3 This is a schematic diagram of the threshold voltage distribution of a memory cell in an embodiment of the present disclosure;

[0046] Figure 4 A schematic diagram illustrating programming interference during programming operations in a memory, provided as an embodiment of this disclosure;

[0047] Figure 5 This is a schematic diagram illustrating the application of positive voltages to the odd and even word lines respectively after an erase operation, as provided in an embodiment of this disclosure.

[0048] Figure 6 A waveform diagram showing the application of positive voltages to the odd and even word lines after an erase operation, provided as an embodiment of this disclosure;

[0049] Figure 7 A schematic diagram of a memory cell array provided in an embodiment of this disclosure;

[0050] Figure 8 This is a schematic diagram illustrating a charge release operation performed after an erasure operation, provided as an embodiment of the present disclosure.

[0051] Figure 9 A waveform diagram showing a charge release operation performed after an erasure operation, provided in an embodiment of this disclosure;

[0052] Figure 10 This is a schematic diagram illustrating an erase verification operation performed after a charge release operation, as provided in an embodiment of this disclosure.

[0053] Figure 11 A schematic diagram of a memory provided for an embodiment of this disclosure;

[0054] Figure 12 A schematic diagram of a peripheral circuit in a memory provided in an embodiment of this disclosure;

[0055] Figure 13 A schematic diagram of an exemplary system and a memory system provided in this disclosure embodiment;

[0056] Figure 14 A schematic diagram of a memory card provided in an embodiment of this disclosure;

[0057] Figure 15 This is a schematic diagram of an SSD provided in an embodiment of the present disclosure. Detailed Implementation

[0058] To facilitate understanding of this disclosure, exemplary embodiments thereof will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0059] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with this disclosure, certain technical features well-known in the art are not described; that is, not all features of actual embodiments, nor well-known functions and structures, may be described herein.

[0060] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Additionally, the use of "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, also depending at least in part on the context.

[0061] Unless otherwise defined, the terminology used herein is intended only to describe particular embodiments and is not intended to limit the scope of this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0062] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0063] In some embodiments, the 3D NAND memory includes multiple blocks, each block comprising multiple strings (STRs) arranged in an array, and each string comprising multiple cells connected in series. Figure 1As shown, the 3D NAND memory 10 includes a stacked structure 11 composed of alternating interlayer insulating layers 111 and gate layers 112, and a memory string 12 (only one memory string 12 is shown in the figure) running vertically through the stacked structure 11. The memory string 12 includes a channel structure 120 running through the stacked structure 11, and the channel structure 120 has a memory layer 121, a channel layer 122, and an insulating layer 123 arranged sequentially from the outside to the inside. The memory layer 121 includes a barrier layer 1211, a charge trapping layer 1212, and a tunneling layer 1213. Exemplarily, the barrier layer 1211 and the tunneling layer 1213 can be made of materials such as oxides, and the charge trapping layer 1212 can be made of materials such as nitrides. The 3D NAND memory is based on the Fowler Nordheim Tunneling (FN-Tunneling) effect, and programming and erasing operations are achieved by injecting electrons or holes into the charge trapping layer 1213. It is worth noting that, in order to clearly show all the structures in the diagram, the dimensional proportions of the structures may not match the actual structures.

[0064] In some embodiments, during the erase operation, a large number of holes tunnel from the channel layer 122 towards the gate layer 112, and some of these holes are easily captured by the oxide layer, such as the tunneling layer 1213. Due to the characteristics of the process materials, these holes cannot exist effectively in the oxide layer for a long time and are easily lost by entering the channel layer 122 over time; this phenomenon is called shallow charge loss. Therefore, as... Figure 2 As shown, after the erase operation is completed, the loss of shallow charge causes the threshold voltage (Vt) distribution of each memory cell to shift to the right over time, reducing the reliability of the stored data.

[0065] In some embodiments, the memory 10 can be a TLC (Triple-Level Cell) architecture, meaning that one memory cell can store 3 bits of data. For example... Figure 3 As shown, the threshold voltage distribution of a TLC memory cell can include eight states, L0 to L7, representing different memory values: 111, 110, 101, 100, 011, 010, 001, and 000. RD1 to RD7 represent the read voltages corresponding to each state. A larger threshold voltage margin (E0 Margin) in state L0 results in a larger window for reading the memory cell, higher read fault tolerance, and thus a better threshold voltage distribution.

[0066] In some embodiments, performing TLC programming immediately after a memory erase operation results in a smaller threshold voltage margin; conversely, waiting a period of time after the erase operation before performing TLC programming results in a larger threshold voltage margin. For example, as... Figure 4 As shown, TLC programming is performed immediately after the erase operation. For the selected memory string (Select STR), a 3V voltage is applied to the top select gate (TSG), a 3V voltage is applied to the bit line (BL) connected to the memory string, a 13V voltage is applied to the word line (WL) coupled to the memory cell being programmed, and a 9V voltage is applied to the word line coupled to the memory cell not being programmed, to achieve data writing. Here, the word line is the gate layer 112 in the above embodiment. For the unselected memory string (Unselect STR), a 0V voltage is applied to the top select gate to turn off the memory string. In this way, shallow charge loss ( Figure 4 (As shown by the solid arrow) This will generate a small current in the direction parallel to the channel structure 120, and during the programming operation, the high voltage applied to the word line will cause a certain hot carrier injection (HCI) effect. Figure 4 (As shown by the dashed arrow), this exacerbates programming interference, ultimately leading to a smaller threshold voltage margin, a poorer threshold voltage distribution, and reduced storage reliability. In some embodiments, the threshold voltage margin obtained by performing a programming operation immediately after an erase operation is smaller, and the threshold voltage margin is approximately 100mV higher than that obtained by waiting 10 minutes after an erase operation before performing a programming operation.

[0067] In some embodiments, after the erase operation is completed and before the erase verification operation, positive voltages can be alternately applied to the odd-numbered lines and even-numbered lines to accelerate the discharge of residual holes after the erase operation, i.e., the process of shallow charge loss, thereby mitigating the problem of deteriorated threshold voltage distribution caused by programming interference. For example, as... Figure 5 and Figure 6As shown, firstly, a voltage of 0V is applied to the bit lines and the array common source (ACS) connected to the memory string. A positive voltage V-curing is applied to the odd-numbered word lines coupled to the memory string, and a supply voltage Vcc is applied to the even-numbered word lines coupled to the memory string, where the positive voltage V-curing is greater than the supply voltage Vcc. Then, keeping the voltages on the bit lines and the array common source constant, the supply voltage Vcc is applied to the odd-numbered word lines coupled to the memory string, and a positive voltage V-curing is applied to the even-numbered word lines coupled to the memory string. This generates an electric field between the word lines and the channel layer of the memory string, thereby accelerating the shallow charge loss process. However, according to actual test data, the threshold voltage margin obtained using this method is small, and the threshold voltage distribution is poor, indicating that residual holes in the oxide layer of the memory string are not discharged in time, and programming interference is not effectively improved.

[0068] refer to Figures 7 to 9 This disclosure provides an operation method for a memory 20, the memory 20 including a plurality of memory blocks 21, each memory block including a plurality of memory strings 211, each memory string having a plurality of memory cells connected in series, the method including:

[0069] After performing an erase operation on the storage block 21, a charge release operation is performed on the storage block 21, the charge release operation including:

[0070] Within a preset time period t1, a first voltage V1 is applied to the bit line BL connected to each memory string 211 in the memory block 21, a ground voltage is applied to the common source ACS connected to each memory string 211 in the memory block 21, and a second voltage V2 is applied to each word line WL in the memory block 21, wherein the second voltage V2 is greater than the first voltage V1.

[0071] In the embodiments disclosed herein, such as Figure 7 As shown, the memory cell array of memory 20 includes several memory blocks 21, each memory block 21 being the smallest unit for performing an erase operation. Each memory block 21 includes several memory strings 211, each memory string 211 having multiple memory cells connected in series. Figure 8 As shown, in a memory string 211, each memory cell is coupled to a word line WL, which is the gate layer in the above embodiment. Each memory string 211 is also connected to a bit line BL and a common source ACS.

[0072] In some embodiments, during the erase operation on memory block 21, a large number of holes tunnel from the channel layer of memory string 211 toward the word line, causing some holes to be captured by oxide layers such as the tunneling layer of memory string 211. These captured holes are the residual charge in the memory cell. For example, if a programming operation is performed immediately after the erase operation, the residual holes in the memory cell experience shallow charge loss, that is, the holes move from the tunneling layer toward the channel layer, causing a small current to be generated in the direction parallel to the channel structure; and during the programming operation, the high voltage applied to the word line WL causes a certain amount of hot carrier injection, that is, electrons move from the channel layer toward the tunneling layer, thereby generating severe programming interference, resulting in a smaller threshold voltage margin, a worse threshold voltage distribution, and reduced memory reliability.

[0073] In this embodiment of the disclosure, after performing an erase operation on storage block 21, a charge release operation can be performed on storage block 21 to remove residual charge in the storage cell. For example, as shown... Figure 8 and Figure 9 As shown, the charge release operation includes: continuously applying a second voltage V2 to each word line WL in the memory block 21 and continuously applying a first voltage V1 to the bit line BL connected to the memory string 211 within a preset time period t1. Optionally, the second voltage V2 can be a voltage Vpass, where the voltage Vpass is greater than the maximum value of the threshold voltage of each memory cell. Thus, an electric field can be formed between the word line WL and the channel layer of the memory string 211, and a certain hot carrier injection effect is generated using the higher second voltage V2 on the word line WL to accelerate the movement of residual charge in the memory cell towards the channel layer. The first voltage V1 can be applied to each memory string 211 through the bit line BL, forming a voltage difference with the ground voltage 0V on the common source ACS, allowing residual charge to be discharged through the channel structure in a timely manner, thereby reducing programming interference after the erase operation and improving the reliability of the stored data. Optionally, the specific values ​​of the first voltage V1, the second voltage V2, and the preset time period t1 can be adjusted according to the memory's process parameters and wafer test results to improve the residual charge discharge effect.

[0074] In some embodiments, the first voltage V1 is greater than the ground voltage, and the second voltage V2 is greater than the threshold voltage of the memory cell.

[0075] In this embodiment, the first voltage V1 applied to the bit line BL connected to each memory string 211 can be greater than the ground voltage 0V, i.e., the first voltage V1 can be a positive voltage. The second voltage V2 applied to each word line WL in the memory block 21 can be greater than the maximum value of the threshold voltage of each memory cell, and the second voltage V2 can be the pass voltage Vpass. Thus, the higher second voltage V2 can generate a certain hot carrier injection effect, and under the combined action of the electric field between the word line WL and the channel layer, it accelerates the movement of residual charge in the memory cell to the channel layer, and through the voltage difference between the bit line BL and the common source ACS, the residual charge is discharged in time, reducing the programming interference phenomenon generated after the erase operation.

[0076] In some embodiments, the charge release operation further includes:

[0077] During the preset time period, a ground voltage is applied to the common source ACS connected to the storage string 211.

[0078] In the embodiments disclosed herein, such as Figure 8 and Figure 9 As shown, the charge release operation performed on memory block 21 further includes: continuously applying a ground voltage to the common source ACS connected to memory string 211 during a preset time period t1, wherein the ground voltage can be 0V. Optionally, the common source ACS connected to memory string 211 can be grounded through a logic gate in the peripheral circuit of memory 20. Thus, there is a large voltage difference between bit line BL and the common source ACS, allowing residual charge to be discharged promptly through the channel structure of memory string 211.

[0079] In some embodiments, such as Figure 7 As shown, the storage string 211 further includes a top selection transistor 212 and a bottom selection transistor 213, and the charge release operation further includes:

[0080] During the preset time period t1, a third voltage is applied to the TSG coupled to the memory string 211, and a second voltage is applied to the BSG (Bottom Select Gate) coupled to the memory string 211 to turn on the top select transistor 212 and the bottom select transistor 213.

[0081] In the embodiments disclosed herein, such as Figure 7 As shown, the memory string 211 also includes a top select transistor 212 located at the top of the channel structure in a direction perpendicular to the substrate, and a bottom select transistor 213 located at the bottom of the channel structure. The top select transistor 212 is controlled to be turned on or off by a TSG, and the bottom select transistor 213 is controlled to be turned on or off by a BSG. Figure 8 and Figure 9As shown, the charge release operation performed on memory block 21 further includes: continuously applying a third voltage V3 to TSG and continuously applying a second voltage V2 to BSG during a preset time period t1 to turn on top selection transistor 212 and bottom selection transistor 213. Optionally, the second voltage V2 can be a pass voltage Vpass, and the third voltage V3 can be greater than the ground voltage 0V, that is, the third voltage V3 can be a positive voltage. Thus, the turned-on top selection transistor 212 and bottom selection transistor 213 allow the voltage difference between bit line BL and common source ACS to act on the channel structure of memory string 211, allowing residual charge to be discharged through the channel structure in a timely manner.

[0082] In some embodiments, the charge release operation further includes:

[0083] During the preset time period t1, the second voltage V2 is applied to the dummy word line (DWL) coupled to the storage string 211.

[0084] In the embodiments disclosed herein, such as Figure 8 As shown, between the top select transistor 212 and the bottom select transistor 213, there are also multiple dummy cells (DCs) that are not used for storing data, each dummy cell being coupled to a dummy word line (DWL). The dummy cells located between the top select transistor 212 and the memory cells reduce the electric field between the top select transistor 212 and the memory cells; similarly, the dummy cells located between the bottom select transistor 213 and the memory cells reduce the electric field between the bottom select transistor 213 and the memory cells. As the number of dummy cells increases, the size of the memory block 21 and its operational reliability increase; conversely, as the number of dummy cells decreases, the size of the memory block 21 and its operational reliability decrease.

[0085] like Figure 8 and Figure 9 As shown, the charge release operation performed on memory block 21 further includes: continuously applying a second voltage V2 to the virtual word line DWL coupled to memory string 211 during the preset time period t1. Optionally, the second voltage V2 can be a pass voltage Vpass. Thus, a higher second voltage V2 can generate a certain hot carrier injection effect, and under the combined action of the electric field between the virtual word line DWL and the channel layer, accelerate the movement of residual charge in the virtual memory cell towards the channel layer, allowing the residual charge to be discharged in a timely manner and reducing programming interference after the erase operation. It is understood that by simultaneously applying the second voltage V2 to both the virtual word line DWL and the word line WL, the operation of memory 20 can be simplified, thereby improving operating efficiency.

[0086] In some embodiments, such as Figure 10 As shown, the method further includes:

[0087] After performing the charge release operation on the storage block, an erase verification operation is performed on the storage block;

[0088] If the erase verification operation fails, the erase operation and the charge release operation continue to be performed on the storage block until the erase verification operation passes.

[0089] like Figure 10 As shown, the operation method of the memory may further include the following steps:

[0090] Step S10: Perform an erase operation on the storage block;

[0091] Step S20: Perform a charge release operation on the storage block;

[0092] Step S30: Perform an erase verification operation on the storage block. If the erase verification operation fails, execute step S10 again; if the erase verification operation passes, continue to execute step S40.

[0093] Step S40: Mark the storage block as a programmable block.

[0094] In this embodiment of the disclosure, after performing a charge release operation on the memory block, an erase verification operation can be performed on the memory block. Optionally, the erase verification operation can be performed on the memory block through the peripheral circuitry of the memory. The erase verification operation is used to determine whether the memory block can be used for subsequent programming and reading operations. Exemplarily, the erase verification operation may include: applying a verification voltage to each word line in the memory block, where the verification voltage can be 0V or other voltages, and pre-charging the bit lines connected in the memory string; then controlling the top select transistor and the bottom select transistor to be turned on, detecting whether the voltage of the bit lines decreases. If the voltage of the bit lines decreases, it indicates that the erase verification operation has passed. If the erase verification operation fails, the erase operation and charge release operation are performed again on the memory block that failed the erase verification operation until the memory block passes the erase verification operation, and then subsequent programming and / or reading operations are performed on it. In some embodiments, the number of times a storage block fails the erase verification operation consecutively can be counted, and a preset value can be set. When the number of times a storage block fails the erase verification operation consecutively reaches the preset value, the storage block is marked as a bad block, so that subsequent programming, erasing, reading and other operations are not performed on the bad block.

[0095] In some embodiments, the method further includes:

[0096] If the erase verification operation passes, the storage block is marked as a programmable block.

[0097] In the embodiments disclosed herein, such as Figure 10 As shown, when a memory block passes the erase verification operation, it can be marked as a programmable block. Optionally, the mark of the programmable block can be stored in a register in the peripheral circuit; alternatively, the mark can be stored using a portion of the memory blocks 21 in the memory cell array. In this way, programming operations are performed only on programmable blocks that have passed the erase verification operation, which can reduce data write errors and improve the reliability of stored data.

[0098] In some embodiments, the method further includes: performing the erase operation on the memory block; wherein, after performing the erase operation, the residual charge is present in the oxide layer or tunneling layer between each word line and the channel layer of the memory string in the memory block.

[0099] In this embodiment, during the erase operation on the memory block, a large number of holes tunnel from the channel layer of the memory string towards the word line. Some of these holes are captured by the oxide layer or tunneling layer between the word line and the channel layer; these captured holes are the residual charges. After the erase operation, these residual charges can cause programming interference during programming operations, resulting in poor threshold voltage distribution of the memory cells. Therefore, this embodiment performs a charge release operation on the memory block after the erase operation to promptly remove residual holes and improve memory reliability.

[0100] like Figure 11 As shown, this application embodiment also provides a memory 30, including:

[0101] The storage cell array includes a plurality of storage blocks 31, each storage block including a plurality of storage strings 311, each storage string 311 having a plurality of storage cells connected in series;

[0102] The peripheral circuit coupled to the memory cell array is configured to perform a charge release operation on the memory block 31 after performing an erase operation on the memory block 31. The charge release operation includes: applying a first voltage V1 to the bit line BL connected to each memory string 311 in the memory block 31 within a preset time period t1, applying a ground voltage to the common source ACS connected to each memory string 311 in the memory block 31, and applying a second voltage V2 to each word line WL in the memory block 31, wherein the second voltage V2 is greater than the first voltage V1.

[0103] In the embodiments disclosed herein, such as Figure 11As shown, the memory cell array of memory 30 includes several memory blocks 31, which can be the smallest unit for performing erase operations. Each memory block 31 includes several memory strings 311, and each memory string 311 has multiple memory cells connected in series. In a memory string 311, each memory cell is coupled to a word line WL. Each memory string 311 is also connected to a bit line BL and a common source ACS.

[0104] In some embodiments, during the erase operation on memory block 31, a large number of holes tunnel from the channel layer of memory string 311 toward the word line, causing some holes to be captured by oxide layers such as the tunneling layer of memory string 311. These captured holes are the residual charge in the memory cell. For example, if a programming operation is performed immediately after the erase operation, the residual holes in the memory cell experience shallow charge loss, that is, the holes move from the tunneling layer toward the channel layer, causing a small current to be generated in the direction parallel to the channel structure; and during the programming operation, the high voltage applied to the word line WL causes a certain amount of hot carrier injection, that is, electrons move from the channel layer toward the tunneling layer, thereby generating serious programming interference, resulting in a smaller threshold voltage margin, a worse threshold voltage distribution, and reduced memory reliability.

[0105] In this embodiment of the present disclosure, after an erase operation is performed on the memory block 31 in the memory cell array, the peripheral circuit can perform a charge release operation on the memory block 31 to remove residual charge in the memory cell. Exemplarily, the charge release operation includes: continuously applying a second voltage V2 to each word line WL in the memory block 31 during a preset time period t1, applying a ground voltage to the common source ACS connected to the memory string 311, and continuously applying a first voltage V1 to the bit line BL connected to the memory string 311, so that residual charge is discharged in a timely manner, thereby reducing programming interference after the erase operation and improving the reliability of stored data.

[0106] In some embodiments, the first voltage V1 is greater than the ground voltage, and the second voltage V2 is greater than the threshold voltage of the memory cell.

[0107] In this embodiment, the first voltage V1 applied to the bit line BL connected to each memory string 311 can be greater than the ground voltage 0V, i.e., the first voltage V1 can be a positive voltage. The second voltage V2 applied to each word line WL in the memory block 31 can be greater than the maximum value of the threshold voltage of each memory cell, and the second voltage V2 can be the pass voltage Vpass. Thus, the higher second voltage V2 can generate a certain hot carrier injection effect, and under the combined action of the electric field between the word line WL and the channel layer, it accelerates the movement of residual charge in the memory cell to the channel layer, and through the voltage difference between the bit line BL and the common source ACS, the residual charge is discharged in time, reducing the programming interference phenomenon generated after the erase operation.

[0108] In some embodiments, such as Figure 12 As shown, the peripheral circuit includes:

[0109] Control logic 32 is configured to issue a first instruction after the erase operation is performed on the storage block;

[0110] Voltage generator 33 is configured to generate the first voltage V1 and the second voltage V2 within the preset time period t1 in response to the first instruction;

[0111] The column driver 34 is configured to apply the first voltage V1 to the bit line BL connected to each memory string 311 in the memory block during the preset time period t1 in response to the first instruction.

[0112] The line driver 35 is configured to apply the second voltage V2 to each word line WL in the memory block during the preset time period t1 in response to the first instruction.

[0113] In the embodiments disclosed herein, such as Figure 12 As shown, the peripheral circuitry of memory 30 may include: control logic 32, voltage generator 33, column driver 34, and row driver 35. Voltage generator 33, row driver 35, and column driver 34 may be coupled to and controlled by control logic 32. Voltage generator 33 may be coupled to row driver 35 and column driver 34. Row driver 35 may be coupled to memory cells via a string select line (SSL), multiple word lines (WL), and a ground select line (GSL). Column driver 34 may be coupled to memory cells via multiple bit lines (BL). It is understood that the peripheral circuitry of memory 30 may also include... Figure 12 Other peripheral circuits not shown.

[0114] For example, control logic 32 may include multiple logic gates and is configured to issue a first instruction after an erase operation is performed on the memory block. Voltage generator 33 can generate voltages for operations such as read, program, erase, verify, and charge release. The generated voltages may exceed the power supply voltage provided to the memory 30. Voltage generator 33 is configured to generate a first voltage V1 and a second voltage V2 within a preset time period t1 in response to the first instruction issued by control logic 32. Row driver 35 can operate according to row address signals from control logic 32 to select word lines WL for operations such as read, program, erase, verify, and charge release. Row driver 35 is configured to apply the second voltage V2 generated by voltage generator 33 to each word line WL in the memory block within the preset time period t1 in response to the first instruction issued by control logic 32. The column driver 34 can operate according to the column address signal from the control logic 32 to select the bit line BL for operations such as reading, programming, erasing, verification, and charge release. The column driver 34 is configured to apply a first voltage V1 generated by the voltage generator 33 to the bit line BL connected to each memory string 311 in the memory block within a preset time period t1 in response to a first instruction issued by the control logic 32.

[0115] In some embodiments, the control logic 32 is further configured to:

[0116] In response to the first instruction, the common source ACS of each memory string 311 in the memory block is grounded during the preset time period t1.

[0117] In this embodiment of the present disclosure, within a preset time period t1, the common source ACS connected to the memory string 311 can be grounded through the control logic 32 in the peripheral circuit of the memory 30. For example, a first voltage V1 is applied to the bit line BL, while the common source ACS is grounded at 0V, resulting in a large voltage difference between the two, thereby allowing residual charge to be discharged in a timely manner through the channel structure of the memory string 311.

[0118] In some embodiments, such as Figure 12 As shown, the storage string 311 also includes a top selection transistor 312 and a bottom selection transistor 313;

[0119] The voltage generator 33 is further configured to generate a third voltage V3 within the preset time period t1 in response to the first instruction;

[0120] The row driver 35 is further configured to: in response to the first instruction, apply the third voltage V3 to the TSG coupled to the memory string 311 and apply the second voltage V2 to the BSG coupled to the memory string 311 during the preset time period t1, so as to turn on the top select transistor 312 and the bottom select transistor 313.

[0121] In the embodiments disclosed herein, such as Figure 12 As shown, the memory string 311 also includes a top select transistor 312 located at the top of the memory string 311 and a bottom select transistor 313 located at the bottom of the memory string 311. The top select transistor 312 is controlled to be turned on or off by the TSG, and the bottom select transistor 313 is controlled to be turned on or off by the BSG. The row driver 35 is coupled to the TSG via the serial select line SSL and to the BSG via the ground select line GSL.

[0122] Exemplarily, voltage generator 33 is further configured to generate a third voltage V3 within a preset time period t1 in response to a first instruction. Row driver 35 is further configured to apply the third voltage V3 to the TSG coupled to memory string 311 via the string select line SSL and to apply a second voltage V2 to the BSG coupled to memory string 311 via the ground select line GSL within the preset time period t1 in response to the first instruction, thereby turning on top select transistor 312 and bottom select transistor 313. Thus, the turned-on top select transistor 312 and bottom select transistor 313 allow the voltage difference between bit line BL and common source ACS to act on the channel structure of memory string 311, allowing residual charge to be discharged through the channel structure in a timely manner.

[0123] In some embodiments, the row driver 35 is further configured to apply the second voltage V2 to the virtual word line DWL coupled to the memory string 311 during the preset time period t1 in response to the first instruction.

[0124] In this embodiment, between the top select transistor 312 and the bottom select transistor 313, there are also a plurality of virtual memory cells not used for storing data, each virtual memory cell being coupled to a virtual word line DWL. The row driver 35 is further configured to, in response to a first instruction, continuously apply a second voltage V2 to the virtual word line DWL for a preset time period t1 to accelerate the movement of residual charge in the virtual memory cells towards the channel layer, allowing the residual charge to be discharged in a timely manner and reducing programming interference after the erase operation. It is understood that by simultaneously applying the second voltage V2 to both the virtual word line DWL and the word line WL, the operation of the memory 30 can be simplified, thereby improving efficiency.

[0125] In some embodiments, the peripheral circuit is further configured as follows:

[0126] After performing the charge release operation on the storage block 31, an erase verification operation is performed on the storage block 31; if the erase verification operation fails, the erase operation and the charge release operation are performed on the storage block 31 again until the erase verification operation passes.

[0127] In this embodiment, after the peripheral circuit controls the memory block 31 to perform a charge release operation, the peripheral circuit can also perform an erase verification operation on the memory block 31. The erase verification operation is used to determine whether the memory block 31 can perform subsequent programming and reading operations. For example, the erase verification operation may include: the row driver 35 applying a verification voltage generated by the voltage generator 33 to each word line WL in the memory block 31. This verification voltage can be 0V or other voltages. Simultaneously, the column driver 34 pre-charges the bit line BL connected to the memory string 311. Then, the top select transistor 312 and the bottom select transistor 313 are turned on to detect whether the voltage of the bit line BL decreases. If the voltage of the bit line BL decreases, it indicates that the erase verification operation has passed. If the erase verification operation fails, the erase operation and charge release operation are performed again on the memory block 31 that failed the erase verification operation until the memory block 31 passes the erase verification operation, and then subsequent programming and / or reading operations are performed on it. In some embodiments, control logic 32 can count the number of consecutive erase verification operations that a certain storage block 31 fails, and set a preset value. When the number of consecutive erase verification operations that a certain storage block 31 fails reaches the preset value, the storage block 31 is marked as a bad block, so that subsequent programming, erasing, reading, and other operations are not performed on the bad block. Optionally, as... Figure 12 As shown, the peripheral circuit may also have a register 36 to store the aforementioned preset values ​​and bad block markers.

[0128] In some embodiments, the peripheral circuit is further configured as follows:

[0129] If the erase verification operation passes, the storage block 31 is marked as a programmable block.

[0130] In this embodiment of the disclosure, when storage block 31 passes the erase verification operation, the peripheral circuit can mark storage block 31 as a programmable block. Optionally, the mark of the programmable block can be stored through register 36 in the peripheral circuit; alternatively, the mark of the programmable block can be stored using a portion of the storage blocks 31 in the storage cell array. In this way, programming operations are performed only on programmable blocks that pass the erase verification operation, which can reduce data write errors and improve the reliability of stored data.

[0131] like Figure 13As shown in the illustration, this disclosure presents an exemplary system 40, which may include a host 50 and a memory system 60. The exemplary system 40 may include, but is not limited to, a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having the memory described in the above embodiments. The host 50 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)) of the electronic device. The host 50 may be configured to send data to or receive data from the memory system 60.

[0132] like Figure 13 As shown, this application embodiment also provides a memory system 60, including:

[0133] The memory 61 is used to perform at least any of the operation methods described in the above embodiments; the memory controller 62 is coupled to the memory 61.

[0134] In this embodiment of the disclosure, the memory system 60 may include a memory controller 62 and one or more memories 61, wherein the memories 61 are at least used to perform the operation methods described in any of the above embodiments. The memories 61 may include, but are not limited to, NAND flash memory, vertical NAND flash memory, NOR flash memory, dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), nano random access memory (NRAM), etc.

[0135] In this embodiment of the disclosure, the storage controller 62 may be coupled to the memory 61 and the host 50, and is used to control the memory 61. Exemplarily, the storage controller 62 may be designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, the storage controller 62 may also be designed to operate in a high duty cycle environment, such as a Solid State Drive (SSD) or an Embedded Multimedia Card (eMMC), and the SSD or eMMC may also be used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays. Further, the storage controller 62 may manage data in the memory 61 and communicate with the host 50. The storage controller 62 can be configured to control operations such as reading, erasing, and programming of the memory 61; it can also be configured to manage various functions related to data stored or to be stored in the memory 61, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.; and it can also be configured to handle error correction codes (ECC) for data read from or written to the memory 61. Furthermore, the storage controller 62 can perform any other suitable functions, such as formatting the memory 61, or communicating with external devices (e.g., according to a specific communication protocol) according to a specific communication protocol. Figure 13 The storage controller 62 communicates with the host 50. For example, the storage controller 62 can communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0136] In embodiments of this disclosure, the storage controller 62 and one or more memories 61 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 60 can be implemented and packaged into different types of end electronic products. Figure 14As shown, the storage controller 62 and a single memory 61 can be integrated into a memory card. The memory card can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card can also include a connector for linking the memory card to a host computer (e.g., ...). Figure 13 The host 50) is coupled to the memory card connector. In such a... Figure 15 In another embodiment shown, the storage controller 62 and the plurality of memories 61 may be integrated into the SSD. The SSD may also include a connection between the SSD and the host (e.g., Figure 13 The host 50 in the memory card is coupled to the SSD connector. In some implementations, the storage capacity and / or operating speed of the SSD is greater than that of the memory card.

[0137] It should be noted that the memory involved in the embodiments of this disclosure can be a semiconductor memory, which is a solid-state electronic device for storing data information made using semiconductor integrated circuit technology.

[0138] It should be noted that the features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method or device embodiments without conflict.

[0139] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for operating a memory, characterized in that, The memory includes several memory blocks, each memory block includes several memory strings, and each memory string has multiple memory cells connected in series. The method includes: After performing an erase operation on the memory block, a charge release operation is performed on the residual charge in the oxide layer or tunneling layer between each word line in the memory block and the channel layer of the memory string. The charge release operation includes: Within a preset time period, a first voltage is applied to the bit lines connected to each memory string in the memory block, a ground voltage is applied to the common source of each memory string connected to the memory block, and a second voltage is applied to each word line in the memory block. The second voltage is greater than the first voltage, and the first voltage is greater than the ground voltage.

2. The method according to claim 1, characterized in that, The second voltage is greater than the threshold voltage of the memory cell.

3. The method according to claim 1, characterized in that, The storage string further includes a top select transistor and a bottom select transistor, and the charge release operation further includes: During the preset time period, a third voltage is applied to the top select gate of the memory string coupling and a second voltage is applied to the bottom select gate of the memory string coupling to turn on the top select transistor and the bottom select transistor.

4. The method according to claim 1, characterized in that, The charge release operation further includes: During the preset time period, the second voltage is applied to the virtual word line coupled to the memory string.

5. The method according to claim 1, characterized in that, The method further includes: After performing the charge release operation on the storage block, an erase verification operation is performed on the storage block; If the erase verification operation fails, the erase operation and the charge release operation continue to be performed on the storage block until the erase verification operation passes.

6. The method according to claim 5, characterized in that, The method further includes: If the erase verification operation passes, the storage block is marked as a programmable block.

7. The method according to any one of claims 1 to 6, characterized in that, The method further includes: performing the erase operation on the storage block; wherein, after performing the erase operation, residual charge exists in the oxide layer or tunneling layer between each word line in the storage block and the channel layer of the storage string.

8. A memory, characterized in that, include: A storage cell array includes several storage blocks, each storage block including several storage strings, and each storage string having multiple storage cells connected in series. A peripheral circuit coupled to the memory cell array is configured to perform a charge release operation on residual charges in the oxide layer or tunnel layer between each word line in the memory block and the channel layer of the memory string after an erase operation is performed on the memory block. The charge release operation includes: applying a first voltage to the bit lines connected to each memory string in the memory block, applying a ground voltage to the common source of each memory string in the memory block, and applying a second voltage to each word line in the memory block within a preset time period. The second voltage is greater than the first voltage, and the first voltage is greater than the ground voltage.

9. The memory according to claim 8, characterized in that, The second voltage is greater than the threshold voltage of the memory cell.

10. The memory according to claim 8, characterized in that, The peripheral circuit includes: The control logic is configured to issue a first instruction after the erase operation is performed on the storage block; A voltage generator configured to generate the first voltage and the second voltage during the preset time period in response to the first instruction; A column driver configured to apply the first voltage to the bit lines connecting each memory string in the memory block during the preset time period in response to the first instruction; A row driver configured to apply the second voltage to each word line in the memory block during the preset time period in response to the first instruction.

11. The memory according to claim 10, characterized in that, The control logic is also configured to: In response to the first instruction, the common source of each memory string connected in the memory block is grounded during the preset time period.

12. The memory according to claim 10, characterized in that, The storage string also includes a top selection transistor and a bottom selection transistor; The voltage generator is further configured to generate a third voltage during the preset time period in response to the first instruction; The row driver is further configured to: in response to the first instruction, apply the third voltage to the top select gate of the memory string coupled with the second voltage to the bottom select gate of the memory string coupled with the second voltage during the preset time period, so as to turn on the top select transistor and the bottom select transistor.

13. The memory according to claim 10, characterized in that, The row driver is further configured to apply the second voltage to the virtual word line coupled to the memory string during the preset time period in response to the first instruction.

14. The memory according to claim 8, characterized in that, The peripheral circuit is also configured as follows: After performing the charge release operation on the storage block, an erase verification operation is performed on the storage block; If the erase verification operation fails, the erase operation and the charge release operation continue to be performed on the storage block until the erase verification operation passes.

15. The memory according to claim 14, characterized in that, The peripheral circuit is also configured as follows: If the erase verification operation passes, the storage block is marked as a programmable block.

16. A memory system, characterized in that, include: A memory, at least configured to perform the operating method as described in any one of claims 1 to 7; A memory controller, which is coupled to the memory.

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