Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor device includes a conductor disposed on a substrate, a first contact disposed on the conductor, a second contact having a first portion disposed on the first contact and a second portion extending away from the first portion in a direction parallel to the substrate, wherein the first and second contacts are disposed in an insulating layer, a via disposed on the insulating layer and the second portion of the second contact, and a metal line disposed on the via.

Description

[0001] This invention is a divisional application of the invention patent application filed on November 21, 2016, with application number 201611023256.X and title "Semiconductor Device and Method of Manufacturing Semiconductor Device".

[0002] Cross-reference of related applications

[0003] This patent application claims priority to Korean Patent Application Nos. 10-2015-0162668, 10-2015-0162675, 10-2016-0048379, and 10-2016-0086996, filed with the Korean Intellectual Property Office on November 19, 2015, April 20, 2016, and July 8, 2016, respectively, and to U.S. Patent Application No. 15 / 355,159, filed on November 18, 2016, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0004] The present invention relates to semiconductor devices and methods of manufacturing semiconductor devices, and more specifically, to semiconductor devices comprising field-effect transistors and methods of manufacturing semiconductor devices. Background Technology

[0005] Semiconductor devices are widely used in the electronics industry due to their small size, versatility, and / or low cost. Semiconductor devices can be memory devices for storing data, logic devices for processing data, or hybrid devices that include both memory and logic elements. To meet the increasing demand for electronic devices with high speed and / or low power consumption, semiconductor devices with high reliability, high performance, and / or versatility are required. To meet these technological requirements, the complexity and / or integration density of semiconductor devices are increasing. Summary of the Invention

[0006] According to an exemplary embodiment of the present invention, a semiconductor device is provided, the semiconductor device comprising: a conductor disposed on a substrate; a first contact disposed on the conductor; a second contact having a first portion disposed on the first contact and a second portion extending away from the first portion in a direction parallel to the substrate, wherein the first and second contacts are disposed in an insulating layer; a through-hole disposed on the insulating layer and the second portion of the second contact; and a metal wire disposed on the through-hole.

[0007] According to an exemplary embodiment of the present invention, a semiconductor device is provided, the semiconductor device comprising: a virtual conductor disposed on a substrate; a first contact disposed on the virtual conductor; a trench silicide disposed on the substrate and spaced apart from the virtual conductor; a second contact disposed on the trench silicide; and a third contact disposed directly on the first and second contacts and connecting the first and second contacts to each other.

[0008] According to an exemplary embodiment of the present invention, a semiconductor device is provided, the semiconductor device comprising: a first conductor disposed on a substrate; a first contact disposed on the first conductor; a second contact disposed on the substrate and spaced apart from the first conductor and the first contact; and a third contact disposed directly on the first and second contacts and connecting the first and second contacts to each other.

[0009] According to an exemplary embodiment of the present invention, a semiconductor device is provided, the semiconductor device comprising: a first trench silicide disposed on a substrate; a first contact disposed on an upper surface of the first trench silicide, wherein the upper surface of the first trench silicide is wider than a lower surface of the first contact; a second trench silicide disposed on the substrate; a second contact disposed on the second trench silicide; and a third contact disposed directly on the first and second contacts and connecting the first and second contacts to each other.

[0010] According to an exemplary embodiment of the present invention, a semiconductor device is provided, the semiconductor device comprising: a first contact disposed on a substrate and extending longitudinally in a first direction; a second contact disposed on the substrate and extending longitudinally in the first direction; a conductor disposed between the first and second contacts and extending longitudinally in the first direction; and a third contact disposed on the first and second contacts and extending longitudinally in a second direction intersecting the first direction, wherein a first portion of the third contact extends beyond an edge of the first contact, such that the first contact is disposed in the second direction between the first portion and the conductor.

[0011] According to an exemplary embodiment of the present invention, a semiconductor device is provided, the semiconductor device comprising: a first conductor disposed on a substrate; a first contact disposed on the first conductor; a second conductor disposed on the substrate and spaced apart from the first conductor; a second contact disposed on the second conductor; and a third contact disposed directly on the first and second contacts and connecting the first and second contacts to each other. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating an exemplary embodiment of a computer system for performing a semiconductor design process according to the concept of the present invention.

[0013] Figure 2 This is a flowchart illustrating a method for designing and manufacturing a semiconductor device according to an exemplary embodiment of the concept of the present invention.

[0014] Figure 3 This is a layout diagram illustrating a portion of a standard cell layout according to an exemplary embodiment of the concept of the present invention.

[0015] Figure 4 This is an explanation of the concept based on the present invention. Figure 3 A perspective view of a semiconductor device formed by the layout of the components.

[0016] Figure 5 This is a layout diagram illustrating a portion of a standard cell layout according to an exemplary embodiment of the concept of the present invention.

[0017] Figure 6 This is an illustration of an exemplary embodiment based on the concept of the present invention. Figure 5 A perspective view of a semiconductor device formed by the layout of the components.

[0018] Figure 7 This is a layout diagram illustrating a portion of a standard cell layout according to an exemplary embodiment of the concept of the present invention.

[0019] Figure 8 This is an explanation of the concept based on the present invention. Figure 7 A perspective view of a semiconductor device formed by the layout of the components.

[0020] Figure 9 This is a layout diagram illustrating a portion of a standard cell layout according to an exemplary embodiment of the concept of the present invention.

[0021] Figure 10 This is an illustration of an exemplary embodiment based on the concept of the present invention. Figure 9 A perspective view of a semiconductor device formed by the layout of the components.

[0022] Figure 11 This is a layout diagram illustrating a portion of a standard cell layout according to an exemplary embodiment of the concept of the present invention.

[0023] Figure 12 This is a perspective view illustrating an exemplary semiconductor device according to the concept of the present invention.

[0024] Figure 13 This is a layout diagram including a standard cell layout, which is an exemplary embodiment of the concept according to the present invention.

[0025] Figure 14AThis describes an exemplary embodiment of the concept according to the present invention. Figure 13 The layout diagram of area "M".

[0026] Figure 14B This is to explain based on the comparison examples. Figure 13 The layout diagram of area "M".

[0027] Figure 15A This describes exemplary embodiments based on the inventive concept. Figure 13 The layout diagram of area "N".

[0028] Figure 15B This is to explain based on the comparison examples. Figure 13 The layout diagram of area "N".

[0029] Figure 16 This is a plan view illustrating an exemplary embodiment of a semiconductor device according to the inventive concept.

[0030] Figure 17A , 17B 17C, 17D, 17E, 17F, 17G, 17H, 17I, 17J, 17K, 17L, 17M, 17N, 17O, 17P, 17Q, and 17R are respectively exemplary embodiments of the present invention along the lines of the present invention. Figure 16 The cross-sectional views of lines A-A', B-B', C-C', D-D', E-E', F-F', G-G', H-H', I-I', J-J', K-K', L-L', M-M', N-N', O-O', P-P', Q-Q', and R-R'.

[0031] Figure 18A and 18B This is for illustrating an exemplary semiconductor device according to the concept of the present invention. Figure 16 A cross-sectional view taken from line A-A'.

[0032] Figure 18C This is for illustrating an exemplary semiconductor device according to the concept of the present invention. Figure 16 The cross-sectional view taken by line F-F'.

[0033] Figure 19 , 21 23, 25, 27, 29 and 31 are plan views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the concept of the present invention.

[0034] Figure 20A , 22A 24A, 26A, 28A, 30A, and 32A are respectively exemplary embodiments of the present invention along the lines of the present invention. Figure 19 , 21The cross-sectional view taken from line A-A' of lines 23, 25, 27, 29 and 31.

[0035] Figure 20B , 22B 24B, 26B, 28B, 30B, and 32B are respectively exemplary embodiments of the present invention along the lines of the present invention. Figure 19 , 21 The cross-sectional view of line B-B' taken from lines 23, 25, 27, 29 and 31.

[0036] Figure 22C , 24C 26C, 28C, 30C, and 32C are respectively exemplary embodiments of the present invention along the lines of the present invention. Figure 21 , 23 The cross-sectional view taken from line C-C' of lines 25, 27, 29 and 31.

[0037] Figure 28D , 30D 32D and 32D are respectively exemplary embodiments of the present invention along the concept. Figure 27 , 29 A cross-sectional view taken from line D-D' of line 31.

[0038] Figure 30E and 32E These are respectively, along the exemplary embodiments of the concept according to the present invention. Figure 29 and 31 The cross-sectional view taken from line E-E'.

[0039] Figure 33 This is a plan view illustrating an exemplary embodiment of a semiconductor device manufactured based on a standard cell layout according to the concept of the present invention.

[0040] Figure 34 This is a plan view illustrating an exemplary semiconductor device according to the concept of the present invention.

[0041] Figures 35A to 35C These are respectively, along the exemplary embodiments of the concept according to the present invention. Figure 34 The cross-sectional views taken from lines A-A', B-B', and C-C'. Detailed Implementation

[0042] Figure 1 This is a block diagram illustrating an exemplary embodiment of a computer system for performing a semiconductor design process according to the concept of the present invention. (Reference) Figure 1The computer system may include a central processing unit (CPU) 10, working memory 30, input / output devices 50, and auxiliary memory devices 70. In an exemplary embodiment of the present invention, the computer system may be a customized system for performing a layout design process according to an exemplary embodiment of the present invention. Furthermore, the computer system may include a computing system configured to perform different design and inspection simulation programs.

[0043] CPU 10 can be configured to run various software, such as applications, operating systems, and device drivers. For example, CPU 10 can be configured to run an operating system loaded on working memory 30. Furthermore, CPU 10 can be configured to run various applications on the operating system. For example, CPU 10 can be configured to run a layout design tool 32 loaded on working memory 30.

[0044] An operating system or application may be loaded onto the working memory 30. For example, when the computer system begins its booting operation, an image of the operating system (OS) stored in the secondary storage device 70 may be loaded onto the working memory 30 according to the boot sequence. In the computer system, the operating system manages input / output operations. Certain applications, selectable by the user or available for basic services, may be loaded onto the working memory 30. According to an exemplary embodiment of the present invention, a layout design tool 32 prepared for the layout design process may be loaded from the secondary storage device 70 onto the working memory 30.

[0045] The layout design tool 32 provides functionality for modifying bias data for a specific layout pattern. For example, the layout design tool 32 can be configured to allow a specific layout pattern to have a shape and position different from those defined by design rules. The layout design tool 32 can be configured to perform a design rule check (DRC) under conditions of modified bias data. The working memory 30 can be a volatile memory device (e.g., a static random access memory (SRAM) or dynamic random access memory (DRAM) device) or a non-volatile memory device (e.g., a phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), resistive random access memory (ReRAM), ferroelectric RAM (FRAM), or NOR flash memory device).

[0046] Additionally, simulation tool 34 can be loaded onto working memory 30 to perform optical proximity correction (OPC) operations based on the designed layout data.

[0047] Input-output device 50 can be configured to control user input and output operations of the user interface device. For example, input-output device 50 may include a keyboard or monitor, allowing the designer to input relevant information. By using input-output device 50, the designer can receive information about several areas or data paths of the semiconductor device, and adjusted operating characteristics can be applied to said information. Input-output device 50 can be configured to display the process status or process results of simulation tool 34.

[0048] Auxiliary storage device 70 can be a storage medium for a computer system. Auxiliary storage device 70 can be configured to store applications, OS images, and various data. Auxiliary storage device 70 can be provided in the form of a memory card (e.g., a multimedia card (MMC), embedded multimedia card (eMMC), secure digital card (SD), microSD, etc.) or a hard disk drive (HDD). Auxiliary storage device 70 may include a NAND flash memory device with a large memory capacity. Auxiliary storage device 70 may include a non-volatile memory device (e.g., PRAM, MRAM, ReRAM, or FRAM) or a NOR flash memory device.

[0049] System interconnect 90 can act as a system bus for implementing networking in a computer system. CPU 10, working memory 30, input / output devices 50, and auxiliary memory devices 70 can be electrically connected to each other via system interconnect 90, and thus data can be exchanged between them. However, system interconnect 90 is not limited to the aforementioned configuration. For example, system interconnect 90 may include additional components to increase the efficiency of data communication.

[0050] Figure 2 This is a flowchart illustrating a method for designing and manufacturing a semiconductor device according to an exemplary embodiment of the concept of the present invention.

[0051] refer to Figure 2 References can be used Figure 1 The described computer system performs a high-level design process for semiconductor integrated circuits (in S110). For example, in the high-level design process, the integrated circuit to be designed can be described using a high-level computer language (e.g., C language). The circuit designed through the high-level design process can be described more specifically through register transfer level (RTL) encoding or simulation. Furthermore, the code generated by RTL encoding can be converted into a wiring list, and the results can be combined with each other to fully describe the semiconductor device. The combined schematic circuit can be verified using simulation tools. In an exemplary embodiment of the inventive concept, an adjustment step can be further performed, taking into account the results of the verification step.

[0052] A layout design process can be performed to realize the logically complete form of a semiconductor integrated circuit on a silicon wafer (in S120). For example, the layout design process can be performed based on a schematic circuit or corresponding wiring table prepared during a high-level design process. The layout design process may include routing steps for placing and connecting different standard cells provided from a cell library based on predetermined design rules. A diffusion-blocking pattern may be introduced at the boundary of at least one standard cell and may be configured to have technical features suitable for the electrical characteristics of the corresponding standard cell. Such redesigned standard cells are available in the cell library.

[0053] The cell library may contain information about the operation, speed, and power consumption of multiple cells. In an exemplary embodiment of the present invention concept, the cell library for representing the circuit layout in the gate level may be defined in or by a layout design tool. Here, a layout may be prepared to define or describe the shape, location, or size of a pattern composed of transistors and metal interconnects that will actually be formed on a silicon wafer. For example, in order to actually form an inverter circuit on a silicon wafer, it may be necessary to prepare or draw a layout of patterns (e.g., p-channel metal oxide semiconductor (PMOS), n-channel metal oxide semiconductor (NMOS), N-well, gate electrode, and metal interconnects thereon). Therefore, at least one of the inverters defined in the cell library may be selected.

[0054] Routing steps to connect selected units to each other can also be performed. For example, routing steps can be performed on selected and placed standard units to connect said units to upper interconnects. These steps can be performed automatically or manually in a layout design tool. In an exemplary embodiment of the present invention concept, the steps of placing standard units and establishing a wiring structure thereon can be performed automatically by a placement and routing tool.

[0055] Following the routing steps, a verification step can be performed on the layout to check for any violations of design rules. In an exemplary embodiment of the present invention concept, the verification step may include evaluating verification items such as design rule check (DRC), electrical rule check (ERC), and layout vs. schematic (LVS). The DRC item can be evaluated to assess whether the layout conforms to design rules. The ERC item can be evaluated to assess whether there are any electrical disconnects in the layout. The LVS item can be evaluated to assess whether the layout is prepared to be consistent with the gate-level wiring table.

[0056] An optical proximity correction (OPC) step can be performed (in S130). The OPC step corrects for optical proximity effects that may occur when performing a photolithography process on a silicon wafer using a layout-based photomask. Optical proximity effects can be unintended optical effects (e.g., refraction or diffraction) that may occur during exposure using a layout-based photomask. In the OPC step, the layout can be modified to have a reduced difference between the designed pattern and the shape of the actually formed pattern, which may be caused by optical proximity effects. Due to the optical proximity correction step, the designed shape and position of the layout pattern can be slightly altered.

[0057] A photomask can be fabricated based on a layout modified via the OPC step (in S140). For example, a photomask can be fabricated by patterning a chromium layer provided on a glass substrate using layout pattern data.

[0058] The fabricated photomask can be used to manufacture semiconductor devices (in S150). In the actual manufacturing process, exposure and etching steps can be repeatedly performed, and thus the pattern defined in the layout design process can be sequentially formed on the semiconductor substrate.

[0059] Figure 3 This is a layout diagram illustrating a portion of a standard cell layout according to an exemplary embodiment of the concept of the present invention.

[0060] refer to Figure 3 The standard cell layout may include: a layout for the active region AR (hereinafter referred to as active region AR); a layout for the gate electrode GE (hereinafter referred to as gate pattern GP); a layout for the conductive structure CP (hereinafter referred to as conductive pattern CL); a layout for the via (hereinafter referred to as via pattern V0); and a layout for the interconnect ML (hereinafter referred to as conductor M1).

[0061] The active region AR can be a PMOSFET region or an NMOSFET region. The gate pattern GP can span the active region AR and extend in the first direction D1. The portion of the active region AR that does not overlap with the gate pattern GP can serve as the source / drain region SD.

[0062] The conductive pattern CL may include a connection pattern M0 and an active contact pattern CA. The active contact pattern CA may be disposed on the active region AR. The active contact pattern CA may be spaced apart from the gate pattern GP in a second direction D2 intersecting the first direction D1. The connection pattern M0 and the active contact pattern CA may partially overlap each other. The connection pattern M0 may extend in the second direction D2.

[0063] A through-hole pattern V0 and a wire M1 may be disposed on a connecting pattern M0. The through-hole pattern V0 may overlap with the connecting pattern M0, but may be spaced apart from the active contact pattern CA in the second direction D2. The wire M1 may overlap with the through-hole pattern V0 and may extend in the first direction D1.

[0064] Figure 4 This is a perspective view illustrating an exemplary semiconductor device according to a concept presented in the present invention. For example, Figure 4 This is an explanation based on Figure 3 A perspective view of a semiconductor device formed by the layout of the components.

[0065] refer to Figure 4 A substrate 100 with an active pattern FN can be provided. (See reference...) Figure 3 The active region AR described forms an active pattern FN. The active pattern FN may include a pair of source / drain regions SD and a channel region AF between the source / drain regions SD.

[0066] The gate electrode GE can be disposed on the channel region AF to span the active pattern FN. The gate electrode GE can extend in a first direction D1 parallel to the top surface of the substrate 100. The gate electrode GE can be as specified in the reference. Figure 3 The described gate pattern GP is a pattern formed. A gate insulating pattern may be inserted between the channel region AF and the gate electrode GE. The gate electrode GE may comprise a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride or tantalum nitride), or a metal (e.g., aluminum or tungsten).

[0067] A conductive structure CP may be provided on at least one of the source / drain regions SD. The conductive structure CP may include a first portion P1 and a second portion P2. The conductive structure CP may be as described in the previous reference. Figure 3 The described conductive pattern CL forms a pattern. For example, the first part P1 can be based on a reference. Figure 3 The described connection pattern M0 forms the pattern, and the second part P2 can be based on the previous reference. Figure 3The described active contact pattern CA forms the pattern.

[0068] The second portion P2 may be electrically connected to the source / drain region SD. For example, the second portion P2 may act as a contact plug that directly contacts the source / drain region SD. The second portion P2 may be spaced apart from the gate electrode GE in a second direction D2 that intersects the first direction D1. The second portion P2 may extend in the first direction D1.

[0069] The first portion P1 may extend from the second portion P2 in the second direction D2. Furthermore, the first portion P1 may include a first end portion TP1 protruding from at least one sidewall (e.g., a first sidewall SW1) of the second portion P2. The first sidewall SW1 may be a sidewall extending in the first direction D1 and facing the gate electrode GE. In other words, the first portion P1 may have a shape that extends through the top portion of the second portion P2.

[0070] The top surface P1t of the first portion P1 may be substantially coplanar with the top surface P2t of the second portion P2. The bottom surface P1b of the first portion P1 may be located at a horizontal plane higher than the bottom surface P2b of the second portion P2. In other words, the bottom surface P1b of the first portion is higher than the bottom surface P2b of the second portion P2 relative to the upper surface of the substrate 100. In addition, the bottom surface P1b of the first portion P1 may be located at a horizontal plane higher than the top surface of the gate electrode GE.

[0071] The first portion P1 and the second portion P2 may be connected to each other to form a conductive structure CP, which is provided in the form of a single entity. The conductive structure CP may contain a conductive metal nitride (e.g., titanium nitride or tantalum nitride) or a metal (e.g., aluminum or tungsten).

[0072] Interconnect ML may be provided on conductive structure CP. Interconnect ML may include a line portion LI extending in a first direction D1 and a contact portion VI perpendicularly connecting the line portion LI to conductive structure CP. The line portion LI may be as described in previous references. Figure 3 The described wire M1 forms a pattern, and the contact portion VI can be based on a previous reference. Figure 3 The described via pattern V0 forms a pattern. The interconnect ML may contain a conductive metal nitride (e.g., titanium nitride or tantalum nitride) or a metal (e.g., aluminum or tungsten).

[0073] When viewed in a plan view, line portion LI is spaced apart from second portion P2 in the second direction D2. However, line portion LI can be electrically connected to second portion P2 via contact portion VI and first portion P1; in other words, line portion LI can be electrically connected to the source / drain region SD. Therefore, when line portion LI and second portion P2 are horizontally spaced apart, line portion LI and second portion P2 can be electrically connected to each other via first portion P1. This allows electrical signals to be input to or output from the source / drain region SD via interconnect ML.

[0074] Return to reference Figure 3 The connecting pattern M0 of the conductive pattern CL increases the freedom in placing the wire M1 during the layout design process. Therefore, refer to Figure 2 The described wiring steps can be easily performed on a standard cell layout.

[0075] Figure 5 This is a layout diagram illustrating a portion of a standard cell layout according to an exemplary embodiment of the concept of the present invention. In the following description of embodiments of the invention, for the sake of brevity, the previously referenced documents may not be described in further detail. Figure 3 The described element.

[0076] refer to Figure 5 A standard cell layout may include an active region AR, a gate pattern GP, ​​a conductive pattern CL, a via pattern V0, and a conductor M1. The conductive pattern CL may include a connection pattern M0 and a gate contact pattern CB. The gate contact pattern CB may be disposed on the gate pattern GP. The gate contact pattern CB may overlap with the connection pattern M0. The connection pattern M0 may have a vertical axis parallel to the second direction D2.

[0077] A via pattern V0 and a wire M1 may be disposed on a connection pattern M0. The via pattern V0 may overlap with the connection pattern M0, but may be spaced apart from the gate contact pattern CB in the second direction D2. The wire M1 may overlap with the via pattern V0 and may extend in the first direction D1.

[0078] Figure 6 This is a perspective view illustrating an exemplary semiconductor device according to a concept presented in the present invention. For example, Figure 6 This is an explanation based on Figure 5 A perspective view of a semiconductor device formed by the layout. In the following description of embodiments of the present invention, for the sake of brevity, the previously referenced documents will not be described in further detail. Figure 4 The described element.

[0079] refer to Figure 6 The conductive structure CP can be disposed on the gate electrode GE. The conductive structure CP may include a first portion P1 and a third portion P3. (See previous reference) Figure 4The described conductive structure CP differs; a third part P3 (instead of the second part P2) may be provided in the conductive structure CP. The first part P1 may be as described in the previous reference. Figure 5 The described connection pattern M0 forms the pattern, and the third part P3 can be based on the previous reference. Figure 5 The described gate contact pattern CB forms the pattern.

[0080] The third part P3 can be electrically connected to the gate electrode GE. For example, the third part P3 can act as a contact plug that directly contacts the source / drain region SD. The third part P3 can be perpendicularly spaced from the source / drain region SD.

[0081] The first portion P1 may extend from the third portion P3 in a direction opposite to the second direction D2. Furthermore, the first portion P1 may include a second end portion TP2 extending from the two sidewalls (e.g., the second sidewall SW2) of the third portion P3. In other words, the first portion P1 may have a linewidth greater than that of the third portion P3.

[0082] The top surface P1t of the first portion P1 may be substantially coplanar with the top surface P3t of the third portion P3. The bottom surface P1b of the first portion P1 may be higher than the bottom surface P3b of the third portion P3. For example, the bottom surface P1b of the first portion P1 is higher than the bottom surface P3b of the third portion P3 relative to the upper surface of the substrate 100. Since the bottom surface P3b of the third portion P3 is located at a horizontal plane substantially the same as the top surface of the gate electrode GE, the bottom surface P1b of the first portion P1 may be higher than the top surface of the gate electrode GE.

[0083] Interconnect ML can be provided on the conductive structure CP. When viewed in a plan view, the line portion LI of interconnect ML can be spaced apart from the third portion P3 in the second direction D2. However, the line portion LI can be electrically connected to the third portion P3 via the contact portion VI and the first portion P1. For example, the line portion LI can be electrically connected to the gate electrode GE. Therefore, when the line portion LI and the third portion P3 are horizontally spaced apart, the line portion LI and the third portion P3 can be electrically connected to each other via the first portion P1. This allows electrical signals to be input to or output from the gate electrode GE via interconnect ML.

[0084] Figure 7 This is a layout diagram illustrating a portion of a standard cell layout according to an exemplary embodiment of the concept of the present invention. In the following description of embodiments of the invention, for the sake of brevity, the previously referenced documents may not be described in further detail. Figure 3 and 5 The described element.

[0085] refer to Figure 7A standard cell layout may include an active region AR, a gate pattern GP, ​​a conductive pattern CL, a via pattern V0, and a wire M1. The conductive pattern CL may include a connection pattern M0, an active contact pattern CA, and a gate contact pattern CB.

[0086] The active contact pattern CA can be placed on the active region AR, and the gate contact pattern CB can be placed on the gate pattern GP. The active contact pattern CA and the connection pattern M0 can partially overlap each other, and the gate contact pattern CB can overlap with the connection pattern M0.

[0087] To reduce the complexity of the diagrams and to provide a better understanding of exemplary embodiments of the concepts of this invention, Figure 7 The through-hole pattern V0 and the wire M1 are not shown; however, the through-hole pattern and the wire can be freely arranged on the connection pattern M0, for example, as previously referenced. Figure 3 and 5 As described.

[0088] Figure 8 This is a perspective view illustrating an exemplary semiconductor device according to a concept presented in the present invention. For example, Figure 8 This is an explanation based on Figure 7 A perspective view of a semiconductor device formed by the layout. In the following description of embodiments of the present invention, for the sake of brevity, the previously referenced documents will not be described in further detail. Figure 4 and 6 The described element.

[0089] refer to Figure 8 A conductive structure CP may be disposed on the substrate 100. The conductive structure CP may include a first portion P1, a second portion P2, and a third portion P3. The second portion P2 may be disposed on and electrically connected to the source / drain region SD, and the third portion P3 may be disposed on and electrically connected to the gate electrode GE. The first portion P1 may extend in the second direction D2 and may connect the second portion P2 and the third portion P3 to each other.

[0090] The top surfaces P1t of the first portion P1, P2t of the second portion P2, and P3t of the third portion P3 may be substantially coplanar with each other. The bottom surfaces P1b of the first portion P1, P2b of the second portion P2, and P3b of the third portion P3 may be located at different heights relative to the upper surface of the substrate 100. For example, the bottom surface P1b of the first portion P1 may be higher than the bottom surface P3b of the third portion P3, and the bottom surface P3b of the third portion P3 may be higher than the bottom surface P2b of the second portion P2.

[0091] As previously referenced Figure 3 and 5The described interconnect ML can be provided on the conductive structure CP.

[0092] Figure 9 This is a layout diagram illustrating a portion of a standard cell layout according to an exemplary embodiment of the concept of the present invention. In the following description of embodiments of the invention, for the sake of brevity, the previously referenced documents may not be described in further detail. Figure 3 The described element.

[0093] refer to Figure 9 A standard cell layout may include an active region AR, a gate pattern GP, ​​a conductive pattern CL, a via pattern V0, and a conductor M1. The conductive pattern CL may include a connection pattern M0 and a pair of active contact patterns CA.

[0094] Active contact patterns CA can be respectively disposed on opposite portions of active regions AR, which are located on both sides of gate pattern GP. Each of the active contact patterns CA can overlap with a connecting pattern M0. The connecting pattern M0 can span the gate pattern GP and extend in the second direction D2.

[0095] To reduce the complexity of the diagrams and to provide a better understanding of exemplary embodiments of the concepts of this invention, Figure 9 The through-hole pattern V0 and the wire M1 are not shown; however, the through-hole pattern and the wire can be freely arranged on the connection pattern M0, for example, as previously referenced. Figure 3 As described.

[0096] Figure 10 This is a perspective view illustrating an exemplary semiconductor device according to a concept presented in the present invention. For example, Figure 10 This is an explanation based on Figure 9 A perspective view of a semiconductor device formed by the layout. In the following description of embodiments of the present invention, for the sake of brevity, the previously referenced documents will not be described in further detail. Figure 4 The described element.

[0097] refer to Figure 10 A conductive structure CP may be disposed on a substrate 100. The conductive structure CP may include a first portion P1 and a pair of second portions P2. The second portions P2 may be disposed on and electrically connected to the source / drain regions SD, which are located on opposite sides of the gate electrode GE. Here, the first portion P1 may be formed to extend across the gate electrode GE in a second direction D2 and may be used to connect the second portions P2 to each other. In other words, the first portion P1 can connect the second portions P2 to each other, with the second portions P2 spaced apart from each other by the gate electrode GE inserted therebetween.

[0098] As previously referenced Figure 3As described, interconnects ML can be provided on conductive structures CP.

[0099] Figure 11 This is a layout diagram illustrating a portion of a standard cell layout according to an exemplary embodiment of the concept of the present invention. In the following description of embodiments of the invention, for the sake of brevity, the previously referenced documents may not be described in further detail. Figure 5 The described element.

[0100] refer to Figure 11 A standard cell layout may include an active region AR, a gate pattern GP, ​​a conductive pattern CL, a via pattern V0, and a conductor M1. The conductive pattern CL may include a connection pattern M0 and a pair of gate contact patterns CB.

[0101] Gate contact patterns CB can be disposed on gate patterns GP. Gate contact patterns CB can overlap with connection patterns M0. Connection patterns M0 can span gate patterns GP and extend in the second direction D2.

[0102] To reduce the complexity of the diagrams and to provide a better understanding of exemplary embodiments of the concepts of this invention, Figure 11 The through-hole pattern V0 and the wire M1 are not shown; however, the through-hole pattern and the wire can be freely arranged on the connection pattern M0, for example, as previously referenced. Figure 5 As described.

[0103] Figure 12 This is a perspective view illustrating an exemplary semiconductor device according to a concept presented in the present invention. For example, Figure 12 This is an explanation based on Figure 11 A perspective view of a semiconductor device formed by the layout. In the following description of embodiments of the present invention, for the sake of brevity, the previously referenced documents will not be described in further detail. Figure 6 The described element.

[0104] refer to Figure 12 A conductive structure CP may be disposed on a gate electrode GE formed on a substrate 100. The conductive structure CP may include a first portion P1 and a pair of third portions P3. The third portions P3 may be electrically connected to the gate electrode GE. Here, the first portion P1 may extend in a second direction D2 to cross the gate electrode GE, and the third portions P3 may be connected to each other through the first portion P1.

[0105] As previously referenced Figure 3 As described, interconnects ML can be provided on conductive structures CP.

[0106] Figure 13This is a layout diagram including a standard cell layout according to an exemplary embodiment of the concept of the present invention. In the following description of embodiments of the present invention, for the sake of brevity, the previously referenced documents will not be described in further detail. Figure 3 , 5 The elements described in 7, 9 and 11.

[0107] refer to Figure 13 The layout design tool can be used to arrange standard cell layouts side-by-side. For example, a standard cell layout may include first to third standard cell layouts STD1, STD2, and STD3. The first to third standard cell layouts STD1, STD2, and STD3 can be arranged in a second direction D2. Each of the first to third standard cell layouts STD1, STD2, and STD3 may include a logic layout for logic transistors, an interconnect layout for interconnects provided on the logic transistors, and a contact layout for connecting the logic transistors and interconnects to each other.

[0108] The logic layout may include an active layout for the active region. The active layout may include a PMOSFET region PR and an NMOSFET region NR. The PMOSFET region PR and the NMOSFET region NR may be spaced apart from each other on a first direction D1 that intersects with the second direction D2.

[0109] The logic layout may include a layout for the gate electrode (e.g., a gate pattern GP) extending in a first direction D1 and spanning the PMOSFET region PR and the NMOSFET region NR. The gate patterns GP may be spaced apart from each other in a second direction D2. The PMOSFET region PR, the NMOSFET region NR, and the gate pattern GP may constitute a logic transistor provided on the semiconductor substrate 100.

[0110] The contact layout may include: a layout for the lower conductive structure (e.g., a lower conductive pattern LP) that overlaps with or connects to each of the PMOSFET region PR and the NMOSFET region NR; a layout for the connection pattern M0 (e.g., connection patterns M0a-M0h); a layout for the active contact AC (e.g., active contact patterns CAa-CAl) that overlaps with or connects to the lower conductive pattern LP; and a layout for the gate contact GC (e.g., gate contact patterns CBa-CBh) that overlaps with or connects to the gate pattern GP. Each of the connection patterns M0a-M0h may overlap with or connect to at least one of the active contact patterns CAa-CAl and the gate contact patterns CBa-CBh. Additionally, a layout for the conductive structure CP (e.g., conductive patterns CL1-CL8) may be defined within the contact layout. The conductive patterns CL1-CL8 may include the first to the eighth conductive patterns CL1-CL8.

[0111] The interconnect layout may include: a layout for via patterns (e.g., via pattern V0); a layout for interconnects (e.g., conductors M1a-M1g); and a layout for power interconnection lines (e.g., power lines PM1 and PM2). Each of the first power line PM1 and the second power line PM2 may be a linear structure extending in a second direction D2. The first power line PM1 and the second power line PM2 may be connected to some active contact patterns CAa-CAl via the via pattern V0. Conductors M1a-M1g may be connected to some connection patterns M0a-M0h, some active contact patterns CAa-CAl, and some gate contact patterns CBa-CBh via the via pattern V0.

[0112] The first standard cell layout STD1 will now be described. For example, a first active contact pattern CAa may be provided to overlap with a first power line PM1 and a second power line PM2, respectively. The first power line PM1 and the second power line PM2 may be connected to the first active contact pattern CAa via a via pattern V0, respectively. A first gate contact pattern CBa may be provided to overlap with at least one of the gate patterns GP. A first conductor M1a may be connected to the first gate contact pattern CBa via a via pattern V0.

[0113] A pair of first conductive patterns CL1 may be positioned adjacent to a first conductor M1a. The pair of first conductive patterns CL1 may be positioned on a PMOSFET region PR and an NMOSFET region NR, respectively. Each of the first conductive patterns CL1 may include a second active contact pattern CAb and a first connection pattern MOa. The second active contact pattern CAb and the first connection pattern MOa may partially overlap each other. A second conductor M1b may be connected to the pair of first conductive patterns CL1 via a via pattern V0.

[0114] A pair of second conductive patterns CL2 may be disposed on the boundary between the first standard cell layout STD1 and the second standard cell layout STD2. The pair of second conductive patterns CL2 may be disposed on the PMOSFET region PR and the NMOSFET region NR, respectively. Each of the second conductive patterns CL2 may include a second gate contact pattern CBb, a second connection pattern MOb, and a third active contact pattern CAc. The second gate contact pattern CBb may overlap with the second connection pattern MOb. The third active contact pattern CAc and the second connection pattern MOb may partially overlap each other. However, the second gate contact pattern CBb and the third active contact pattern CAc may be spaced apart from each other in the second direction D2. The first power line PM1 and the second power line PM2 may be connected to the pair of second conductive patterns CL2 through via pattern V0, respectively.

[0115] The second standard cell layout STD2 will now be described. A pair of third conductive patterns CL3 may be disposed on the substrate 100. The pair of third conductive patterns CL3 may be disposed on the PMOSFET region PR and the NMOSFET region NR, respectively. Each of the third conductive patterns CL3 may include a fourth active contact pattern CAd, a fifth active contact pattern CAe, and a third connection pattern MOc. The fourth active contact pattern CAd and the fifth active contact pattern CAe may be spaced apart from each other in the second direction D2 by a gate pattern GP inserted therebetween. The third connection pattern MOc may cross the gate pattern GP and extend in the second direction D2. The fourth active contact pattern CAd and the third connection pattern MOc may partially overlap each other, and the fifth active contact pattern CAe and the third connection pattern MOc may partially overlap each other.

[0116] The fourth conductive pattern CL4 may be positioned adjacent to the third conductive pattern CL3. The fourth conductive pattern CL4 may be positioned between the PMOSFET region PR and the NMOSFET region NR. The fourth conductive pattern CL4 may include a third gate contact pattern CBc, a fourth gate contact pattern CBd, and a fourth connection pattern M0d. The third gate contact pattern CBc and the fourth gate contact pattern CBd may each overlap with an adjacent gate pattern GP. The fourth connection pattern M0d may cross the gate pattern GP and extend in the second direction D2. The third gate contact pattern CBc and the fourth gate contact pattern CBd may overlap with the fourth connection pattern M0d. The third conductor M1c may be connected to the fourth conductive pattern CL4 through the via pattern V0.

[0117] A pair of sixth active contact patterns CAf can be disposed between gate patterns GP, which are respectively connected to the third gate contact pattern CBc and the fourth gate contact pattern CBd. The pair of sixth active contact patterns CAf can be disposed on the PMOSFET region PR and the NMOSFET region NR, respectively. The fourth conductor M1d can be connected to the pair of sixth active contact patterns CAf through the via pattern V0.

[0118] If the fourth connecting pattern M0d is omitted, then it is not necessary to use... Figure 13 The shapes and positions shown form the third conductor M1c and the fourth conductor M1d. For example, the first conductor M1a and the second conductor M1b may have similar shapes. Figure 14B The shapes and positions shown.

[0119] A pair of fifth conductive patterns CL5 may be disposed on the boundary between the second standard cell layout STD2 and the third standard cell layout STD3. The pair of fifth conductive patterns CL5 may be disposed on the PMOSFET region PR and the NMOSFET region NR, respectively. Each of the fifth conductive patterns CL5 may include a seventh active contact pattern CAg, a fifth connection pattern Moe, a fifth gate contact pattern CBe, and an eighth active contact pattern CAh. The fifth gate contact pattern CBe may overlap with the fifth connection pattern Moe. The seventh active contact pattern CAg and the fifth connection pattern Moe may partially overlap each other, and the eighth active contact pattern CAh and the fifth connection pattern Moe may partially overlap each other. The seventh active contact pattern CAg, the eighth active contact pattern CAh, and the fifth gate contact pattern CBe may be spaced apart from each other in the second direction D2. The eighth active contact pattern CAh may extend in the first direction D1 and may partially overlap with the power lines PM1 and PM2. The first electric field line PM1 and the second electric field line PM2 can be connected to the fifth conductive pattern CL5 through the through-hole pattern V0, respectively.

[0120] The third standard cell layout STD3 will now be described. For example, a sixth gate contact pattern CBf and a seventh gate contact pattern CBg may be provided on substrate 100. The sixth gate contact pattern CBf and the seventh gate contact pattern CBg may be disposed between the PMOSFET region PR and the NMOSFET region NR. The sixth gate contact pattern CBf and the seventh gate contact pattern CBg may overlap with adjacent gate patterns GP, respectively. Furthermore, the sixth gate contact pattern CBf and the seventh gate contact pattern CBg may overlap with a fifth conductor M1e. The fifth conductor M1e may include: a first portion that overlaps with the sixth gate contact pattern CBf and the seventh gate contact pattern CBg and extends in a second direction D2; and a second portion that extends in a first direction D1. The fifth conductor M1e may be connected to the sixth gate contact pattern CBf and the seventh gate contact pattern CBg through a via pattern V0.

[0121] The sixth conductive pattern CL6 may be positioned adjacent to the fifth conductor M1e. The sixth conductive pattern CL6 may be positioned between the PMOSFET region PR and the NMOSFET region NR. The sixth conductive pattern CL6 may include an eighth gate contact pattern CBh and a sixth connection pattern M0f. The eighth gate contact pattern CBh may extend in the second direction D2 and may overlap with a pair of adjacent gate patterns GP. The sixth connection pattern M0f may include: a first portion extending in the second direction D2 and overlapping the eighth gate contact pattern CBh; and a second portion extending in the first direction D1. The second portion of the sixth connection pattern M0f may overlap with the sixth conductor M1f. The sixth conductive line M1f may be connected to the sixth conductive pattern CL6 via the via pattern V0.

[0122] A seventh conductive pattern CL7 may be provided on the NMOSFET region NR. The seventh conductive pattern CL7 may include a ninth active contact pattern CAi, a tenth active contact pattern CAj, and a seventh connection pattern Mog. The ninth active contact pattern CAi and the tenth active contact pattern CAj may be spaced apart from each other in the second direction D2 by a gate pattern GP inserted therebetween. The seventh connection pattern Mog may include: a first portion extending in the first direction D1 and overlapping the ninth active contact pattern CAi; a second portion extending in the first direction D1 and overlapping the tenth active contact pattern CAj; and a third portion extending in the second direction D2 and crossing the gate pattern GP.

[0123] The eighth conductive pattern CL8 may be disposed adjacent to the sixth conductive pattern CL6. The eighth conductive pattern CL8 may extend from the PMOSFET region PR to the NMOSFET region NR. The eighth conductive pattern CL8 may include an eleventh active contact pattern CAk, a twelfth active contact pattern CA1, and an eighth connection pattern M0h. The eleventh active contact pattern CAk and the twelfth active contact pattern CA1 may be disposed on the PMOSFET region PR and the NMOSFET region NR, respectively. The eleventh active contact pattern CAk may overlap with the sixth conductor M1f. The eighth connection pattern M0h may include: a first portion extending in the second direction D2 and overlapping the eleventh active contact pattern CAk; a second portion extending in the second direction D2 and overlapping the twelfth active contact pattern CA1; and a third portion extending in the first direction D1 and connecting the first and second portions to each other. The first portion of the eighth connection pattern M0h may span at least one of the gate patterns GP. Furthermore, the eighth connection pattern M0h and the seventh conductor M1g may partially overlap each other. The seventh conductor M1g can be connected to the eighth connection pattern M0h through the through-hole pattern V0.

[0124] In the first conductive pattern CL1 described above, a pair of second active contact patterns CAb can be connected to each other via a first connecting pattern M0a and a second wire M1b. In the eighth conductive pattern CL8, the eleventh active contact pattern CAk and the twelfth active contact pattern CA1 can be electrically connected to each other only via the eighth connecting pattern M0h.

[0125] Examples of first to eighth conductive patterns CL1-CL8 disposed on first to third standard cell layouts STD1, STD2, and STD3 have been described to date. However, the concept of the invention is not limited thereto. For example, the active contact patterns, gate contact patterns, and connection patterns may vary in their shape and position and may be connected to each other in various ways.

[0126] Figure 14A This describes an exemplary embodiment of the concept according to the present invention. Figure 13 The layout diagram of area "M". Figure 14B This is to explain based on the comparison examples. Figure 13 The layout diagram of area "M".

[0127] refer to Figure 14A The first gate contact pattern CBa, the first conductive pattern CL1, and the previously referenced Figure 13The first conductive line M1a and the second conductive line M1b described herein may be disposed on the substrate 100. The first conductive line M1a may be connected to the first gate contact pattern CBa via the via pattern V0. Each of the first conductive patterns CL1 may include a second active contact pattern CAb and a first connection pattern M0a. The first connection pattern M0a and the second conductive line M1b may partially overlap each other. Therefore, the second conductive line M1b may be connected to the first connection pattern M0a via the via pattern V0.

[0128] Each of the first conductor M1a and the second conductor M1b may include a pin region (PI) for establishing a wiring path to the upper interconnect. For example, each of the first conductor M1a and the second conductor M1b may include five pin regions (PI), which are arranged parallel to their longitudinal axis or in a first direction D1. In other words, the first conductor M1a and the second conductor M1b may include ten pin regions (PI).

[0129] refer to Figure 14B The first gate contact pattern CBa, a pair of second active contact patterns CAb, and the first and second conductors M1a and M1b can be disposed on the substrate. However, with Figure 14A different, Figure 14B The first connection pattern M0a is not included. The second conductor M1b may include: a first portion extending in a first direction D1; and a second portion extending in a second direction D2 and overlapping the pair of second active contact patterns CAb respectively. The second conductor M1b can be connected to the pair of second active contact patterns CAb through a through-hole pattern V0.

[0130] Each of the first conductor M1a and the second conductor M1b may include a pin area PI for establishing a wiring path to the upper interconnect. Due to the second portion of the second conductor M1b, the length of the first conductor M1a in the first direction D1 may be shorter than [the specified length]. Figure 14A The length of the first conductor M1a. Therefore, the first conductor M1a may contain, for example, three pin areas PI, and the second conductor M1b may contain five pin areas PI. Therefore, the first conductor M1a and the second conductor M1b may contain eight pin areas PI. In other words, the number of pin areas PI on the first conductor M1a and the second conductor M1b may be less than the reference. Figure 14A The number of examples described.

[0131] Figure 15A This is an exemplary embodiment of the concept according to the present invention. Figure 13 The layout diagram of area "N". Figure 15B This is to explain based on the comparison examples. Figure 13 The layout diagram of area "N".

[0132] refer to Figure 15A The sixth conductive pattern CL6, the eighth conductive pattern CL8, and the previously referenced Figure 13 The described sixth conductor M1f and seventh conductor M1g can be disposed on substrate 100. The sixth conductive pattern CL6 may include an eighth gate contact pattern CBh and a sixth connection pattern M0f. The eighth conductive pattern CL8 may include an eleventh active contact pattern CAk, a twelfth active contact pattern CA1, and an eighth connection pattern M0h. The sixth connection pattern M0f and the sixth conductor M1f may partially overlap each other, and the eighth connection pattern M0h and the seventh conductor M1g may partially overlap each other. Therefore, the sixth conductor M1f can be connected to the sixth connection pattern M0f through via pattern V0, and the seventh conductor M1g can be connected to the eighth connection pattern M0h through via pattern V0.

[0133] Each of the sixth conductor M1f and the seventh conductor M1g may include a pin area PI for establishing a wiring path to the upper interconnect. For example, each of the sixth conductor M1f and the seventh conductor M1g may include five pin areas PI, which are arranged parallel to their longitudinal axis or in the first direction D1. In other words, the sixth conductor M1f and the seventh conductor M1g may include ten pin areas PI.

[0134] refer to Figure 15B The sixth conductive pattern CL6, the eleventh active contact pattern CAk, the twelfth active contact pattern CA1, and the sixth wire M1f and the seventh wire M1g can be disposed on the substrate. However, with Figure 15A different, Figure 15B The eighth connection pattern M0h is not included. The seventh conductor M1g may include: a first portion extending in a first direction D1; and a second portion extending in a second direction D2 and overlapping with the eleventh active contact pattern CAk and the twelfth active contact pattern CA1, respectively. The seventh conductor M1g can be connected to each of the eleventh active contact pattern CAk and the twelfth active contact pattern CA1 through the through-hole pattern V0.

[0135] Each of the sixth conductor M1f and the seventh conductor M1g may include a pin area PI for establishing a wiring path to the upper interconnect. Due to the second portion of the seventh conductor M1g, the length of the sixth conductor M1f in the first direction D1 may be shorter than [the specified length]. Figure 15A The length of the sixth conductor M1f. Therefore, the sixth conductor M1f may contain, for example, three pin areas PI, and the seventh conductor M1g may contain five pin areas PI. Therefore, the sixth conductor M1f and the seventh conductor M1g may contain eight pin areas PI. In other words, the number of pin areas PI on the sixth conductor M1f and the seventh conductor M1g may be less than the reference. Figure 15A The number of examples described.

[0136] As described with reference to Figures 14 and 15, a standard cell layout according to an exemplary embodiment of the present invention may include additional connection patterns as well as active contact patterns and gate contact patterns. Therefore, degrees of freedom are increased when placing the layout for interconnects or wires, and the pin area for establishing wiring paths to the upper interconnects is increased. In other words, the connection patterns make it easier to construct wiring structures.

[0137] Figure 16 This is a plan view illustrating an exemplary embodiment of a semiconductor device according to the inventive concept. Figures 17A to 17R They are along Figure 16 The cross-sectional views taken from lines A-A', B-B', C-C', D-D', E-E', F-F', G-G', H-H', I-I', J-J', K-K', L-L', M-M', N-N', O-O', P-P', Q-Q', and R-R'. For example, Figure 16 and Figures 17A to 17R Explanation based on Figure 13 Examples of semiconductor devices formed using a standard cell layout. In the following description of embodiments of the present invention, for the sake of brevity, further details of the previously referenced [references] will not be described. Figure 4 , 6 The elements described in 8, 10 and 12.

[0138] Reference Figure 16 and 17A In the semiconductor device described up to 17R, each element of the semiconductor device can be transmitted through... Figure 2 The photolithography process S150 is integrated on the semiconductor substrate 100, and therefore the element can be separated from the constituent components. Figure 13 The corresponding pattern is the same as the standard cell layout. The semiconductor device can be, for example, a system-on-chip.

[0139] refer to Figure 16 and 17A Up to 17R, a second device isolation pattern ST2 may be provided on substrate 100 to define the PMOSFET region PR and the NMOSFET region NR. The second device isolation pattern ST2 may be provided in the upper portion of substrate 100. In an exemplary embodiment of the present invention, substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-on-insulator (SOI) substrate.

[0140] The PMOSFET region PR and the NMOSFET region NR are spaced apart from each other in a first direction D1 parallel to the top surface of the substrate 100 by a second device isolation pattern ST2 inserted therebetween. Although each of the PMOSFET region PR and the NMOSFET region NR is described as a single region, each of the PMOSFET region PR and the NMOSFET region NR may comprise multiple regions spaced apart from each other by the second device isolation pattern ST2.

[0141] A plurality of first active patterns FN1 may be provided on the PMOSFET region PR to extend in a second direction D2 intersecting the first direction D1, and a plurality of second active patterns FN2 may be provided on the NMOSFET region NR to extend in the second direction D2. The first active patterns FN1 and the second active patterns FN2 may be part of the substrate 100 and may have a protruding shape. In other words, the active patterns may protrude from the substrate 100. The first active patterns FN1 and the second active patterns FN2 may be arranged in the first direction D1. A first device isolation pattern ST1 extending in the second direction D2 may be disposed on both sides of each of the first active patterns FN1 and the second active patterns FN2.

[0142] Between the first device isolation patterns ST1, the upper portions of the first active pattern FN1 and the second active pattern FN2 may protrude vertically relative to the first device isolation pattern ST1. In other words, each of the upper portions of the first active pattern FN1 and the second active pattern FN2 may have a fin-like shape between the first device isolation patterns ST1.

[0143] The second device isolation pattern ST2 may be substantially connected to the first device isolation pattern ST1 to form a single insulating pattern. The second device isolation pattern ST2 may be thicker than the first device isolation pattern ST1. In this case, the first device isolation pattern ST1 and the second device isolation pattern ST2 may be formed by different processes. For example, the first device isolation pattern ST1 and the second device isolation pattern ST2 may be made of or contain a silicon oxide layer.

[0144] Gate electrodes GE are provided on a first active pattern FN1 and a second active pattern FN2 to extend in a first direction D1 and across the first active pattern FN1 and the second active pattern FN2. Gate electrodes GE may be spaced apart from each other in a second direction D2. Each of the gate electrodes GE may extend in the first direction D1 and cross the PMOSFET region PR, the second device isolation pattern ST2, and the NMOSFET region NR.

[0145] In an exemplary embodiment of the present invention, the virtual gate electrode DM may be provided on the boundary between the first standard cell STDC1 and the second standard cell STDC2, and on the boundary between the second standard cell STDC2 and the third standard cell STDC3, respectively. Each of the virtual gate electrodes DM may be divided into two electrodes by a second device isolation pattern ST2, but the present invention is not limited thereto. The virtual gate electrode DM may have a substantially the same structure as the gate electrode GE and may be made of substantially the same material as the gate electrode GE. In a circuit, the virtual gate electrode DM may act as a conductor of a transistor.

[0146] A gate insulating pattern GI may be provided beneath each of the gate electrodes GE, and a gate spacer GS may be provided on both sides of each of the gate electrodes GE. Additionally, a cap pattern CP may be provided to cover the top surface of each of the gate electrodes GE. However, in an exemplary embodiment of the present invention, the cap pattern CP may be partially removed from a portion of the top surface of the gate electrode GE, to which the gate contact GC, described below, is connected. The gate insulating pattern GI may extend vertically to cover both sidewalls of the gate electrode GE. For example, the gate insulating pattern GI may be inserted between the gate electrode GE and the gate spacer GS. First to third interlayer insulating layers 110-130 may be provided to cover the first active pattern FN1 and the second active pattern FN2, as well as the gate electrode GE.

[0147] The gate electrode GE may be formed or comprised of a doped semiconductor material, a conductive metal nitride, or a metal. The gate insulating pattern GI may be formed or comprised of a silicon oxide layer, a silicon oxynitride layer, or a high-dielectric-constant material, wherein the dielectric constant of the high-dielectric-constant material is lower than that of silicon oxide. Each of the top cover pattern CP and the gate spacer GS may comprise a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. Each of the first to third interlayer insulating layers 110-130 may comprise a silicon oxide layer or a silicon oxynitride layer.

[0148] The source / drain region SD can be provided on or within the upper portions of the first active pattern FN1 and the second active pattern FN2. The source / drain region SD on the PMOSFET region PR can be a p-type impurity region, and the source / drain region SD on the NMOSFET region NR can be an n-type impurity region. The channel region AF can be provided in the upper portion of each of the first active pattern FN1 and the second active pattern FN2, which overlap with the gate electrode GE, respectively. Each of the channel regions AF can be inserted between the source / drain regions SD.

[0149] The source / drain region SD can be an epitaxial pattern formed by a selective epitaxial growth process. Therefore, the source / drain region SD may have a top surface located above a horizontal plane above the channel region AF. The source / drain region SD may contain a semiconductor element different from the semiconductor element of the substrate 100. For example, the source / drain region SD may be constituted or contain a semiconductor material having a lattice constant different from (e.g., greater than or less than) that of the substrate 100. Therefore, compressive or tensile stress may be applied to the channel region AF in the source / drain region SD.

[0150] The lower conductive structure TS can be provided on the PMOSFET region PR and the NMOSFET region NR between the gate electrodes GE. The lower conductive structure TS can be based on... Figure 13 The lower conductive pattern LP forms a pattern. The lower conductive structure TS can be provided in the first interlayer insulating layer 110 and can be directly connected to the source / drain region SD. The lower conductive structure TS can extend in the first direction D1. When viewed in a plan view, each of the lower conductive structures TS can partially overlap with the first power interconnect PL1 or the second power interconnect PL2. The lower conductive structure TS can have a top surface that is substantially coplanar with the top surface of the first interlayer insulating layer 110. In embodiments of the invention, each of the lower conductive structures TS is illustrated as contacting a plurality of source / drain regions SD, but the concept of the invention is not limited thereto. For example, at least one of the lower conductive structures TS can contact one or both of the source / drain regions SD. The lower conductive structure TS can be composed of or contain doped semiconductor material, conductive metal nitride, metal or metal silicide.

[0151] Conductive structures GC, AC, and CP1-CP8 may be provided in the second interlayer insulating layer 120. Conductive structures GC, AC, and CP1-CP8 may include a gate contact GC, an active contact AC, and first to eighth conductive structures CP1-CP8. Conductive structures GC, AC, and CP1-CP8 may be based on... Figure 13 The pattern is formed by the connection patterns M0a-M0h, the active contact patterns CAa-CAl, and the gate contact patterns CBa-CBh. The conductive structures GC, AC, and CP1-CP8 may contain conductive metal nitrides or metals.

[0152] Conductive structures GC, AC, and CP1-CP8 may have a top surface that is substantially coplanar with the top surface of the second interlayer insulating layer 120. Additionally, the active contact AC may have a bottom surface that is substantially coplanar with the bottom surface of the second interlayer insulating layer 120. The bottom surface of the gate contact GC may be lower than the bottom surface of the second interlayer insulating layer 120. In other words, the bottom surface of the gate contact GC may be lower than the bottom surface of the active contact AC. The first to eighth conductive structures CP1-CP8 will be described in more detail below.

[0153] The barrier layer pattern BL can be inserted between the second interlayer insulating layer 120 and the conductive structures GC, AC, and CP1-CP8, respectively. Except for the top surface of the conductive structures GC, AC, and CP1-CP8, the barrier layer pattern BL can directly cover the side and bottom surfaces of the conductive structures GC, AC, and CP1-CP8. The barrier layer pattern BL may contain metal nitrides to prevent the diffusion of metal elements from the conductive structures GC, AC, and CP1-CP8. For example, the barrier layer pattern BL may be composed of or contain titanium nitride.

[0154] The first power interconnect PL1, the second power interconnect PL2, and the first to sixth interconnects ML1-ML6 may be provided in the third interlayer insulation layer 130. The first power interconnect PL1 and the second power interconnect PL2 may be based on... Figure 13 The pattern formed by power lines PM1 and PM2, and the first to sixth interconnecting lines ML1-ML6 can be based on Figure 13 The pattern formed by the conductors M1a-M1f.

[0155] Each of the first power interconnect PL1 and the second power interconnect PL2, and each of the first to sixth interconnects ML1-ML6, may include: a line portion LI extending parallel to the top surface of the substrate 100; and a contact portion VI perpendicularly connected to the conductive structures GC, AC, and CP1-CP8. The contact portion VI may be based on... Figure 13 The pattern formed by the through-hole pattern V0.

[0156] The barrier layer pattern BL can be inserted between the third interlayer insulating layer 130 and the first electrical interconnect PL1 and the second electrical interconnect PL2, and between the third interlayer insulating layer 130 and the first to sixth interconnects ML1-ML6, respectively. The barrier layer pattern BL may contain a metal nitride to prevent the diffusion of metal elements. For example, the barrier layer pattern BL may be composed of or contain titanium nitride.

[0157] Reference Figure 16 and 17AThe first standard unit STDC1 is described up to 17E. A pair of active contacts AC is provided on a lower conductive structure TS, which is positioned below a first power interconnect PL1 or a second power interconnect PL2. In other words, when viewed in a cross-sectional view, the pair of active contacts AC can be inserted between the first power interconnect PL1 or the second power interconnect PL2 and the lower conductive structure TS. The pair of active contacts AC can be based on... Figure 13 The pattern formed by the first active contact pattern CAa. The active contact AC is electrically connected to the first power interconnect PL1 and the second power interconnect PL2. The power or ground voltage applied to the first power interconnect PL1 and the second power interconnect PL2 can be transmitted through the active contact AC (e.g., see...). Figure 17D The voltage is applied to the lower conductive structure TS. Here, since the lower conductive structure TS can overlap with the first power interconnect PL1 and the second power interconnect PL2 when viewed in a plan view, the power or ground voltage can be applied to the lower conductive structure TS through vertical and straight current paths.

[0158] Gate contact GC can be provided on at least one gate electrode GE of the first standard cell STDC1. Gate contact GC can be provided on the second device isolation pattern ST2 between the PMOSFET region PR and the NMOSFET region NR. Gate contact GC can be based on... Figure 13 The first gate contact pattern CBa is formed by the pattern. A first interconnect ML1 is provided on and connected to the gate contact GC. For example, the first interconnect ML1 and the gate electrode GE can be electrically connected to each other through the gate contact GC.

[0159] A pair of first conductive structures CP1 can be provided on the PMOSFET region PR and NMOSFET region NR of the first standard cell STDC1, respectively. The pair of first conductive structures CP1 can be based on... Figure 13 The pattern formed on the first conductive pattern CL1. Each of the first conductive structures CP1 may include a first portion P1 and a second portion P2.

[0160] Part 1, P1, can be based on... Figure 13 The first connecting pattern M0a forms the pattern, and the second part P2 can be based on Figure 13 The pattern formed by the second active contact pattern CAb. For example, the second portion P2 may be connected to the lower conductive structure TS, and the first portion P1 may extend from the second portion P2 in a direction parallel to the top surface of the substrate 100.

[0161] The first conductive structure CP1 can be similar to the previously referenced Figure 4The conductive structure CP is described. However, the semiconductor device according to embodiments of the present invention may further include a lower conductive structure TS provided between the active region AR and the first conductive structure CP1. For example, the first portion P1 and the second portion P2 may have top surfaces that are substantially coplanar with each other, but the bottom surface of the first portion P1 may be higher than the bottom surface of the second portion P2. The bottom surface of the second portion P2 may be located at substantially the same height as the bottom surface of the active contact AC.

[0162] The second interconnect ML2 can be provided on and connected to the first conductive structure CP1. In other words, the second interconnect ML2 and the lower conductive structure TS can be electrically connected to each other through the first conductive structure CP1. In addition, the source / drain region SD on the PMOSFET region PR can be electrically connected to the source / drain region SD on the NMOSFET region NR through the lower conductive structure TS, the first conductive structure CP1, and the second interconnect ML2.

[0163] Reference Figure 16 and 17F Section 17H describes a second conductive structure CP2 provided at the interface between the first standard cell STDC1 and the second standard cell STDC2. A pair of second conductive structures CP2 may be provided on the PMOSFET region PR and the NMOSFET region NR, respectively. The pair of second conductive structures CP2 may be based on... Figure 13 The pattern formed on the second conductive pattern CL2. Each of the second conductive structures CP2 may include a first portion P1, a second portion P2, and a third portion P3.

[0164] Part 1, P1, can be based on... Figure 13 The second connection pattern M0b forms the pattern, and the second part P2 can be based on... Figure 13 The pattern formed by the third active contact pattern CAc, and the third part P3 can be based on Figure 13 The second gate contact pattern CBb is formed by the pattern. For example, the second portion P2 may be connected to the lower conductive structure TS, and the third portion P3 may be connected to the gate electrode GE. The first portion P1 may extend in a direction parallel to the top surface of the substrate 100 and connect the second portion P2 and the third portion P3 to each other.

[0165] The second conductive structure CP2 can be similar to the previous reference. Figure 8The described conductive structure CP may have, for example, a first portion P1, a second portion P2, and a third portion P3 with top surfaces that are substantially coplanar with each other. However, the first portion P1, the second portion P2, and the third portion P3 may have bottom surfaces located at different heights. For example, the bottom surface of the second portion P2 may be higher than the bottom surface of the third portion P3, and the bottom surface of the first portion P1 may be higher than the bottom surface of the second portion P2. The bottom surface of the third portion P3 may be located at substantially the same height as the bottom surface of the gate contact GC.

[0166] The first power interconnect PL1 and the second power interconnect PL2 can be connected to the second conductive structure CP2 via the second portion P2, respectively. In other words, the first power interconnect PL1 and the second power interconnect PL2 can be electrically connected to the lower conductive structure TS and the gate electrode GE via the second conductive structure CP2.

[0167] Reference Figure 16 and 17I The second standard cell STDC2 is described up to 17M. A pair of third conductive structures CP3 may be provided adjacent to each of the pair of second conductive structures CP2. The pair of third conductive structures CP3 may be provided on the PMOSFET region PR and the NMOSFET region NR, respectively. The pair of third conductive structures CP3 may be based on... Figure 13 The pattern formed by the third conductive pattern CL3. Each of the third conductive structures CP3 may include a first portion P1 and a pair of second portions P2.

[0168] Part 1, P1, can be based on... Figure 13 The pattern formed by the third connecting pattern M0c, and the second part P2 can be respectively based on Figure 13 The pattern is formed by the fourth active contact pattern CAd and the fifth active contact pattern CAe. For example, the second portion P2 can be connected to a pair of lower conductive structures TS, which are arranged adjacent to each other by a gate electrode GE inserted therebetween. The first portion P1 can extend parallel to the top surface of the substrate 100 and the second portions P2 can be connected to each other.

[0169] The third conductive structure CP3 can be similar to the previous reference. Figure 10The described conductive structure CP. For example, the first portion P1 and the second portion P2 may have top surfaces that are substantially coplanar with each other, but the bottom surface of the first portion P1 may be higher than the bottom surface of the second portion P2. Since the bottom surface of the first portion P1 is higher than the top surface of the lower conductive structure TS and the top surface of the gate electrode GE, the third conductive structure CP3 can electrically connect the lower conductive structures TS to each other, which are spaced apart from each other in the second direction D2. Therefore, the gate electrode GE is not short-circuited. In other words, the third conductive structure CP3 can each act as a jumper for electrically connecting the source / drain regions SD, which are separated from each other in the second direction D2.

[0170] A fourth conductive structure CP4 can be provided on a pair of adjacent gate electrodes GE of the second standard cell STDC2. The fourth conductive structure CP4 can also be provided on the second device isolation pattern ST2 between the PMOSFET region PR and the NMOSFET region NR. The fourth conductive structure CP4 can be based on... Figure 13 The pattern formed by the fourth conductive pattern CL4. The fourth conductive structure CP4 may include a first part P1 and a pair of third parts P3.

[0171] Part 1, P1, can be based on... Figure 13 The pattern formed by the fourth connecting pattern M0d, and the third part P3 can be respectively based on Figure 13 The pattern is formed by the third gate contact pattern CBc and the fourth gate contact pattern CBd. For example, the third portion P3 can be connected to the gate electrode GE respectively. The first portion P1 can extend parallel to the top surface of the substrate 100 and the third portions P3 can be connected to each other.

[0172] The fourth conductive structure CP4 can be similar to the previous reference. Figure 12 The conductive structure CP is described. For example, the first portion P1 and the third portion P3 may have top surfaces that are substantially coplanar with each other, but the bottom surface of the first portion P1 may be higher than the bottom surface of the third portion P3. Since the bottom surface of the first portion P1 is higher than the top surface of the lower conductive structure TS, the third conductive structure CP3 can electrically connect the gate electrodes GE to each other without short-circuiting the adjacent lower conductive structure TS.

[0173] A third interconnect ML3 may be provided on and connected to the fourth conductive structure CP4. When viewed in a plan view, the third interconnect ML3 may be spaced apart from the counter gate electrode GE in the second direction D2. When the third interconnect ML3 does not overlap with at least one of the counter gate electrodes GE in the plan view, the third interconnect ML3 may be electrically connected to the counter gate electrode GE via a first portion P1.

[0174] A pair of active contacts AC can be provided on the PMOSFET region PR and NMOSFET region NR adjacent to the fourth conductive structure CP4, respectively. The pair of active contacts AC can be based on... Figure 13 The pattern formed by the sixth active contact pattern CAf.

[0175] A fourth interconnect ML4 may be provided on and connected to the pair of active contacts AC. When viewed in a plan view, the fourth interconnect ML4 may span the fourth conductive structure CP4 and extend in the first direction D1. Since the bottom surface of the line portion LI of the fourth interconnect ML4 is higher than the top surface of the fourth conductive structure CP4, the fourth interconnect ML4 may be perpendicularly separated from the fourth conductive structure CP4.

[0176] Reference Figure 16 and 17N A fifth conductive structure CP5 is described at the interface between the second standard cell STDC2 and the third standard cell STDC3. A pair of fifth conductive structures CP5 may be provided on the PMOSFET region PR and the NMOSFET region NR, respectively. The pair of fifth conductive structures CP5 may be based on... Figure 13 The pattern formed by the fifth conductive pattern CL5. Each of the fifth conductive structures CP5 may include a first portion P1, a second portion P2, and a third portion P3.

[0177] Part 1, P1, can be based on... Figure 13 The pattern formed by the fifth connecting pattern M0e, the second part P2 can be respectively based on Figure 13 The pattern formed by the seventh active contact pattern CAg and the eighth active contact pattern CAh, and the third part P3 can be based on Figure 13 The fifth gate contact pattern CBe is formed by the pattern. For example, the second portion P2 may be connected to a pair of adjacent lower conductive structures TS, and the third portion P3 may be connected to the gate electrode GE between the pair of lower conductive structures TS. In other words, when viewed in a plan view, the third portion P3 may be inserted between the second portions P2. When viewed in a plan view, one of the second portions P2 may extend further in the first direction D1 than the other, and therefore may overlap with the first power interconnect PL1 or the second power interconnect PL2. The first portion P1 may extend in the second direction D2 and may connect the second portion P2 and the third portion P3 to each other. In addition to providing multiple second portions P2, the fifth conductive structure CP5 may be similar to the second conductive structure CP2 described above.

[0178] Reference Figure 16 and 17OThe third standard cell STDC3 is described up to 17R. A first gate group GG1 and a second gate group GG2 may be provided on the third standard cell STDC3. Each of the first gate group GG1 and the second gate group GG2 may include a pair of gate electrodes GE disposed adjacent to each other. Furthermore, the first gate group GG1 and the second gate group GG2 may be adjacent to each other.

[0179] A pair of gate contacts GC can be provided on the opposite gate electrode GE of the first gate group GG1. Furthermore, a sixth conductive structure CP6 can be provided on the second gate group GG2. The opposite gate contacts GC can be respectively based on... Figure 13 The pattern formed by the sixth gate contact pattern CBf and the seventh gate contact pattern CBg. The sixth conductive structure CP6 can be based on... Figure 13 The pattern formed by the sixth conductive pattern CL6. The sixth conductive structure CP6 may include a first part P1 and a third part P3.

[0180] Part 1, P1, can be based on... Figure 13 The pattern formed by the sixth connecting pattern M0f, and the third part P3 can be based on Figure 13 The pattern formed by the eighth gate contact pattern CBh. The third portion P3 may extend in the second direction D2 and may be connected to the two gate electrodes in the gate electrode GE of the second gate group GG2. The first portion P1 of the sixth conductive structure CP6 may include a first extension portion HP1 extending in the second direction D2 and a second extension portion HP2 extending in the first direction D1. The first extension portion HP1 may overlap with the third portion P3. In this case, the first extension portion HP1 and the third portion P3 may be connected to each other to form a single body.

[0181] A fifth interconnect ML5 may be provided on the gate contact GC, and a sixth interconnect ML6 may be provided on the sixth conductive structure CP6. The fifth interconnect ML5 may comprise a first region extending in a first direction D1 and a second region extending from the first region in a second direction D2. When viewed in a plan view, the second region of the fifth interconnect ML5 may overlap with the gate contact GC. The fifth interconnect ML5 can be connected to the gate contact GC via the second region.

[0182] When viewed in a plan view, the second extension HP2 of the sixth conductive structure CP6 may overlap with a portion of the sixth interconnect ML6. The sixth interconnect ML6 can be connected to the sixth conductive structure CP6 via the second extension HP2.

[0183] A seventh conductive structure CP7 can be provided on the NMOSFET region NR adjacent to the gate contact GC and the sixth conductive structure CP6. The seventh conductive structure CP7 can be based on... Figure 13 The pattern formed by the seventh conductive pattern CL7. The seventh conductive structure CP7 may include a first part P1 and a pair of second parts P2. The seventh conductive structure CP7 may be similar to the third conductive structure CP3 described above.

[0184] Part 1, P1, can be based on... Figure 13 The pattern formed by the seventh connecting pattern Mog, and the second part P2 can be respectively based on Figure 13 The pattern formed by the ninth active contact pattern CAi and the tenth active contact pattern CAj. The second portion P2 can be spaced apart from each other by at least one of the gate electrodes GE inserted therebetween. The first portion P1 of the seventh conductive structure CP7 may include a first extension portion HP1 extending in the second direction D2 and a pair of second extension portions HP2 extending in the first direction D1. The pair of second extension portions HP2 may overlap with the pair of second portions P2 respectively. In other words, the first portion P1 can connect the pair of second portions P2 to each other.

[0185] The eighth conductive structure CP8 can be provided as adjacent to the seventh conductive structure CP7. The eighth conductive structure CP8 can extend from the PMOSFET region PR to the NMOSFET region NR. The eighth conductive structure CP8 can be based on... Figure 13 The pattern formed by the eighth conductive pattern CL8. The eighth conductive structure CP8 may include a first part P1 and a pair of second parts P2.

[0186] Part 1, P1, can be based on... Figure 13 The pattern formed by the eighth connecting pattern M0h, and the second part P2 can be respectively based on Figure 13 The pattern formed by the eleventh active contact pattern CAk and the twelfth active contact pattern CA1.

[0187] For example, the second portion P2 can be connected to the lower conductive structure TS on the PMOSFET region PR and the lower conductive structure TS on the NMOSFET region NR, respectively. For instance, when viewed in a plan view, the second portion P2 on the PMOSFET region PR can overlap with the sixth interconnect ML6.

[0188] The first portion P1 of the eighth conductive structure CP8 may include a pair of first extension portions HP1 extending in the second direction D2 and a second extension portion HP2 extending in the first direction D1. The pair of first extension portions HP1 may overlap with the pair of second portions P2. For example, a first extension portion HP1 on the PMOSFET region PR may be provided to span at least one of the gate electrodes GE. In other words, the first portion P1 can connect the pair of second portions P2 to each other. Therefore, the source / drain region SD on the PMOSFET region PR and the source / drain region SD on the NMOSFET region NR can be electrically connected to each other through the lower conductive structure TS and the eighth conductive structure CP8.

[0189] In the case of the first conductive structure CP1 described above, the source / drain regions SD on the PMOSFET region PR and the source / drain regions SD on the NMOSFET region NR can be connected to each other in the first direction D1 via the second interconnect ML2. In the case of the eighth conductive structure CP8, the source / drain regions SD on the PMOSFET region PR and the source / drain regions SD on the NMOSFET region NR can be electrically connected to each other in the first direction D1 via the first portion P1 of the eighth conductive structure CP8.

[0190] A seventh interconnect ML7 may be provided on the eighth conductive structure CP8. When viewed in a plan view, the second extension HP2 of the eighth conductive structure CP8 may partially overlap with the seventh interconnect ML7. The seventh interconnect ML7 can be connected to the eighth conductive structure CP8 through the second extension HP2.

[0191] Figure 18A and 18B This is for illustrating an exemplary semiconductor device according to the concept of the present invention. Figure 16 A cross-sectional view taken from line A-A'. Figure 18C This is for illustrating an exemplary semiconductor device according to the concept of the present invention. Figure 16 A cross-sectional view taken by line F-F'. In the following description of embodiments of the invention, for the sake of brevity, the previously referenced documents will not be described in further detail. Figure 16 and Figures 17A to 17P The described element.

[0192] refer to Figure 16 and 18A This can provide the first conductive structure CP1. With Figure 17AUnlike the first conductive structure CP1, the first conductive structure CP1 may further include a first vertical extension portion VP1. For example, the second portion P2 of the first conductive structure CP1 may include a first vertical extension portion VP1 extending vertically toward the substrate 100. The first vertical extension portion VP1 may be provided to cover the upper portion of the sidewall of the lower conductive structure TS. The bottom surface of the first vertical extension portion VP1 may be lower than the top surface of the lower conductive structure TS. When viewed in a plan view, the first vertical extension portion VP1 may overlap with the first portion P1 of the first conductive structure CP1.

[0193] refer to Figure 16 and 18B This can provide the first conductive structure CP1. With Figure 17A Unlike the first conductive structure CP1, the first conductive structure CP1 may further include a pair of first vertical extensions VP1. For example, the second portion P2 of the first conductive structure CP1 may include the pair of first vertical extensions VP1 extending vertically toward the substrate 100. The pair of first vertical extensions VP1 may be provided to cover the upper portions of the two sidewalls of the lower conductive structure TS. The bottom surface of the first vertical extensions VP1 may be lower than the top surface of the lower conductive structure TS. When viewed in a plan view, the first vertical extensions VP1 may overlap with the first portion P1 of the first conductive structure CP1.

[0194] refer to Figure 16 and 18C This can provide a second conductive structure CP2. (And...) Figure 17F Unlike the second conductive structure CP2, the second conductive structure CP2 may further include a first vertical extension portion VP1 and a second vertical extension portion VP2. For example, the second portion P2 of the second conductive structure CP2 may include a first vertical extension portion VP1 extending vertically toward the substrate 100, and the third portion P3 of the second conductive structure CP2 may include a second vertical extension portion VP2 extending vertically toward the substrate 100. The first vertical extension portion VP1 may be provided to cover the upper portion of the sidewall of the lower conductive structure TS. The bottom surface of the first vertical extension portion VP1 may be lower than the top surface of the lower conductive structure TS. The second vertical extension portion VP2 may be provided to cover the upper portion of the sidewall of the gate electrode GE. The bottom surface of the second vertical extension portion VP2 may be lower than the top surface of the gate electrode GE. When viewed in a plan view, the first vertical extension portion VP1 and the second vertical extension portion VP2 may overlap with the first portion P1 of the second conductive structure CP2.

[0195] Figure 19 , 21 23, 25, 27, 29 and 31 are plan views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the concept of the present invention. Figure 20A , 22A 24A, 26A, 28A, 30A, and 32A are respectively along... Figure 19 , 21 The cross-sectional view of line A-A' intercepted by lines 23, 25, 27, 29, and 31. Figure 20B , 22B 24B, 26B, 28B, 30B, and 32B are respectively along... Figure 19 , 21 The cross-sectional view taken by line B-B' of lines 23, 25, 27, 29, and 31. Figure 22C , 24C 26C, 28C, 30C and 32C are respectively along the Figure 21 , 23 The cross-sectional view taken by line C-C' of lines 25, 27, 29, and 31. Figure 28D , 30D 32D and 32D are respectively along Figure 27 , 29 The cross-sectional view taken by line D-D' of line 31, and Figure 30E and 32E They are along Figure 29 and 31 A cross-sectional view taken from line E-E'. The following will describe the use of... Figure 13 This describes a method for fabricating semiconductor devices using a standard cell layout. For simplicity, the following description will refer to methods involving the use of... Figure 16 This is an example of a manufacturing method for the first standard unit STDC1; however, this method can be applied to other standard units (e.g., STDC2, STDC3, etc.).

[0196] refer to Figure 19 , 20A Substrate 100 may be provided, along with 20B. In an exemplary embodiment of the present invention, substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-on-insulator (SOI) substrate. Active patterns FN may be formed in the upper portion of substrate 100. A first device isolation pattern ST1 may be formed to fill the gaps between active patterns FN. The first device isolation pattern ST1 may be recessed to expose the upper portion of the active patterns FN. A second device isolation pattern ST2 may be formed on substrate 100 to define the boundary between the PMOSFET region PR and the NMOSFET region NR. In an exemplary embodiment of the present invention, when the second device isolation pattern ST2 is formed, the active patterns FN may be removed from the region other than the PMOSFET region PR and the NMOSFET region NR. The active pattern FN on the PMOSFET region PR may be referred to as "first active pattern FN1", and the active pattern FN on the NMOSFET region NR may be referred to as "second active pattern FN2".

[0197] The first device isolation pattern ST1 and the second device isolation pattern ST2 can be formed by a shallow trench isolation (STI) process. The first device isolation pattern ST1 and the second device isolation pattern ST2 can be formed of or contain silicon oxide. The first device isolation pattern ST1 can be formed to have a depth less than that of the second device isolation pattern ST2. In this case, the first device isolation pattern ST1 and the second device isolation pattern ST2 can be formed by different processes. In an exemplary embodiment of the present invention, the first device isolation pattern ST1 can be formed to have substantially the same depth as the second device isolation pattern ST2. For example, the first device isolation pattern ST1 and the second device isolation pattern ST2 can be formed by the same process at substantially the same time.

[0198] refer to Figure 21 and 22A At point 22C, the gate electrode GE can be formed across the first active pattern FN1 and the second active pattern FN2 and extend in the first direction D1. The gate electrodes GE can be spaced apart from each other in the second direction D2. A gate insulating pattern GI can be formed below each of the gate electrodes GE, and a gate spacer GS can be formed on both side surfaces of each of the gate electrodes GE. In addition, a top cover pattern CP can be formed to cover the top surface of each of the gate electrodes GE.

[0199] For example, forming the gate electrode GE may include forming a sacrificial pattern across a first active pattern FN1 and a second active pattern FN2; forming gate spacers GS on both sides of the sacrificial pattern; and replacing the sacrificial pattern with the gate electrode GE.

[0200] The gate electrode GE may be formed or comprised of a doped semiconductor material, a conductive metal nitride, or a metal. The gate insulating pattern GI may be formed or comprised of a silicon oxide layer, a silicon oxynitride layer, or a high-dielectric-constant material, wherein the dielectric constant of the high-dielectric-constant material is lower than that of silicon oxide. Each of the top cover pattern CP and the gate spacer GS may be formed or comprised of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0201] The source / drain region SD can be formed on the upper portion of the first active pattern FN1 and the second active pattern FN2 or in the upper portion of the first active pattern FN1 and the second active pattern FN2. The source / drain region SD on the PMOSFET region PR can be doped with p-type impurities, while the source / drain region SD on the NMOSFET region NR can be doped with n-type impurities.

[0202] In an exemplary embodiment of the present invention, the source / drain region SD can be an epitaxial pattern formed using a selective epitaxial growth process. For example, forming the source / drain region SD may include: partially recessing a first active pattern FN1 and a second active pattern FN2 on both sides of each of the gate electrodes GE; and performing an epitaxial growth process to form the source / drain region SD in the recessed regions of the first active pattern FN1 and the second active pattern FN2. The epitaxial growth process can be performed using a semiconductor material different from that of the substrate 100. For example, the source / drain region SD may be constituted or comprised of a semiconductor material having a lattice constant different from (e.g., greater than or less than) that of the substrate 100. Since the source / drain region SD is constituted of a semiconductor material different from that of the substrate 100, compressive or tensile stress can be applied to the channel region AF therebetween.

[0203] Next, a first interlayer insulating layer 110 may be formed to cover the source / drain region SD and the gate electrode GE. The first interlayer insulating layer 110 may be formed of or contain a silicon oxide layer or a silicon oxynitride layer.

[0204] refer to Figure 23 and 24A Up to 24C, the lower conductive structure TS can be formed on the source / drain regions SD of the PMOSFET region PR and the NMOSFET region NR. Each of the lower conductive structures TS may include at least a portion extending in the first direction D1 or may have a linear or strip structure. In addition, a portion of each of the lower conductive structures TS may be located on a second device isolation pattern ST2, which is adjacent to the PMOSFET region PR or the NMOSFET region NR. The lower conductive structure TS can be formed to have a top surface that is substantially coplanar with the top surface of the first interlayer insulating layer 110.

[0205] For example, the formation of the lower conductive structure TS may include: patterning a first interlayer insulating layer 110 to form a hole exposing the source / drain region SD; and filling the hole with a conductive material. The upper portion of the source / drain region SD may be etched or removed during hole formation. The lower conductive structure TS may be composed of or contain doped semiconductor material, conductive metal nitride, metal, or metal silicide.

[0206] refer to Figure 25 and 26A At 26C, a second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110. The second interlayer insulating layer 120 may be composed of a silicon oxide layer or a silicon oxynitride layer.

[0207] A first photoresist pattern 125 may be formed on the second interlayer insulating layer 120. The first photoresist pattern 125 may include, according to Figure 13 The opening formed by the first connection pattern Moa. For example, the formation of the first photoresist pattern 125 may include: forming a first photoresist layer on the second interlayer insulating layer 120; and subsequently using a photoresist-based... Figure 13 The first photomask fabricated by the first connection pattern M0a performs exposure and development processes on the first photoresist layer (e.g., see...). Figure 2 Steps S140 and S150).

[0208] The second interlayer insulating layer 120 can be patterned by using the first photoresist pattern 125 as an etching mask to form a connection hole MoaH. The connection hole MoaH can be formed to partially (e.g., incompletely) penetrate the second interlayer insulating layer 120. In other words, the bottom of the connection hole MoaH can be higher than the top surfaces of the lower conductive structure TS and the gate electrode GE. Therefore, the connection hole MoaH does not expose the top surfaces of the lower conductive structure TS and the gate electrode GE.

[0209] refer to Figure 27 and 28A At step 28D, the first photoresist pattern 125 can be selectively removed. Thereafter, a first mask layer 140 can be formed on the second interlayer insulating layer 120. The first mask layer 140 can be formed to completely fill the connection via MoaH.

[0210] The second photoresist pattern 145 may be formed on the first mask layer 140. The second photoresist pattern 145 may include, according to Figure 13 The opening is formed by the first active contact pattern CAa and the second active contact pattern CAb. For example, the formation of the second photoresist pattern 145 may include: forming a second photoresist layer on the first mask layer 140; and subsequently using a photoresist layer based on... Figure 13 The exposure and development process is performed on the second photomask, which is made of the first active contact pattern CAa and the second active contact pattern CAb, on the second photoresist layer.

[0211] The first mask layer 140 and the second interlayer insulating layer 120 can be sequentially patterned by using the second photoresist pattern 145 as an etching mask to form the first active via CAaH and the second active via CAbH. The first active via CAaH can be respectively based on... Figure 13 The first active contact pattern CAa forms the hole pattern, and the second active hole CAbH can be respectively based on... Figure 13 The second active contact pattern CAb forms the hole pattern.

[0212] A first active via CAaH and a second active via CAbH can be formed to completely penetrate the second interlayer insulating layer 120. In other words, a first active via CAaH and a second active via CAbH can be formed to expose the top surface of the lower conductive structure TS. When viewed in a plan view, each of the second active vias CAbH can overlap with a corresponding portion of a connecting via MOaH. Each of the second active vias CAbH can be combined with each of the connecting vias MOaH to form a single connecting via.

[0213] Return to reference Figure 18A If misalignment occurs during the formation of the second active aperture CAbH, then the vertical extension aperture can be formed in the area overlapping with both the second active aperture CAbH and the connecting aperture MoaH. In subsequent steps, the vertical extension aperture can be used to form the first vertical extension portion VP1, such as... Figure 18A As shown in the diagram. Due to the process used to form the connection hole MoaH, a portion of the second interlayer insulating layer 120 can be thinner than other portions, and thus a vertically extending hole can be formed by the process used to form the second active hole CAbH.

[0214] As another example, if... Figure 18B As shown, the second active aperture CAbH is formed to be wider than the lower conductive structure TS in the second direction D2. Therefore, a vertical extension aperture can be formed in the region overlapping with both the second active aperture CAbH and the connecting aperture MoaH. In subsequent steps, the vertical extension aperture can be used to form the first vertical extension portion VP1, as shown. Figure 18B As shown in the image.

[0215] refer to Figure 29 and 30A At step 30E, the second photoresist pattern 145 can be selectively removed. Next, a second mask layer 150 can be formed on the first mask layer 140. The second mask layer 150 can be formed to fill the entire area of ​​the first active via CAaH and the second active via CAbH.

[0216] The third photoresist pattern 155 may be formed on the second mask layer 150. The third photoresist pattern 155 may include, according to Figure 13 The first gate contact pattern CBa forms an opening. For example, the formation of the third photoresist pattern 155 may include: forming a third photoresist layer on the second mask layer 150; and subsequently using a photoresist layer based on... Figure 13 The third photomask, fabricated from the first gate contact pattern CBa, performs the exposure and development process on the third photoresist layer.

[0217] A gate hole CBaH can be formed by sequentially patterning the second mask layer 150, the first mask layer 140, and the second interlayer insulating layer 120 using the third photoresist pattern 155 as an etching mask.

[0218] A gate via CBaH can be formed to completely penetrate the second interlayer insulating layer 120. Additionally, a gate via CBaH can be formed to penetrate the upper portion of the first interlayer insulating layer 110. In other words, a gate via CBaH can be formed to expose the top surface of the gate electrode GE.

[0219] In an exemplary embodiment of the concept of the present invention, referencing... Figure 18C If misalignment occurs during the formation of the gate via CBaH, or if the gate via CBaH is formed with an increased width in the second direction D2, then a vertical extension via can be formed in the region overlapping both the gate via CBaH and the connection via MoaH. In subsequent steps, the vertical extension via can be used to form a second vertical extension portion VP2, such as... Figure 18C As shown in the image.

[0220] refer to Figure 31 and 32A At 32E, the third photoresist pattern 155, the second mask layer 150, and the first mask layer 140 can be removed. Next, conductive structures AC, GC, and CP1 can be formed by filling the connection vias MoaH, the first active via CAaH, the second active via CAbH, and the gate via CBaH with conductive materials.

[0221] For example, an active contact AC can be formed in a first active via CAaH. A gate contact GC can be formed in a gate via CBaH. A first conductive structure CP1 can be formed in a connection via MOaH and a second active via CAbH, respectively. For example, the first conductive structure CP1 can be formed by filling the connection via with a conductive material, the connection via being formed by the connection via MOaH and the second active via CAbH. In an exemplary embodiment of the present invention, the same process can be used to form the active contact AC, the gate contact GC, and the first conductive structure CP1 in substantially the same amount of time.

[0222] The barrier layer pattern BL can be formed between the second interlayer insulating layer 120 and the active contact AC, between the second interlayer insulating layer 120 and the gate contact GC, and between the second interlayer insulating layer 120 and the first conductive structure CP1.

[0223] For example, the formation of conductive structures AC, GC, and CP1, as well as the barrier layer pattern BL, may include: conformally forming a barrier layer to cover the connection via MoaH, the first active via CAaH, the second active via CAbH, and the gate via CBaH; forming a conductive layer to completely fill the connection via MoaH, the first active via CAaH, the second active via CAbH, and the gate via CBaH; and performing a planarization process on the conductive layer and the barrier layer to expose the second interlayer insulating layer 120. The conductive layer may contain a conductive metal nitride or a metal, and the barrier layer may contain a metal nitride capable of preventing the diffusion of metal elements.

[0224] Return to reference Figure 16 and 17A In 17E, a third interlayer insulating layer 130 may be formed on the second interlayer insulating layer 120. The third interlayer insulating layer 130 may be formed of or contain a silicon oxide layer or a silicon oxynitride layer. First electrical interconnects PL1 and PL2, as well as first interconnects ML1 and ML2, may be formed in the third interlayer insulating layer 130. The first electrical interconnects PL1 and PL2, as well as the first interconnects ML1 and ML2, may be formed using methods similar to those used to form conductive structures AC, GC, and CP1.

[0225] Figure 33 This is a plan view illustrating an exemplary embodiment of a semiconductor device manufactured based on a standard cell layout according to the concept of the present invention. In this embodiment, an exemplary description is provided. Figure 13 The third standard cell layout STD3 is used, but the concept of the present invention is not limited thereto. In the following description of embodiments of the present invention, for the sake of brevity, the previously referenced documents will not be described in further detail. Figure 13 The described element.

[0226] refer to Figure 33 ,and Figure 13 Unlike the previous embodiment, the lower conductive pattern LP may not be included. Instead of the lower conductive pattern, the thirteenth to eighteenth active contact patterns CAm, CAn, CAo, CAp, CAq, and CAr may be additionally arranged. Each of the thirteenth to eighteenth active contact patterns CAm, CAn, CAo, CAp, CAq, and CAr may overlap with or be connected to one of the PMOSFET region PR or NMOSFET region NR.

[0227] The fifteenth active contact pattern Cao may be spaced apart from the seventh connection pattern Mog (e.g., not overlapping). The seventeenth active contact pattern CAq may be spaced apart from the sixth connection pattern Mof (e.g., not overlapping). The eighteenth active contact pattern CAr may be spaced apart from the eighth connection pattern Moh (e.g., not overlapping).

[0228] Figure 34 This is a plan view illustrating an exemplary semiconductor device according to the concept of the present invention. Figures 35A to 35C They are along Figure 34 Cross-sectional views taken from lines A-A', B-B', and C-C'. For example, Figure 34 and Figures 35A to 35C Showing will be based on Figure 33 Examples of semiconductor devices fabricated using a standard cell layout. In the following description of embodiments of the invention, for the sake of brevity, further details of the previously referenced documents are omitted. Figure 16 and 17A The elements described up to 17R.

[0229] refer to Figure 34 and 35A Up to 35°C, with Figure 16 and 17A Unlike the previous embodiment of 17R, it may not include the lower conductive structure TS. Instead of the lower conductive structure, the first to sixth active contacts AC1-AC6 can be separately disposed. The first to sixth active contacts AC1-AC6 can be respectively composed of… Figure 33 The structure defined by the thirteenth to eighteenth active contact patterns CAm, CAn, CAo, CAp, CAq and CAr.

[0230] Adjacent source / drain regions SD can be merged to form a single unit. Each of the first to sixth active contacts AC1-AC6 can contact at least a portion of the merged source / drain regions SD. Since the merged source / drain regions SD are connected to form a single unit, it is not necessary for each of the first to sixth active contacts AC1-AC6 to completely cover the merged source / drain regions SD. Furthermore, similar to... Figure 4 In the previous embodiment, the second portion P2 of each of the fifth conductive structure CP5, the seventh conductive structure CP7 and the eighth conductive structure CP8 may also contact the merged source / drain region SD.

[0231] For example, refer to Figure 35B The third active contact AC3 can contact a portion of the merged source / drain region SD. Therefore, the first portion P1 of the seventh conductive structure CP7 can be positioned across the merged source / drain region SD without short-circuiting the third active contact AC3.

[0232] The first to sixth active contacts AC1-AC6 may have a bottom surface lower than the bottom surface of the gate contact GC and the bottom surface of the third portion P3 of the sixth conductive structure CP6. The bottom surface of the second portion P2 of the fifth conductive structure CP5, the seventh conductive structure CP7, and the eighth conductive structure CP8 may be lower than the bottom surface of the gate contact GC and the bottom surface of the third portion P3 of the sixth conductive structure CP6.

[0233] According to exemplary embodiments of the present invention, a semiconductor device may include a conductive structure electrically connected to an impurity region or a gate electrode. The conductive structure may include horizontally extending portions, and thus interconnects can be freely disposed on the conductive structure. This results in a semiconductor device with reliable operating characteristics.

[0234] Although the concepts of the invention have been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the concepts of the invention as defined by the appended claims.

Claims

1. A semiconductor device, characterized in that, include: A first active pattern protrudes above the substrate, and the upper part of the first active pattern includes a first channel region and a first source / drain region connected to the first channel region. The device isolation pattern is on the lower sidewall of the first active pattern; The first gate electrode is located on the first channel region of the first active pattern; A first interlayer insulating layer covers the first source / drain region and the first gate electrode; A first lower conductive structure is provided in the first interlayer insulating layer and is directly electrically connected to the first source / drain region. The first lower conductive structure has a top surface that is coplanar with the top surface of the first interlayer insulating layer. A first conductive structure, on a first lower conductive structure, includes a first portion and a second portion connected to each other to form a single body, the second portion extending from the first portion toward and connecting to the first lower conductive structure. Interconnecting lines on the first conductive structure; as well as A through-hole is located between the interconnect and the first portion, and connects the interconnect and the first conductive structure. The first conductive structure further includes a first vertically extending portion that covers the upper sidewall of the first lower conductive structure, and the bottom surface of the first vertically extending portion is covered by the first interlayer insulating layer. The first conductive structure further includes a third portion extending from the first portion toward and connected to the first gate electrode, and a second vertically extending portion covering the upper portion of the sidewall of the first gate electrode.

2. The semiconductor device according to claim 1, characterized in that, The third portion is disposed on the first active pattern.

3. The semiconductor device according to claim 1, characterized in that, Further includes: A pair of gate spacers on opposite sidewalls of the first gate electrode; and A gate insulating pattern is formed between the first gate electrode and the first channel region. The gate insulating pattern includes: The horizontal portion is located between the bottom surface of the first gate electrode and the top surface of the first channel region; as well as A pair of vertical portions are located between the opposite sidewalls of the first gate electrode and the pair of gate spacers, respectively.

4. The semiconductor device according to claim 3, characterized in that, Further includes a gate cap pattern on the top surface of the first gate electrode.

5. The semiconductor device according to claim 1, characterized in that, The first conductive structure contains aluminum or tungsten.

6. The semiconductor device according to claim 1, characterized in that, The upper portion of the first active pattern further includes a second channel region and a second source / drain region connected to the second channel region. The semiconductor device further includes: The second gate electrode is located on the second channel region of the first active pattern; and The second lower conductive structure is electrically connected to the second source / drain region. The first conductive structure further includes a fourth portion extending from the first portion toward and connecting to the second lower conductive structure. The first portion extends from the second portion over at least one of the first gate electrode and the second gate electrode to the fourth portion.

7. The semiconductor device according to claim 6, characterized in that, The first portion extends over and across the first gate electrode and the second gate electrode.

8. The semiconductor device according to claim 1, characterized in that, The bottom surface of the first vertical extension is lower than the top surface of the first lower conductive structure.

9. The semiconductor device according to claim 1, characterized in that, The upper portion of the first active pattern further includes a second channel region. The semiconductor device further includes: The second gate electrode is located on the second channel region of the first active pattern; and The second conductive structure is located on both the first gate electrode and the second gate electrode. The second conductive structure includes a first part, a second part, and a third part that are connected to each other to form a single main body. The second portion extends from the first portion toward the first gate electrode and connects to the first gate electrode, and The third portion extends from the first portion toward the second gate electrode and is connected to the second gate electrode.

10. The semiconductor device according to claim 1, characterized in that, Further includes: A second active pattern protrudes above the substrate, the second active pattern being spaced apart from the first active pattern, and the upper part of the second active pattern including a second source / drain region. as well as The second lower conductive structure is electrically connected to the second source / drain region. The first conductive structure further includes a fourth portion extending from the first portion toward the second lower conductive structure and connected to the second lower conductive structure. The first portion extends over and across the first active pattern and the second active pattern.

11. The semiconductor device according to claim 1, characterized in that, The top surface of the first lower conductive structure is higher than the top surface of the first gate electrode.

12. The semiconductor device according to claim 1, characterized in that, The bottom surface of the second portion is higher than the top surface of the first gate electrode.

13. The semiconductor device according to claim 1, characterized in that, The width of the second part is greater than the width of the first lower conductive structure.

14. The semiconductor device according to claim 1, characterized in that, The first part has a flat plate structure.

15. A semiconductor device, characterized in that, include: Substrate; First power interconnect and second power interconnect; as well as The first standard unit is located between the first power interconnect and the second power interconnect. The first standard unit includes: The first fin structure includes a first channel region and a first source / drain region connected to the first channel region; The device isolation pattern is on the lower sidewall of the first fin-shaped structure; The first gate electrode is located on the first channel region of the first fin structure; A first interlayer insulating layer covers the first source / drain region and the first gate electrode; A first lower conductive structure is provided in the first interlayer insulating layer and is directly electrically connected to the first source / drain region. The first lower conductive structure has a top surface that is coplanar with the top surface of the first interlayer insulating layer. A first conductive structure, on a first lower conductive structure, includes a first portion and a second portion connected to each other to form a single body, the second portion extending from the first portion toward and connecting to the first lower conductive structure. Interconnects, on the first conductive structure; and A through-hole is located between the interconnect and the first portion, and connects the interconnect and the first conductive structure. The first conductive structure further includes a first vertically extending portion that covers the upper sidewall of the first lower conductive structure, and the bottom surface of the first vertically extending portion is covered by the first interlayer insulating layer. The first conductive structure further includes a third portion extending from the first portion toward and connected to the first gate electrode, and a second vertically extending portion covering the upper portion of the sidewall of the first gate electrode.

16. The semiconductor device according to claim 15, characterized in that, Further includes: The second standard unit is located between the first power interconnect and the second power interconnect; as well as The virtual gate electrode is located at the boundary between the first standard cell and the second standard cell. The first portion extends from the first standard cell to the second standard cell across the virtual gate electrode.

17. The semiconductor device according to claim 15, characterized in that, The third part is disposed on the first fin structure.

18. The semiconductor device according to claim 15, characterized in that, The first fin structure further includes a second channel region and a second source / drain region connected to the second channel region. The first standard unit further includes: The second gate electrode is located on the second channel region of the first fin structure; and The second lower conductive structure is electrically connected to the second source / drain region. The first conductive structure further includes a fourth portion extending from the first portion toward and connecting to the second lower conductive structure. The first portion extends from the second portion over at least one of the first gate electrode and the second gate electrode to the fourth portion.

19. The semiconductor device according to claim 18, characterized in that, The first portion extends over and across the first gate electrode and the second gate electrode.

20. The semiconductor device according to claim 15, characterized in that, The bottom surface of the first vertical extension is lower than the top surface of the first lower conductive structure.

21. The semiconductor device according to claim 15, characterized in that, The first fin-shaped structure further includes a second channel region. The first standard unit further includes: The second gate electrode is located on the second channel region of the first fin structure; and The second conductive structure is located on both the first gate electrode and the second gate electrode. The second conductive structure includes a first part, a second part, and a third part that are connected to each other to form a single main body. The second portion extends from the first portion toward the first gate electrode and connects to the first gate electrode, and The third portion extends from the first portion toward the second gate electrode and is connected to the second gate electrode.

22. The semiconductor device according to claim 15, characterized in that, The first standard unit further includes: A second fin-shaped structure, spaced apart from the first fin-shaped structure, includes a second source / drain region; and The second lower conductive structure is electrically connected to the second source / drain region. The first conductive structure further includes a fourth portion extending from the first portion toward the second lower conductive structure and connected to the second lower conductive structure. The first portion extends above and across the first and second fin structures.

23. The semiconductor device according to claim 15, characterized in that, The top surface of the first lower conductive structure is higher than the top surface of the first gate electrode.

24. The semiconductor device according to claim 15, characterized in that, The bottom surface of the second portion is higher than the top surface of the first gate electrode.

25. The semiconductor device according to claim 15, characterized in that, The width of the second part is greater than the width of the first lower conductive structure.

26. The semiconductor device according to claim 15, characterized in that, The first part has a flat plate structure.

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