Semiconductor structure fabrication methods and semiconductor structures

Abstract

This disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself, relating to the field of semiconductor technology. The method for fabricating the semiconductor structure includes: providing a substrate; forming a first dielectric layer with grooves, the grooves including a first groove and a second groove with a first difference in inner diameter; forming an initial filling layer within the first and second grooves, the first groove forming a third groove, the second groove forming a fourth groove, and the inner diameters of the third and fourth grooves having a second difference less than the first difference; processing the initial filling layer to form a filling layer; and forming a plurality of etching openings with preset inner diameter differences on the substrate surface. This disclosure utilizes the initial filling layer to repair the spacing between adjacent grooves and processes the initial filling layer, thereby ensuring that any subsequently formed etching openings can meet the etching process requirements, effectively improving the uniformity and electrical properties of local critical dimensions of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory that allows for high-speed, random writing and reading of data and is widely used in data storage devices.

[0003] With the continuous development of dynamic random access memory (DRAM) manufacturing technology, the feature dimensions of semiconductor structures in integrated circuits, such as the critical dimension (CD) of the active region, are also constantly shrinking. When manufacturing semiconductor structures with even smaller critical dimensions, excessively low local critical dimension uniformity (LCDU) can adversely affect the electrical performance of the semiconductor structure. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself.

[0006] The first aspect of this disclosure provides a method for fabricating a semiconductor structure, the method comprising:

[0007] Provide a base;

[0008] A first dielectric layer is formed on the substrate, the first dielectric layer having an array of grooves, the grooves including a first groove and a second groove, and there is a first difference between the inner diameter of the first groove and the second groove;

[0009] An initial filling layer is formed, which covers the sidewalls and bottom wall of the first groove and the sidewalls and bottom wall of the second groove. The initial filling layer in the first groove forms a third groove, and the initial filling layer in the second groove forms a fourth groove. There is a second difference between the inner diameter of the third groove and the fourth groove, and the second difference is smaller than the first difference.

[0010] The initial fill layer is processed to form a fill layer;

[0011] The filling layer and / or the first dielectric layer are etched to form a plurality of etched openings with a preset difference inner diameter on the substrate surface.

[0012] According to some embodiments of this disclosure, the groove has a target size, the inner diameter of the first groove is smaller than the target size, and the inner diameter of the second groove is larger than the target size;

[0013] The target size is any value within the range of 30 to 60 nm;

[0014] The maximum difference between the inner diameters of the first groove and the second groove is 6 nm.

[0015] According to some embodiments of this disclosure, processing the initial fill layer to form a fill layer includes:

[0016] Ion implantation is performed on the initial filling layer;

[0017] The initial filling layer after ion implantation is subjected to rapid thermal treatment to form the filling layer.

[0018] According to some embodiments of this disclosure, ion implantation is performed on the initial filling layer, including:

[0019] The initial filling layer is ion implanted using group III or group V elements.

[0020] According to some embodiments of this disclosure, the ion implantation dose is 10 14 ~10 15 / cm 2 The ion implantation energy ranges from 10 keV to 40 keV.

[0021] According to some embodiments of this disclosure, forming an initial fill layer includes:

[0022] The initial filling layer is formed in the first groove and the second groove using a chemical vapor deposition process or a physical vapor deposition process.

[0023] According to some embodiments of this disclosure, the thickness of the initial filling layer is 5 nm to 8 nm.

[0024] According to some embodiments of this disclosure, the material of the first dielectric layer includes one of silicon oxynitride, silicon nitride, silicon oxide, silicon carbide, and spin-coated hard mask layer.

[0025] According to some embodiments of this disclosure, the first dielectric layer comprises undoped polysilicon.

[0026] According to some embodiments of this disclosure, a substrate is provided, comprising:

[0027] Provide substrate;

[0028] A support structure is formed on the substrate;

[0029] The support structure includes:

[0030] An isolation layer, a first sacrificial layer, at least one support layer, a second sacrificial layer, and an etching layer are formed sequentially on the substrate.

[0031] Each of the support layers comprises an alternately arranged first support layer and a spin-coated hard mask layer.

[0032] According to some embodiments of this disclosure, a first dielectric layer is formed on the substrate, the first dielectric layer having an array of grooves, including:

[0033] The first dielectric layer is formed on the etched layer;

[0034] A first mask layer is formed on the first dielectric layer;

[0035] A first mask pattern is provided, and based on the first mask pattern, a portion of the first mask layer is removed to form a plurality of initial grooves on the first mask layer;

[0036] Based on the initial groove, a portion of the first dielectric layer is removed using the remaining first mask layer as a mask to form the groove on the first dielectric layer.

[0037] According to some embodiments of this disclosure, the method for fabricating the semiconductor structure further includes:

[0038] Based on the etching opening, a portion of the etched layer is removed to form a plurality of first through holes spaced apart along the first direction within the etched layer.

[0039] According to some embodiments of this disclosure, the method for fabricating the semiconductor structure further includes:

[0040] Based on the first through-hole, a portion of the second sacrificial layer is removed to form a plurality of second through-holes spaced apart along the first direction within the second sacrificial layer.

[0041] According to some embodiments of this disclosure, the method for fabricating the semiconductor structure further includes:

[0042] Based on the second through hole, a plurality of contact holes spaced apart along the first direction are formed within the support structure.

[0043] A second aspect of this disclosure provides a semiconductor structure, which is fabricated by the method for fabricating the semiconductor structure in any of the above embodiments.

[0044] In the semiconductor structure fabrication method and semiconductor structure provided in this disclosure, the initial filling layer is used to repair the spacing between adjacent grooves, and the initial filling layer is processed so that any subsequent etched opening can meet the etching process requirements, effectively improving the uniformity and electrical properties of local critical dimensions of the semiconductor structure.

[0045] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0046] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0047] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0048] Figure 2 This is a schematic diagram illustrating the formation of a first dielectric layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0049] Figure 3 This is a top view of a first mask pattern in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0050] Figure 4 This is a schematic diagram illustrating the formation of a fifth and a sixth groove in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0051] Figure 5 This is a schematic diagram illustrating the formation of a first groove and a second groove in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0052] Figure 6 This is a schematic diagram illustrating the formation of an initial filling layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0053] Figure 7 This is a schematic diagram illustrating ion implantation of an initial filling layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0054] Figure 8 This is a schematic diagram illustrating the rapid thermal processing of the initial filling layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0055] Figure 9This is a schematic diagram illustrating the formation of etched openings in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0056] Figure 10 yes Figure 9 Top view.

[0057] Figure 11 This is a schematic diagram illustrating the formation of a first via in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0058] Figure 12 This is a schematic diagram illustrating the formation of a second via in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0059] Figure 13 This is a schematic diagram illustrating the formation of contact holes in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0060] Figure label:

[0061] 10. Substrate; 20. First dielectric layer;

[0062] 11. Substrate; 12. Support structure;

[0063] 30. Mask structure; 31. Groove;

[0064] 40. First groove; 50. Second groove;

[0065] 60. Fill layer; 61. Initial fill layer;

[0066] 70. Third groove; 80. Fourth groove;

[0067] 90. Etched opening; 100. First mask layer;

[0068] 101. First mask pattern; 102. Initial groove;

[0069] 110. Fifth groove; 111. Isolation structure;

[0070] 112. Active region; 120. Sixth groove;

[0071] 121. Isolation layer; 122. First sacrificial layer;

[0072] 123. Support layer; 124. Second sacrificial layer;

[0073] 125. Etched layer; 130. First through-hole;

[0074] 140. Second through hole; 150. Contact hole;

[0075] 1231, First support layer; 1232, Spin-coated hard mask layer. Detailed Implementation

[0076] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0077] Dynamic Random Access Memory (DRAM) is a semiconductor memory that allows for high-speed, random writing and reading of data and is widely used in data storage devices.

[0078] With the continuous development of Dynamic Random Access Memory (DRAM) manufacturing technology, the feature dimensions of semiconductor structures in integrated circuits, such as the critical dimension (CD) of the active region, are constantly shrinking. However, when manufacturing semiconductor structures with even smaller critical dimensions, the local critical dimension uniformity (LCDU) is too low, leading to inconsistencies in the local critical dimensions between subsequently formed semiconductor structures. Specifically, during the formation of vias (which can form contact structures or capacitor structures) in semiconductor structures, the mask patterns formed in the photomask are not entirely uniform in size. While the size distribution is normally distributed due to limitations in the photomask fabrication process, and most mask holes in the mask pattern meet the requirements of subsequent etching processes, some mask holes have inner diameters or widths that differ significantly from the target dimensions. These mask holes may cause overlaps between subsequently formed semiconductor structures (such as bit line contacts), thus adversely affecting the electrical performance of the semiconductor structure.

[0079] To address one of the aforementioned technical problems, this disclosure provides a method for fabricating a semiconductor structure in exemplary embodiments, which will be described below in conjunction with... Figures 1-13 The methods for fabricating semiconductor structures are introduced.

[0080] This embodiment does not limit the semiconductor structure. The following description will take the bit line contact structure in dynamic random access memory (DRAM) as an example. However, this embodiment is not limited to this. The semiconductor structure can also be a capacitor contact structure, an electrode contact, a source contact, etc.

[0081] like Figure 1As shown, an exemplary embodiment of this disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:

[0082] Step S100: Provide a substrate.

[0083] Step S200: A first dielectric layer is formed on the substrate. The dielectric layer has an array of grooves, including a first groove and a second groove. There is a first difference between the inner diameter of the first groove and the second groove.

[0084] Step S300: An initial filling layer is formed, which covers the bottom and side walls of the first groove and the side and bottom walls of the second groove. The first groove forms a third groove, and the second groove forms a fourth groove. There is a second difference between the inner diameters of the third groove and the fourth groove, which is smaller than the first difference.

[0085] Step S400: Process the initial fill layer to form a fill layer.

[0086] Step S500: Etch the filling layer and / or the first dielectric layer to form a plurality of etched openings with preset differential inner diameters on the substrate surface.

[0087] Reference Figure 2 As shown, in step S100, the substrate 10 serves as a support component for dynamic random access memory (DRAM), supporting other components disposed thereon. The substrate 10 can be made of a semiconductor material, which can be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carb compounds. In this embodiment, silicon is used as the substrate 10. The use of silicon as the substrate 10 in this embodiment is for the convenience of those skilled in the art in understanding the subsequent formation method and does not constitute a limitation. In practical applications, a suitable substrate material can be selected according to requirements.

[0088] Reference Figure 2 As shown, in step S200, a first dielectric layer 20 can be deposited on the substrate 10 using atomic layer deposition, physical vapor deposition, or chemical vapor deposition. The material of the first dielectric layer 20 can include, but is not limited to, silicon oxynitride or undoped polysilicon. To form other semiconductor structures (such as bit line structures, word line structures, etc.) on the first dielectric layer 20, openings (not shown in the figure) need to be formed on the first dielectric layer 20. For example, a mask layer (not shown in the figure) and photoresist (not shown in the figure) are deposited on the first dielectric layer 20. Then, an etching process is used to form multiple arrayed openings on the first dielectric layer 20, wherein the first dielectric layer 20 between adjacent openings forms a mask structure 30.

[0089] Reference Figure 5 and combined Figure 4 As shown, the first dielectric layer 20 has an array of grooves 31. Specifically, the groove 31 is the area between two adjacent mask structures 30 in the same row and / or column. The groove 31 includes a first groove 40 and a second groove 50. The first groove 40 can be the area between two partially adjacent mask structures 30 in the same row and / or column, and the second groove 50 can be the area between two partially adjacent mask structures 30 in the same row and / or column, wherein the first groove 40 and the second groove 50 are distributed in different areas on the first dielectric layer 20.

[0090] Among them, multiple mask structures 30 in the same row are defined to be spaced apart along the first direction X, as shown in the reference. Figure 2 Taking the directions shown in the diagram as an example, the first direction is... Figure 2 In the X direction, that is, the first direction X is parallel to the front side of the substrate 10. Along the first direction X, there can be multiple first grooves 40 and multiple second grooves 50. During the formation of the mask structure 30, the dimensions of each mask structure 30 are different along the first direction X; therefore, the inner diameter of the first groove 40 is different from the inner diameter of the second groove 50. The inner diameter of the first groove 40 can be larger or smaller than the inner diameter of the second groove 50.

[0091] The inner diameter can be the measured dimension of the groove 31 in the same direction, and is not limited to... Figure 3 The inner diameter of a groove 31 is the diameter obtained by measuring all grooves 31 in the same direction, specifically the first direction X and the second direction X. It should be noted that the second direction X is... Figure 3 In the Y direction, that is, the second direction Y is perpendicular to the first direction X, and the second direction Y is parallel to the left or right side of the base 10.

[0092] Wherein, the inner diameter of the first groove 40 meets the requirements of the subsequent etching process; or, the inner diameter of the second groove 50 meets the requirements of the subsequent etching process. In this embodiment and the following embodiments, the example is taken where the inner diameter of the second groove 50 is larger than the inner diameter of the first groove 40, and there is a first difference between the inner diameter of the second groove 50 and the inner diameter of the first groove 40.

[0093] In other embodiments, refer to Figure 3 As shown, along the first direction X, the first dielectric layer 20 may also include a third initial groove, a fourth initial groove, etc., whose inner diameter is different from that of the first groove 40 and the second groove 50.

[0094] Reference Figure 6As shown, in step S300, an initial filling layer 61 can be deposited in the first groove 40 and the second groove 50 using atomic layer deposition, chemical vapor deposition, or physical vapor deposition. The initial filling layer 61 is deposited on the bottom surface and sidewalls of the first groove 40 and the second groove 50, and also covers the top surface of the mask structure 30.

[0095] It should be noted that during the formation of the initial filling layer 61 using the above deposition process, the deposition parameters (such as deposition rate, deposition time, particle deposition energy, etc.) of the deposition material used to form the initial filling layer 61 can be controlled so that the deposition material used to form the initial filling layer 61 will form a part of the initial filling layer 61 with a thicker deposition thickness on the bottom wall and side wall of the second groove 50, while a part of the initial filling layer 61 with a thinner deposition thickness will be formed on the bottom wall and side wall of the first groove 40.

[0096] After the initial filling layer 61 is deposited and formed, the initial filling layer 61 in the first groove 40 forms the third groove 70, and the initial filling layer 61 in the second groove 50 forms the fourth groove 80.

[0097] Along the first direction X, there is a second difference between the inner diameter of the third groove 70 and the inner diameter of the fourth groove 80, wherein the second difference is less than the first difference. After the third groove 70 and the fourth groove 80 are formed, along the first direction X, the inner diameter of the fourth groove 80 may be greater than, or less than or equal to, the inner diameter of the third groove 70.

[0098] Reference Figure 7 and Figure 8 As shown, in step S400, the initial filling layer 61 is processed to form the filling layer 60, thereby increasing the rate of subsequent etching and reducing the production cycle of the semiconductor structure.

[0099] Reference Figure 9 and Figure 10 As shown, in step S500, an etching process is used to etch the filling layer 60 and / or the first dielectric layer 20, thereby forming a plurality of etching openings 90 with preset difference inner diameters on the surface of the substrate 10. It should be noted that the preset difference can be a difference size that meets the requirements of subsequent etching processes or is within the error operating range, and the preset difference can be 1 nm.

[0100] In this embodiment, the initial filling layer is used to repair the gap between adjacent grooves, and the initial filling layer is processed so that any etch opening formed subsequently can meet the etching process requirements, effectively improving the local critical dimension uniformity and electrical properties of the semiconductor structure.

[0101] Reference Figure 3As shown, in some embodiments, the groove 31 has a target size, which can be understood as a size that meets the requirements of the etching process. The inner diameter of the first groove 40 is smaller than the target size, and the inner diameter of the second groove 50 is larger than the target size.

[0102] The target size can be any value within the range of 30nm to 60nm. For example, the target size can be 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, etc. The maximum difference between the inner diameters of the first groove 40 and the second groove 50 is 6nm, which is the allowable difference in the photomask fabrication process. If the difference is greater than this, the fabricated photomask will not meet the requirements of subsequent processes due to the excessive difference in inner diameter.

[0103] Reference Figure 7 and Figure 8 As shown, in some embodiments, the initial fill layer 61 can be processed using the following method:

[0104] like Figure 7 As shown, ion implantation is performed on the initial filling layer 61. Group V elements can be selected for ion implantation of the initial filling layer 61. For example, phosphorus ions (P) or arsenic ions (As) from Group V can be selected. Alternatively, Group IV elements can be selected for ion implantation of the initial filling layer 61, such as germanium ions (Ge) from Group IV.

[0105] During the ion implantation process of the initial filling layer 61, the amount of ions implanted in the sidewalls and bottomwalls of the fourth groove 80 is greater than that in the sidewalls and bottomwalls of the third groove 70. That is, by selectively changing the amount of ions implanted at different locations and with different deposition thicknesses in the initial filling layer 61, the subsequent etching rate of the filling layer 60 at different locations and with different deposition thicknesses is affected. For example, in the subsequent etching process, using the same etching process parameters, the etching rate of the third groove 70 is 10% to 30% faster than that of the fourth groove 80, thereby effectively ensuring that the size of the formed etching opening 90 is within the preset difference range.

[0106] like Figure 8As shown, after the ion implantation process of the initial filling layer 61 is completed, the initial filling layer 61 is processed using Rapid Thermal Processing (RTP). RTP effectively activates the implanted ions in the initial filling layer 61. Specifically, the ion doping concentration in the fourth groove 80 is higher than that in the third groove 70, so that the etching rate of the fourth groove 80 is relatively slower and the etching rate of the third groove 70 is relatively faster during subsequent etching of the initial filling layer 61. During the etching process, by reasonably controlling parameters such as etching time and etching gas, the target size etching opening 90 with an inner diameter that meets the etching process requirements can be formed on the first dielectric layer 20 and / or the filling layer 60. This effectively improves the problem of low uniformity of local critical dimensions in the etching process of the prior art and enhances the electrical properties of the semiconductor structure.

[0107] Reference Figure 7 As shown, in some embodiments, to effectively improve the etching rate in subsequent semiconductor structures, group III elements can be used to ion implant the initial filling layer 61, such as boron ions (B) from group III elements. Alternatively, group V elements can be used to perform ion implantation on the initial filling layer 61, such as phosphorus ions (P) or arsenic ions (As) from group V elements. In one example, when ion implanting the initial filling layer 61, the ion implantation dose is 10. 14 ~10 15 / cm 2 The ion implantation energy ranges from 10 keV to 40 keV.

[0108] When the etching process parameters are 3-4 nm / min and the deposition thickness of the first dielectric layer 20 is 20-30 nm, boron ions (B) from group III elements can be selected.

[0109] When the etching process parameters are 4-5 nm / min and the deposition thickness of the first dielectric layer 20 is 25 nm-40 nm, arsenic ions (As) from group V elements can be selected.

[0110] When the etching process parameters are 4-5 nm / min and the deposition thickness of the first dielectric layer 20 is 30-50 nm, phosphorus ions (P) from group V elements can be selected.

[0111] It should be noted that after the ions of the aforementioned Group III or Group V elements are implanted into the initial filling layer 61, the amount of ions implanted in the sidewalls and bottomwalls of the fourth groove 80 is greater than the amount implanted in the sidewalls and bottomwalls of the third groove 70.

[0112] In this embodiment, group III or group V element ions are implanted into the initial filling layer. The amount of group III or group V element ions implanted at different locations in the initial filling layer 61 varies. Specifically, the amount of ion implanted in the region with a thicker deposition thickness (i.e., the bottom and sidewalls of the fourth groove 80) is greater than the amount of ion implanted in the region with a thinner deposition thickness (i.e., the bottom and sidewalls of the third groove 70). By selectively changing the amount of ion implanted at different locations and with different deposition thicknesses in the initial filling layer, it is convenient to influence the subsequent etching rate at different locations in the initial filling layer.

[0113] Reference Figure 6 As shown, in some embodiments, an initial filling layer 61 is formed in the first groove 40 and the second groove 50 using a chemical vapor deposition (CVD) or physical vapor deposition (PVD) process. The material of the initial filling layer 61 may include, but is not limited to, silicon oxide.

[0114] During the formation of the initial filling layer 61 through the aforementioned deposition process, and given the uneven coverage of the chemical vapor deposition or physical deposition process, the deposited material forms overhangs at the groove openings, with the smaller inner diameter groove openings preferentially closing. Since the inner diameter of the second groove 50 is larger than that of the first groove 40, the deposition thickness of the deposited material forming the initial filling layer 61 on the sidewalls and bottom wall of the second groove 50 is greater than that on the sidewalls and bottom wall of the first groove 40. Simultaneously, during the deposition of the initial filling layer 61, the difference between the inner diameter of the third groove 70 and the inner diameter of the fourth groove 80 can be reduced by controlling the deposition parameters (such as deposition rate, deposition time, particle deposition energy, etc.) of the deposited material used to form the initial filling layer 61.

[0115] After deposition, the initial filler layer 61 deposited on the top surface of the grinding mask structure 30 can be ground to remove the uneven thickness of the initial filler layer 61 at the openings of the first groove 40 and the second groove 50, ensuring that the opening of the first groove 40 is open and exposing the initial filler layer 61 located on the bottom and side walls of the first groove 40 and the second groove 50. At this time, the initial filler layer 61 is evenly distributed on the bottom and side walls of the first groove 40 and the second groove 50.

[0116] Reference Figure 6 As shown, in some embodiments, the thickness of the initial filling layer 61 is 5nm to 8nm, for example, the thickness of the initial filling layer 81 is 5nm, 5.5nm, 6nm, 6.5nm, 7nm, 7.5nm, 8nm, etc.

[0117] In this embodiment, an initial filling layer with a thickness of 5nm to 8nm is formed, and the ion types in group III or group V elements are matched. At the same time, by controlling the ion implantation amount, the thickness of the initial filling layer deposited on the bottom wall and side wall of the second groove 50 is greater than the thickness of the initial filling layer deposited on the bottom wall and side wall of the first groove 40, which facilitates the subsequent control of the etching rate of the formed third groove 70 and fourth groove 80.

[0118] Reference Figure 2 As shown, in some embodiments, the material of the first dielectric layer 20 may include, but is not limited to, silicon oxynitride, silicon oxide, silicon carbide, and spin-coated hard mask layers. In other embodiments, the material of the first dielectric layer 20 may also include undoped polysilicon. The first dielectric layer 20 is deposited from the above-described deposition materials, and the initial filler layer 61 formed on the first dielectric layer 20 may be deposited from silicon oxide. In other words, the first dielectric layer 20 and the initial filling layer 61 are deposited from different materials. During the chemical vapor deposition process, the material deposited at the step of the groove 31 is thicker than that at the bottom of the groove 31. Therefore, during the subsequent deposition of the initial filling layer 61, the opening of the first groove 40 with a smaller inner diameter will close preferentially, and the amount of material deposited in the initial filling layer 61 in the first groove 40 is less. On the other hand, there is more material deposited in the second groove 50 with a larger inner diameter, and the amount of material deposited in the initial filling layer 61 is more. Therefore, the thickness of the initial filling layer 61 deposited in the second groove 50 with a larger inner diameter is greater than the thickness of the initial filling layer 61 deposited in the first groove 40 with a smaller inner diameter.

[0119] After the initial filler layer 61 is formed, the initial filler layer 61 in the first groove 40 forms the third groove 70, and the initial filler layer 61 in the second groove 50 forms the fourth groove 80. Since the initial filler layer 61 in the fourth groove 80 has a thicker deposition thickness, the second difference between the fourth groove 80 and the third groove 70 is smaller than the first difference, which facilitates subsequent ion implantation and rapid thermal processing to affect the etching rate at different positions of the initial filler layer 61.

[0120] It should be noted that, by utilizing the interplay of parameters such as deposition material, ion doping, and deposition thickness, after the formation of the third groove 70 and the fourth groove 80, a suitable etching selectivity ratio is selected between the mask structure 30 and the filler layer 60. The etching selectivity ratio ranges from 1:3 to 1:6. During subsequent etching, the etching rate for the filler layer 60 in the third groove 70 is faster, while the etching rate for the filler layer 60 in the fourth groove 80 is slower. This includes the following situations:

[0121] After the filling layer 60 in the third groove 70 is completely etched away, etching stops. The filling layer 60 in the fourth groove 80 is not completely removed. Due to the presence of the filling layer 60, the inner diameter of the fourth groove 80 becomes smaller. If the inner diameter of the fourth groove 80 and the inner diameter of the third groove 70 after the filling layer 60 has been removed meet a preset difference, subsequent etching is performed using the sidewalls of the fourth groove 80 and the third groove 70 as masks. This ensures the formation accuracy of the subsequent first through-hole 130, second through-hole 140, and contact hole 150 (refer to...). Figures 11 to 13 )

[0122] After the filling layer 60 in the fourth groove 80 is completely etched away, the filling layer 60 in the third groove 70 is also completely removed. At this time, the first dielectric layer 20 on the side inside the third groove 70 will be etched and a portion of the first dielectric layer 20 will be removed. This ensures the formation accuracy of the subsequent multiple etched openings 90 with preset difference inner diameters, thereby ensuring the formation accuracy of the subsequent first through hole 130, second through hole 140, and contact hole 150 (refer to...). Figures 11 to 13 ).

[0123] The etching time of the third groove 70 and the fourth groove 80 is determined based on the target size, with the etching opening 90 having a preset difference inner diameter.

[0124] Reference Figure 2 As shown, in some embodiments, the substrate 10 may include a substrate 11 and a support structure 12 disposed on the substrate 11. In this embodiment, the substrate 10 may employ the following methods:

[0125] A substrate 11 is provided, which may be made of a semiconductor material, which may be one or more of silicon, germanium, silicon-germanium compounds and silicon-carbon compounds.

[0126] A support structure 12 is formed on the top surface of the substrate 11 using atomic layer deposition, physical vapor deposition, or chemical vapor deposition. It should be noted that the support structure 12 can be a single-layer structure or a multilayer structure. When the support structure 12 is a multilayer structure, it may include a first support layer, a second support layer, etc., stacked together. The support structure 12 can be used to form vias to be formed in subsequent fabrication processes. These vias may include contact holes for forming contact structures, capacitor holes for forming capacitor structures, bit line contact holes for forming bit lines, etc. After forming the vias, the support structure 12 surrounding the vias can also be used to subsequently form other semiconductor structures between adjacent vias, such as bit line structures, metal line layers, etc.

[0127] Reference Figure 2 As shown, in some embodiments, a plurality of spaced isolation structures 111 may be provided in the substrate 11 along the first direction X.

[0128] The isolation structure 111 can be formed using the following methods:

[0129] A photoresist layer (not shown) and a mask layer (not shown) are deposited on the top surface of a substrate 11 using atomic layer deposition (ALD), physical vapor deposition (PVD), or chemical vapor deposition (CVD). A mask pattern is formed on the photoresist layer by exposure or etching. Using the photoresist layer with the mask pattern as a mask, a portion of the photoresist layer and a portion of the mask layer are etched away, thereby forming multiple isolation trenches (not shown) spaced apart along a first direction X on the substrate 11. Then, the remaining photoresist layer and mask layer are removed by etching. Next, isolation structures 111 are deposited within the isolation trenches using ALD, PVD, or CVD. Active regions 112 are formed on the substrate 11 portions between adjacent isolation structures 111. The isolation structures 111 can be made of insulating materials, such as silicon dioxide or silicon oxynitride. In this process, multiple spaced isolation structures are used to form spaced active regions within the substrate, so that other structures connected to the active regions can be formed on the substrate subsequently, such as capacitor contacts, source line contacts, bit line contacts, etc.

[0130] Reference Figure 2 As shown, the support structure 12 is a layered structure, and the support structure 12 can be formed by the following methods:

[0131] An isolation layer 121, a first sacrificial layer 122, at least one support layer 123, a second sacrificial layer 124, and an etching layer 125 are sequentially stacked on a substrate 11 using atomic layer deposition, physical vapor deposition, or chemical vapor deposition. The material of the isolation layer 121 may include, but is not limited to, silicon nitride; the materials of the first sacrificial layer 122 and the second sacrificial layer 124 may include, but are not limited to, silicon dioxide; and the etching layer 125 may include, but is not limited to, a spin-coated hard mask layer.

[0132] The support layer 123 includes alternating first support layer 1231 and spin-coated hard mask layer 1232. The material of the first support layer 1231 may include, but is not limited to, silicon oxynitride. In this example, the support layer 123 has two layers, that is, two support layers 123 are disposed between the first sacrificial layer 122 and the second sacrificial layer 124. It should be noted that the thickness of the upper spin-coated hard mask layer 1232 of the two support layers 123 may be equal to the thickness of the lower spin-coated hard mask layer 1232, or the thickness of the upper spin-coated hard mask layer 1232 may be greater than or less than the thickness of the lower spin-coated hard mask layer 1232.

[0133] In this embodiment, by utilizing the stacked support structure, the etching dimensions of the etching opening can be precisely transferred sequentially to the support structure, thereby improving the forming accuracy of other semiconductor structures (bit line contact structures, capacitor contact structures, etc.) formed in the support structure, and thus improving the yield of semiconductor structures.

[0134] Reference Figures 2 to 5 As shown, in some embodiments, the mask structure 30 can also be formed using the following methods:

[0135] like Figure 2 As shown, after the etched layer 125 is formed, the first dielectric layer 20 is formed on the etched layer 125 using atomic layer deposition, physical vapor deposition, or chemical vapor deposition.

[0136] Reference Figure 3 and Figure 4 The first mask layer 100 is formed on the first dielectric layer 20 by continuing the deposition process.

[0137] Then, a first mask pattern 101 is provided. Based on the first mask pattern 101, an etching process is used to remove part of the first mask layer 100, thereby forming a plurality of initial grooves 102 on the first mask layer 100.

[0138] Based on the initial groove 102, a portion of the first dielectric layer 20 is removed using the remaining first mask layer 100 as a mask to form a groove 31 on the first dielectric layer 20. The initial groove 102 may include a plurality of fifth grooves 110 and a plurality of sixth grooves 120, wherein the inner diameter of the fifth groove 110 is different from that of the sixth groove 120 along the first direction X.

[0139] Then, using an etching process, a portion of the first dielectric layer 20 is removed based on the fifth groove 110 to form a first groove 40 on the first dielectric layer 20. And, using an etching process, a portion of the first dielectric layer 20 is removed based on the sixth groove 120 to form a second groove 50 on the first dielectric layer 20. The remaining first dielectric layer 20 forms a plurality of mask structures 30 spaced apart along the first direction X (see reference). Figure 5 ).

[0140] In this embodiment, the first and second grooves can be quickly formed on the first dielectric layer using the first mask pattern. The method is simple and easy to operate.

[0141] Reference Figures 11 to 13 As shown, in some embodiments, the method for fabricating this semiconductor structure further includes:

[0142] like Figure 11As shown, based on the etched opening 90 that meets the target size requirements, a portion of the etched layer 125 is removed using an etching process, thereby forming multiple arrayed first vias 130 within the etched layer 125. After the first vias 130 are formed, the remaining first dielectric layer 20 on top of the etched layer 125 is removed using a polishing process.

[0143] like Figure 12 As shown, after the first dielectric layer 20 is removed, a portion of the second sacrificial layer 124 is removed using an etching process based on the first via 130, so as to form a plurality of arrayed second vias 140 within the second sacrificial layer 124. After the second vias 140 are formed, the remaining etched layer 125 is removed using an etching process.

[0144] like Figure 13 As shown, after the etched layer 125 is removed, a portion of the support structure 12 is removed using an etching process based on the second via 140, so as to form a plurality of arrayed contact holes 150 within the support structure 12. The contact holes 150 expose at least a portion of the active region 112.

[0145] In this embodiment, by utilizing the etched opening and the first via, the forming accuracy of the second via can be effectively improved, thereby facilitating the subsequent formation of other semiconductor structures in the support structure, such as bit line contact structures and capacitor contact structures.

[0146] like Figure 1 As shown, an exemplary embodiment of this disclosure provides a semiconductor structure, which can be fabricated using the semiconductor structure fabrication method provided in any of the above embodiments. The semiconductor structure can be a dynamic random access memory (DRAM), but of course, it can also be other structures.

[0147] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0148] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0149] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0150] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method for fabricating the semiconductor structure includes: Provide a base; A first dielectric layer is formed on the substrate, the first dielectric layer having an array of grooves, the grooves including a first groove and a second groove, and there is a first difference between the inner diameter of the first groove and the second groove; An initial filling layer is formed, which covers the sidewalls and bottom wall of the first groove and the sidewalls and bottom wall of the second groove. The initial filling layer in the first groove forms a third groove, and the initial filling layer in the second groove forms a fourth groove. There is a second difference between the inner diameter of the third groove and the fourth groove, and the second difference is smaller than the first difference. The initial fill layer is processed to form a fill layer; The filling layer and / or the first dielectric layer are etched to form a plurality of etched openings with a preset difference inner diameter on the substrate surface. The substrate includes: Provide substrate; A support structure is formed on the substrate; The supporting structure includes: An isolation layer, a first sacrificial layer, at least one support layer, a second sacrificial layer, and an etching layer are formed sequentially on the substrate. Each of the support layers includes an alternately arranged first support layer and a spin-coated hard mask layer; A first dielectric layer is formed on the substrate, and the first dielectric layer has an array of grooves, including: The first dielectric layer is formed on the etched layer; A first mask layer is formed on the first dielectric layer; A first mask pattern is provided, and based on the first mask pattern, a portion of the first mask layer is removed to form a plurality of initial grooves on the first mask layer; Based on the initial groove, a portion of the first dielectric layer is removed using the remaining first mask layer as a mask to form the groove on the first dielectric layer.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The groove has a target size, the inner diameter of the first groove is smaller than the target size, and the inner diameter of the second groove is larger than the target size; The target size is any value within the range of 30~60nm; The maximum difference between the inner diameters of the first groove and the second groove is 6 nm.

3. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Processing the initial fill layer to form a fill layer includes: Ion implantation is performed on the initial filling layer; The initial filling layer after ion implantation is subjected to rapid thermal treatment to form the filling layer.

4. The method for fabricating a semiconductor structure according to claim 3, characterized in that, Ion implantation of the initial filling layer includes: The initial filling layer is ion implanted using group III or group V elements.

5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, The ion implantation dose is 10 14 ~10 15 / cm 2 The ion implantation energy ranges from 10 keV to 40 keV.

6. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Forming the initial fill layer includes: The initial filling layer is formed in the first groove and the second groove using a chemical vapor deposition process or a physical vapor deposition process.

7. The method for fabricating a semiconductor structure according to claim 6, characterized in that, The thickness of the initial filling layer is 5nm to 8nm.

8. The method for fabricating a semiconductor structure according to any one of claims 1-6, characterized in that, The material of the first dielectric layer includes one of silicon oxynitride, silicon nitride, silicon oxide, silicon carbide, and spin-coated hard mask layer.

9. The method for fabricating a semiconductor structure according to any one of claims 1-6, characterized in that, The first dielectric layer comprises undoped polycrystalline silicon.

10. The method for fabricating a semiconductor structure according to any one of claims 1-6, characterized in that, The method for fabricating the semiconductor structure further includes: Based on the etching opening, a portion of the etched layer is removed to form a plurality of first through holes spaced apart along a first direction within the etched layer.

11. The method for fabricating a semiconductor structure according to claim 10, characterized in that, The method for fabricating the semiconductor structure further includes: Based on the first through-hole, a portion of the second sacrificial layer is removed to form a plurality of second through-holes spaced apart along the first direction within the second sacrificial layer.

12. The method for fabricating a semiconductor structure according to claim 11, characterized in that, The method for fabricating the semiconductor structure further includes: Based on the second through hole, a plurality of contact holes spaced apart along the first direction are formed within the support structure.

13. A semiconductor structure, characterized in that, It is prepared by the method of fabricating the semiconductor structure according to any one of claims 1-12.

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