Maskless process for improving drain to gate breakdown voltage in semiconductor devices

Abstract

A semiconductor device can include a first device on a first portion of a substrate, a second device on a second portion of the substrate, and a third device on a third portion of the substrate. The third device can include an oxide layer formed from an oxide layer that is a sacrificial oxide layer for the first and second devices. The third device can include a gate disposed on the oxide layer, a set of spacers disposed on opposite sides of the gate, and a source region disposed in the third portion of the substrate on one side of the gate. The third device can include a drain region disposed in the third portion of the substrate on another side of the gate and a protective oxide layer disposed on portions of the gate and the drain region.

Description

Technical Field

[0001] Some embodiments of the present invention relate to a maskless process for improving drain-to-gate breakdown voltage in semiconductor devices. Background Technology

[0002] Power semiconductor devices are semiconductor devices used as switches or rectifiers in power electronics (e.g., in switch-mode power supplies). These devices are also called power devices, or power ICs when used in integrated circuits (ICs). Summary of the Invention

[0003] As described in more detail above, some embodiments described herein provide a method for manufacturing a semiconductor device. The method includes depositing a first oxide layer on a first portion, a second portion, and a third portion of a substrate, wherein the first oxide layer is a sacrificial oxide layer for the first and second portions of the substrate. The method includes depositing a first photoresist layer on the first oxide layer deposited on the third portion of the substrate. The method includes removing the first oxide layer from the first and second portions of the substrate. The method includes removing the first photoresist layer from the first oxide layer deposited on the third portion of the substrate. The method includes depositing a second oxide layer on the first and second portions of the substrate and on the first oxide layer deposited on the third portion of the substrate, wherein the first oxide layer and the second oxide layer on the third portion of the substrate define a modified first oxide layer on the third portion of the substrate. The method includes depositing a second photoresist layer on the modified first oxide layer and on the second oxide layer deposited on the second portion of the substrate. The method includes removing the second oxide layer deposited on the first portion of the substrate. The method includes depositing a third oxide layer on the first portion of the substrate. The method includes removing the second photoresist layer. The method includes providing a first device on the third oxide layer deposited on the first portion of the substrate. The method includes providing a second device on the second oxide layer deposited on the second portion of the substrate. The method includes providing a third device on the modified first oxide layer deposited on the third portion of the substrate.

[0004] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a substrate comprising a first portion, a second portion, and a third portion. The semiconductor device includes a first device located on the first portion of the substrate. The semiconductor device includes a second device located on the second portion of the substrate. The semiconductor device includes a third device located on the third portion of the substrate and includes: an oxide layer located on the third portion, wherein the thickness of the oxide layer is greater than the thickness of the oxide layers used for the first and second devices; a gate located on the oxide layer; a set of spacers located on opposite sides of the gate; a source region located on one side of the gate in the third portion of the substrate; a drain region located on the other side of the gate in the third portion of the substrate; and a protective oxide layer located on the portion of the gate and the portion of the drain region.

[0005] As described in more detail above, some embodiments described herein provide a method for manufacturing a semiconductor device. The method includes depositing a first oxide layer on a first portion, a second portion, and a third portion of a substrate using in-situ vapor generation, wherein the first oxide layer is a sacrificial oxide layer for the first and second portions of the substrate. The method includes depositing a first photoresist layer on the first oxide layer disposed on the third portion of the substrate. The method includes removing the first oxide layer from the first and second portions of the substrate. The method includes removing the first photoresist layer from the first oxide layer deposited on the third portion of the substrate. The method includes depositing a second oxide layer on the first and second portions of the substrate and on the first oxide layer deposited on the third portion of the substrate, wherein the first oxide layer and the second oxide layer on the third portion of the substrate define a modified first oxide layer on the third portion of the substrate. The method includes depositing a second photoresist layer on the modified first oxide layer and on the second oxide layer deposited on the second portion of the substrate. The method includes removing the second oxide layer deposited on the first portion of the substrate. The method includes depositing a third oxide layer on the first portion of the substrate. The method includes removing the second photoresist layer. The method includes providing a first device including a first gate, a first source region, and a first drain region on the third oxide layer on the first portion of the substrate. The method includes providing a second device including a second gate, a second source region, and a second drain region on the second oxide layer on the second portion of the substrate. The method includes providing a third device including a third gate, a third source region, and a third drain region on the modified first oxide layer on the third portion of the substrate. The method includes depositing a protective oxide layer on the portion of the third gate and the portion of the third drain region. Attached Figure Description

[0006] The best understanding of all aspects of this disclosure will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 This is a diagram of an exemplary environment in which the systems and / or methods described herein can be implemented.

[0008] Figures 2A to 2O This is a diagram illustrating one or more exemplary operations involved in the manufacture of the exemplary semiconductor device described herein.

[0009] Figure 3This is a diagram of an exemplary core device described in this article.

[0010] Figure 4 This is a diagram of an exemplary input / output (I / O) device described in this article.

[0011] Figure 5 This is a diagram of an exemplary high-voltage device described in this article.

[0012] Figure 6 This is a graph illustrating an exemplary improvement in the drain-to-gate breakdown voltage of the exemplary semiconductor device described herein.

[0013] Figure 7 yes Figure 1 A diagram showing exemplary components of one or more tools and / or devices.

[0014] Figure 8 and Figure 9 This is a flowchart of an exemplary maskless process for improving drain-to-gate breakdown voltage in semiconductor devices. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the description in the following text, "above" or "on" a second feature, may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity and is not, in itself, intended to indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, for ease of explanation, spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” and similar expressions may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0017] In some cases, power semiconductor devices may include field-effect transistors (FETs). An FET is a transistor that uses an electric field to control current. An FET includes three terminals: a source, a gate, and a drain. An FET controls current by applying a voltage to the gate, which in turn changes the conductivity between the drain and source. In power semiconductor devices, drain-side drift region engineering is important for high-voltage operation. However, current processes used to manufacture power semiconductor devices create divots near the oxide diffusion / shallow trench isolation region. These divots result in a thinner, high-voltage gate oxide region in the power semiconductor device, which severely degrades the drain-to-gate breakdown voltage and limits the power semiconductor device to high-voltage operation (e.g., operating voltages greater than the operating voltages of input / output devices).

[0018] According to some embodiments described herein, a method for manufacturing a semiconductor device (e.g., a power semiconductor device) is based on a maskless process for improving the drain-to-gate breakdown voltage in the semiconductor device. For example, the method may include forming or depositing a first oxide layer on a first portion, a second portion, and a third portion of a substrate, wherein the first oxide layer is a sacrificial oxide layer for the first and second portions of the substrate. The method may include: forming or depositing a first photoresist layer on the first oxide layer formed on the third portion of the substrate; and removing the first oxide layer from the first and second portions of the substrate. The method may include: removing the first photoresist layer from the first oxide layer formed on the third portion of the substrate; and forming or depositing a second oxide layer on the first and second portions of the substrate and on the first oxide layer formed on the third portion of the substrate, wherein the first oxide layer and the second oxide layer on the third portion of the substrate define a modified first oxide layer on the third portion of the substrate. The method may include: forming or depositing a second photoresist layer on the modified first oxide layer and on the second oxide layer formed on the second portion of the substrate; and removing the second oxide layer formed on the first portion of the substrate. The method may include: forming or depositing a third oxide layer on a first portion of a substrate; removing a second photoresist layer; and forming or providing a first device on the third oxide layer formed on the first portion of the substrate. The method may also include: forming or providing a second device on a second oxide layer formed on a second portion of the substrate; and forming or providing a third device on a modified first oxide layer formed on a third portion of the substrate.

[0019] In this manner, the method for manufacturing semiconductor devices is based on a maskless process that improves the drain-to-gate breakdown voltage in semiconductor devices. The method may include using sacrificial oxide (e.g., formed via in-situ steam generation (ISSG)) for the gate oxide region of the semiconductor device, which prevents the formation of thinner gate oxide regions caused by pitting. Compared to current manufacturing processes, the method increases the drain-to-gate breakdown voltage by more than two volts, or by more than thirty percent (30%). Therefore, the semiconductor device can be used for high-voltage operation (e.g., as a power semiconductor device). Furthermore, compared to current manufacturing processes, the method does not require additional masks or additional thermal budgets and includes fewer process steps and reduced process time. The method can be used to simultaneously manufacture core devices (e.g., for performing functions), input / output devices (e.g., for transferring the performed functions to external devices), and high-voltage devices (e.g., power semiconductor devices) without affecting the performance of such devices.

[0020] Figure 1 This is a diagram of an exemplary environment 100 in which the systems and / or methods described herein may be implemented. Figure 1 As shown, environment 100 may include pre-cleaning tools 102, deposition tools 104, annealing tools 106, photoresist tools 108, etching tools 110, and wafer / die transport devices 112. The tools and / or devices included in the exemplary environment 100 may be found in semiconductor cleanrooms, semiconductor foundries, semiconductor processing and / or manufacturing facilities, and / or similar facilities.

[0021] The pre-cleaning tool 102 includes a pre-cleaning chamber 114 and one or more devices capable of performing a pre-cleaning process on a semiconductor device to remove byproduct layers from the semiconductor device. The one or more devices may include a gas source 116, a plasma source 118, a heat source 120, and / or similar sources. The gas source 116 may supply various gases to the pre-cleaning chamber 114, such as ammonia, nitrogen trifluoride, and / or similar gases. The plasma source 118 may generate plasma that causes a reaction between the gases supplied to the pre-cleaning chamber 114. For example, the plasma source 118 may include an inductively coupled plasma (ICP) source, a transformer coupled plasma (TCP) source, or another type of plasma source capable of causing a reaction between ammonia and nitrogen trifluoride to form ammonium fluoride. The heat source 120 may be capable of heating the semiconductor device in the pre-cleaning chamber 114 to decompose one or more layers on the semiconductor device, as described herein. For example, heat source 120 may include a heat lamp, a heating coil, or another type of heating device that heats a semiconductor device to decompose the ammonium fluoride layer on the semiconductor device into ammonia and hydrogen fluoride gases, as described herein.

[0022] Deposition tool 104 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a semiconductor device. For example, deposition tool 104 may include chemical vapor deposition devices (e.g., electrostatic spray devices, epitaxial devices, and / or another type of chemical vapor deposition device), physical vapor deposition devices (e.g., sputtering devices and / or another type of physical vapor deposition device), ion implantation devices, and / or similar devices. In some embodiments, deposition tool 104 may deposit metal layers onto the source or drain regions of a semiconductor device, deposit contact materials to form contacts of a semiconductor device, and / or perform similar operations as described herein.

[0023] Annealing tool 106 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of heating the semiconductor device. For example, annealing tool 106 may include a rapid thermal annealing (RTA) tool or another type of annealing tool and / or similar tool capable of heating the semiconductor device to induce a reaction between two or more materials or gases, thereby causing material decomposition. For example, annealing tool 106 may heat the semiconductor device to induce a reaction in a metal layer on an epitaxial region (e.g., a source region or drain region) to form a metal silicide layer, as described herein.

[0024] Photoresist tool 108 is a semiconductor processing tool that removes or supplies material to a semiconductor device based on a photoresist layer (e.g., a photoresist mask) applied to the semiconductor device. Photoresist is a light-sensitive material used in processes such as photolithography, photoengraving, and / or similar processes to form a patterned coating on the surface of a semiconductor device. Photoresist tool 108 may coat the semiconductor device with a photosensitive organic material and may apply a patterned mask to the semiconductor device to block light, such that only the unmasked areas of the photosensitive organic material are exposed to light. Photoresist tool 108 or another tool (e.g., etching tool 110) may apply a solvent called a developer to the semiconductor device. In the case of positive photoresist, the photosensitive organic material is photodegraded and the developer is dissolved in the areas exposed to light, leaving the coating on which the mask was placed. In the case of negative photoresists, the photosensitive organic material is enhanced by light (e.g., polymerized or crosslinked), and the developer dissolves only the areas not exposed to light, thus leaving a coating in the areas where no mask is placed.

[0025] Etching tool 110 is a semiconductor processing tool that removes material from the surface of a semiconductor device. In some embodiments, portions of the semiconductor device are protected from the etchant by an etch-resistant masking material. For example, the masking material may include a photoresist patterned using photolithography. Etching tool 110 can perform wet etching or dry (e.g., plasma) etching processes on the semiconductor device. In a wet etching process, the semiconductor device is immersed in a batch of liquid phase (e.g., wet) etchant, which can be agitated to achieve process control. For example, buffered hydrofluoric acid (BHF) can be used to etch silicon dioxide onto a silicon substrate. Plasma etching processes can operate in several modes based on adjustments to plasma parameters. For example, plasma etching processes can operate at pressures ranging from approximately 0.01 Torr to approximately 5 Torr. The plasma generates high-energy free radicals, which are neutrally charged and react at the surface of the semiconductor device. Plasma etching can be isotropic (e.g., exhibiting a lateral undercut rate approximately the same as the downward etching rate on a patterned surface) or anisotropic (e.g., exhibiting a lateral undercut rate lower than the downward etching rate). The source gas of the plasma can contain small molecules rich in chlorine or fluorine. For example, carbon tetrafluorine can be used to etch silicon, chlorine can be used to etch aluminum, and trifluoromethane can be used to etch silicon dioxide and silicon nitride and / or similar materials. The plasma may also include oxygen to oxidize the photoresist and promote its removal.

[0026] The wafer / die transport device 112 includes a mobile robot, robotic arm, tram, or railcar, and / or another type of device used for transporting wafers and / or dies between semiconductor processing tools 102 and 110, and / or transporting wafers and / or dies to other locations (e.g., wafer racks, storage rooms, and / or similar locations) and from said other locations. In some embodiments, the wafer / die transport device 112 may be a programmable device that travels a specific path and / or is semi-autonomous or autonomous.

[0027] supply Figure 1 The number and arrangement of the devices shown are one or more examples. In fact, with... Figure 1 Compared to the devices shown, there may be additional devices, fewer devices, different devices, or devices arranged differently. Furthermore, Figure 1 The two or more devices shown can be implemented within a single device, or Figure 1The single device shown can be implemented as multiple distributed devices. Alternatively, a group of devices in environment 100 (e.g., one or more devices) can perform one or more functions described as being performed by another group of devices in environment 100.

[0028] Figures 2A to 2O This is a diagram illustrating one or more exemplary operations 200 involved in manufacturing the exemplary semiconductor devices (e.g., logic devices, memory devices, FinFETs, metal-oxide-semiconductor FETs (MOSFETs), and / or the like) described herein. Figure 2A As shown, the semiconductor device may include a core device 202, an input / output (I / O) device 204, and a high-voltage device 206. The core device 202 may include a device that performs one or more functions (e.g., logic operations, memory operations, and / or similar operations). The I / O device 204 may include a device that transmits the one or more functions to external devices. The high-voltage device 206 may include a power semiconductor device, such as a FET that uses an electric field to control current.

[0029] like Figure 2A As further shown, a core device 202 may be disposed on a first portion of substrate 208, an I / O device 204 may be disposed on a second portion of substrate 208, and a high-voltage device 206 may be disposed on a third portion of substrate 208. Substrate 208 may contain conductive or semiconductive materials, such as silicon, aluminum, copper, and / or the like. A pad oxide layer 210 may be formed or deposited on substrate 208, and a pad silicon nitride layer 212 may be formed or deposited on pad oxide layer 210. Pad oxide layer 210 may contain materials used as isolation materials for substrate 208, such as silicon oxide, iron oxide, aluminum oxide, and / or the like. Pad silicon nitride layer 212 may be formed or deposited from silicon nitride and may act as an oxide barrier for pad oxide layer 210.

[0030] like Figure 2B As shown, the silicon nitride layer 212 can be removed from the pad oxide layer 210 of the core device 202, I / O device 204, and high-voltage device 206. In some embodiments, one or more etching operations can be performed to remove the silicon nitride layer 212 from the pad oxide layer 210. For example, a dry etching operation using carbon tetrafluoride gas, nitrogen trifluoride gas, chlorine gas, and / or the like can be performed to remove the silicon nitride layer 212 from the pad oxide layer 210. In some embodiments, the above combination can be utilized. Figure 1The etching tool 110 in the described environment 100 removes the silicon nitride layer 212 from the pad oxide layer 210 of the core device 202, I / O device 204 and high voltage device 206.

[0031] like Figure 2C As shown, a photoresist layer 214 may be formed or deposited on the pad oxide layer 210 of the core device 202 and I / O device 204, but not on the pad oxide layer 210 of the high-voltage device 206. The photoresist layer 214 may comprise a photoresist material, such as a photopolymerizable photoresist (e.g., methyl methacrylate), a photodegradable photoresist (e.g., diazonaphthoquinone), a photocrosslinking photoresist, and / or the like. In some embodiments, the photoresist layer 214 is patterned on portions of the semiconductor device (e.g., the core device 202 and I / O device 204) to protect the substrate 208 of the core device 202 and I / O device 204, as described below. In some embodiments, the above combination may be utilized... Figure 1 In the described environment 100, the photoresist tool 108 forms or deposits a photoresist layer 214 on the pad oxide layer 210 of the core device 202 and the I / O device 204.

[0032] like Figure 2C As further shown, an ion implantation process can be performed to implant ions (e.g., via pad oxide layer 210) into the substrate 208 of the high-voltage device 206 and form a p-type body region 216 and an n-type drift region 217 in the substrate 208 of the high-voltage device 206. The p-type body region 216 can be formed by implanting a trivalent acceptor impurity (e.g., boron, gallium, indium, aluminum, and / or the like) into the substrate 208 of the high-voltage device 206. The n-type drift region 217 can be formed by implanting a donor impurity (e.g., phosphorus, arsenic, antimony, bismuth, and / or the like) into the substrate 208 of the high-voltage device 206. In some embodiments, the above combination can be utilized... Figure 1 The deposition tool 104 (e.g., ion implantation tool) of the described environment 100 implants ions in the substrate 208 of the high-voltage device 206 and forms a p-type body region 216 and an n-type drift region 217 in the substrate 208 of the high-voltage device 206.

[0033] like Figure 2DAs shown, the photoresist layer 214 and the pad oxide layer 210 can be removed from the core device 202 and I / O device 204, and the pad oxide layer 210 can be removed from the high-voltage device 206. In some embodiments, one or more etching operations can be performed to remove the photoresist layer 214 and the pad oxide layer 210 from the core device 202 and I / O device 204, and to remove the pad oxide layer 210 from the high-voltage device 206. For example, a dry etching operation using carbon tetrafluoride gas, nitrogen trifluoride gas, chlorine gas, and / or the like can be performed to remove the photoresist layer 214 and the pad oxide layer 210 from the core device 202 and I / O device 204, and to remove the pad oxide layer 210 from the high-voltage device 206. In some embodiments, the above combination can be utilized Figure 1 The etching tool 110 in the described environment 100 removes the photoresist layer 214 and the pad oxide layer 210 from the core device 202 and the I / O device 204, and removes the pad oxide layer 210 from the high voltage device 206.

[0034] like Figure 2E As shown, a sacrificial oxide layer 218 can be formed or deposited on the substrate 208 of the core device 202, I / O device 204, and high-voltage device 206 via an in-situ vapor generation (ISSG) process. The sacrificial oxide layer 218 may contain materials used as insulating materials for the substrate 208, such as silicon oxide, iron oxide, aluminum oxide, and / or the like. In some embodiments, the sacrificial oxide layer 218 is a sacrificial layer for the core device 202 and I / O device 204 because it is removed from the core device 202 and I / O device 204 in subsequent processing steps. However, since the sacrificial oxide layer 218 is not removed from the high-voltage device 206 in subsequent processing steps, but is instead used to create a thicker oxide layer for the gate of the high-voltage device 206 as described below, the sacrificial oxide layer 218 is not a sacrificial layer for the high-voltage device 206. ISSG is an oxidation technique for rapid thermal processing of semiconductor devices and a different method for generating vapor. ISSG is a low-pressure process (e.g., typically below 20 Torr) in which premixed hydrogen and oxygen are directly introduced into the processing chamber without pre-combustion. In some embodiments, the above combination can be utilized. Figure 1 The deposition tool 104 of the described environment 100 forms or deposits a sacrificial oxide layer 218 on the substrate 208 of the core device 202, I / O device 204 and high voltage device 206 through the ISSG process.

[0035] like Figure 2FAs shown, a photoresist layer 220 can be formed or deposited on the sacrificial oxide layer 218 of the high-voltage device 206. The photoresist layer 220 may comprise a photoresist material, such as a photopolymerizable photoresist (e.g., methyl methacrylate), a photodegradable photoresist (e.g., diazonaphthoquinone), a photocrosslinking photoresist, and / or the like. In some embodiments, the photoresist layer 220 is patterned on the sacrificial oxide layer 218 of the high-voltage device 206 to protect the sacrificial oxide layer 218 of the high-voltage device 206, as described below. In some embodiments, the above combination can be utilized... Figure 1 In the described environment 100, a photoresist tool 108 forms or deposits a photoresist layer 220 on a sacrificial oxide layer 218 of a high-voltage device 206.

[0036] like Figure 2F As further shown, an ion implantation process can be implemented to implant ions (e.g., via sacrificial oxide layer 218) into the substrate 208 of the core device 202 and I / O device 204, forming an ion-implanted substrate 208 for the core device 202 and I / O device 204. The ion-implanted substrate 208 can be formed by implanting ions (e.g., boron, gallium, indium, aluminum, phosphorus, arsenic, antimony, bismuth, and / or the like) into the substrate 208 of the core device 202 and I / O device 204. In some embodiments, the above combination can be utilized... Figure 1 The deposition tool 104 (e.g., ion implantation tool) of the described environment 100 implants ions in the substrate 208 of the core device 202 and the I / O device 204 and forms the ion-implanted substrate 208 for the core device 202 and the I / O device 204.

[0037] like Figure 2G As shown, the sacrificial oxide layer 218 can be removed from the core device 202 and the I / O device 204. The photoresist layer 220 of the high-voltage device 206 protects the sacrificial oxide layer 218 of the high-voltage device 206 from removal. In some embodiments, one or more etching operations can be performed to remove the sacrificial oxide layer 218 from the core device 202 and the I / O device 204. For example, a dry etching operation using carbon tetrafluoride gas, nitrogen trifluoride gas, chlorine gas, and / or the like can be performed to remove the sacrificial oxide layer 218 from the core device 202 and the I / O device 204. In some embodiments, the above combination can be used... Figure 1 The etching tool 110 in the described environment 100 removes the sacrificial oxide layer 218 from the core device 202 and the I / O device 204.

[0038] like Figure 2HAs shown, the photoresist layer 220 can be removed from the high-voltage device 206. In some embodiments, one or more etching operations can be performed to remove the photoresist layer 220 from the high-voltage device 206. For example, a dry etching operation using carbon tetrafluoride gas, nitrogen trifluoride gas, chlorine gas, and / or the like can be performed to remove the photoresist layer 220 from the high-voltage device 206. In some embodiments, the above combination can be utilized. Figure 1 The etching tool 110 in the described environment 100 removes the photoresist layer 220 from the high-voltage device 206.

[0039] like Figure 2H As further shown, an oxide layer 222 may be formed or deposited on the substrate 208 of the core device 202, I / O device 204, and high-voltage device 206. The oxide layer 222 may contain a material used as an isolation material for the substrate 208, such as silicon oxide, iron oxide, aluminum oxide, and / or the like. In some embodiments, the oxide layer 222 may be combined with the sacrificial oxide layer 218 of the high-voltage device 206 to create an oxide layer 224 that is thicker than the oxide layer 222 of the core device 202 and I / O device 204. The thicker oxide layer 224 of the high-voltage device 206 prevents the formation of a thinner gate oxide region caused by pitting and increases the drain-to-gate breakdown voltage of the high-voltage device 206 by two volts or more, or by more than approximately thirty percent (30%), relative to current manufacturing processes. In some embodiments, the above combination may be utilized... Figure 1 In the described environment 100, the deposition tool 104 forms or deposits an oxide layer 222 on the substrate 208 of the core device 202, the I / O device 204 and the high voltage device 206.

[0040] like Figure 2I As shown, a photoresist layer 226 can be formed or deposited on the oxide layer 222 of the I / O device 204 and on the oxide / sacrificial oxide layer 224 of the high-voltage device 206. The photoresist layer 226 may comprise a photoresist material, such as a photopolymerizable photoresist (e.g., methyl methacrylate), a photodegradable photoresist (e.g., diazonaphthoquinone), a photocrosslinking photoresist, and / or the like. In some embodiments, the photoresist layer 226 is patterned on the oxide layer 222 of the I / O device 204 and the oxide / sacrificial oxide layer 224 of the high-voltage device 206 to protect the oxide layer 222 of the I / O device 204 and the oxide / sacrificial oxide layer 224 of the high-voltage device 206, as described below. In some embodiments, the above combination can be utilized... Figure 1 In the described environment 100, the photoresist tool 108 forms or deposits a photoresist layer 226 on the oxide layer 222 of the I / O device 204 and on the oxide layer / sacrificial oxide layer 224 of the high voltage device 206.

[0041] like Figure 2I As further shown, the oxide layer 222 of the core device 202 can be removed. The photoresist layer 226 of the I / O device 204 and the high-voltage device 206 protects the oxide layer 222 of the I / O device 204 and the oxide / sacrificial oxide layer 224 of the high-voltage device 206 from removal. In some embodiments, one or more etching operations may be performed to remove the oxide layer 222 from the core device 202. For example, a dry etching operation using carbon tetrafluoride gas, nitrogen trifluoride gas, chlorine gas and / or the like may be performed to remove the oxide layer 222 from the core device 202. In some embodiments, the above combination may be utilized Figure 1 The etching tool 110 in the described environment 100 removes the oxide layer 222 from the core device 202.

[0042] like Figure 2J As shown, a thin oxide layer 228 may be formed or deposited on the substrate 208 of the core device 202. The thin oxide layer 228 may contain a material used as an insulating material for the substrate 208, such as silicon oxide, iron oxide, aluminum oxide, and / or the like. In some embodiments, the photoresist layer 226 of the I / O device 204 and the high-voltage device 206 may prevent the formation or deposition of the thin oxide layer 228 (e.g., an oxide layer thinner than that of the I / O device 204) on the I / O device 204 and the high-voltage device 206. In some embodiments, the above combination may be utilized. Figure 1 In the described environment 100, the deposition tool 104 forms or deposits a thin oxide layer 228 on the substrate 208 of the core device 202.

[0043] like Figure 2J As further shown, the photoresist layer 226 can be removed from the I / O device 204 and the high-voltage device 206. In some embodiments, one or more etching operations can be performed to remove the photoresist layer 226 from the I / O device 204 and the high-voltage device 206. For example, dry etching operations using carbon tetrafluoride gas, nitrogen trifluoride gas, chlorine gas and / or the like can be performed to remove the photoresist layer 226 from the I / O device 204 and the high-voltage device 206. In some embodiments, the above combination can be used... Figure 1 The etching tool 110 in the described environment 100 removes the photoresist layer 226 from the I / O device 204 and the high-voltage device 206.

[0044] like Figure 2JAs further shown, the oxide layer / sacrificial oxide layer 224 of the high-voltage device 206 may be thicker than the oxide layer 222 of the I / O device 204, and the oxide layer 222 of the I / O device 204 may be thicker than the thin oxide layer 228 of the core device 202. The thicker oxide layer 224 of the high-voltage device 206 prevents the formation of a thinner gate oxide region caused by pitting, and increases the drain-to-gate breakdown voltage of the high-voltage device 206 by two or more volts, or by more than approximately thirty percent (30%), compared to current manufacturing processes. The thickness of the thin oxide layer 228 of the core device 202 and the oxide layer 222 of the I / O device 204 depends on the functionality of the core device 202 and the I / O device 204. For example, the functionality of the I / O device 204 may require an oxide layer thicker than the thin oxide layer 228 of the core device 202, the functionality of the core device 202 may require a thinner oxide layer, and / or similar situations.

[0045] like Figure 2K As shown, a gate 230 with spacers 232 may be formed or provided on the thin oxide layer 228 of the core device 202, on the oxide layer of the I / O device 204, and on the oxide / sacrificial oxide layer 224 of the high-voltage device 206. The gate 230 may comprise a metal, such as cobalt, tungsten, aluminum, copper, and / or the like. The spacers 232 may comprise a dielectric material (e.g., polysilicon, silicon nitride, silicon oxide, and / or the like) that electrically isolates the gate 230 from other components of the semiconductor device. In some embodiments, the above combination may be utilized. Figure 1 The deposition tool 104 in the described environment 100 deposits metal layers on the thin oxide layer 228 of the core device 202, on the oxide layer of the I / O device 204, and on the oxide / sacrificial oxide layer 224 of the high-voltage device 206. The above combination can be used to... Figure 1 The photoresist tool 108 in the described environment 100 patterns a photoresist layer on a metal layer. This can be achieved using the above combination... Figure 1 The etching tool 110 in the described environment 100 etches a metal layer (e.g., excluding the metal layer disposed beneath the photoresist layer) and defines the gate 230 for the core device 202, I / O device 204, and high-voltage device 206. The photoresist layer can be removed from the gate 230 for the core device 202, I / O device 204, and high-voltage device 206 using the etching tool 110. The above combination can be used... Figure 1 The deposition tool 104 of the described environment 100 deposits a dielectric layer on and around the gate 230 of the core device 202, I / O device 204, and high-voltage device 206. A portion of the dielectric layer can then be removed using an etching tool 110, defining spacers 232 for the gate 230 of the core device 202, I / O device 204, and high-voltage device 206.

[0046] like Figure 2L As shown, an ion implantation process can be performed to form source regions 234 and drain regions 236 in the substrate 208 of the core device 202, I / O device 204, and high-voltage device 206. As shown, source regions 234 and drain regions 236 can be formed on opposite sides of the gates 230 of the core device 202, I / O device 204, and high-voltage device 206. In some embodiments, the above combination can be utilized... Figure 1 The deposition tool 104 (e.g., an ion implantation tool) in the described environment 100 implants ions in the substrate 208 of the core device 202, I / O device 204, and high-voltage device 206, and forms doped polysilicon regions in the substrate 208 of the core device 202, I / O device 204, and high-voltage device 206. The above combination can be utilized... Figure 1 The described environment 100 uses an annealing tool 106 to perform rapid thermal annealing of the ion dopants that activate the doped polysilicon regions formed in the substrate 208 of the core device 202, I / O device 204, and high-voltage device 206. The activated doped polysilicon regions can form source regions 234 and drain regions 236 in the substrate 208 of the core device 202, I / O device 204, and high-voltage device 206.

[0047] like Figure 2M As shown, a protective oxide layer 238 may be formed on a portion of the gate 230 and a portion of the drain region 236 of the high-voltage device 206. The protective oxide layer 238 may also be formed on one of the spacers 232 and a portion of the n-type drift region 217 of the substrate 208. In some embodiments, the protective oxide layer 238 may be formed without covering any portion of the gate 230 and / or any portion of the drain region 236 of the high-voltage device 206. In some embodiments, in addition to or instead of the protective oxide layer 238 described above, a protective oxide layer may be formed or deposited on a portion of the gate 230 and a portion of the source region 234 of the high-voltage device 206. In some embodiments, the protective oxide layer 238 covers a portion of a third portion of the substrate 208 and the entire surface of the spacers in the set of spacers 232.

[0048] The protective oxide layer 238 may comprise a material used as an isolation material for the portion of the gate 230 and the portion of the drain region 236 of the high-voltage device 206, such as silicon oxide, iron oxide, aluminum oxide, and / or the like. In some embodiments, the above combination may be utilized. Figure 1 The deposition tool 104 of the described environment 100 forms or deposits a protective oxide layer 238 on the portion of the gate 230 and the portion of the drain region 236 of the high voltage device 206.

[0049] like Figure 2N As shown, a silicide layer 240 may be formed or deposited over portions of the gate 230, source region 234, and drain region 236 of the core device 202, I / O device 204, and high-voltage device 206. As further shown, a protective oxide layer 238 prevents the formation or deposition of the silicide layer 240 on portions of the gate 230 and drain region 236 of the high-voltage device 206. In some embodiments, the above combination may be utilized. Figure 1 The deposition tool 104 in the described environment 100 forms or deposits an oxide layer on portions of the silicide layer 240 defining the gate 230, source region 234, and drain region 236 of the core device 202, I / O device 204, and high-voltage device 206. The deposition tool 104 can also be used to form or deposit a metal layer on the oxide layer formed or deposited on the aforementioned portions of the gate 230, source region 234, and drain region 236 of the core device 202, I / O device 204, and high-voltage device 206. The above combination can be used... Figure 1 The annealing tool 106 of the described environment 100 is used to perform rapid thermal annealing to interact with the metal layer to form or deposit a silicide layer 240 on the portions of the gate 230, source region 234 and drain region 236 of the core device 202, I / O device 204 and high voltage device 206.

[0050] like Figure 2O As shown, the current process described herein (e.g., in which the oxide layer is thicker) improves the drain-to-gate breakdown voltage by more than 30 percent compared to previous processes. For example, the current process described herein improves the drain-to-gate breakdown voltage of high-voltage device 206 by more than two volts or by more than approximately 30 percent (30%) compared to current manufacturing processes.

[0051] As indicated above, Figures 2A to 2O This is provided only as one or more instances. Other instances may differ from those provided. Figures 2A to 2O The examples described.

[0052] Figure 3 This is a diagram of the exemplary core device 300 described herein. As shown, the core device 300 may include the components described above. Figure 2F The ion-implanted substrate 310 is described above. The ion-implanted substrate 310 may include the combinations described above. Figure 2L The source region 320 and drain region 330 are described above. Figure 2J As described above, a thin oxide layer 340 may be formed or deposited on the surface of the ion-implanted substrate 310 and between the source region 320 and the drain region 330. Figure 2KAs described above, the gate 350 may be formed or deposited on the thin oxide layer 340. Figure 2K As described above, spacers 360 may be formed or deposited on the sides of the thin oxide layer 340 and the gate 350. Figure 2N The silicide layer 370 may be formed or deposited on the gate 350 and on portions of the source region 320 and drain region 330.

[0053] As indicated above, Figure 3 This is provided only as an example. Other instances may differ from the ones provided. Figure 3 The examples described.

[0054] Figure 4 This is a diagram of the exemplary I / O device 400 described herein. As shown, the I / O device 400 may include the combinations described above. Figure 2F The ion-implanted substrate 410 is described above. The ion-implanted substrate 410 may include the combinations described above. Figure 2L The source region 420 and drain region 430 are described above. Figure 2H As described above, an oxide layer 440 may be formed or deposited on the surface of the ion-implanted substrate 410 and between the source region 420 and the drain region 430. Figure 2K As described above, a gate 450 may be formed or provided on the oxide layer 440. Figure 2K As described above, spacers 460 may be formed on the sides of oxide layer 440 and gate 450. Figure 2N The silicide layer 470 may be formed or deposited on the gate 450 and on portions of the source region 420 and drain region 430.

[0055] As indicated above, Figure 4 This is provided only as an example. Other instances may differ from the ones provided. Figure 4 The examples described.

[0056] Figure 5 This is a diagram of an exemplary high-voltage device 500 described herein. As shown, the high-voltage device 500 may include the components described above. Figure 2A The substrate 505 may include the components described above. Figure 2C The p-type body region 510 and n-type drift region 515 are described above. Figure 2L The p-type body region 510 may include a source region 520, and the n-type drift region 515 may include a drain region 525. As described above... Figure 2H As described above, an oxide layer and a sacrificial oxide layer 530 may be formed or deposited on the surface of the substrate 505 and between the source region 520 and the drain region 525. Figure 2KAs described above, a gate 535 may be formed or provided on the oxide layer and the sacrificial oxide layer 530. Figure 2K As described above, spacers 540 may be formed or provided on the oxide layer, the sacrificial oxide layer 530, and the side of the gate 535. Figure 2M As described above, a protective oxide layer 545 may be formed or deposited on a portion of the gate 535, one of the spacers 540, a portion of the n-type drift region 515, and a portion of the drain region 525. Figure 2N The silicide layer 550 may be formed or deposited on portions of the gate 535, source region 520, and drain region 525, excluding the portion disposed below the protective oxide layer 545.

[0057] As indicated above, Figure 5 This is provided only as an example. Other instances may differ from the ones provided. Figure 5 The examples described.

[0058] Figure 6 This is a graph 600 illustrating an exemplary improvement in the drain-to-gate breakdown voltage of the exemplary semiconductor device described herein. As shown, the maskless method described herein improves the drain-to-gate breakdown voltage in the exemplary semiconductor device (e.g., in the high-voltage device 500 of the exemplary semiconductor device). For example, the method increases the drain-to-gate breakdown voltage by two or more volts, or by more than approximately thirty percent (30%), relative to current manufacturing processes. Therefore, the semiconductor device can be used for high-voltage operation (e.g., as a power semiconductor device).

[0059] As indicated above, Figure 6 This is provided only as an example. Other instances may differ from the ones provided. Figure 6 The examples described.

[0060] Figure 7 This is a diagram of exemplary components of device 700. Device 700 may correspond to a pre-cleaning tool 102, a deposition tool 104, an annealing tool 106, a photoresist tool 108, an etching tool 110, and / or a wafer / die transport device 112. In some embodiments, the pre-cleaning tool 102, deposition tool 104, annealing tool 106, photoresist tool 108, etching tool 110, and / or wafer / die transport device 112 may include one or more devices 700 and / or one or more components of device 700. Figure 7 As shown, device 700 may include bus 710, processor 720, memory 730, storage component 740, input component 750, output component 760 and communication interface 770.

[0061] Bus 710 includes components that allow communication between components of device 700. Processor 720 is implemented in hardware, firmware, or a combination of hardware and software. Processor 720 is a central processing unit (CPU), graphics processing unit (GPU), accelerated processing unit (APU), microprocessor, microcontroller, digital signal processor (DSP), field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), or another type of processing component. In some embodiments, processor 720 includes one or more processors that can be programmed to perform functions. Memory 730 includes random access memory (RAM), read-only memory (ROM), and / or another type of dynamic or static storage device (e.g., flash memory, magnetic memory, and / or optical memory) that stores information and / or instructions for use by processor 720.

[0062] Storage component 740 stores information and / or software related to the operation and use of device 700. For example, storage component 740 may include hard disk (e.g., magnetic disk, optical disk, magneto-optical disk and / or solid-state disk), compact disc (CD), digital versatile disc (DVD), floppy disk, cartridge, magnetic tape and / or another type of non-transitory computer-readable medium and a corresponding drive.

[0063] Input component 750 includes components that allow device 700 to receive information, such as via user input (e.g., a touchscreen display, keyboard, keypad, mouse, button, switch, and / or microphone). Alternatively, input component 750 may include sensors for sensing information (e.g., a global positioning system (GPS) component, accelerometer, gyroscope, and / or actuator). Output component 760 includes components that provide output information from device 700 (e.g., a display, speaker, and / or one or more light-emitting diodes (LEDs)).

[0064] The communication interface 770 includes transceiver-like components (e.g., a transceiver and / or separate receiver and transmitter) that enable the device 700 to communicate with other devices, for example, via a wired connection, a wireless connection, or a combination of wired and wireless connections. The communication interface 770 allows the device 700 to receive information from and / or provide information to another device. For example, the communication interface 770 may include an Ethernet interface, an optical interface, a coaxial interface, an infrared interface, a radio frequency (RF) interface, a universal serial bus (USB) interface, a wireless LAN interface, a cellular network interface, and / or similar interfaces.

[0065] Device 700 may implement one or more of the processes described herein. Device 700 may implement these processes based on software instructions stored in a non-transitory computer-readable medium (e.g., memory 730 and / or storage component 740) executed by processor 720. Computer-readable medium is defined herein as a non-transitory memory device. Memory devices include memory space within a single physical memory device or memory space distributed across multiple physical memory devices.

[0066] Software instructions can be read from another computer-readable medium or from another device into memory 730 and / or storage component 740 via communication interface 770. When executed, the software instructions stored in memory 730 and / or storage component 740 cause processor 720 to perform one or more of the processes described herein. Alternatively, hardwired circuitry can be used in place of or in combination with software instructions to perform one or more of the processes described herein. Therefore, the embodiments described herein are not limited to any particular combination of hardware circuitry and software.

[0067] Figure 5 The number and arrangement of components shown are provided as an example. In reality, with... Figure 5 Compared to the components shown, device 700 may include additional components, fewer components, different components, or components arranged differently. Alternatively, a set of components of device 700 (e.g., one or more components) may perform one or more functions described as being performed by another set of components of device 700.

[0068] Figure 8This is a flowchart of an exemplary process 800 associated with a maskless process for improving the drain-to-gate breakdown voltage in a semiconductor device. In some embodiments, Figure 8 One or more process blocks shown can be derived from devices (e.g., the combination of the above). Figure 1 One or more of the semiconductor processing tools described are used. Alternatively, or as another option, Figure 8 The one or more process blocks shown may be implemented by one or more components of device 700 (e.g., processor 720, memory 730, storage component 740, input component 750, output component 760 and / or communication interface 770).

[0069] like Figure 8 As shown, process 800 may include depositing a first oxide layer on a first portion, a second portion, and a third portion of a substrate, wherein the first oxide layer is a sacrificial oxide layer for the first and second portions of the substrate (block 805). For example, as described above, the device may deposit a first oxide layer on a first portion, a second portion, and a third portion of a substrate, wherein the first oxide layer is a sacrificial oxide layer for the first and second portions of the substrate.

[0070] like Figure 8 As further shown, process 800 may include depositing a first photoresist layer on a first oxide layer deposited on a third portion of the substrate (block 810). For example, as described above, the device may deposit a first photoresist layer on a first oxide layer deposited on a third portion of the substrate.

[0071] like Figure 8 As further shown, process 800 may include removing a first oxide layer from a first portion and a second portion of the substrate (block 815). For example, as described above, the device may remove the first oxide layer from the first portion and the second portion of the substrate.

[0072] like Figure 8 As further shown, process 800 may include removing a first photoresist layer from a first oxide layer deposited on a third portion of the substrate (block 820). For example, as described above, the device may remove the first photoresist layer from a first oxide layer deposited on a third portion of the substrate.

[0073] like Figure 8As further shown, process 800 may include depositing a second oxide layer on a first oxide layer deposited on a first portion and a second portion of the substrate and on a first oxide layer deposited on a third portion of the substrate, wherein the first oxide layer and the second oxide layer on the third portion of the substrate define a modified first oxide layer on the third portion of the substrate (block 825). For example, as described above, the device may deposit a second oxide layer on a first oxide layer deposited on a first portion and a second portion of the substrate and on a first oxide layer deposited on a third portion of the substrate, wherein the first oxide layer and the second oxide layer on the third portion of the substrate define a modified first oxide layer on the third portion of the substrate.

[0074] like Figure 8 As further shown, process 800 may include depositing a second photoresist layer on the modified first oxide layer and on the second oxide layer deposited on the second portion of the substrate (block 830). For example, as described above, the device may deposit a second photoresist layer on the modified first oxide layer and on the second oxide layer deposited on the second portion of the substrate.

[0075] like Figure 8 As further shown, process 800 may include removing a second oxide layer deposited on a first portion of the substrate (block 835). For example, as described above, the device may remove a second oxide layer deposited on a first portion of the substrate.

[0076] like Figure 8 As further shown, process 800 may include depositing a third oxide layer (block 840) on a first portion of the substrate. For example, as described above, the device may deposit a third oxide layer on a first portion of the substrate.

[0077] like Figure 8 As further shown, process 800 may include removing the second photoresist layer (block 845). For example, as described above, the device may remove the second photoresist layer.

[0078] like Figure 8 As further shown, process 800 may include providing a first device on a third oxide layer deposited on a first portion of the substrate (block 850). For example, as described above, the device may be provided on a third oxide layer deposited on a first portion of the substrate.

[0079] like Figure 8 As further shown, process 800 may include providing a second device on a second oxide layer deposited on a second portion of the substrate (block 855). For example, as described above, the device may be provided on a second oxide layer deposited on a second portion of the substrate.

[0080] like Figure 8As further shown, process 800 may include providing a third device on a modified first oxide layer deposited on a third portion of the substrate (block 860). For example, as described above, the device may be provided as a third device on a modified first oxide layer deposited on a third portion of the substrate.

[0081] Process 800 may include additional embodiments, such as any single embodiment or any combination of embodiments set forth below and / or in conjunction with one or more other processes set forth elsewhere herein.

[0082] In a first embodiment, process 800 includes implanting ions in a first and second portion of a substrate to form an ion-implanted portion of the substrate. In a second embodiment, either alone or in combination with the first embodiment, the third device is a high-voltage device. In a third embodiment, either alone or in combination with one or more of the first and second embodiments, the modified first oxide layer is an in-situ vapor-generating oxide layer. In a fourth embodiment, either alone or in combination with one or more of the first to third embodiments, providing a third device on a modified first oxide layer deposited on a third portion of the substrate includes: forming a gate with spacers on the modified first oxide layer; implanting ions to form a source region and a drain region in the third portion of the substrate and on opposite sides of the gate; depositing a protective oxide layer on portions of the gate and drain regions; and depositing a silicide layer on portions of the gate, source, and drain regions other than those covered by the protective oxide layer.

[0083] In the fifth embodiment, either alone or in combination with one or more of the first to fourth embodiments, process 800 includes a first device being a core device, a second device being an input / output device, and a third device being a high-voltage device. In the sixth embodiment, either alone or in combination with one or more of the first to fifth embodiments, the thickness of the modified first oxide layer is greater than the thickness of the second oxide layer, and the thickness of the second oxide layer is greater than the thickness of the third oxide layer.

[0084] although Figure 8 An exemplary block of process 800 is shown; however, in some embodiments, with Figure 8 Compared to the blocks shown in the diagram, process 800 may include additional blocks, fewer blocks, different blocks, or blocks arranged differently. Alternatively, two or more of the blocks in process 800 may be executed in parallel.

[0085] Figure 9 This is a flowchart of an exemplary process 900 associated with a maskless process for improving the drain-to-gate breakdown voltage in a semiconductor device. In some embodiments, Figure 9 One or more process blocks shown can be derived from devices (e.g., the combination of the above). Figure 1 One or more of the semiconductor processing tools described are used. Alternatively, or as another option, Figure 9 The one or more process blocks shown may be implemented by one or more components of device 700 (e.g., processor 720, memory 730, storage component 740, input component 750, output component 760 and / or communication component 770).

[0086] like Figure 9 As shown, process 900 may include depositing a first oxide layer on a first portion, a second portion, and a third portion of a substrate using in-situ vapor generation, wherein the first oxide layer is a sacrificial oxide layer for the first and second portions of the substrate (block 905). For example, as described above, the device may deposit a first oxide layer on a first portion, a second portion, and a third portion of a substrate using in-situ vapor generation, wherein the first oxide layer is a sacrificial oxide layer for the first and second portions of the substrate.

[0087] like Figure 9 As further shown, process 900 may include depositing a first photoresist layer on a first oxide layer disposed on a third portion of the substrate (block 910). For example, as described above, the device may deposit a first photoresist layer on a first oxide layer disposed on a third portion of the substrate.

[0088] like Figure 9 As further shown, process 900 may include removing a first oxide layer from a first portion and a second portion of the substrate (block 915). For example, as described above, the device may remove the first oxide layer from the first portion and the second portion of the substrate.

[0089] like Figure 9 As further shown, process 900 may include removing a first photoresist layer from a first oxide layer deposited on a third portion of the substrate (block 920). For example, as described above, the device may remove the first photoresist layer from a first oxide layer deposited on a third portion of the substrate.

[0090] like Figure 9As further shown, process 900 may include depositing a second oxide layer on a first oxide layer deposited on a first portion and a second portion of the substrate and on a first oxide layer deposited on a third portion of the substrate, wherein the first oxide layer and the second oxide layer on the third portion of the substrate define a modified first oxide layer on the third portion of the substrate (block 925). For example, as described above, the device may deposit a second oxide layer on a first oxide layer deposited on a first portion and a second portion of the substrate and on a first oxide layer deposited on a third portion of the substrate, wherein the first oxide layer and the second oxide layer on the third portion of the substrate define a modified first oxide layer on the third portion of the substrate.

[0091] like Figure 9 As further shown, process 900 may include depositing a second photoresist layer on the modified first oxide layer and on the second oxide layer deposited on the second portion of the substrate (block 930). For example, as described above, the device may deposit a second photoresist layer on the modified first oxide layer and on the second oxide layer deposited on the second portion of the substrate.

[0092] like Figure 9 As further shown, process 900 may include removing a second oxide layer deposited on a first portion of the substrate (block 935). For example, as described above, the device may remove a second oxide layer deposited on a first portion of the substrate.

[0093] like Figure 9 As further shown, process 900 may include depositing a third oxide layer (block 940) on a first portion of the substrate. For example, as described above, the device may deposit a third oxide layer on a first portion of the substrate.

[0094] like Figure 9 As further shown, process 900 may include removing the second photoresist layer (block 945). For example, as described above, the device may remove the second photoresist layer.

[0095] like Figure 9 As further shown, process 900 may include providing a first device (block 950) including a first gate, a first source region, and a first drain region on a third oxide layer on a first portion of the substrate. For example, as described above, the device may be a first device including a first gate, a first source region, and a first drain region provided on a third oxide layer on a first portion of the substrate.

[0096] like Figure 9As further shown, process 900 may include providing a second device (block 955) including a second gate, a second source region, and a second drain region on a second oxide layer on a second portion of the substrate. For example, as described above, the device may be a second device including a second gate, a second source region, and a second drain region provided on a second oxide layer on a second portion of the substrate.

[0097] like Figure 9 As further shown, process 900 may include providing a third device (block 960) comprising a third gate, a third source region, and a third drain region on a modified first oxide layer on a third portion of the substrate. For example, as described above, the device may be a third device comprising a third gate, a third source region, and a third drain region provided on a modified first oxide layer on a third portion of the substrate.

[0098] like Figure 9 As further shown, process 900 may include depositing a protective oxide layer on a portion of the third gate region and a portion of the third drain region (block 965). For example, as described above, the device may deposit a protective oxide layer on a portion of the third gate region and a portion of the third drain region.

[0099] Process 900 may include additional embodiments, such as any single embodiment or any combination of embodiments set forth below and / or in conjunction with one or more other processes set forth elsewhere herein.

[0100] In a first embodiment, process 900 includes defining a first gate, a first source region, and a first drain region for a core device of a semiconductor device; a second gate, a second source region, and a second drain region for an input / output device of the semiconductor device; and a third gate, a third source region, and a third drain region for a high-voltage device of the semiconductor device. In a second embodiment, either alone or in combination with the first embodiment, process 900 includes depositing a silicide layer over portions of the first gate, second gate, third gate, first source region, second source region, third source region, first drain region, second drain region, and third drain region.

[0101] In a third embodiment, process 900 includes depositing a silicide layer on portions of the third gate, third source region, and third drain region, excluding the portions of the third gate and third drain region covered by the protective oxide layer. In a fourth embodiment, the thickness of the modified first oxide layer is greater than the thickness of the second oxide layer, and the thickness of the second oxide layer is greater than the thickness of the third oxide layer, either alone or in combination with one or more of the first to third embodiments. In a fifth embodiment, the third device is a high-voltage device, either alone or in combination with one or more of the first to fourth embodiments.

[0102] although Figure 9 An exemplary block of process 900 is shown; however, in some embodiments, with Figure 9 Compared to the blocks shown in the diagram, process 900 may include additional blocks, fewer blocks, different blocks, or blocks arranged differently. Alternatively, two or more of the blocks in process 900 may be implemented in parallel.

[0103] In this manner, a method for manufacturing semiconductor devices is based on a maskless process to improve the drain-to-gate breakdown voltage in a high-voltage device 500 of the semiconductor device. The method may include using sacrificial oxide for the gate oxide region of the high-voltage device 500, which increases the thickness of the gate oxide region and prevents the formation of a thinner gate oxide region caused by pitting. Compared to current manufacturing processes, this method increases the drain-to-gate breakdown voltage of the high-voltage device 500 by more than two volts, or by more than approximately thirty percent (30%). Therefore, the semiconductor device can be used for high-voltage operation (e.g., as a power semiconductor device). Furthermore, this method can be used to simultaneously manufacture the core device 300, I / O devices, and the high-voltage device 500 without affecting the performance of such devices.

[0104] As described in more detail above, some embodiments described herein provide a method for manufacturing a semiconductor device. The method includes depositing a first oxide layer on a first portion, a second portion, and a third portion of a substrate, wherein the first oxide layer is a sacrificial oxide layer for the first and second portions of the substrate. The method includes depositing a first photoresist layer on the first oxide layer deposited on the third portion of the substrate. The method includes removing the first oxide layer from the first and second portions of the substrate. The method includes removing the first photoresist layer from the first oxide layer deposited on the third portion of the substrate. The method includes depositing a second oxide layer on the first and second portions of the substrate and on the first oxide layer deposited on the third portion of the substrate, wherein the first oxide layer and the second oxide layer on the third portion of the substrate define a modified first oxide layer on the third portion of the substrate. The method includes depositing a second photoresist layer on the modified first oxide layer and on the second oxide layer deposited on the second portion of the substrate. The method includes removing the second oxide layer deposited on the first portion of the substrate. The method includes depositing a third oxide layer on the first portion of the substrate. The method includes removing the second photoresist layer. The method includes providing a first device on a third oxide layer deposited on a first portion of the substrate. The method includes providing a second device on a second oxide layer deposited on a second portion of the substrate. The method includes providing a third device on a modified first oxide layer deposited on a third portion of the substrate. In some embodiments, the method further includes implanting ions in the first and second portions of the substrate to form an ion-implanted portion of the substrate. In some embodiments, the third device is a high-voltage device. In some embodiments, the modified first oxide layer is an in-situ vapor-generating oxide layer. In some embodiments, providing a third device on the modified first oxide layer deposited on the third portion of the substrate includes: forming a gate with spacers on the modified first oxide layer; implanting ions to form a source region and a drain region in the third portion of the substrate and on opposite sides of the gate; depositing a protective oxide layer on portions of the gate and drain regions; and depositing a silicide layer on portions of the gate, source, and drain regions other than those covered by the protective oxide layer. In some embodiments, the first device is a core device, the second device is an input / output device, and the third device is a high-voltage device.In some embodiments, the thickness of the modified first oxide layer is greater than the thickness of the second oxide layer, and the thickness of the second oxide layer is greater than the thickness of the third oxide layer.

[0105] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a substrate comprising a first portion, a second portion, and a third portion. The semiconductor device includes a first device located on the first portion of the substrate. The semiconductor device includes a second device located on the second portion of the substrate. The semiconductor device includes a third device located on the third portion of the substrate and includes: an oxide layer located on the third portion, wherein the thickness of the oxide layer is greater than the thickness of the oxide layers used for the first and second devices; a gate located on the oxide layer; a set of spacers located on opposite sides of the gate; a source region located on one side of the gate in the third portion of the substrate; a drain region located on the other side of the gate in the third portion of the substrate; and a protective oxide layer located on portions of the gate and the drain region. In some embodiments, the semiconductor device further includes: a silicide layer located over portions of the gate, the source region, and the drain region. In some embodiments, the protective oxide layer covers portions of the third portion of the substrate and covers the entire surface of the spacers in the set of spacers. In some embodiments, the third device further includes a silicide layer located over portions of the gate, source, and drain regions, excluding portions of the gate and drain regions covered by the protective oxide layer. In some embodiments, the first device is a core device, the second device is an input / output device, and the third device is a high-voltage device. In some embodiments, the third portion of the substrate includes a p-type body region and an n-type drift region, the source region being located in the p-type body region and the drain region being located in the n-type drift region. In some embodiments, the third device is a high-voltage device.

[0106] As described in more detail above, some embodiments described herein provide a method for manufacturing a semiconductor device. The method includes depositing a first oxide layer on a first portion, a second portion, and a third portion of a substrate using in-situ vapor generation, wherein the first oxide layer is a sacrificial oxide layer for the first and second portions of the substrate. The method includes depositing a first photoresist layer on the first oxide layer disposed on the third portion of the substrate. The method includes removing the first oxide layer from the first and second portions of the substrate. The method includes removing the first photoresist layer from the first oxide layer deposited on the third portion of the substrate. The method includes depositing a second oxide layer on the first and second portions of the substrate and on the first oxide layer deposited on the third portion of the substrate, wherein the first oxide layer and the second oxide layer on the third portion of the substrate define a modified first oxide layer on the third portion of the substrate. The method includes depositing a second photoresist layer on the modified first oxide layer and on the second oxide layer deposited on the second portion of the substrate. The method includes removing the second oxide layer deposited on the first portion of the substrate. The method includes depositing a third oxide layer on the first portion of the substrate. The method includes removing the second photoresist layer. The method includes providing a first device including a first gate, a first source region, and a first drain region on the third oxide layer on the first portion of the substrate. The method includes providing a second device including a second gate, a second source region, and a second drain region on the second oxide layer on the second portion of the substrate. The method includes providing a third device including a third gate, a third source region, and a third drain region on the modified first oxide layer on the third portion of the substrate. The method includes depositing a protective oxide layer on portions of the third gate and the third drain region. In some embodiments, the first gate, the first source region, and the first drain region define core devices for the semiconductor device; the second gate, the second source region, and the second drain region define input / output devices for the semiconductor device; and the third gate, the third source region, and the third drain region define high-voltage devices for the semiconductor device. In some embodiments, a silicide layer is deposited over portions of the first gate, the second gate, the third gate, the first source region, the second source region, the third source region, the first drain region, the second drain region, and the third drain region.In some embodiments, the method further includes depositing a silicide layer over portions of the third gate, the third source region, and the third drain region, excluding portions of the third gate and the third drain region covered by the protective oxide layer. In some embodiments, the thickness of the modified first oxide layer is greater than the thickness of the second oxide layer, and the thickness of the second oxide layer is greater than the thickness of the third oxide layer. In some embodiments, the third device is a high-voltage device.

[0107] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

[0108] [Explanation of Symbols]

[0109] 100: Environment

[0110] 102: Pre-cleaning tools

[0111] 104: Sedimentation Tools

[0112] 106: Annealing tools

[0113] 108: Photoresist Tools

[0114] 110: Etching tools

[0115] 112: Wafer / Die Transport Device

[0116] 114: Pre-cleaning chamber

[0117] 116: Gas Source

[0118] 118: Plasma Source

[0119] 120: Heat source

[0120] 200: Exemplary Operation

[0121] 202, 300: Core components

[0122] 204, 400: I / O devices

[0123] 206, 500: High-voltage devices

[0124] 208, 310, 410, 505: Substrates

[0125] 210: Pad oxide layer

[0126] 212: Silicon nitride layer for solder pads

[0127] 214, 220, 226: Photoresist layer

[0128] 216, 510: p-type body region

[0129] 217, 515: n-type drift zone

[0130] 218, 530: Sacrificial oxide layer

[0131] 222: Oxide layer

[0132] 224: Oxide layer / Sacrificial oxide layer

[0133] 228, 340: Thin oxide layer

[0134] 230, 350, 450, 535: Gate

[0135] 232, 360, 460, 540: Spacers

[0136] 234, 320, 420, 520: Source regions

[0137] 236, 330, 430, 525: Drain region

[0138] 238, 545: Protective oxide layer

[0139] 240, 370, 470, 550: silicide layer

[0140] 440: Oxide layer

[0141] 600: Curve Graph

[0142] 700: Device

[0143] 710: Bus

[0144] 720: Processor

[0145] 730: Memory

[0146] 740: Storage Component

[0147] 750: Input component

[0148] 760: Output Component

[0149] 770: Communication interface

[0150] 800, 900: Process

[0151] 805, 810, 815, 820, 825, 830, 835, 840, 845, 850, 855, 860, 910, 915, 920, 925, 930, 935, 940, 945, 950, 955, 960, 965: Square

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The method includes: A first oxide layer is deposited on a first portion, a second portion, and a third portion of a substrate, wherein the first oxide layer is a sacrificial oxide layer for the first portion and the second portion of the substrate; A first photoresist layer is deposited on the first oxide layer deposited on the third portion of the substrate; Remove the first oxide layer from the first portion and the second portion of the substrate; Remove the first photoresist layer from the first oxide layer deposited on the third portion of the substrate; A second oxide layer is deposited on the first and second portions of the substrate and on the first oxide layer deposited on the third portion of the substrate, wherein the first oxide layer and the second oxide layer on the third portion of the substrate define a modified first oxide layer on the third portion of the substrate. A second photoresist layer is deposited on the modified first oxide layer and on the second oxide layer deposited on the second portion of the substrate; Remove the second oxide layer deposited on the first portion of the substrate; A third oxide layer is deposited on the first portion of the substrate; Remove the second photoresist layer; A first device is provided on the third oxide layer deposited on the first portion of the substrate; A second device is provided on the second oxide layer deposited on the second portion of the substrate; and A third device is provided on the modified first oxide layer deposited on the third portion of the substrate.

2. The method according to claim 1, characterized in that, Further includes: Ions are implanted in the first and second portions of the substrate to form ion-implanted portions of the substrate.

3. The method according to claim 1, characterized in that, The third device is a high-voltage device.

4. The method according to claim 1, characterized in that, The modified first oxide layer is an in-situ steam-generated oxide layer.

5. The method according to claim 1, characterized in that, Providing a third device on the modified first oxide layer deposited on the third portion of the substrate includes: A gate with spacers is formed on the modified first oxide layer; Implanted ions to form source and drain regions in the third portion of the substrate and on the opposite side of the gate; A protective oxide layer is deposited on a portion of the gate region and a portion of the drain region; and A silicide layer is deposited on portions of the gate, source, and drain regions, excluding the portions of the gate and drain regions covered by the protective oxide layer.

6. The method according to claim 1, characterized in that, in The first device is the core device. The second device is an input / output device, and The third device is a high-voltage device.

7. The method according to claim 1, characterized in that, The thickness of the modified first oxide layer is greater than the thickness of the second oxide layer, and the thickness of the second oxide layer is greater than the thickness of the third oxide layer.

8. A method for manufacturing a semiconductor device, characterized in that, The method includes: A first oxide layer is deposited on a first portion, a second portion, and a third portion of a substrate using in-situ vapor generation, wherein the first oxide layer is a sacrificial oxide layer for the first portion and the second portion of the substrate; A first photoresist layer is deposited on the first oxide layer disposed on the third portion of the substrate; Remove the first oxide layer from the first portion and the second portion of the substrate; Remove the first photoresist layer from the first oxide layer deposited on the third portion of the substrate; A second oxide layer is deposited on the first and second portions of the substrate and on the first oxide layer deposited on the third portion of the substrate, wherein the first oxide layer and the second oxide layer on the third portion of the substrate define a modified first oxide layer on the third portion of the substrate. A second photoresist layer is deposited on the modified first oxide layer and on the second oxide layer deposited on the second portion of the substrate; Remove the second oxide layer deposited on the first portion of the substrate; A third oxide layer is deposited on the first portion of the substrate; Remove the second photoresist layer; A first device comprising a first gate, a first source region, and a first drain region is provided on the third oxide layer on the first portion of the substrate; A second device comprising a second gate, a second source region, and a second drain region is provided on the second oxide layer on the second portion of the substrate; A third device comprising a third gate, a third source region, and a third drain region is provided on the modified first oxide layer on the third portion of the substrate; and A protective oxide layer is deposited on the portion of the third gate and the portion of the third drain region.

9. The method according to claim 8, characterized in that, The first gate, the first source region, and the first drain region define the core device of the semiconductor device; the second gate, the second source region, and the second drain region define the input / output device of the semiconductor device; and the third gate, the third source region, and the third drain region define the high-voltage device of the semiconductor device.

10. The method according to claim 8, characterized in that, Further includes: A silicide layer is deposited on portions of the first gate, the second gate, the third gate, the first source region, the second source region, the third source region, the first drain region, the second drain region, and the third drain region.

11. The method according to claim 8, characterized in that, Further includes: A silicide layer is deposited on portions of the third gate, the third source region, and the third drain region, excluding the portions of the third gate and the third drain region covered by the protective oxide layer.

12. The method according to claim 8, characterized in that, The thickness of the modified first oxide layer is greater than the thickness of the second oxide layer, and the thickness of the second oxide layer is greater than the thickness of the third oxide layer.

13. The method according to claim 8, characterized in that, The third device is a high-voltage device.

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