Semiconductor wafer

Abstract

A semiconductor wafer includes a substrate including a boundary defined by a substrate termination edge; an active region isolated from the substrate termination edge by a barrier region; and a charge redistribution path on the barrier region, wherein the charge redistribution path is coupled to an electrical potential. The semiconductor wafer of the present application has improved strength.

Description

[0001] This application is a divisional application of Chinese Patent Invention Application No. 201880077213.0, filed on November 2, 2018, entitled "Semiconductor Wafer with Improved Strength". Technical Field

[0002] This disclosure relates to semiconductor devices, and more particularly to semiconductor devices with increased strength and methods of manufacturing the same. Background Technology

[0003] Many semiconductor devices can be fabricated together on a semiconductor wafer. For illustrative purposes, Figure 1 A conventional semiconductor wafer 10 is shown, comprising a substrate 12, a first passivation layer 14 above the substrate 12, a second passivation layer 16 above the first passivation layer 14, a third passivation layer 18 above the second passivation layer 16, and a plurality of contact pads 20. The boundary of the substrate 12 is defined by a substrate termination edge 22. The substrate 12 includes an active region 24 and a barrier region 26 surrounding the active region 24, in which a plurality of semiconductor devices (not shown) may be provided, for example, by one or more implantation regions and one or more metallization layers. The barrier region 26 electrically isolates the active region 24 from the substrate termination edge 22 and thus from the surrounding environment. The barrier region 26 is generally configured as an implant to reduce the conductivity of the substrate 12, but may also be an etched mesa or shallow trench isolation (STI). Typically, the barrier region 26 extends from an inner barrier region termination edge 28 to the substrate termination edge 22 to form a barrier around the perimeter of the conventional semiconductor wafer 10.

[0004] A first passivation layer 14 is disposed above the active region 24 and extends over the barrier region 26 to a passivation termination edge 30. A second passivation layer 16 is disposed above the first passivation layer 14 and similarly extends to the passivation termination edge 30. A third passivation layer 18 is disposed above the second passivation layer 16 and similarly extends to the passivation termination edge 30. Contact pads 20 may be disposed on the second passivation layer 16 and exposed to the external environment via one or more openings in the third passivation layer 18. Although not shown, metallization layers within the first and second passivation layers 14 and 16 may couple the contact pads to one or more semiconductor devices in the active region 24. The passivation termination edge 30 is offset inward by a distance D from the substrate termination edge 22.

[0005] The first passivation layer 14, the second passivation layer 16, and the third passivation layer 18 are configured to electrically and physically isolate the semiconductor device in the active region 24 from the surrounding environment. However, when the conventional semiconductor wafer 10 is in a humid environment and subjected to high temperature and / or bias, one or more of the first passivation layer 14, the second passivation layer 16, and the third passivation layer 18 may delaminate from the underlying layer to allow moisture to penetrate into the active region 24. This can lead to failure of the conventional semiconductor wafer 10. This problem is exacerbated by the electric field generated by operating one or more semiconductor devices in the active region 24, which can be very high at the passivation termination edge 30. This electric field may attract moisture from the passivation termination edge 30 toward the active region 24, thereby causing failure of the conventional semiconductor wafer 10 as described above.

[0006] In view of the above, there is a need for a semiconductor wafer with improved strength and a method for manufacturing the same. Summary of the Invention

[0007] This disclosure relates to semiconductor devices, and more particularly to semiconductor devices with increased strength and methods of manufacturing the same. In one embodiment, a semiconductor wafer includes a substrate, a first passivation layer over the substrate, and a first passivation layer and a second passivation layer over the substrate. The substrate has a boundary defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inwardly disposed from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inwardly disposed from the substrate termination edge by a second distance. The second distance is less than the first distance, such that the second passivation layer overlaps with the first passivation layer. By making the second passivation layer overlap with the first passivation layer, the strength of the semiconductor wafer can be significantly increased because moisture penetration through the first and second passivation layers is prevented.

[0008] In one embodiment, a method for manufacturing a semiconductor wafer includes the steps of: setting a substrate; setting a first passivation layer over the substrate; and setting a second passivation layer over the first passivation layer. The substrate has a boundary defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inwardly offset by a first distance from the substrate termination edge. The second passivation layer is disposed over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inwardly offset by a second distance from the substrate termination edge. The second distance is less than the first distance, such that the second passivation layer overlaps with the first passivation layer. By making the second passivation layer overlap with the first passivation layer, the strength of the semiconductor wafer can be significantly increased because moisture penetration through the first and second passivation layers is prevented.

[0009] After reading the following detailed description of preferred embodiments in conjunction with the accompanying drawings, those skilled in the art will understand the scope of this disclosure and recognize its additional aspects. Attached Figure Description

[0010] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0011] Figure 1 A conventional semiconductor wafer is shown.

[0012] Figures 2 to 13 Semiconductor wafers according to various embodiments of the present disclosure are shown.

[0013] Figure 14 This is a flowchart describing a method for manufacturing a semiconductor wafer according to various embodiments of the present disclosure. Detailed Implementation

[0014] The embodiments described below represent the necessary information enabling those skilled in the art to practice the embodiments, and illustrate the best mode for practicing the embodiments. Those skilled in the art will understand the concepts of this disclosure and recognize the application of these concepts, which are not specifically addressed herein, when reading the following description in conjunction with the accompanying drawings. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

[0015] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0016] It should be understood that when an element, such as a layer, region, or substrate, is referred to as being "on" or extending "on" another element, it may be directly on or directly extending to that other element, or intermediate elements may be present. Conversely, when an element is referred to as being "directly on" or "directly extending" to another element, no intermediate elements are present. Similarly, it should be understood that when an element, such as a layer, region, or substrate, is referred to as being "above" or extending "above" another element, it may be directly above or directly extending above that other element, or intermediate elements may be present. Conversely, when an element is referred to as being "directly above" or "directly extending" above another element, no intermediate elements are present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected to or coupled to that other element, or intermediate elements may be present. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, no intermediate elements are present.

[0017] Relative terms, such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical”, may be used herein to describe the relationship between one element, layer, or region and another element, layer, or region as shown in the figures. It should be understood that these terms, and those discussed above, are intended to include different orientations of the device other than those shown in the figures.

[0018] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the terms “comprising,” “including,” “containing,” and / or “having” as used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0019] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that the terms used herein shall be interpreted as having the same meaning as they have in the context of this specification and in the relevant art, and shall not be interpreted as having an idealized or overly formal meaning unless expressly defined herein.

[0020] Figure 2A semiconductor wafer 32 according to an embodiment of the present disclosure is shown. The semiconductor wafer 32 includes a substrate 34, a first passivation layer 36 over the substrate 34, a second passivation layer 38 over the substrate 34, a third passivation layer 40 over the second passivation layer 38, and a plurality of contact pads 42. The boundary of the substrate 34 is defined by a substrate termination edge 44. The substrate 34 includes an active region 46 and a barrier region 48 surrounding the active region 46, in which a plurality of semiconductor devices (not shown) may be provided, for example, by one or more implantation regions and one or more metallization layers. The barrier region 48 electrically isolates the active region 46 from the substrate termination edge 44 and thus from the surrounding environment. The barrier region 48 may be configured as an implantation region (e.g., a region implanted with nitrogen, hydrogen, helium, magnesium, zirconium, krypton, argon, and / or iron) that reduces the conductivity of the substrate 34, and may extend from the inner edge 50 of the barrier region to the substrate termination edge 44. Semiconductor devices can include any type of device, such as diodes, high electron mobility transistors (HEMTs), field-effect transistors (FETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), etc.

[0021] A first passivation layer 36 is disposed over the active region 46 and extends over the barrier region 48 to a first passivation termination edge 52. A second passivation layer 38 is disposed over the first passivation layer 36 and the substrate 34 and extends to a second passivation termination edge 54. A third passivation layer 40 is disposed over the second passivation layer 38 and similarly extends to the second passivation termination edge 54. Contact pads 42 may be disposed on the second passivation layer 38 and exposed to the external environment via one or more openings in the third passivation layer 40. Although not shown, metallization layers within the first passivation layer 36 and the second passivation layer 38 may couple the contact pads to one or more semiconductor devices in the active region 46.

[0022] The first passivation termination edge 52 is moved inward from the substrate termination edge 44 by a first distance D1. In various embodiments, the first distance D1 can be between 1 μm and 150 μm. The second passivation termination edge 54 is moved inward from the substrate termination edge 44 by a second distance D2. In various embodiments, the second distance D2 can be between 0.5 μm and 50 μm. Notably, the second distance D2 is smaller than the first distance D1, causing the second passivation layer 38 and the third passivation layer 40 to overlap with the first passivation layer 36. Therefore, the first passivation termination edge 52 is shielded from the surrounding environment by the second passivation layer 38 and the third passivation layer 40. By setting the first passivation layer 36, the second passivation layer 38, and the third passivation layer 40 in this way, the strength of the semiconductor wafer 32 is increased by preventing moisture from entering the active region 46. In one embodiment, the difference between the first distance D1 and the second distance D2 is greater than 0.5 μm and less than 100 μm. Typically, the difference between the first distance D1 and the second distance D2 can be greater than x and less than y. In various embodiments, x can be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, and up to but not including 50 μm. For any of these embodiments, y can be 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, and up to 100 μm.

[0023] Although only three passivation layers are shown, the principles discussed herein can be applied to any number of passivation layers without departing from the principles of this disclosure. Furthermore, the first passivation layer 36, the second passivation layer 38, and the third passivation layer 40 may themselves comprise multiple layers. Finally, the principles of this disclosure can be applied to as few as two passivation layers. That is, the third passivation layer 40 is optional in the embodiments discussed above. Additionally, although the substrate 34 is shown as a single layer, the substrate 34 may comprise multiple layers (e.g., a carrier layer and one or more epitaxial layers on top of the carrier layer). In these embodiments, the barrier region 48 may be provided by one or more epitaxial layers instead of a carrier layer. In one embodiment, the substrate 34 may comprise gallium nitride (GaN). In other embodiments, the substrate 34 may comprise silicon (Si), silicon carbide (SiC), or any other semiconductor material system.

[0024] In one embodiment, the first passivation layer 36, the second passivation layer 38, and the third passivation layer 40 comprise stoichiometric and non-stoichiometric formulations of alumina, silicon dioxide, silicon nitride, silicon oxynitride, silicon oxide, and / or zirconium oxide. Furthermore, in some embodiments, the compositions of the first passivation layer 36, the second passivation layer 38, and the third passivation layer 40 may be alternated. Applying passivation layers separately and / or alternating the compositions of the passivation layers can reduce the presence of defects (e.g., pinholes) in layers that span more than one layer, thereby preventing the active region 46 from being exposed to the external environment.

[0025] Figure 3 A top view of a semiconductor wafer 32 according to an embodiment of the present disclosure is shown, illustrating the relative positions of a first passivation termination edge 52 and a second passivation termination edge 54 relative to a substrate termination edge 44. As shown, the first passivation termination edge 52 and the second passivation termination edge 54 are moved inward from the periphery of the semiconductor wafer 32 such that the second passivation termination edge 54 is nested within the substrate termination edge 44 and the first passivation termination edge 52 is nested within the second passivation termination edge 54.

[0026] Figure 4 A semiconductor wafer 32 according to an additional embodiment of the present disclosure is shown. Figure 4 The semiconductor wafer 32 shown is Figure 2 The images shown are basically the same, except... Figure 4 The third passivation layer 40 extends over the second passivation layer 38 to a third passivation termination edge 56, which is moved inward by a third distance D3 from the substrate termination edge 44. The third distance D3 is smaller than the second distance D2, causing the third passivation layer 40 to overlap with the first passivation layer 36 and the second passivation layer 38. This further increases the strength of the semiconductor wafer 32 because it provides a potential barrier between the second passivation termination edge 54 and the surrounding environment, and an additional barrier between the first passivation termination edge 52 and the surrounding environment. Because the passivation layers can be separately disposed and / or alternately arranged in composition, these layers can resist delamination under different conditions, which can prevent moisture ingress over a wide range of environmental conditions.

[0027] exist Figure 4 In the illustrated embodiment, the first distance D1 can be larger, such that it can be between 1.5 μm and 250 μm. The second distance D2 can be between 1 μm and 150 μm. The third distance can be between 0.5 μm and 50 μm. In one embodiment, the difference between the first distance D1 and the second distance D2 is greater than 5 μm and less than 50 μm. Similarly, the difference between the second distance D2 and the third distance D3 is greater than 0.5 μm and less than 50 μm. Typically, the difference between the first distance D1 and the second distance D2, and the difference between the second distance D2 and the third distance D3, can be greater than x and less than y. In various embodiments, x can be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, and at most but not including 50 μm. For any of these embodiments, y can be 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, and up to 100 μm.

[0028] Figure 5A top view of a semiconductor wafer 32 according to an embodiment of the present disclosure is shown, illustrating the relative positions of a first passivation termination edge 52, a second passivation termination edge 54, and a third passivation termination edge 56 relative to a substrate termination edge 44. As shown, the first passivation termination edge 52, the second passivation termination edge 54, and the third passivation termination edge 56 are moved inward from the periphery of the semiconductor wafer 32 such that the third passivation termination edge 56 is nested within the substrate termination edge 44, the second passivation termination edge 54 is nested within the third passivation termination edge 56, and the first passivation termination edge 52 is nested within the second passivation termination edge 54.

[0029] As mentioned above, the establishment of an electric field at the termination edge of any passivation layer can facilitate the entry of moisture and / or ions, as it can attract particles towards the active region 46, thereby promoting their delamination. To mitigate this effect, Figure 6 It shows Figure 2 An enlarged view of one side of the semiconductor wafer 32 shown also includes a charge redistribution path 58. The charge redistribution path 58 is configured as a metal layer on the substrate 34 between a first passivation termination edge 52 and a second passivation termination edge 54. Although not shown, in some embodiments, the charge redistribution path 58 may be disposed within the first passivation termination edge 52 or may traverse the first passivation termination edge 52 and / or the second passivation termination edge 54. In one embodiment, the charge redistribution path 58 may be disposed around the periphery of the semiconductor wafer 32 and coupled to a fixed potential, such as ground.

[0030] In addition to mitigating moisture and / or ion ingress into the active regions of semiconductor wafer 32, charge redistribution path 58 can also provide other operational benefits. Although Figure 6The charge redistribution path 58 shown forms a loop around the periphery of the semiconductor wafer 32, but the charge redistribution path 58 can be positioned in any region where charge redistribution may be beneficial (e.g., to prevent moisture and / or ion ingress), and therefore can be positioned in any shape at any location on the semiconductor wafer (e.g., above a portion of the active region, bisecting the active region, etc.). In some embodiments, the charge redistribution path 58 forms a closed path, while in other embodiments, the charge redistribution path 58 may remain open. Furthermore, although the charge redistribution path 58 is shown as a metal layer on the substrate 34 between the substrate 34 and the first passivation layer 36, without departing from the principles described herein, the charge redistribution path 58 can be positioned on the opposite side of the substrate 34 (opposite to the first passivation layer 36), on the first passivation layer 36, on the second passivation layer 38, on the third passivation layer 40, or on any other layer. In various embodiments, the location of the charge redistribution path 58 may vary in different regions of the device. For example, one lateral edge of the semiconductor wafer 32 may be reserved for the gate contact of a semiconductor device in its active region 46 and is therefore referred to as the "gate side," while the opposite lateral edge of the semiconductor wafer may be reserved for the drain contact of a semiconductor device in its active region 46 and is therefore referred to as the "drain side." Since the electric fields in these different portions of the semiconductor wafer 32 can be different, the charge redistribution path 58 can be configured in a first pattern at a first location on one of the substrate 34, the first passivation layer 36, the second passivation layer 38, the third passivation layer 40, or any other layer on the gate side of the semiconductor wafer 32, and in a second pattern at a second location on one of the substrate 34, the first passivation layer 36, the second passivation layer 38, the third passivation layer 40, or any other layer on the drain side of the semiconductor wafer. Typically, the specific pattern and location of the charge redistribution path 58 can be different for different regions of the semiconductor wafer 32 because the fields in these different regions can be different and therefore may need to be redistributed in different ways to improve the performance of the semiconductor wafer 32.

[0031] Figure 7 A top view of a semiconductor wafer 32 including a charge redistribution path 58 according to an embodiment of the present disclosure is shown. As shown, the charge redistribution path 58 is shifted inward from the periphery of the semiconductor wafer 32 between a first passivation termination edge 52 and a second passivation termination edge 54. Provided as Figure 6 and Figure 7The charge redistribution path 58 shown reduces the electric field at the first passivation termination edge 52 and the second passivation termination edge 54, which in turn reduces moisture and ion ingress and increases the strength of the semiconductor wafer 32. The charge redistribution path 58 may be a metal layer comprising alloys of aluminum, titanium, silicon, nickel and platinum, alloys of titanium, aluminum, nickel and gold, alloys of titanium, nickel and aluminum, alloys of germanium, nickel and aluminum, and any other metal system for forming electrical contact with an accompanying active device.

[0032] Figure 8 An embodiment according to this disclosure is shown. Figure 4 An enlarged view of one side of the semiconductor wafer 32 shown also includes a charge redistribution path 58. The charge redistribution path 58 is configured as a metal layer on the substrate 34 between a first passivation termination edge 52 and a second passivation termination edge 54. Although not shown, in some embodiments, the charge redistribution path 58 may be disposed within the first passivation termination edge 52, between the second passivation termination edge 54 and a third passivation termination edge 56, or across the first passivation termination edge 52, the second passivation termination edge 54, and the third passivation termination edge 56. The charge redistribution path 58 may be disposed around the periphery of the semiconductor wafer 32 and coupled to a fixed potential, such as ground.

[0033] Figure 9 A top view of a semiconductor wafer 32 according to an embodiment of the present disclosure is shown, which includes a charge redistribution path 58. As shown, the charge redistribution path 58 is shifted inward from the periphery of the semiconductor wafer 32 between a first passivation termination edge 52 and a second passivation termination edge 54. Provided as Figure 8 and Figure 9 The charge redistribution path 58 shown reduces the electric field at the first passivation termination edge 52, the second passivation termination edge 54, and the third passivation termination edge 56, which in turn reduces moisture ingress and increases the strength of the semiconductor wafer 32. The charge redistribution path 58 can be a metal layer comprising alloys of aluminum, titanium, silicon, nickel, and platinum; alloys of titanium, aluminum, nickel, and gold; alloys of titanium, nickel, and aluminum; alloys of germanium, nickel, and aluminum; and any other metal system for forming electrical contact with an accompanying active device.

[0034] Figure 10 An embodiment according to this disclosure is shown. Figure 2The enlarged view of one side of the semiconductor wafer 32 shown also includes a charge redistribution path 60. The charge redistribution path 60 is preferably configured as a conductive (i.e., unimplanted or conductively implanted) region of the substrate 34 outside the barrier region 48. Specifically, the barrier region 48 does not extend between the inner edge 50 of the barrier region and the substrate termination edge 44, but rather between the inner edge 50 of the barrier region and the outer edge 62 of the barrier region, which is moved inward from the substrate termination edge 44 by a third distance D3. The region including the charge redistribution path 60 may also be partially implanted with a conductive dopant to have a higher conductivity than the surface conductive portion of the active region. The third distance D3 may be less than the first distance D1 between the first passivation termination edge 52 and the substrate termination edge 44 and greater than the second distance D2 between the second passivation termination edge 54 and the substrate termination edge 44. The conductive region of the substrate 34 forming the charge redistribution path 60 can be coupled to ground via the substrate 34 or via contact pads that are directly contacting the top-side ground or non-zero bias. For example, the surface conductive region of substrate 34 can be connected to ground via contact pads (not shown) on the back side of substrate 34. This can be achieved by applying an additional mask when injecting the barrier region 48, as described below. Without departing from the principles of this paper, the charge redistribution path 60 can be configured in any number of shapes and can be configured as a closed or open path.

[0035] Figure 11 A top view of a semiconductor wafer 32 according to an embodiment of the present disclosure is shown, which includes a charge redistribution path 60. As shown, the charge redistribution path 60 serves as a conductive region or an unimplanted region on the outer side of a barrier region 48. Although not shown, the outer edge 62 of the barrier region may be located within a first passivation termination edge 52 (i.e., a third distance D3 may be greater than a first distance D1) or at any other point between the first passivation termination edge 52 and a second passivation termination edge 54. Provided as Figure 10 and Figure 11 The charge redistribution path 60 shown reduces the electric field at the first passivation termination edge 52 and the second passivation termination edge 54, which in turn reduces moisture ingress and increases the strength of the semiconductor wafer 32. Although the charge redistribution path 60 can be an unimplanted region, it can also be implanted as a conductive region, for example using silicon (Si), calcium (Ca), oxygen (O), germanium (Ge), or carbon (C).

[0036] Figure 12 An embodiment according to this disclosure is shown. Figure 4The enlarged view of one side of the semiconductor wafer 32 shown also includes a charge redistribution path 60. The charge redistribution path 60 is configured as a conductive (i.e., unimplanted) region of the substrate 34 outside the barrier region 48. Specifically, the barrier region 48 does not extend between the inner edge 50 of the barrier region and the substrate termination edge 44, but rather between the inner edge 50 of the barrier region and the outer edge 62 of the barrier region, which is a fourth distance D4 inward from the substrate termination edge 44. This fourth distance D4 may be less than a first distance D1 between the first passivation termination edge 52 and the substrate termination edge 44 and greater than a second distance D2 between the second passivation termination edge 54 and the substrate termination edge 44. The conductive region of the substrate 34 forming the charge redistribution path 60 can be coupled to ground via the substrate 34. For example, the conductive region of the substrate 34 can be connected to ground via contact pads (not shown) on the back side of the substrate 34.

[0037] Figure 13 A top view of a semiconductor wafer 32 according to an embodiment of the present disclosure is shown, including a charge redistribution path 60. As shown, the charge redistribution path 60 serves as a conductive region or an unimplanted region on the outer side of a barrier region 48. Although not shown, the outer edge 62 of the barrier region may be located inside a first passivation termination edge 52 (i.e., a fourth distance D4 may be greater than a first distance D1), may be located between a second passivation termination edge 54 and a third passivation termination edge 56 (i.e., a fourth distance D4 may be greater than a third distance D3 and less than a second distance D2), or may be located at any other point between the first passivation termination edge 52 and the second passivation termination edge 54. Provided as Figure 12 and Figure 13 The charge redistribution path 60 shown reduces the electric field at the first passivation termination edge 52, the second passivation termination edge 54, and the third passivation termination edge 56, which in turn reduces moisture ingress and increases the strength of the semiconductor wafer 32. Although the charge redistribution path 60 can be an unimplanted region, it can also be implanted as a conductive region, for example using silicon (Si), calcium (Ca), oxygen (O), germanium (Ge), or carbon (C).

[0038] While the above discussion focused on charge redistribution paths in semiconductor wafers, the principles described in this article can also be applied to other devices, such as monolithic microwave integrated circuits.

[0039] Figure 14This is a flowchart illustrating a method for manufacturing a semiconductor wafer according to an embodiment of the present disclosure. First, a substrate is formed (step 100). Then, a barrier region is formed around an active region in the substrate (step 102). This may include, for example, implanting a region of the substrate such that it is no longer conductive. This can be achieved by implanting the substrate with nitrogen (N), hydrogen (H), helium (He), magnesium (Mg), zirconium (Zr), krypton (Kr), argon (Ar), and iron (Fe), but may also be by etching mesa or shallow trench isolation (STI). In embodiments where the charge redistribution path is set in a conductive region or an unimplanted region outside the barrier region, this may include applying an additional mask during the implantation of the barrier region such that it terminates at an outer edge of the barrier region that is moved inward from the termination edge of the substrate. In other embodiments, this may include providing additional implantation outside the barrier region to make this region more conductive. This can be achieved by implanting the substrate with silicon (Si), calcium (Ca), oxygen (O), germanium (Ge), or carbon (C). Then, a plurality of semiconductor devices are formed in the active region of the semiconductor wafer (step 104). This may include, for example, implanting various regions within the active region, setting a metal layer for contacts, and other steps that those skilled in the art will understand. If the charge redistribution path is not set as a conductive region outside the barrier region, but as a metal layer on the substrate, then a charge redistribution path is set (step 106). This may include performing a mask as described above and depositing a metal layer on the substrate surface. A first passivation layer is then set over the substrate (step 108). As described above, the first passivation layer may terminate at a first passivation termination edge. A second passivation layer is then set over the first passivation layer and the substrate (step 110). As described above, this second passivation layer may terminate at a second passivation termination edge between the first passivation termination edge and the substrate termination edge, such that the second passivation layer overlaps with the first passivation layer. A third passivation layer may then be set over the second passivation layer (step 112). As described above, the third passivation layer may terminate at the second passivation termination edge, or may terminate at a third passivation termination edge between the second passivation termination edge and the substrate termination edge.

[0040] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of this disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the appended claims.

Claims

1. A semiconductor wafer, comprising: The substrate includes a boundary defined by a substrate termination edge; An active region, which is isolated from the substrate termination edge by a barrier region, the barrier region extending to the substrate termination edge; as well as A charge redistribution path contacts the potential barrier region, wherein the charge redistribution path is coupled to the ground.

2. The semiconductor wafer according to claim 1, wherein, The charge redistribution path includes a metal layer.

3. The semiconductor wafer according to claim 2, wherein, The metal layer includes one or more of aluminum, titanium, silicon, nickel, platinum, gold, and germanium.

4. The semiconductor wafer according to claim 1, wherein, The charge redistribution path shifts inward from the substrate termination edge.

5. The semiconductor wafer according to claim 1, wherein, The charge redistribution path forms a loop around the periphery of the substrate.

6. The semiconductor wafer according to claim 1, wherein, The charge redistribution path forms a first pattern along a first lateral edge of the substrate and a second pattern along a second lateral edge of the substrate, wherein the first pattern is different from the second pattern.

7. The semiconductor wafer according to claim 6, wherein, The gate contacts for the active region are arranged closer to the first lateral edge.

8. The semiconductor wafer according to claim 1, further comprising: A first passivation layer is provided above the substrate, the first passivation layer terminating at a first passivation termination edge; as well as A second passivation layer is located above the first passivation layer and the substrate, the second passivation layer terminating at a second passivation termination edge, the second passivation termination edge being closer to the substrate termination edge than the first passivation termination edge.

9. The semiconductor wafer according to claim 8, wherein, The charge redistribution path is arranged between the first passivation termination edge and the second passivation termination edge.

10. The semiconductor wafer according to claim 8, wherein, The charge redistribution path is arranged to traverse one or more of the first passivation termination edge and the second passivation termination edge.

11. A semiconductor wafer, comprising: The substrate includes a boundary defined by a substrate termination edge; An active region, the active region including one or more active devices; A barrier region surrounding the active region, wherein the barrier region terminates at an outer edge of the barrier region that is inwardly displaced from the termination edge of the substrate; and A charge redistribution path is formed between the outer edge of the barrier region and the substrate termination edge and contacts the barrier region, wherein the charge redistribution path is coupled to the ground and extends to the substrate termination edge.

12. The semiconductor wafer according to claim 11, wherein, The charge redistribution path is formed in a portion of the substrate between the outer edge of the barrier region and the termination edge of the substrate.

13. The semiconductor wafer according to claim 11, wherein, The charge redistribution path is injected with dopants.

14. The semiconductor wafer according to claim 13, wherein, The conductivity of the charge redistribution path is higher than the conductivity of the surface of the active region.

15. The semiconductor wafer according to claim 11, wherein, The charge redistribution path is the uninjected region of the substrate.

16. The semiconductor wafer according to claim 11, further comprising: A first passivation layer is provided above the substrate, the first passivation layer terminating at a first passivation termination edge; as well as A second passivation layer is located above the first passivation layer and the substrate, the second passivation layer terminating at a second passivation termination edge, the second passivation termination edge being closer to the substrate termination edge than the first passivation termination edge.

17. The semiconductor wafer according to claim 16, wherein, The outer edge of the barrier region is located between the first passivation termination edge and the second passivation termination edge.

18. The semiconductor wafer according to claim 16, wherein, The charge redistribution path is arranged to cross the second passivation termination edge.

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