Vertical interconnects for semiconductor devices

Abstract

Embodiments herein relate to vertical contacts for semiconductor devices. For example, a memory device having vertical contacts can include a substrate including a circuitry component, a vertical stack of layers formed from a repeating iteration of a group of layers disposed on the substrate, the group of layers comprising a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer including horizontal wires formed in the second dielectric material layer along a horizontal plane, and a vertical contact coupled to the horizontal wires, the vertical contact extending within the vertical stack of layers along a vertical plane to directly electrically couple the horizontal wires to the circuitry component.

Description

Technical Field

[0001] This disclosure generally relates to memory devices, and more specifically, to vertical direct contacts for semiconductor devices. Background Technology

[0002] Memory is commonly implemented in electronic systems such as computers, mobile phones, and handheld devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory requires power to maintain its data and can include random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), and synchronous dynamic random access memory (SDRAM). Non-volatile memory provides persistent data by retaining the stored data when no power is supplied and can include NAND flash memory, NOR flash memory, nitride read-only memory (NROM), phase-change memory (e.g., phase-change random access memory), resistive memory (e.g., resistive random access memory), crosspoint memory, ferroelectric random access memory (FeRAM), or similar.

[0003] As design rules shrink, the semiconductor space available for manufacturing memories containing DRAM arrays is decreasing. A corresponding memory cell for DRAM may include access means (e.g., transistors) having first and second source / drain regions separated by a channel region. A gate may be opposite to and separated from the channel region by a gate dielectric. Access lines, such as word lines, are electrically connected to the gate of the DRAM cell. The DRAM cell may include memory nodes, such as capacitor cells, coupled to wires, such as digital lines, via access means. Access means can be activated (e.g., to select a cell) via access lines coupled to access transistors. Capacitors may store charge corresponding to the data value (e.g., logic "1" or "0") of the respective cell. Summary of the Invention

[0004] One embodiment of this disclosure provides a memory device having an array of vertically stacked memory cells with vertical direct contacts. The memory device includes: a substrate containing circuit system components; a vertical stack of layers formed from repeated iterations of a group of layers disposed on the substrate, the group of layers including: a first dielectric layer; a semiconductor material layer; and a second dielectric layer containing horizontal conductors formed along a horizontal plane (D1) in the second dielectric layer; and vertical direct contacts coupled to the horizontal conductors, the vertical direct contacts extending along a vertical plane within the vertical stack of layers to directly electrically couple the horizontal conductors to the circuit system components.

[0005] Another embodiment of this disclosure provides a method for forming an array of vertically stacked memory cells with vertical direct contacts, comprising: vertically forming a plurality of layers in repeated iterations to form a vertical stack on a substrate, said layers comprising: a first dielectric material layer having wires formed therein along a horizontal plane (D1), a semiconductor material layer, and a second dielectric material layer; the second dielectric material layer having a plurality of multi-directional horizontal wires having a first portion extending in the first horizontal direction (D1) and a second portion extending in a second horizontal direction (D2) at an angle to the first horizontal direction, wherein said second portion is... For the second portion, which is laterally spaced apart to allow vertical direct contact coupling; a removal process is performed in repeated vertical iterations in the region of the second portion containing at least the conductors to form a staircase contact structure; spaced vertical openings are formed through the vertical stack adjacent to each of the multiple multidirectional horizontal conductors in the staircase contact structure having multiple levels; insulating material is conformally deposited in the spaced vertical openings; and conductive material is deposited in the spaced vertical openings to form vertical direct contacts to directly electrically couple the multiple multidirectional horizontal conductors in the staircase contact structure to circuit system components in the substrate.

[0006] Another embodiment of this disclosure provides a memory device comprising: conductive circuit system contacts; a plurality of stacked horizontal conductors having an insulating layer inserted between each of the plurality of stacked horizontal conductors; an insulating material disposed on the sidewalls of the insulating layer and inserted between each of the horizontal conductors and on the sidewalls of each of the stacked horizontal conductors; and a plurality of vertical direct contacts coupled to respective top surfaces of the plurality of stacked horizontal conductors to directly electrically couple the respective top surfaces to a corresponding conductive circuit system contact among the conductive circuit system contacts. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a vertical three-dimensional (3D) memory device according to an embodiment of the present disclosure.

[0008] Figure 2 The illustration shows a perspective view of a 3D semiconductor memory device according to an embodiment of the present disclosure.

[0009] Figure 3 This is a perspective view of a portion of the illustrative wires according to an embodiment of the present disclosure.

[0010] Figure 4 This is a top view illustrating the configuration of a conventional memory device.

[0011] Figure 5A to 5T This describes an example method for forming an array of vertically stacked memory cells according to embodiments of the present disclosure.

[0012] Figures 6A to 6N This is a cross-sectional view illustrating a method for forming vertically oriented contact structures for different levels of a vertical memory array, according to embodiments of the present disclosure.

[0013] Figure 7A This is a cross-sectional view illustrating a portion of a conventional 3D memory array.

[0014] Figure 7B This is a cross-sectional view illustrating a portion of a conventional 3D memory array.

[0015] Figure 7C This is a top view of a typical 3D memory array.

[0016] Figure 7D This is a top view of a 3D memory array according to an embodiment of the present disclosure.

[0017] Figure 8 This is a block diagram of a device in the form of a computing system including a memory device, according to embodiments of the present disclosure. Detailed Implementation

[0018] For example, a stacked memory device, such as a three-dimensional (3D) dynamic random access memory (DRAM) device, comprises multiple layers of vertically stacked memory cells. Coupled to sense amplifiers or word line drivers via wires (e.g., digital lines, word lines) contained within the stacked memory device can be challenging and / or can result in increased interconnect area sizes. For instance, conventional wire geometries can result in relatively large interconnect areas associated with contacts used to indirectly connect wires (e.g., digital lines) to one or more circuitry components, such as sense amplifiers. For example, conventional geometries can employ jumper-based indirect connections / routing between wires and / or other types of interconnects (e.g., horizontal interconnects) to one or more circuitry components.

[0019] Therefore, various embodiments of this disclosure describe vertical direct contacts for semiconductor devices. For example, embodiments of this disclosure can provide multi-directional conductors and can allow connections to those multi-directional conductors through a notably layered (e.g., staircase) structure employing vertical direct contacts. For example, in some embodiments, the conductors can be digital lines directly coupled to one or more circuit system components (e.g., sense amplifiers) via vertical direct contacts in the absence of another separate and dissimilar interconnect, such as jumpers, and / or other types of horizontal interconnects. Advantages of the embodiments described herein include greater interconnect density, reduced total number of components (e.g., without jumpers or other types of separate and dissimilar horizontal interconnects), and / or improved (reduced) parasitic current losses, etc. For example, embodiments of this disclosure can provide the benefit of, for example, greater density of connections between conductors and sense amplifiers in interconnect regions compared to conventional structures.

[0020] The diagrams in this document follow a numbering convention, where the first one or more numbers correspond to the diagram number, and the remaining numbers identify the elements or components within the diagram. Similar elements or components between different diagrams can be identified by using similar numbers. For example, reference number 104 can be used... Figure 1 The symbol "04" indicates the component, and similar components can be found in... Figure 2 The symbol is represented as 204. Multiple similar elements within a diagram can be represented by a number followed by a hyphen and another number or letter. For example, 302-1 can be... Figure 3 The symbol 302-1 represents element 302-1, and 302-2 can represent element 302-2, which is similar to element 302-1. Such similar elements can typically be represented without hyphens and additional numbers or letters. For example, elements 302-1 and 302-2, or other similar elements, can generally be represented as 302. The use of the letter 302-N, for example, means that any number of items 302 can be used.

[0021] Figure 1 This is a block diagram of an apparatus according to an embodiment of the present disclosure. Figure 1 A circuit diagram illustrating a cell array of a 3D semiconductor memory device according to an embodiment of the present disclosure is provided. Figure 1The cell array can have multiple sub-cell arrays 101-1, 101-2, ..., 101-N. Sub-cell arrays 101-1, 101-2, ..., 101-N can be arranged along a second direction (D2) 105. Each of the sub-cell arrays (e.g., sub-cell array 101-2) can contain multiple access lines 103-1, 103-2, ..., 103-Q (which may also be referred to as word lines). Furthermore, each of the sub-cell arrays (e.g., sub-cell array 101-2) can contain multiple digital lines 107-1, 107-2, ..., 107-Q (which may also be referred to as bit lines, data lines, or sensing lines). Figure 1 In the diagram, digital lines 107-1, 107-2, ..., 107-Q are described as extending in the first direction (D1) 109, and access lines 103-1, 103-2, ..., 103-Q are described as extending in the third direction (D3) 111.

[0022] The first direction (D1) 109 and the second direction (D2) 105 can be considered to be in a horizontal (“XY”) plane. The third direction (D3) 111 can be considered to be in a vertical (“Z”) direction (e.g., transverse to the XY plane). Therefore, according to the embodiments described herein, access lines 103-1, 103-2, ..., 103-Q extend in a vertical direction (e.g., the third direction (D3) 111).

[0023] A memory cell (e.g., 110) may include access means (e.g., access transistors) and memory nodes located at the intersections of each access line 103-1, 103-2, ..., 103-Q and each digital line 107-1, 107-2, ..., 107-Q. Data can be written to or read from the memory cell using the access lines 103-1, 103-2, ..., 103-Q and the digital lines 107-1, 107-2, ..., 107-Q. Digital lines 107-1, 107-2, ..., 107-Q can electrically interconnect memory cells along the horizontal columns of each sub-cell array 101-1, 101-2, ..., 101-N, and access lines 103-1, 103-2, ..., 103-Q can electrically interconnect memory cells along the vertical rows of each sub-cell array 101-1, 101-2, ..., 101-N. A memory cell, for example, 110, can be located between an access line (e.g., 103-2) and a digital line (e.g., 107-2). Each memory cell can be uniquely addressed by a combination of access lines 103-1, 103-2, ..., 103-Q and digital lines 107-1, 107-2, ..., 107-Q.

[0024] Digital lines 107-1, 107-2, ..., 107-Q may be or comprise conductive patterns (e.g., metal lines) disposed on and spaced apart from the substrate. Digital lines 107-1, 107-2, ..., 107-Q may extend in a first direction (D1) 109. Digital lines 107-1, 107-2, ..., 107-Q in a sub-cell array (e.g., 101-2) may be spaced apart from each other in a vertical direction (e.g., in a third direction (D3) 111).

[0025] Access lines 103-1, 103-2, ..., 103-Q may be or include conductive patterns (e.g., metal lines) extending in a vertical direction (e.g., on a third direction (D3) 111) relative to the substrate. Access lines in a sub-cell array (e.g., 101-2) may be spaced apart from each other in a first direction (D1) 109.

[0026] The gate of a memory cell (e.g., memory cell 110) may be connected to an access line (e.g., 103-2), and the first conductive node (e.g., the first source / drain region) of the access means (e.g., transistor) of memory cell 110 may be connected to a digital line (e.g., 107-2). Each of the memory cells (e.g., memory cell 110) may be connected to a storage node (e.g., a capacitor). The second conductive node (e.g., the second source / drain region) of the access means (e.g., transistor) of memory cell 110 may be connected to a storage node (e.g., a capacitor). For example, the storage node of the capacitor may be formed of a ferroelectric and / or dielectric material, such as zirconium oxide (ZrO2), hafnium oxide (HfO2), lanthanum oxide (La2O3), lead zirconate titanate (PZT, Pb[Zr(x)Ti(1-x)]O3), barium titanate (BaTiO3), aluminum oxide (e.g., Al2O3), combinations of these with or without dopants, or other suitable materials.

[0027] Although this document uses first and second source / drain region references to denote two separate and distinct source / drain regions, it is not intended that the source / drain regions referred to as "first" and / or "second" have a single meaning. It is only desirable that one of the source / drain regions is connected to a digital line (e.g., 107-2), and the other can be connected to a memory node.

[0028] Figure 2 The illustration shows a 3D semiconductor memory device (e.g., according to some embodiments of the present disclosure) Figure 1 The perspective view shown is a portion of the sub-cell array 101-2 as a vertical stack of memory cells in the array. Figure 3 The description shows Figure 2 The unit cell of the 3D semiconductor memory device shown (e.g., Figure 1 A perspective view of the memory cell 110 shown.

[0029] like Figure 2 As shown, substrate 200 may have a bonding formed thereon. Figure 1 One of the described array of sub-cells (e.g., 101-2). For example, substrate 200 may be or comprise a silicon substrate, a germanium substrate, or a silicon-germanium substrate, etc. However, the embodiments are not limited to these examples.

[0030] like Figure 2 As shown in the example embodiment, the substrate 200 may have memory cells (e.g., extending in a vertical direction (D3) 111) fabricated thereon. Figure 1 The memory cells 110 in the memory are vertically stacked. According to some embodiments, the vertical stacking of the memory cells can be manufactured such that each memory cell (e.g., Figure 1 The memory cells 110 are formed on multiple vertical levels (e.g., a first level (L1), a second level (L2), and a third level (L3)). Repeating vertical levels L1, L2, and L3 can be arranged (e.g., "stacked") in the vertical direction (e.g., ...). Figure 1 The third direction (D3) 111 shown is on the substrate 200 and can be separated from it by insulating material 220. Each of the repeating vertical layers L1, L2, and L3 may include multiple discrete components (e.g., regions) of the lateral access device 229 (e.g., transistors) and memory nodes (e.g., capacitors), including access lines 103-1, 103-2, ..., 103-Q connections and digital lines 107-1, 107-2, ..., 107-Q connections. The multiple discrete components of the lateral access device 229 (e.g., transistors) may be formed in multiple iterations of the vertically repeating layers within each layer, as described below. Figure 4 A more detailed description, and may be available in similar formats. Figure 1 The second direction (D2) 105 shown extends horizontally on the second direction (D2) 205.

[0031] Multiple discrete components of a lateral access device 229 (e.g., a transistor) may include a first source / drain region 221 and a second source / drain region 223 separated by a channel region 225, extending laterally in a second direction (D2) 205 and formed in the body of the access device. In some embodiments, the channel region 225 may comprise silicon, germanium, silicon-germanium, and / or indium gallium zinc oxide (IGZO). In some embodiments, the first source / drain region 221 and the second source / drain region 223 may comprise n-type dopant regions formed in the p-type doped body of the access device to form n-type conductive transistors. In some embodiments, the first source / drain region 221 and the second source / drain region 223 may comprise p-type dopant formed in the n-type doped body of the access device to form p-type conductive transistors. By way of example, but not limitation, the n-type dopant may comprise phosphorus (P) atoms, and the p-type dopant may comprise boron (B) atoms formed in a relatively doped body region of a polycrystalline silicon semiconductor material. However, the embodiments are not limited to these examples.

[0032] Storage node 227 (e.g., a capacitor) can be connected to a corresponding terminal of the access device. For example... Figure 2 As shown, storage node 227 (e.g., a capacitor) may be connected to the second source / drain region 223 of the access device. A storage node may be or contain a memory element capable of storing data. Each of the storage nodes may be a memory element using one of a capacitor, a magnetic tunnel junction pattern, and / or a variable resistor body containing a phase change material. However, embodiments are not limited to these examples. In some embodiments, with unit cells (e.g., Figure 1 Each access device associated with a memory node in memory cell 110 can be in a similar manner to... Figure 1 The second direction (D2) 105 shown extends similarly on the second direction (D2) 205.

[0033] like Figure 2 As shown, multiple horizontal numerical lines 207-1, 207-2, ..., 207-Q are similar to Figure 1 The first direction (D1) of 109 extends upwards from 209. Multiple horizontal number lines 207-1, 207-2, ..., 207-Q can be similar to... Figure 1The digital lines 107-1, 107-2, ..., 107-Q are shown. Multiple horizontal digital lines 207-1, 207-2, ..., 207-Q may be arranged (e.g., "stacked") along a third direction (D3) 211. The multiple horizontal digital lines 207-1, 207-2, ..., 207-Q may contain a conductive material. For example, the conductive material may contain one or more of the following: doped semiconductors (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.), and / or metal-semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). However, the embodiments are not limited to these examples.

[0034] In each of the vertical hierarchies (L1) 213-1, (L2) 213-2, and (L3) 213-P, the horizontal memory cell (e.g., Figure 1 The memory cells 110 in the memory may be horizontally spaced apart from each other in the first direction (D1) 209. However, as described below... Figure 4 As described in more detail below, a plurality of discrete components of the lateral access device 229 extending laterally in the second direction (D2) 205 (e.g., a first source / drain region 221 and a second source / drain region 223 separated by channel region 225) and a plurality of horizontal digital lines 207-1, 207-2, ..., 207-Q extending laterally in the first direction (D1) 209 may be formed in different vertical layers within each level. For example, the plurality of horizontal digital lines 207-1, 207-2, ..., 207-Q extending in the first direction (D1) 209 may be disposed on the top surface of the first source / drain region 221 and electrically contact the top surface of the first source / drain region 221 and orthogonal to the lateral access device 229 (e.g., a transistor) extending laterally in the second direction (D2) 205. In some embodiments, a plurality of horizontal digital lines 207-1, 207-2, ..., 207-Q extending in the first direction (D1) 209 are formed in a higher vertical layer, more distant from the substrate 200, compared to the layer in which discrete components forming lateral access devices (e.g., the first source / drain region 221 and the second source / drain region 223 separated by the channel region 225). In some embodiments, the plurality of horizontal digital lines 207-1, 207-2, ..., 207-Q extending in the first direction (D1) 209 may be directly and / or connected to the top surface of the first source / drain region 221 via additional contacts comprising metal silicide.

[0035] like Figure 2As shown in the example embodiment, access lines 203-1, 203-2, ..., 203-Q extend vertically relative to substrate 200 (e.g., on third-direction (D3) 211). Furthermore, as... Figure 2 As shown, in a sub-cell array (e.g., Figure 1 In the sub-cell array 101-2, access lines 203-1, 203-2, ..., 203-Q are spaced apart from each other in a first direction (D1) 209. Access lines 203-1, 203-2, ..., 203-Q can be provided as a pair of lateral access devices 229 (e.g., transistors) extending laterally in a second direction (D2) 205, extending vertically relative to the substrate 200 in a third direction (D3) 211, but adjacent to each other in a layer (e.g., a first layer (L1)) in the first direction (D1) 209. Each of access lines 203-1, 203-2, ..., 203-Q can extend vertically in the third direction (D3) on the sidewall of the corresponding one of the vertically stacked lateral access devices 229 (e.g., transistors).

[0036] For example, and as Figure 3 As shown in more detail, the first of the vertically extending access lines (e.g., 203-1) may be adjacent to the sidewall of the channel region 225 of the first lateral access device 229 (e.g., transistor) on the first level (L1) 213-1, the sidewall of the channel region 225 of the first lateral access device 229 (e.g., transistor) on the second level (L2) 213-2, and the sidewall of the channel region 225 of the first lateral access device 229 (e.g., transistor) on the third level (L3) 213-P, etc. Similarly, the second vertically extending access line (e.g., 203-2) may be adjacent to the sidewall of the channel region 225 of the second lateral access device 229 (e.g., transistor) on the first level (L1) 213-1, and spaced apart from the first lateral access device 229 (e.g., transistor) on the first level (L1) 213-1 in the first direction (D1) 209. The second vertically extending access line (e.g., 203-2) may also be adjacent to the sidewall of the channel region 225 of the second lateral access device 229 (e.g., transistor) on the second level (L2) 213-2, and the sidewall of the channel region 225 of the second lateral access device 229 (e.g., transistor) on the third level (L3) 213-P, etc. The embodiments are not limited to a specific number of levels.

[0037] The vertically extending access lines 203-1, 203-2, ..., 203-Q may contain a conductive material, such as a doped semiconductor material, a conductive metal nitride, a metal, and / or a metal-semiconductor compound. Access lines 203-1, 203-2, ..., 203-Q may correspond to... Figure 1 The word line (WL) of the description.

[0038] like Figure 2 As shown in the example embodiment, the conductive body contact 295 may be formed to extend in a first direction (D1) 209 along the end surface of the lateral access device 229 (e.g., a transistor) on each layer (L1) 213-1, (L2) 213-2, and (L3) 213-P above the substrate 200. The conductive body contact 295 may be connected to the body, as by Figure 3 As shown in 336, in each memory cell (e.g., Figure 1 The lateral access device 229 (e.g., a transistor) in the memory cell 110 (e.g., the body region). The conductive body contact 295 may contain a conductive material, such as a doped semiconductor material, a conductive metal nitride, a metal, and / or a metal-semiconductor compound.

[0039] Although Figure 2 Not shown, but insulating material may fill other spaces in the vertically stacked memory cell array. For example, the insulating material may comprise one or more of silicon oxide, silicon nitride, and / or silicon oxynitride. However, the embodiments are not limited to these examples.

[0040] Figure 3 A more detailed description of vertically stacked memory cell arrays according to some embodiments of the present disclosure (e.g., in...) Figure 1 The unit cells (e.g., within the sub-unit array 101-2) in the sub-unit array 101-2 Figure 1 (Memory unit 110 in the memory). For example Figure 3 As shown, the first source / drain region 321 and the second source / drain region 323 can be impurity-doped regions of the lateral access device 329 (e.g., a transistor). The first source / drain region 321 and the second source / drain region 323 can be similar to... Figure 2 The first source / drain region 221 and the second source / drain region 223 are shown. The first source / drain region and the second source / drain region may be separated by a channel region 325 formed in a body (e.g., body 326) of the semiconductor material of the lateral access device 329 (e.g., a transistor). The first source / drain region 321 and the second source / drain region 323 may be formed by an n-type or p-type dopant doped in the body 326 (i.e., the body region). Embodiments are not limited thereto.

[0041] For example, in an n-type conductive transistor configuration, the body 326 of the lateral access device 329 (e.g., a transistor) may be formed of a lightly doped (p-)p-type semiconductor material. In some embodiments, the body 326 and the channel region 325 separating the first source / drain region 321 and the second source / drain region 323 may comprise a lightly doped p-type (e.g., lower dopant concentration (p-)) polysilicon material composed of boron (B) atoms as an impurity dopant for the polysilicon. The first source / drain region 321 and the second source / drain region 323 may also comprise metals and / or metal composite materials containing ruthenium (Ru), molybdenum (Mo), nickel (Ni), titanium (Ti), copper (Cu), highly doped degenerate semiconductor materials, and / or indium oxide (In₂O₃) or indium tin oxide (In₂O₃). 2-x Sn x At least one of O3). However, the embodiments are not limited to these examples.

[0042] As used herein, degenerate semiconductor material refers to a semiconductor material, such as polycrystalline silicon, containing high-level doping with significant interactions between dopants (e.g., phosphorus (P), boron (B), etc.). In contrast, non-degenerate semiconductors contain intermediate-level doping, where dopant atoms are well separated from each other in the semiconductor bulk lattice with negligible interactions.

[0043] In this example, the first source / drain region 321 and the second source / drain region 323 may contain highly doped n-type conductive impurities (e.g., highly doped (n+)) doped in the first source / drain region 321 and the second source / drain region 323. In some embodiments, the highly doped n-type conductive first drain region 321 and the second drain region 323 may contain a high concentration of phosphorus (P) atoms deposited therein. However, the embodiments are not limited to this example. In other embodiments, the lateral access device 329 (e.g., a transistor) may have a p-type conductive configuration, in which case the conductivity type of the impurity (e.g., the dopant) will be reversed.

[0044] As in Figure 3 As shown in the example embodiment, the first source / drain region 321 may occupy the upper portion of the body 326 of the lateral access device 329 (e.g., a transistor). For example, the first source / drain region 321 may have a bottom surface 324 within the body 326 of the lateral access device 329, which is vertically positioned higher on a third direction (D3) 311 than the bottom surface of the body 326 of the laterally horizontal access device 329. Therefore, the laterally horizontal transistor 329 may have a body 326 below the first source / drain region 321 and adjacent to a body contact (e.g., in... Figure 2 (As shown in 295) Electrical contact. Furthermore, as in... Figure 3 As shown in the example embodiments, similar to Figure 2 The number lines 207-1, 207-2, ..., 207-Q and Figure 1 The digital lines 107-1, 107-2, ..., 107-Q shown (e.g., 307-1) may be disposed on and electrically coupled to the top surface 322 of the first source / drain region 321. For example, the digital line 307-1 may extend in a first horizontal direction (D1) 309.

[0045] As in Figure 3 As shown in the example embodiments, the access line (e.g., 303-1, which is similar to...) Figure 2 Access lines 203-1, 203-2, ..., 203-Q and Figure 1 The 103-1, 103-2, ..., 103-Q) in the second direction (D2) 305 may be adjacent to the sidewall of the channel region 325 portion of the body 326 of the lateral access device 329 (e.g., a transistor) that is horizontally conductive between the first source / drain region 321 and the second source / drain region 323, extending vertically in the third direction (D3) 311. A gate dielectric material 304 may be inserted between the access line 303-1 (a portion of which forms the gate of the lateral access device 329 (e.g., a transistor)) and the channel region 325.

[0046] The gate dielectric material 304 may comprise, for example, a high-k dielectric material, a silicon oxide material, a silicon nitride material, a silicon oxynitride material, or a combination thereof. Embodiments are not limited thereto. For example, in a high-k dielectric material example, the gate dielectric material 304 may comprise one or more of the following: hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, etc.

[0047] Figure 4 This is a top view illustrating a conventional 3D memory device configuration. A 3D array 440 of vertically stacked memory cells may include a vertical stack of horizontal conductors (e.g., 407-1, 407-2). The conductors may be digital lines or access lines (i.e., word lines). Each conductor 407 formed within the 3D array 440 may include a first portion 441-1, ..., 441-2 extending in a first horizontal direction (D1) 409. Each horizontal conductor may further include a second portion 442-1, ..., 442-T extending at an angle to the first horizontal direction (D1) 409 in a second horizontal direction D2. In other words, the memory cell array 440 may include a plurality of multi-directional conductors 407 (also referred to as curved conductors).

[0048] In some embodiments, the array of vertically stacked memory cells may be electrically coupled, for example, in an open digital line architecture. In other embodiments, the array of vertically stacked memory cells may be electrically coupled in a folded digital line architecture.

[0049] For example, such as Figure 4 As shown, in some embodiments, the second portion of each conductor (e.g., 442-1, 442-2) may extend at an angle to the first portion (e.g., perpendicular to the first horizontal direction (D1) 409) in a second horizontal direction (D2) 405.

[0050] Although Figure 4 The wires 407-1 and 407-2 are described as having two portions 442-1 and 442-2, but embodiments of this disclosure are not limited thereto. For example, in some embodiments, each wire may further include a third portion extending upward from a third portion. The third portion may extend in direction (D1) 409. The third portion may be coupled to an end of the second portion.

[0051] like Figure 4 As described herein, a conventional memory device may further include a plurality of horizontal interconnects 434-1, ..., 434-S. In some embodiments, each horizontal interconnect 434-1, ..., 434-S may be electrically coupled to a second portion 442-1, 442-2 of wires 407-1, 407-2. In some embodiments, each of the horizontal interconnects 434-1, ..., 434-S may be coupled to a second portion 442-1, 442-2 of wires 407-1, 407-2 via a horizontal storage node. These horizontal storage nodes may include capacitor cells.

[0052] Conductors 407-1, 407-2 can be coupled to the sense amplifier region 435 via interconnects 434-1, ..., 434-S. In some embodiments, conductors 407-1, 407-2 may be digital lines, and the sense amplifier region 435 may contain several sense amplifiers. Although not described herein, in some embodiments, conductors 407-1, 407-2 may be access lines (i.e., word lines), which may not be coupled to the sense amplifier region 435 but may instead be coupled via contacts to one or more other circuit system components (e.g., word line drivers).

[0053] In such a configuration, a 3D DRAM array 440 (i.e., a memory cell array) of vertically stacked memory cells may have several digital lines (e.g., 407-1, ..., 407-2) formed therein (collectively referred to as wires 407). Each digital line may travel in a first horizontal direction (D1) 409.

[0054] Each digital line can be coupled to one or more access devices (not shown). For example, in Figure 4 In the embodiment described herein, a 3D DRAM array 440 of vertically stacked memory cells has two digital lines 407 formed therein and travels parallel to each other in direction (D1) 409, and each of the digital lines 407 in the array region is coupled via interconnects 434-1, ..., 434-S (i.e., additional horizontal interconnects) to a circuit system component of a sense amplifier, for example, located in a sense amplifier region 435.

[0055] Although not stated, in Figure 4 It may contain multiple vertical levels, or it may be referred to as a group of multiple levels. Each vertical level may contain one or more layers, in which one or more horizontal conductors 407 are formed.

[0056] In some embodiments, each second portion 442-1, ..., 442-T of each conductor 407 may have a length greater than that of the second portions 442-1, ..., 442-T of the conductor 407 in the lower vertical hierarchy. Therefore, if the 3D array comprises levels L1, L2, ..., LN and L1 is the top level of the vertical stack, then the length of the second portion of the conductor in L1 may be less than the length of the second portion of the conductor in L2, ..., LN. For example, considering... Figure 4 It's a top view. Figure 4 The conductors 407-1 and 407-2 described herein may be formed on the top layer L1 of the vertical 3D array 440. Therefore, conductors 407-1 and 407-2 may each include second portions 442-1 and 442-2, which are shorter than the length of the second portion of each conductor on the lower layers of the 3D array 440.

[0057] This conventional configuration of horizontal interconnects 434-1, ..., 434-S and digital lines 407-1, ..., 407-Q adds additional device space to the memory cell array 440 (described at 436-1), which may be undesirable if space constraints are imposed. Furthermore, interconnects 434-1, ..., 434-S inherently provide indirect and relatively long electrical paths between digital lines 407 and circuitry components such as sense amplifiers (a portion of which extends at least some distance above 411 in the D3 direction and / or horizontally in direction (D1) 409), which, as detailed herein, is located below digital lines 407 at a distance in the D3 411 direction. These indirect and relatively long electrical paths can have a relatively high amount of parasitic signal / current loss (i.e., a relatively high amount of signal attenuation).

[0058] Therefore, the embodiments herein provide such direct vertical coupling of digital lines to one or more circuit system contacts via vertical direct contacts (e.g., in the absence of horizontal interconnects such as horizontal interconnects 434-1, ..., 434-S). As detailed herein, providing direct vertical coupling of digital lines via vertical direct contacts can provide greater interconnect density, a reduced total number of components, and / or at least in part, improved (i.e., reduced) parasitic resistance due to the shorter electrical path provided by the connection between the digital lines and one or more circuit system contacts compared to conventional structures. For example, embodiments of this disclosure can provide the benefit of, for example, a greater density of connections between conductors and sense amplifiers in the interconnect region compared to previous methods.

[0059] Figure 5A to 5T This describes an example method for forming an array of vertically stacked memory cells according to embodiments of the present disclosure. Figure 5A This is a top view illustrating the configuration of a memory device according to embodiments of the present disclosure.

[0060] As described, the memory device may include a plurality of 3D array regions 540-1, ..., 540-W (i.e., a plurality of memory cell arrays). Each of these array regions 540-1, ..., 540-W contains vertically stacked memory cells (e.g., ...). Figure 1 (Memory cell 110). Several memory cell array regions 540-1, ..., 540-W can be positioned in a configuration to form an array 550. During formation, each of the memory cell array regions 540-1, ..., 540-W can be temporarily coupled to an adjacent array region 540-1, ..., 540-W in the same column via one or more bridges 546 (e.g., 546-1, ..., 546-Y) and one or more wire contact regions 547 (e.g., digital line contact regions 547-1, ..., 547-X), such as... Figure 5A As shown in the diagram. This coupling will be cut off later in the process, resulting in a single array with one or more bridge and wire contact areas.

[0061] Figure 5B This describes the stages along which the process for forming a wire contact area with multiple multidirectional wires and staircase wire contact structures for semiconductor devices is described. Figure 5A A cross-sectional view of line A-A', for example in Figures 1 to 3 The description is based on, and according to, embodiments of this disclosure. For example... Figure 5BAs described, the method includes forming alternating layers of a first dielectric material 530-0, 530-1, …, 530-D (collectively the first dielectric material 530), a semiconductor material 532-0, 532-1, …, 532-D (collectively the semiconductor material 532), and a second dielectric material 533-0, 533-1, …, 533-D (collectively the second dielectric material 533) in repeated iterations to form a vertical stack 501 on a working surface of a substrate 500 similar to the substrate 200 in Figure 2 In some embodiments, the method may further include depositing a top layer of the first dielectric material 530 and a top layer of the second dielectric material 533 above the alternating layers. As Figure 5B shown, the horizontal direction is illustrated as a first horizontal direction (D2) (e.g., the Y direction in an X-Y-Z coordinate system), similar to the first direction (D2) among the first, second, and third directions shown in Figure 4 The second horizontal direction (D3) is also illustrated in Figure 5B as (e.g., the X direction in an X-Y-Z coordinate system) similar to the second horizontal direction (D3) shown in Figure 4 The vertical direction (D1) (e.g., the Z direction in an X-Y-Z coordinate system) is also illustrated in Figure 5B and is similar to the vertical direction (D1) shown in Figure 4

[0062] In some embodiments, the first dielectric material may be an interlayer dielectric (ILD). By way of example and not limitation, the first dielectric material may include a silicon nitride (Si3N4) material (also referred to herein as (“SiN”)). In another example, the first dielectric material may include a silicon oxynitride material (SiO x N Y ) material (also referred to herein as “SiON”) and / or combinations thereof. Embodiments are not limited to these examples.

[0063] In some embodiments, the semiconductor material may include a silicon material. The semiconductor material may be in a polycrystalline and / or amorphous state. For example, the semiconductor material may be a lightly doped p-type (p-) silicon material. For example, the semiconductor material may be formed by doping boron atoms (B) as an impurity dopant at a low concentration in a gas phase to form a lightly doped p-type (p-) silicon material. In some embodiments, the lightly doped p-type (p-) silicon material may be a polycrystalline silicon material. However, embodiments are not limited to these examples.

[0064] In some embodiments, the second dielectric material may be an interlayer dielectric (ILD). By way of example and not limitation, the second dielectric material may include a nitride material. The nitride material may be silicon nitride (Si x ​N4 material (also referred to in this paper as (“SiN”)).

[0065] In another example, the second dielectric material 533-0, 533-1, ..., 533-D may comprise silicon oxycarbide (SiOC) material. In another example, the second dielectric material may comprise silicon oxynitride (SiON), and / or combinations thereof. Embodiments are not limited to these examples. However, according to some embodiments, the second dielectric material may be intentionally selected to differ in material or composition from the first dielectric material, such that a selective etching process can be performed on one of the first and second dielectric layers, selectively for the other of the first and second dielectric layers (e.g., the second SiN dielectric material may be selectively etched relative to a semiconductor material).

[0066] Alternating layers of first dielectric material 530-0, 530-1, ..., 530-D, semiconductor material 532-0, 532-1, ..., 532-D, and second dielectric material 533-0, 533-1, ..., 533-D can be deposited according to a semiconductor manufacturing process, such as chemical vapor deposition (CVD), in a semiconductor manufacturing apparatus. However, the embodiments are not limited to this example, and other suitable manufacturing techniques can be used to deposit alternating layers of first dielectric material, semiconductor material, and second dielectric material in repeated iterations to form a vertical stack 501.

[0067] exist Figure 5B In the example, three levels of repeated iterations are shown. For example, the stack may include: a first dielectric material 530-1, a semiconductor material 532-1, a second dielectric material 533-1, a third dielectric material 530-2, a second semiconductor material 532-2, a fourth dielectric material 533-2, a fifth dielectric material 530-3, a third semiconductor material 532-3, and a sixth dielectric material 533-3. Therefore, in further repeated iterations, the stack may include: a first oxide material 530-1, a first semiconductor material 532-1, a first nitride material 533-1, a second oxide material 530-2, a second semiconductor material 532-2, a second nitride material 533-2, a third oxide material 530-D, a third semiconductor material 532-D, and a third nitride material 533-D. However, the embodiments are not limited to this example and may include more or fewer repeated iterations.

[0068] Readers should note that although in Figure 5A or Figure 5B Not explicitly stated, but several trenches may be formed between rows of interconnects in the memory cell array. These trenches may be configured such that conductors can be formed within them. Conductors formed in these trenches may be referred to as "undercut" or "buried" conductors.

[0069] Figure 5C This is a top view of another stage of a method for forming an array of vertically stacked memory cells using horizontal digital lines and vertical access lines. (See image.) Figure 5C As shown, conductors 507-1, ..., 507-4 may be formed in the second dielectric (e.g., in...). Figure 5B Within (533-0, 533-1, ..., 533-D). The conductors in this disclosure include portions that are angled relative to each other (e.g., 541-1, 542-1, 543-1, 544-1, 545-1, 551-1 and 541-2, 542-2, 543-2, 544-2, 545-2, 551-2), for example, when they advance through array regions 540-1, ..., 540-W, bridges 546-1, ..., 546-Y, and conductor contact regions 547-1, ..., 547-X, as... Figure 5C As shown in the figure. For example, these conductors 507-1, ..., 507-4 may be aligned with the edges of the perimeter of the array area, bridge, and / or conductor contact area (i.e., typically travel parallel to the edges of the array area 540, bridge 546, or conductor contact area 547, as shown). In some embodiments, the conductors may be undercut or embedded.

[0070] Figure 5D It is along Figure 5C The description of line A-A' is a cross-sectional view of a stage in a method for forming a conductor contact area having multiple multidirectional conductors and staircase conductor contact structures for semiconductor devices, for example in... Figures 1 to 3 The description is based on the embodiments of this disclosure.

[0071] In some embodiments, wires may be formed within one or more layers of stacked second dielectric materials 533-0, 533-1, ..., 533-D. This can be achieved by a wire forming process that includes, for example, selectively removing the second dielectric materials 533-0, 533-1, ..., 533-D (e.g., to form a first horizontal opening by removing the second dielectric material backward from a reference line 562 (e.g., a centerline in a vertical opening between memory cell stacks 501) to a first distance).

[0072] The wire forming process may further include depositing a conductive material into a vertical opening. In some embodiments, this may include conformally depositing the conductive material into a portion of the vertical opening (e.g., using a chemical vapor deposition (CVD) process) such that the conductive material may also be deposited into a first horizontal opening. In some embodiments, the conductive material may comprise titanium nitride (TiN) material. The conductive material may be formed into a horizontally (e.g., laterally) oriented digital line.

[0073] The conductive material may then be recessed in the horizontal opening (e.g., etched away from the vertical opening using reactive ion etching or other suitable techniques). In some instances, the conductive material may be moved back in the horizontal opening at a second distance from the vertical opening to form a digital line. The conductive material may be selectively etched, fully preserving the dielectric material 530, a portion of the conductive material, and the semiconductor material 532. The conductive material may be etched to define a desired wire width. In some embodiments, an atomic layer etching (ALE) process may be used to etch the conductive material. In some embodiments, an isotropic etching process may be used to etch the conductive material.

[0074] Therefore, the conductive material can be selectively removed a second distance backward from the vertical opening, forming a smaller horizontal opening between the first dielectric layers 530-0, ..., 530-D and the semiconductor layers 532-0, ..., 532-D. A third dielectric layer 531-L can then be deposited into each of the horizontal openings laterally adjacent to the conductive material. In some embodiments, the third dielectric material 531-L may be the same as or similar to the second dielectric material 533. For example, in some embodiments, the second and third dielectric materials may each comprise a nitride material.

[0075] The third dielectric material 531-L can be retracted to a second distance from the reference line 562 to remove it from the first vertical opening and maintain the first vertical opening to allow the deposition of conductive material to connect such conductive material deposited in the vertical opening with horizontal interconnects (e.g., access devices) within the memory cell array region 540 (not in Figure 5D Direct electrical contacts are formed between the low-doped semiconductor materials 532-0, ..., 532-D (e.g., body region contacts) as depicted in the diagram. In some embodiments, the third dielectric material 531-L may be removed away from the vertical opening to expose the sidewalls of the first dielectric materials 530-0, ..., 530-D, the third dielectric material 531-L, and the semiconductor materials 532-0, ..., 532-D.

[0076] Figure 5E This is a top view of another stage of a method for forming a wire contact area having a plurality of multidirectional wire and staircase wire contact structures for a semiconductor device, according to embodiments of the present disclosure. For simplicity, Figure 5E Describe the upper half of the memory cell structure (e.g., in Figure 5C (as shown in the image), however, relative to Figure 5E The method described can also be applied to those elements in the lower half of the memory cell structure.

[0077] This method may include depositing a conductive material 576 (e.g., polysilicon) above, around, or between one or more memory cell regions 540-1, ..., 540-W, bridges 546-1, ..., 546-Y, and digital line contact regions 547, ..., 547-X, for example, for body bias control during this portion of the formation process. The conductive material 576 may comprise, for example, a conductive polymer material. In some embodiments, the conductive material 576 may be formed to bond Figure 4 The doped host contacts of the several interconnects described. The conductive material 576 can also be etched back when appropriate.

[0078] Although Figure 5E Only two memory cell regions 540-1 and 540-2 are described, but embodiments of this disclosure are not limited thereto. For example, conductive material 576 may be deposited on the array (e.g., in...). Figure 5A and 5C The four cell arrays 550 described herein are arranged between or around the groups of memory cell array regions, as well as other arrangements of the cell arrays.

[0079] Figure 5F yes Figure 5E The cross-sectional view of line A-A' in the diagram is similar to... Figure 5C The line A-A' in the middle and Figure 5A Line A-A' in the middle. Figure 5F As shown, due to the combination Figure 5E The described process, memory cell array area (e.g., Figure 5E The vertical opening 571 between 540-1 and 540-2 can be filled with conductive material 576.

[0080] Figure 5G This is a top view of another stage of a method for forming a wire contact area having a plurality of multidirectional wire and staircase wire contact structures for a semiconductor device, according to embodiments of the present disclosure. Figure 5G As shown, conductive material 576 can be partially removed from regions 590 (e.g., 590-1, ..., 590-3). Although in Figure 5G Not shown, but a mask (e.g., a photoresist layer) may be deposited over region 590 before the conductive material 576 is removed.

[0081] Figure 5H It is in combination Figure 5G After the described process has been executed, along Figure 5G A cross-sectional view of line B-B'. Figure 5H illustrate Figure 5G The portions 543-1 and 543-2 of conductors 507-1 and 507-2 have been formed at this stage. However, embodiments of this disclosure are not limited thereto. For example, in some embodiments, Figure 5H The area of ​​the conductor described herein may contain empty trenches, and in a later stage those trenches may be filled with conductive material to form a conductor. Figure 5H Also identifies formation in Figure 5G The conductor portions 543-5 and 543-6 and portions 543-9 and 543-10 of the digital lines below conductors 507-1 and 507-2 shown.

[0082] Figure 5I This is a top view of another stage of a method for forming a wire contact area having a plurality of multidirectional wire and staircase wire contact structures for a semiconductor device, according to embodiments of the present disclosure. Figure 5I As shown, a fourth dielectric material 537 (e.g., a swivel element on the dielectric) may be deposited in region 590 around and between bridges 546-1, 546-2, 546-3, 546-4 and digital line contact regions 547-1 and 547-2. In some embodiments, the fourth dielectric material 537 may be similar to or the same as the first dielectric material 530. For example, in some embodiments, the first dielectric material 530 and the fourth dielectric material 537 may each comprise an oxide material.

[0083] Figure 5J It is in combination Figure 5I After the described process has been executed, along Figure 5I A cross-sectional view of line B-B'. (Similar to...) Figure 5I , Figure 5J The fourth dielectric material 537 is shown to be deposited into the region on the side of the stack.

[0084] Figure 5K This is a top view of another stage of a method for forming wire contact areas having a plurality of multidirectional wire and staircase wire contact structures for a semiconductor device, according to embodiments of the present disclosure. In some embodiments, a hard mask material (e.g., a photoresist layer) may be deposited over portions 592 of array regions 540-1, 540-2. In other embodiments, the hard mask material may be deposited over portions of each memory array region. The hard mask material may be used to protect the memory cell array regions and body contacts throughout the remainder of the process described herein.

[0085] In some embodiments, a photoresist layer may be deposited over region 592. The photoresist layer may act as a protective layer to maintain the integrity of portions of the memory cell array that are not removed during the staircase formation process.

[0086] In addition, such as Figure 5KAs shown, a portion of the array area (e.g., 540-1 and 540-2) containing the digital lines (e.g., 542-1 and 542-2) may be exposed for further processing, as described in more detail below. In this way, a portion of the staircase structure can be formed.

[0087] Figure 5L Explanation along Figure 5K A cross-sectional view of line C-C'. In other words, Figure 5L Explanation along Figure 5K Cross-sectional views of the second portions 542-1 and 542-2 of the conductor shown. Figure 5L As described, each memory cell region contains a vertical stack of horizontal wires, and each wire includes a portion 542 extending in the horizontal direction.

[0088] Each memory cell region may contain a group of several layers (e.g., 539-1, 539-2, 539-3), wherein each group of layers includes a first dielectric material layer 530-0, ..., 530-D, a semiconductor material layer 532-0, ..., 532-D, and a second dielectric material layer 533-0, ..., 533-D. One or more conductive lines are formed in the second dielectric material.

[0089] For example, the second dielectric material layers 533-0, ..., 533-D of each layer group 539-0, ..., 539-2 may contain a second portion 542 of one or more conductors. Each memory cell 540-1, ..., 540-W may be contained in a second dielectric material layer 533 above the top layer group 539-2.

[0090] Figure 5M This is a top view of a stage of an embodiment of a method for forming a conductor contact area having a plurality of multidirectional conductor and staircase conductor contact structures for a semiconductor device in an odd-even arrangement, according to an embodiment of the present disclosure. Figure 5M As shown, in some embodiments, each conductor may include a third portion (e.g., 543-1, ..., 543-4) extending in a third horizontal direction at an angle to the second horizontal direction. In some embodiments, such as Figure 5M As shown, the third part 543-1, ..., 543-4 can extend at an angle perpendicular to the second part 542-1, ..., 542-4 and parallel to the first part 541-1, ..., 541-4.

[0091] In some embodiments, the masking, patterning, and etching processes can be used to selectively open areas, for example, by... Figure 5MThe rectangles shown are identified as 594 (e.g., zones 594-1, ..., 594-2) to form a staircase structure as described below. Each zone may be a zone spanning multiple regions of the array structure. For example, a zone may include portions of array zone 540, bridge 546, and wire contact zone 547.

[0092] Zone 594 may include combinations such as Figure 5L The described group of vertically stacked layers, in which material can be removed from each zone to form, for example... Figure 5S The structures shown are as follows. For example, zones 594-1, ..., 594-2 may comprise groups of vertically stacked layers, each group of layers comprising a first dielectric material layer, a semiconductor layer, and a second dielectric material layer having wires formed therein. For example, zones 594-1, ..., 594-2 may comprise groups of layers 539-0, ..., 539-2, such as... Figure 5L As shown in the image.

[0093] Figure 5M Zones 594-1 to 594-7 are the already opened zones to form the lowest level of the staircase, for example, in Figure 5S The diagram in 5M shows level 535-1. As will be understood by the reader, the diagram in 5M represents the lowest level used to form the staircase and the opening area located above those parts of the staircase. Therefore, when forming other levels of the staircase, for example... Figure 5S As shown in 535-2 and 535-3, different areas will be open to form those structures.

[0094] One method that can be used to form these staircases involves two processes. First, an etching trimming sequence can be used to form the steps themselves, and subsequently, cutting or shredding a mask can be used to reduce the staircase structure to the desired level of a layered stack. Typically, a series of steps is formed, for example in... Figure 5S The three steps shown in C1-C1' (e.g., in) Figure 5S (as shown in 535-1, 535-2, and 535-3), and then the entire series of steps are introduced to their desired levels (e.g., in) through a cutting or shredding mask process. Figure 5S (as shown in vd-2, vd-3, and vd-4). For deeper layers, more than one cutting or shredding mask can be used.

[0095] Additionally, if multiple staircases (e.g., three steps of a staircase) are formed in different locations (e.g., Figure 5RIn some embodiments, all the stairs can be formed at the same level (e.g., all sets of stairs are formed at vertical depths of vd-1, vd-2, vd-3), and subsequently different cutting or shredding masking processes can be used to lower these sets of stairs to different levels. For example, in Figure 5S The two staircases shown at C1-C1' and C3-C3' can initially have vertical depths of vd-1, vd-2, and vd-3, but further cutting or shredding masking can be done at C3-C3' to lower the set of steps to vd-8, vd-9, and vd-10.

[0096] For example, a hypothetical reference line could be drawn through the center of each memory cell array to provide the reader with a reference when discussing the formation process in this article. Vertical openings could be formed, such as... Figure 5N As described in the document. In some embodiments, the reference line may be centered around the vertical opening. In some embodiments, the vertical opening may be centered around the intersection of the reference line and line C-C'.

[0097] Figure 5N It is along Figure 5M A cross-sectional view of line C-C'. (See example.) Figure 5N As shown, a vertical opening 580 may be formed through layers within vertically stacked memory cells to expose vertical sidewalls in the vertical stack. A hypothetical reference line 564 may pass through the center of each memory cell array region. The vertical opening 580 may be formed. In some embodiments, the reference line 564 may be centered on the vertical opening 580. In some embodiments, the vertical opening 580 may be centered around the intersection of the reference line 564 and line C-C'.

[0098] The vertical opening 580 may have a first horizontal width ( Figure 5N (w1) and the first vertical depth ( Figure 5N (as shown in "vd-1"). The vertical opening 580 can be formed by selectively removing one or more groups of layers from the top layers 538, 533 and subsequently vertically stacked layers 539-0, ..., 539-2. The vertically stacked layers are selectively removed at a first distance on each side of the reference line 564 (i.e., a first distance to the left side of the reference line 564 and a first distance to the right side of the reference line 564).

[0099] In some embodiments, a vertical opening 580 may be formed through a mask 538 and a second dielectric material 533. Forming a vertical opening 580 may involve removing a first portion of the mask 538 and a first portion of the second dielectric layer 533. The first portions of the mask 538 and the second dielectric material layer 533 may be equal in horizontal length. Although not explicitly stated... Figure 5NAs shown, in some embodiments where the mask 538 has not yet been deposited over the vertical stack 501, the vertical opening 580 may be formed through the top layer of the first dielectric material 530-D and / or the top layer of the second dielectric material 533.

[0100] like Figure 5N As shown, the vertical stack may include a layer of second dielectric material 533 having portions 542 of digital lines formed therein. In some embodiments, the vertical opening 580 may be formed by removing each layer of material between the top of the vertical stack and the first layer of the first dielectric material 530-D.

[0101] like Figure 5N As shown, a vertical stack can contain multiple levels (also called hierarchies) 539-0, ..., 539-2 (e.g., Figure 5N The three layers shown herein, wherein each layer 539-0, ..., 539-2 comprises a layer of semiconductor material 532 having one or more wires formed therein, a layer of first dielectric material 530, and a layer of second dielectric material 533. A vertical stack may comprise any number of such layers 539-0, ..., 539-2. As discussed herein, a vertical stack may be formed on a substrate 500.

[0102] As in Figure 5O to 5S , Figure 5T , Figures 6A to 6C The method for forming the various levels of the array region is shown in more detail below. It can be repeated in any number of iterations to form multi-level wire contacts at more than two levels. For example, the method can be repeated in several iterations to form eight levels of wire contacts, as in... Figure 5O to 5S , Figure 5T , Figures 6A to 6N As explained in the text.

[0103] Figure 5O Similar to embodiments of this disclosure Figure 5M The embodiment along Figure 5M The cross-sectional view taken along line C-C' illustrates another stage of the method for forming a conductor contact area having multiple multidirectional conductor and staircase conductor contact structures for a semiconductor device. In this embodiment, a stack of corresponding groups 539 having more layers 530, 532, 533 and layers 539 is provided.

[0104] The vertical depth of the vertical opening can be increased to a second vertical depth "vd-2". This can be accomplished by removing a portion of the second dielectric material 533 layer, which also contains the first portions 542-1 and 542-2 of the wires formed therein. A portion of the semiconductor material layer 532 can also be removed. At this stage, the openings in layers 533 (top layer), 530, 533, and 532 all have the same width as the width w1, as shown below. Figure 5O As shown in the image.

[0105] Figure 5P Similar to embodiments of this disclosure Figure 5M The embodiment along Figure 5M A cross-sectional view taken along line C-C' illustrates another stage of a method for forming a conductor contact area having multiple multidirectional conductor and staircase conductor contact structures for a semiconductor device. The method includes producing a first layer 548-1 and a second layer 548-2 that differ from the remaining portions of the layers in the vertically stacked layers 548-3.

[0106] This can be accomplished by removing a first portion of each layer in the first group of layers from reference line 564 backwards at a second distance 535-2 on either side, where the second distance 535-2 is greater than the first distance 535-1. And, by removing a first portion of each layer in the second group of layers from reference line 564 backwards at a first distance 535-1 on either side, where the second distance 535-2 is greater than the first distance 535-1. This will also create two distinct depths, vd-2 (for the top / first layer 548-1) and vd-3 (for the second layer 548-2).

[0107] In some embodiments, top level 548-1 may include levels not present in... Figure 5P The mask (e.g., photoresist layer), the top second dielectric material layer 533 having portions of digital lines formed therein, the first dielectric material layer 530, the second dielectric material layer 533, and the semiconductor material layer 532 shown are as discussed in the previous figures. However, embodiments of this disclosure are not limited thereto.

[0108] Figure 5QThe method describes the formation of a third layer 548-3, comprising layers of semiconductor material, conductive lines, and a first dielectric material. The method includes producing a first layer 548-1, a second layer 548-2, and a third layer 548-3 that differ from the remaining portions of the layers in a vertically stacked layer 548-4. This can be accomplished by removing a portion of each layer in a first group 548-1 from a third distance 535-3 backwards from reference line 564 on either side, where the third distance 535-3 is greater than the first distance 535-1 and the second distance 535-2. Furthermore, this is accomplished by removing a portion of each layer in a second group 548-2 from a second distance 535-2 backwards from reference line 564 on either side, where the second distance 535-2 is greater than the first distance 535-1. Additionally, this is accomplished by removing a portion of each layer in a third group 548-3 from a first distance 535-1 backwards from reference line 564 on either side, where the second distance 535-2 is greater than the first distance 535-1. This will also create three different depths: vd-2 (for the first level 548-1), vd-3 (for the second level 548-2), and vd-4 (for the third level 548-3).

[0109] Figure 5R This is a top view illustrating another stage of a method for forming wire contact areas having multiple multidirectional wire and staircase wire contact structures for a semiconductor device according to embodiments of the present disclosure. Lines C1-C1' travel along second portions 542-1 and 542-2, lines C2-C2' travel along fourth portions 544-1 and 544-2, and lines C3-C3' travel along second portions 551-1 and 551-2. As discussed below, each of these regions is differently formed to allow for connections to different levels of the stack.

[0110] Figure 5S Explanation along Figure 5R The cross-sections of lines C1-C1', C2-C2', and C3-C3' illustrate different structures that can be used to access different levels of the stack. Each cross-section contains the same vertical stack of horizontal digital lines and layers of first dielectric material 530, semiconductor material 532, and second dielectric material 533, but different staircase patterns are visible at different viewing lines in different locations within the stack. (See also...) Figure 5S As explained, group 548-4 of the layers at the bottom of the vertical stack can remain unchanged (no material is removed). This is as follows: Figure 5S It is understood that the number of layers in group 548-4 can vary based on the layers to be accessed for contact with sense amplifiers or other circuitry.

[0111] exist Figure 5SIn the illustration on the left, multiple levels 548-1, 548-2, and 548-3 can be accessed at depths within the stack of vd-2, vd-3, and vd-4. Furthermore, in Figure 5S In the diagram at the middle, multiple levels 548-1, 548-2, and 548-3 can be accessed at depths within the stack of vd-5, vd-6, and vd-7, and... Figure 5S In the illustration on the left, multiple levels 548-1, 548-2, and 548-3 can be accessed at depths within the stack of vd-8, vd-9, and vd-10. This is achieved by having vertical openings 535-1, 535-2, and 535-3 with widths different from reference line 564. Although three widths are shown, any suitable number of widths can be formed.

[0112] This staircase structure allows for direct vertical contact with sensing amplifiers or other circuit systems, such as in Figures 6A to 6N The explanation is in the text. Figure 5S In the embodiment described herein, this allows for contact with wires from nine sensing amplifiers or other circuits, thereby providing an increased density of wire contact areas that would not have been previously available. The reader should understand that this staircase concept can be used to connect wires to many (e.g., hundreds) sensing amplifiers or other circuits.

[0113] Figure 5T This illustration depicts a top view of several connections according to embodiments of the present disclosure and an example arrangement of these connections on a conductor contact area having multiple multidirectional conductors. This diagram illustrates a vertical connection area in which contact between a digital line and a sensing amplifier can be made. Although, as illustrated, each horizontal digital line area has three vertical connection areas in which contacts can be positioned, more or fewer areas may be available based on the space available for connection. In the illustrated diagram, the left side of the left array has three connection areas along each horizontal conductor section. For example, the points marked 0, 1, and 2 will each be connected to a second portion 542 / 642 of a different vertically stacked layer, as... Figure 6A As shown in the image. Figure 5T Each array shown has nine available interconnect locations (labeled 0, 1, 2, 3, 4, 5, 6, 7, 8); however, embodiments of this disclosure may have more or fewer interconnect locations. As can be understood based on the interconnect location numbering, the regions with interconnects 876-678 and the regions with interconnect locations 210-012 are configured as valleys, such as at C1-C1' and C3-C3'. Figure 5S As shown, the regions with interconnection locations 345-543 are configured as peaks, such as at C2-C2'. Figure 5SAs shown in the diagram. If more horizontal sections (and corresponding vertical levels) are provided, then more connected areas can be formed.

[0114] Figure 6A It is along Figure 5R A cross-sectional view of line C1-C1'. Figure 6B It is along Figure 5R A cross-sectional view of line C2-C2'. Figure 6C It is along Figure 5R The figures are cross-sectional views of line C3-C3'. These figures illustrate other example views of a method for forming a conductor contact area having a plurality of multidirectional conductors for a semiconductor device and a vertically oriented staircase conductor contact structure according to embodiments of the present disclosure.

[0115] In some embodiments and as Figures 6A to 6C As shown, a fourth dielectric material 637 may be deposited into the vertical opening 680. The fourth dielectric material 637 may be similar in composition to the first dielectric material 630. For example, in some embodiments, the first dielectric material 630 and the fourth dielectric material 637 may each comprise an oxide material.

[0116] exist Figures 6A to 6C The different levels of the numerical lines 642, 644, and 651 described herein can correspond to the following: Figure 5R The different levels of the digital lines 542, 544, and 551 described herein. In some embodiments, each digital line portion 642, 644, and 651 in the vertical stack may have a length greater than the corresponding digital line 642, 644, or 651 above it in the vertical stack 601.

[0117] Each vertically stacked level may contain digital lines 642, 644, or 651 coupled via vertical direct contacts to a sense amplifier or other circuitry, as described herein, on either side of reference line 664. For example, as... Figures 6A to 6C As described herein, conductor portions 642, 644, or 651 may be connected to the corresponding vertical direct contact 659 at or near the end of conductor portions 642, 644, or 651 (i.e., close to the end of a given level 648). Figure 6A As shown in Figure C, the vertical direct contact 659 can extend downward from the corresponding digital line 642, 644, or 651 above it in the vertical stack 601 to couple the corresponding digital line 642, 644, or 651 to the substrate 600. In some embodiments, due to each array region (e.g., Figure 5C There are two wires in array area 504-1, so the number of vertical direct contacts can be twice the number of levels 648. For example, such as Figure 6AThe three-tiered staircase structure described herein may have six vertical direct contacts as shown (e.g., in a folded digital line architecture).

[0118] like Figure 6A As explained, vertical direct contacts can extend in a vertical plane (e.g., as per [reference]). Figure 1 The third orientation (D3) 111 described. For example, a vertically oriented contact 659 can extend a distance 662 from the top surface 657 of the stack at a given level 648-2 to the substrate 600. Similarly, other vertically oriented contacts 659 can extend a corresponding distance 662 along the vertical plane 611 from the top surface of the respective levels 648-1, 648-3 to the substrate 600. That is, as Figure 6A As shown, the vertical direct contact 659 may have a length that can be varied among the vertical direct contacts 659.

[0119] The corresponding vertically oriented length 662 is equal to or greater than the distance between the corresponding conductors 642, 644 and 651 and the substrate 600.

[0120] like Figure 6D to 6G As shown, various embodiments may include a plurality of spaced-apart vertical openings 652 formed by a vertical stack passing through each of a plurality of multidirectional horizontal conductors 651 adjacent to the stair contact structure. Each level or tier in the stair contact structure may have at least one opening adjacent to each of the plurality of multidirectional horizontal conductors 651 to allow for the subsequent formation of at least one vertical direct contact for each of the plurality of multidirectional horizontal conductors. In various embodiments, the total number of the plurality of vertical openings 652 may be equal to twice the total number of levels or tiers in the stair contact structure. For example, each level may have a total of two laterally spaced openings, such that a first opening is on a corresponding side of opening 680 and a second opening is on the same level on the opposite side of opening 680, and other possibilities exist. The number of vertical openings 652 may be equal to the corresponding number of vertical direct contacts 659 subsequently formed in the openings 652. The number of vertical openings 652 may be equal to or greater than, for example, the corresponding number of horizontal conductors 642, 644, and 651.

[0121] Figure 6D This occurs after the process for forming the vertical opening has already been performed. Figure 6CA top view of portion 660. Masking, patterning, and etching processes can be used to form a vertical opening including a first opening 652-1 and a second opening 652-1 (commonly referred to as 652). For example, a selective etching process can be performed to selectively form the vertical opening 652 through the vertical stack 601. For example, in an embodiment where the conductor 651 is a metal such as tungsten, subsequent selective etching of the tungsten can be used to form the vertical opening 652. Due to selective etching, the vertical opening 652 can extend along a vertical plane within the vertical stack 601 (e.g., as per [reference to...]). Figure 1 The third party described (D3) 111).

[0122] For example, a vertical opening 652 may extend continuously from the top surface (e.g., top surface 657) of a given stacked layer (e.g., layer 648-2) to the substrate 600. The vertical opening 652 may have a length equal to or greater than the length of the vertically oriented conductor formed in the vertical opening 652 (extending along the vertical plane 611). The opening may allow vertical direct contacts (e.g., as...) Figure 6K to 6N The 659 described herein is formed in an opening to directly couple a corresponding digital line (e.g., 651) to a circuit system component 655-1, ..., 655-2 located below the corresponding digital line in the substrate 600. The circuit system component 655 may be disposed on or at least partially disposed within the substrate 600. In some embodiments, the vertical direct contact 659 may extend downward from the corresponding digital line in the vertical stack 601 to directly couple the corresponding digital line 642, 644, or 651 to the circuit system component 655-1, ..., 655-2 located below the corresponding digital line in the substrate 600. Such direct coupling can occur without the presence of intervention components such as interventional horizontal interconnects / jump wires that may be employed in a conventional manner. Directly coupling, for example, the horizontal conductors of digital lines to circuit system components 655-1, ..., 655-2 in substrate 600 can provide greater interconnect density, a reduced total number of components, and / or improved (i.e., reduced) parasitic resistance, at least in part due to the shorter electrical path provided by the connection between the digital lines and one or more circuit system contacts compared to conventional structures, such as those employing horizontal interconnects.

[0123] In some embodiments, the vertical opening (e.g., vertical opening 652-2) may have a length equal to the length of the corresponding vertically oriented conductor (e.g., vertically oriented conductor 659) formed in the opening (extending along the vertical plane 611). However, in some embodiments, the length to the vertical opening 652 may be greater than the length of the corresponding vertically oriented conductor 659 formed in the opening. In such embodiments, another material, such as a fourth dielectric material 637, may be disposed in the remaining length of the vertical opening 652 in which no vertically oriented conductor is formed (e.g., the distal portion of the opening furthest from the substrate 600 in which the conductive material in which no vertically oriented conductor is present). Although the figures depict a given number of openings, it should be understood that the total number of openings and / or the resulting vertically oriented contacts formed in the openings may vary.

[0124] Figure 6E This occurs after the process for forming the opening has already been performed. Figure 6C A top view of part 660. (e.g.) Figure 6E As shown, the vertical opening 652, including vertical openings 652-2 and 652-3, can extend through the top surface 657 of the stack 601 and can extend from the top surface of the stack through the conductor 651 to the substrate (for ease of illustration). Figure 6E (Not specified in the text).

[0125] Figure 6F It is along Figure 6D The cross-sectional view taken by line A-A', and Figure 6G It is along Figure 6D The cross-sectional view taken by line B-B'. For example... Figure 6F As shown, for example, the opening of a vertical opening 652-1 can extend around conductor 651 and into circuit system component 655-1 in the substrate. Similarly, as Figure 6F As shown, for example, the opening of the vertical opening 652-1 can extend around the conductor 651 and into the circuit system component 655-2 in the substrate.

[0126] like Figures 6H to 6J As shown, various embodiments include conformally depositing insulating material 667 in a plurality of spaced vertical openings 652. Figure 6H This occurs after the processes for forming the vertical opening 652 and depositing insulating material 667 within the opening have been performed. Figure 6C A top view of portion 660. The insulating material 667 may comprise one or more of silicon oxide, silicon nitride, and / or silicon oxynitride. However, the embodiments are not limited to these examples.

[0127] In various embodiments, the insulating material 667 can be deposited conformally in the vertical opening 652. For example, such as Figure 6H-6J As shown, insulating material 667 can be deposited on the sidewalls of the openings in the stack and on the sidewalls of the pillars (e.g., the sidewalls of the pillars on which conductor 651 is located). The sidewalls of the openings and the sidewalls of the pillars in the stack can be a result of forming the openings, such as... Figure 6D to 6G As described herein. In various embodiments, once formed, the insulating material 667 may be adjacent to at least a portion of the vertical direct contact. In other words, once the conductive material 661 (e.g., as described herein) is formed, Figure 6K to 6N As described in the text, the insulating material 667 is placed in a vertical opening 652 in which an insulating material 667 is deposited, such that the insulating material 667 may be adjacent to at least a portion of the conductive material 661. In some instances, the insulating material 667 may be conformally deposited in the opening 652 and subsequent etching may be performed.

[0128] Figure 6I It is along Figure 6H The cross-sectional view taken by line A-A', and Figure 6J It is along Figure 6H The cross-sectional view taken by line B-B'. For example... Figure 6I As shown, insulating material 667 can be deposited conformally in opening 652-1. Similarly, as Figure 6J As shown, insulating material 667 can be conformally deposited in opening 652-3. In various embodiments, insulating material 667 in opening 652-1 can be the same insulating material as insulating material 667 in opening 652-2. Insulating material 667 can electrically isolate components, such as isolating corresponding wires in conductor 659 from other conductors 651.

[0129] like Figure 6K to 6N As shown, various embodiments include depositing conductive material 661 in a plurality of spaced-apart vertical openings to form vertical direct contacts 659. As... Figure 6K to 6N As shown, the vertical direct contact 659 can directly electrically couple wires 651 (e.g., multiple multi-directional horizontal wires) to circuit system components 655-1, 655-2 in the substrate 600. In some embodiments, the conductive material 661 can be a doped semiconductor material, a conductive metal nitride, a metal, a metal-semiconductor compound, or any combination thereof. In some embodiments, the conductive material 661 can be a metal such as tungsten.

[0130] Figure 6K This occurs after the processes for forming opening 652 and depositing insulating material 667 and conductive material 661 in the opening have been performed. Figure 6C A partial 660-degree view. Figure 6LThis illustrates a vertically oriented contact 659 after the processes for forming opening 652 and depositing insulating material 667 and conductive material 661 into the opening have been performed. Figure 6C A partial 660° top view. In other words, Figure 6L This shows a vertically oriented contact 659. Figure 6C A top view of part 660.

[0131] Figure 6M It is along Figure 6K The cross-sectional view taken by line A-A', and Figure 6N It is along Figure 6K The cross-sectional view taken by line B-B'. For example... Figure 6M As shown, conductive material 661 can be deposited in the remaining portion of opening 652-1 after the deposition of insulating material 667 in opening 652-1. Similarly, as Figure 6N As shown, conductive material 661 can be deposited in the remainder of opening 652-2 after the deposition of insulating material 667 in opening 652-2. In various embodiments, the conductive material 661 in opening 652-1 can be the same as the conductive material (e.g., a metal such as tungsten) in opening 652-2. Figure 6L , 6M As described in 6N, in some embodiments the insulating material 667 may be adjacent to the vertical direct contact, such as the vertical direct contact 659.

[0132] Figure 7A This indicates that it has a lateral relationship. Figure 7C A cross-sectional view of a portion of a conventional 3D memory array, cut along line C-C'. (See image.) Figure 7A As shown, portions of different levels of digital line 751 can be coupled to several sense amplifiers or other circuit systems via interconnects 734 located at a distance (e.g., distance 753) above digital line 751, such interconnects as in Figure 7B and 7C The details include horizontal interconnects. That is, a conventional 3D memory array can extend from a relatively long electrical path (e.g., distance 753) over the conductors (e.g., above the digital line 751 in the direction opposite to the substrate 600), and once at the top / far end of distance 753, it extends horizontally to distance 758, after which the conductive path eventually extends downwards another distance (e.g., as shown in the diagram). Figure 7B The distance described in the document is 754 to the substrate 600.

[0133] Figure 7B It means to explain along Figure 7C A cross-sectional view of another portion of a conventional 3D memory array, cut by the cutting line D-D'. (As shown relative to...) Figure 7A As mentioned, once the conductor is at the top / far end of 753, it extends horizontally a distance (e.g., equal to at...). Figure 7C The distance between the cutting lines C-C' and D-D' in the circuit is from the circuit system contact 755, and then the conductive path eventually extends downwards by another distance 754 to the substrate 700.

[0134] Figure 7C This is a top view of a conventional 3D memory array with horizontal interconnects. (Example) Figure 7C As explained in the document, the conductors (707-1, 707-2) can be formed with a multi-pointed fork-like arrangement (when from, for example...). Figure 7C As described above when viewed from above in a vertically stacked configuration, the first portions 741 of the conductors (e.g., 741-1, 741-2) are aligned in a first direction D1 (e.g., aligned with one side of the memory array) and the second portions 742 (i.e., each located on a different level of the vertically stacked layers) are angled to the first portions (e.g., in direction D2). The second portions 742 are also laterally spaced (e.g., arranged parallel to each other) to allow for the formation of interconnects containing vertical interconnects for each segment 742.

[0135] Each second (minor) part 742-1, ..., 742-G can extend at an angle perpendicular to the first part 741. In other words, the first part 741 can extend in the D1 direction, and the minor parts 742-1, ..., 742-G can each extend in the D2 direction. For example, Figure 7D This describes the four secondary sections 742-1, ..., 742-G of conductors 707-1 and 707-2 that extend in the second direction D2 of the first direction D1 of the first sections 741-1 and 741-2 of conductors 707-1 and 707-2, respectively.

[0136] For example, each secondary portion 742-1, ..., 742-G may be interconnected to a sense amplifier or other circuitry contact 755 via, for example, a horizontal interconnection of a contact jumper 749. At least a portion of the contact jumper 749 extends in a first direction D1 (e.g., horizontally at a distance 758). The number of contact jumpers 749 coupled to the sense amplifier or other circuitry connected to each secondary portion 742-1, ..., 742-G may be equal to the number of secondary portions 742-1, ..., 742-G for each conductor. Although Figure 7BFour secondary portions 742-1, ..., 742-G are described, but the number of secondary portions can be varied. Source / drain regions can be formed within the semiconductor material. In some embodiments, the secondary portions 742-1, ..., 742-G can be spaced approximately equidistant from each other. Contact jumpers 749 with top teeth coupled to the secondary portions 742-1, ..., 742-G can be aligned in columns C1, C2, C3, and C4, and other possible arrangements.

[0137] Each contact jumper 749 can be coupled to the conductor 707 via an interconnect 734. The interconnect 734 may include interconnects to the source / drain regions. That is, the electrical path from the conductor 707 to the contact 755 of the sense amplifier or other circuitry includes horizontal interconnects in the form of at least jumpers 749. Therefore, the electrical path of a conventional 3D memory array with horizontal interconnects is longer compared to the approach described herein, which uses vertical direct contacts (e.g., formed in the absence of horizontal interconnects). The relatively long electrical path with horizontal interconnects can make conventional three-dimensional (3D) memory arrays with horizontal interconnects susceptible to signal attenuation, etc.

[0138] Compared to conventional 3D memory arrays with horizontal interconnects, the embodiments described herein relate to vertical direct contacts for memory devices. For example, Figure 7D This is a top view of a 3D memory array according to an embodiment of the present disclosure. (As shown) Figure 7D As shown, the 3D memory array has vertical direct contacts 759, as described herein. Notably, the vertical direct contacts 759 provide a direct and shorter electrical path between the conductor 707 and the circuit system contacts 755, at least due to the absence of horizontal interconnects and / or due to the absence of interconnects extending a distance above the conductor. In other words, in Figure 7D The electrical paths in the 3D memory array are shorter due to the absence of a horizontal distance of 758 and / or due to, for example, in Figures 7A to 7C The lack of distance above the wires inherent in those conventional arrays described in the text.

[0139] Figure 8 This is a block diagram of a device in the form of a computing system 880 including a memory device 882, according to embodiments of the present disclosure. As used herein, for example, the memory device 882, memory array 888, and / or host 881 may also be individually considered a "device". According to embodiments, the memory device 882 may include at least one memory array 888 having memory cells formed by wire contact areas having a plurality of multidirectional wires and vertical direct contacts, according to embodiments described herein.

[0140] In this example, system 880 includes a host 881 coupled to memory device 882 via interface 883. The computing system 880 can be a personal laptop, desktop computer, digital camera, mobile phone, memory card reader, or Internet of Things (IoT) enabled device, as well as various other types of systems. Host 881 may include several processing resources (e.g., one or more processors, microprocessors, or other types of control circuitry) capable of accessing memory 882. System 880 may include a separate integrated circuit, or host 881 and memory device 882 may be on the same integrated circuit. For example, host 881 may be a system controller for a memory system including multiple memory devices 882, wherein system controller 884 provides access to the respective memory devices 882 via another processing resource, such as a central processing unit (CPU).

[0141] exist Figure 8 In the example shown, host 881 is responsible for executing an operating system (OS) and / or various applications (e.g., processes) that can be loaded onto it (e.g., from memory device 882 via controller 884). The OS and / or various applications can be loaded from memory device 882 by providing access commands from host 881 to memory device 882 for accessing data including the OS and / or various applications. Host 881 can also access said data used by the OS and / or various applications by providing access commands to memory device 882 for retrieving data used during the execution of the OS and / or various applications.

[0142] For clarity, system 880 has been simplified to focus on features particularly relevant to this disclosure. Memory array 888 may be a DRAM array comprising at least one memory cell having vertical direct contacts formed according to the techniques described herein. For example, memory array 888 may be an unshielded DL 4F2 array, such as a 3D-DRAM memory array. Array 888 may contain memory cells arranged in rows coupled via word lines (which may be referred to herein as access lines or select lines) and columns coupled via digital lines (which may be referred to herein as sense lines or data lines). Although in Figure 1 The diagram shows a single array 888, but embodiments are not limited thereto. For example, a memory device 882 may include several arrays 888 (e.g., an array of DRAM cells).

[0143] Memory device 882 includes address circuitry 885 to latch address signals provided via interface 883. The interface may include, for example, a physical interface employing a suitable protocol (e.g., a data bus, address bus, and command bus, or a combined data / address / command bus). This protocol may be custom or proprietary, or interface 883 may employ a standardized protocol, such as Peripheral Component Interconnect High Speed ​​(PCIe), Gen-Z, CCIX, or similar. Row decoder 887 and column decoder 890 receive and decode the address signals to access memory array 888. Data can be read from memory array 888 by sensing voltage and / or current changes on a sensing line using sensing circuitry 889. Sensing circuitry 889 may include, for example, a sensing amplifier that can read and latch pages (e.g., rows) of data from memory array 888. I / O circuitry 886 can be used for bidirectional data communication with host 881 via interface 883. Read / write circuitry 891 is used to write data to or read data from memory array 888. As an example, circuit system 891 may include various drivers, latching circuit systems, etc.

[0144] The control circuitry 884 decodes signals provided by the host 881. These signals can be commands provided by the host 881. These signals may include chip enable signals, write enable signals, and address latch signals, which control operations performed on the memory array 888, including data read operations, data write operations, and data erase operations. In various embodiments, the control circuitry 884 is responsible for executing instructions from the host 881. The control circuitry 884 may include a state machine, a sequencer, and / or some other type of control circuitry system, which may be implemented in hardware, firmware, or software, or any combination of these. In some instances, the host 881 may be a controller external to the memory device 882. For example, the host 881 may be a memory controller coupled to the processing resources of a computing device.

[0145] For example, the term semiconductor can refer to a material, wafer, or substrate, and includes any substrate semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon supported by a substrate semiconductor structure, and other semiconductor structures. Furthermore, when referenced to semiconductor in the foregoing description, prior process steps may have been used to form regions / junctions in the substrate semiconductor structure, and the term semiconductor can include an underlying material containing such regions / junctions.

[0146] As will be understood, elements shown in the various embodiments herein may be added, swapped, and / or removed to provide several additional embodiments of this disclosure. Additionally, as will be understood, the scales and relative dimensions of the elements provided in the figures are intended to illustrate embodiments of this disclosure and should not be construed as limiting.

[0147] As used herein, “several” or “a certain number” of something can refer to one or more of such things. For example, “several” or “a certain number” of memory cells can refer to one or more memory cells. “A certain number” of something means two or more. As used herein, multiple actions performed simultaneously refer to actions that overlap at least partially within a specific time period. As used herein, the term “coupling” can include electrical coupling, direct coupling and / or direct connection (e.g., through direct physical contact) without an intervening element, or indirect coupling and / or connection with an intervening element, or wireless coupling. The term coupling can further include two or more elements that cooperate or interact with each other (e.g., causally related). An element coupled between two elements can be between the two elements and coupled to each of the two elements.

[0148] As used herein, the term "minor portion" may be used synonymously with the term "secondary portion," meaning a portion that extends in a different direction compared to the "first portion" or "major portion." For example, the first portion may extend in a first direction, and several minor portions may extend in a second direction perpendicular to the first direction.

[0149] The terms "first part" and "second part" may be used herein to refer to two parts of a single element. For example, "first part" and "second part" of a digital line may refer to two parts of a single digital line. It is not desired that the parts referred to as "first" and / or "second" have a single, unique meaning. It is only desired that one of the "parts" extends in a direction different from the other.

[0150] It should be recognized that the term "vertical" refers to a change from "fully" vertical due to variations in routine manufacturing, measurement, and / or assembly, and the meaning of the term "vertical" will be understood by one of ordinary skill in the art. For example, vertical can correspond to the z-direction. As used herein, when a particular element is "adjacent" to another element, the particular element may cover the other element, may be above or laterally to the other element, and / or may be in direct physical contact with the other element. For example, laterally to can refer to a horizontal direction that may be perpendicular to the z-direction (e.g., the y-direction or x-direction).

[0151] While specific embodiments have been described and illustrated herein, those skilled in the art will understand that arrangements calculated to achieve the same results may replace the specific embodiments shown. This disclosure is intended to cover adaptations or variations of various embodiments of this disclosure. It should be understood that the above description has been presented in an illustrative rather than restrictive manner. Combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art upon review of the foregoing description. The scope of the various embodiments of this disclosure includes other applications using the above structures and methods. Therefore, the scope of the various embodiments of this disclosure should be determined by reference to the appended claims together with the full scope of the equivalents granted thereto.

Claims

1. A memory device (882) having an array of vertically stacked memory cells (110) with vertical direct contacts (659, 759), the memory device comprising: A substrate (600) comprising circuit system components (655); A vertical stack of layers (601), formed from repeated iterations of a group of layers disposed on the substrate, the group of layers comprising: First dielectric material layer (530), Semiconductor material layer (532), and A second dielectric material layer (533) comprising horizontal conductors (507) formed along a horizontal plane (D1) in the second dielectric material layer; and A vertical direct contact (659) coupled to the horizontal conductor extends along a vertical plane (D3) within the vertical stack of the layers to directly electrically couple the horizontal conductor to the circuit system component.

2. The memory device of claim 1, wherein the vertical direct contact is formed of a conductive material.

3. The memory device of claim 2, wherein the vertical direct contact is formed of a doped semiconductor material, a conductive metal nitride, a metal, a metal-semiconductor compound, or any combination thereof.

4. The memory device of claim 1, wherein the vertical direct contact directly electricalally couples the horizontal wire to the circuit system component without additional interconnects.

5. The memory device of claim 1, wherein the electrical path between the horizontal conductors directly electrically coupled to the circuit system component is shorter than the electrical path of a different memory device employing at least an additional horizontal interconnect located between the horizontal conductors and the circuit system component.

6. The memory device of claim 1, further comprising an insulating material (667) adjacent to at least a portion of the vertical direct contact.

7. The memory device of claim 6, wherein the insulating material is selected from silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

8. The memory device according to any one of claims 1 to 2, wherein the horizontal conductor is a digital line.

9. The memory device according to any one of claims 1 to 2, wherein the memory device is a three-dimensional (3D) dynamic random access memory device.

10. The memory device according to any one of claims 1 to 2, wherein the horizontal conductor is configured in a stair contact structure having multiple levels (535).

11. The memory device of claim 1, wherein the array of vertically stacked memory cells further comprises a plurality of horizontal access devices.

12. The memory device of claim 11, wherein each of the plurality of horizontal access devices is directly electrically coupled to a corresponding circuit system component in the circuit system component via a corresponding vertical direct contact in the vertical direct contact.

13. The memory device of claim 12, wherein the total number of the vertical direct contacts is equal to the total number of the plurality of horizontal access devices.

14. A method for forming an array of vertically stacked memory cells (110) having vertical direct contacts (659), comprising: In repeated iterations, several layers (530, 532, 533) are vertically formed to form a vertical stack (601) on a substrate, the layers comprising: a first dielectric material layer (530) having conductors (507, 707) formed therein along a horizontal plane (D1), a semiconductor material layer (532), and a second dielectric material layer (533); the second dielectric material layer having a plurality of multidirectional horizontal conductors (707), the multidirectional horizontal conductors (707) having a first portion (741) extending in a first horizontal direction (D1) and a second portion (742) extending in a second horizontal direction (D2) at an angle to the first horizontal direction, and wherein the second portions are laterally spaced apart from each other to allow vertical direct contacts (659, 759) to couple to the second portions; In the region containing at least the second portion of the conductor, a removal process is performed in repeated vertical iterations to form a staircase contact structure. The vertical stacks passing through each of the plurality of multidirectional horizontal guides in the stair contact structure having multiple levels (535) form spaced vertical openings (580). An insulating material (667) is conformally deposited in the spaced-apart vertical openings; and Conductive material (661) is deposited in the spaced vertical openings to form vertical direct contacts (659) to directly electrically couple the plurality of multidirectional horizontal wires in the stair contact structure to the circuit system assembly (655) in the substrate.

15. The method of claim 14, wherein forming the spaced-apart vertical opening further comprises forming the spaced-apart vertical opening by the vertical stack passing through the second portion of each of the plurality of multidirectional horizontal guides adjacent to the stair contact structure.

16. The method of claim 14, wherein forming the spaced-apart vertical opening further comprises forming the spaced-apart vertical opening extending at least along the entire corresponding distance between each of the plurality of multidirectional horizontal conductors and the substrate.

17. The method according to any one of claims 14 to 16, wherein performing the removal process to form the stair contact structure comprises: Selectively remove a portion of each layer in a first group of layers of the plurality of layers by removing the portion of each layer in the first group of layers between a reference line (564) and a first distance (535-1) from the reference line; Selectively remove a portion of each layer in a second group of layers from the plurality of layers by removing the portion of each layer in the second group of layers between the reference line and a second distance (535-2) from the reference line; as well as Selectively remove a portion of each layer in a third group of the plurality of layers by removing the portion of each layer in the third group of layers between a reference line and a third distance (535-3) from the reference line. The third distance is greater than the second distance, and the second distance is greater than the first distance.

18. A memory device (882) comprising: Contacts for conductive circuit systems, which are disposed on a substrate; Multiple stacked horizontal conductors (651) are above the substrate and have an insulating layer inserted between each of the multiple stacked horizontal conductors; Insulating material (667), which is disposed on the sidewall of the insulating layer and on the sidewall of each of the stacked horizontal conductors; as well as Multiple vertical direct contacts (659) are coupled to the respective top surfaces (657) of the multiple stacked horizontal conductors to directly electrically couple the respective top surfaces to the corresponding conductive circuit system contacts in the conductive circuit system contacts.

19. The memory device of claim 18, wherein the plurality of stacked horizontal conductors are horizontal digital lines or word lines.

20. The memory device according to any one of claims 18 to 19, wherein the insulating material is conformally disposed on the sidewalls of the entire insulating layer and on the sidewalls of each of the stacked conductors, but not on the respective top surfaces of the plurality of stacked horizontal conductors.

Images