Semiconductor device and method of manufacturing the same

Abstract

Embodiments provide a semiconductor device and a manufacturing method thereof capable of easily establishing correspondence between a position on an observation image and a position on design data. According to an embodiment, a semiconductor device is provided, including: a circuit pattern including a plurality of unit patterns arranged repeatedly in at least one direction; and a discrimination pattern provided in the circuit pattern, capable of discriminating the unit patterns.

Description

[0001] [Related Application]

[0002] This application claims priority to Japanese Patent Application No. 2021-32632 (filed on March 2, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to semiconductor devices and methods for manufacturing the same. Background Technology

[0004] In semiconductor device manufacturing methods, in addition to the processes of forming semiconductor devices such as etching and deposition, there are also observation processes that observe interlayer insulating films with trenches and holes for wiring, vias, and contacts, or wiring layers with wiring formed. In the observation process, for example, an optical microscope or a scanning electron microscope (SEM) is used to confirm the presence or absence of manufacturing problems such as unexpected particle scattering. If a location causing a manufacturing problem is found, its location information becomes important for improving yield. However, when the same pattern is repeatedly formed on a substrate, it is sometimes difficult to determine which part of the design data corresponds to the image obtained through observation. Summary of the Invention

[0005] One embodiment provides a semiconductor device and a method thereof capable of easily establishing a correspondence between positions on an observed image and positions on design data.

[0006] According to one embodiment, a semiconductor device is provided, comprising: a circuit pattern including a plurality of unit patterns repeatedly arranged in at least one direction; and a discrimination pattern disposed within the circuit pattern, capable of discriminating the unit patterns. Attached Figure Description

[0007] Figure 1 It is a diagram illustrating a circuit pattern formed by repeating and arranging unit patterns in a semiconductor device according to an embodiment.

[0008] Figure 2 This is a diagram illustrating the effect of the circuit pattern of the semiconductor device according to this embodiment.

[0009] Figure 3 It is a top view schematically representing a modified circuit pattern.

[0010] Figure 4 It is a top view schematically representing the circuit pattern of other variations.

[0011] Figure 5 It is a top view schematically representing the circuit pattern of other variations.

[0012] Figure 6 It is a top view schematically representing the circuit pattern of other variations.

[0013] Figure 7 It is a top view schematically representing the circuit pattern of other variations.

[0014] Figure 8 This is an explanatory diagram illustrating the circuit pattern of another variation.

[0015] Figure 9 This is a block diagram schematically representing the structure of a NAND flash memory.

[0016] Figure 10 It is a block diagram schematically representing the structure of a DRAM memory.

[0017] Figure 11 It is a block diagram that schematically represents the structure of a camera element.

[0018] Explanation of reference numerals in the attached figures

[0019] 1… Semiconductor device; 10, 100, 101, 102… Unit pattern; 114, 120, 121, 130, 131, 150, 161, 170… Circuit pattern; 14, 16, 140, 160… Discrimination pattern; C, C1, C2, C3… Connection part; OPL, OPL1~OPL6, OPU, OPU1~OPU6, OPM… Opening; DP, DP1, DP2, DP3… Cut-off part. Detailed Implementation

[0020] Hereinafter, non-limiting exemplary embodiments of the present invention will be described with reference to the accompanying drawings. Throughout the drawings, identical or corresponding parts or components are labeled with the same or corresponding reference numerals, and repeated descriptions are omitted. Furthermore, the drawings are not intended to show relative comparisons between parts or components; therefore, specific thicknesses and dimensions can be determined by those skilled in the art by referring to the following non-limiting embodiments.

[0021] Reference Figure 1An example of a circuit pattern in a semiconductor device according to the embodiment will be described. The semiconductor device in this embodiment is not limited; for example, it could be a semiconductor memory device. Furthermore, as a circuit pattern, an example is a circuit pattern formed by repeatedly arranging multiple unit patterns having the same shape in one direction. When an observation image is obtained during the semiconductor device manufacturing process, the circuit pattern in this embodiment is considered as the object of the observation image. Therefore, it is assumed that the observation image is an image obtained from the upper surface of the semiconductor substrate. In addition, the shapes of wiring connected to components on the circuit diagram and the shapes of wiring not connected to components on the circuit diagram both appear in the observation image and are therefore considered as objects of the circuit pattern. Furthermore, as described later, the circuit pattern is not limited to wiring; it can also be slots or holes appearing in the observation image. Examples of circuits and semiconductor devices forming such circuit patterns will be described later.

[0022] Figure 1 (a) is a schematic top view representing the unit pattern. Figure 1 (b) is a schematic top view representing a circuit pattern formed by multiple unit patterns. Figure 1 (c) is a top view schematically showing the circuit pattern of the semiconductor device 1 according to this embodiment. The unit pattern, circuit pattern, and discrimination pattern include, for example, wiring formed on an insulating film by a conductive material such as metal or conductive polysilicon. In other words, the unit pattern, circuit pattern, and discrimination pattern may be wiring formed on the same layer in the semiconductor device 1.

[0023] like Figure 1 As shown in (b), Figure 1 The unit pattern 10 shown in (a) is repeated in the X direction to form a circuit pattern 12. The unit pattern 10 may be a wiring pattern formed relative to, for example, a column (or row) of the semiconductor device 1 of this embodiment, which is a semiconductor memory device. In the illustrated example, the unit pattern 10 includes a plurality of lines 10A extending in the Y direction, a line 10B that also extends in the Y direction but is shorter than the line 10A, and a connection portion 10C connecting the line 10B to the line 10A. The unit pattern 10 is formed, for example, relative to a column (or row), and the column (or row) is repeated. The repeated arrangement of the unit pattern 10 forms the circuit pattern 12.

[0024] The circuit pattern 120 in this embodiment is as follows: Figure 1As shown in (c), in addition to circuit pattern 12, there is also a discrimination pattern 14. In the illustrated example, discrimination pattern 14 has four discrimination shapes 14A, 14B, 14C, and 14D. Discrimination shape 14A is a line extending continuously in the Y direction, and discrimination shapes 14B to 14D are combinations of multiple lines of different lengths in the Y direction. Thus, discrimination shapes 14A to 14D have different shapes, and therefore can be distinguished from each other. In addition, discrimination shapes 14A to 14D are sequentially arranged in the blank areas BA of the four unit patterns 10. Figure 1 Therefore, they are arranged in this order along the X direction. Here, the blank area BA is an area where circuit elements such as lines are not formed, but where the insulating film of the same layer as the base layer of the wiring layer constituting the circuit pattern or the wiring layer constituting the circuit pattern is exposed over a relatively wide range. In addition, although the illustration is omitted, the unit pattern 10 is also repeatedly arranged on the left and right sides of the figure, and the discrimination patterns 14A to 14D are also periodically arranged in this order along the X direction relative to these unit patterns 10.

[0025] The circuit pattern 120 is generated in advance based on design data. The positions of each unit pattern 10 and the discrimination patterns 14A to 14D can be determined on the design data with coordinates originating from a specified coordinate reference point (e.g., an alignment mark). Alternatively, the circuit pattern 120 can be formed using a photolithography process employing a photomask fabricated based on design data, such as forming trenches on an insulating film, filling trenches with a conductive material like metal, and then removing the conductive material from the insulating film using chemical mechanical polishing (CMP). Alternatively, the circuit pattern 120 can be formed using a reactive ion etching (RIE) process, which involves depositing a thin film of a conductive material such as metal or conductive polysilicon, a photolithography process employing a photomask fabricated based on design data, and an etching process.

[0026] Furthermore, the unit patterns 10 within the circuit pattern 12 each include discrimination patterns 14A to 14D, and therefore do not have the same shape. Thus, a circuit pattern consisting of repeatedly arranged unit patterns of the same shape does not exist. Therefore, here, a circuit pattern consisting of repeatedly arranged unit patterns of the same shape refers to a pattern in which, if there is no discrimination pattern capable of discriminating the unit patterns, the unit patterns cannot be individually discriminated by surface observation.

[0027] Furthermore, the shapes of the unit patterns 10 within the circuit pattern 12 only need to be the same within the tolerance range of the manufacturing process. In the attached drawings, for example, the identification patterns 14A to 14D have right-angled corners, but in reality, depending on the manufacturing process (etching), they may also have rounded corners.

[0028] Next, refer to Figure 2The effects of circuit pattern 120 will be explained. Figure 2 This diagram illustrates the effect of the circuit pattern 120 of the semiconductor device 1 according to this embodiment. Specifically, Figure 2 (a) is a schematic top view of a semiconductor substrate having circuit pattern 12 as a comparative example. Figure 2 (b) is a schematic top view showing a semiconductor substrate having circuit pattern 120. Figure 2 In (a) and (b), the imaging range (field of view) IR of circuit patterns 12 and 120 is shown when they are photographed using a scanning electron microscope (SEM) as a means of surface observation. That is, the shape within the imaging range IR is obtained as an image data.

[0029] When observing circuit pattern 12 using SEM in a so-called die-to-die manner, the result is the detection of particulate PCL, such as... Figure 2 As shown in (a), an image of the circuit pattern 12 with microparticles PCL is displayed in the SEM image data. At this time, although the microparticles PCL are actually located at position Pt, coordinate information such as "microparticles PCL at position Pf" is sometimes represented in a die-to-die manner. Such offset may occur, for example, due to errors arising from the movement of the stage holding the substrate being measured within the SEM. In this case, even if it is desired to determine the actual location Pt of the microparticles PCL in the design data, it is not easy to determine which unit pattern 10 is near where position Pt is located because the unit pattern 10 is repeated in the circuit pattern 12.

[0030] However, according to this embodiment, such as Figure 2 As shown in (b), the circuit pattern 120 has a discrimination pattern 14, with discrimination patterns 14A to 14D having different shapes. Therefore, based on the SEM image data, it can be determined that a discrimination pattern 14B exists near the position Pt of the particle PCL. Thus, even if the coordinates of the particle's position Pf shown in a die-to-die manner deviate from the coordinates in the design data of the actual position Pt of the particle PCL, correction can be made based on the coordinates of the discrimination pattern 14B. In this way, the position of the particle PCL in the design data can be determined. That is, because of the existence of the discrimination pattern 14, matching the image data obtained by SEM with the design data becomes easy, and the position of the particle PCL can be determined in the design data.

[0031] Furthermore, the number of discrimination patterns may not be equal to the number of repetitions of the unit pattern 10. For example, instead of assigning a discrimination pattern to each of the unit pattern 10, discrimination patterns may be assigned every other one, every two, or at intervals of two or more. This reduces the number of discrimination patterns that need to be prepared, and makes the shapes of each discrimination pattern clearly distinct.

[0032] Furthermore, the number of discrimination patterns to be prepared can be determined based on the number of unit patterns captured by the SEM image as a whole under a specified imaging range and magnification. For example, if the width (repetition interval) of each unit pattern repeatedly arranged in the X direction is 400 nm and the width of the SEM imaging range IR on the substrate is equivalent to 9 μm, 22 unit patterns 10 can be captured in the SEM image. In this case, 22 discrimination patterns with different shapes can be prepared and assigned to the 22 unit patterns 10 respectively. In this case, the 22 discrimination patterns with different shapes are arranged periodically, and all unit patterns 10 have discrimination patterns. Alternatively, 11 discrimination patterns with different shapes can be prepared and assigned every other unit pattern 10, and 22 unit patterns 10 with discrimination patterns assigned every other one can be arranged periodically. Alternatively, for example, 8 different discrimination patterns with different shapes can be prepared and assigned every two unit patterns 10, and 22 unit patterns 10 with discrimination patterns assigned every two can be arranged periodically. Furthermore, a discrimination graphic can be set every three or more unit patterns.

[0033] Furthermore, the number of discrimination patterns to be prepared can be determined by the potential positional error (in the example above, the difference between position Pt and position Pf) that may arise from the die-to-die method. The potential positional error from the die-to-die method is considered to be, for example, 0.5 μm to 2 μm, but assuming it is 1.5 μm and the width of the unit pattern 10 is 400 nm, only 3 discrimination patterns need to be prepared. Thus, the positions of the discrimination patterns near position Pf shown by the die-to-die method can be known, and therefore the actual position Pt can be determined. Similarly, with a positional error of 1.5 μm and a repeating interval of 80 nm, only 13 discrimination patterns need to be prepared; with a repeating interval of 40 nm, only 25 discrimination patterns need to be prepared. Furthermore, with a position error of 1.5 μm, if the discrimination pattern is configured in a manner smaller than the position error but larger than half of the position error, for example, every 1 μm, the position Pf of the particle PCL shown in the die-to-die manner can be corrected, and the actual position Pt can be determined.

[0034] Furthermore, the magnification of the SEM is considered to vary depending on the width, line width, and spacing of the circuit pattern 12. If the SEM magnification is different, the imaging range IR, the possible positional errors, and the number of unit patterns 10 observed within the imaging range IR will differ. Therefore, the magnification and resolution can also be considered in determining the type and configuration of the pattern.

[0035] (Modified Example)

[0036] Next, refer to Figure 3 Examples of variations of the circuit pattern are explained. Figure 3 It is a top view schematically representing a modified circuit pattern.

[0037] Reference Figure 3 (a) Circuit pattern 121 has a unit pattern 10 and a discrimination pattern 16 that are repeatedly arranged in the X direction. The discrimination pattern 16 has discrimination shapes 16A, 16B, 16C, and 16D, which are arranged corresponding to the unit pattern 10. The discrimination shapes 16A to 16D each have line shapes of different lengths, and are arranged in the blank area BA of the unit pattern 10 (refer to...). Figure 1 In (a)), the lines 10A and 10B of the unit pattern 10 are arranged separately. Due to their different lengths, the discrimination patterns 16A to 16D can be distinguished, thereby enabling the discrimination of the unit pattern 10, which is respectively arranged with discrimination patterns 16A to 16D.

[0038] Reference Figure 3 (b) Circuit pattern 130 has a unit pattern 10 and a discrimination pattern 160 repeatedly arranged in the X direction. Discrimination pattern 160 has discrimination patterns 160A, 160B, 160C, and 160D, which are arranged corresponding to the unit pattern 10. Discrimination patterns 160A to 160D are arranged in a manner corresponding to the unit pattern 10. Figure 3 Similarly, the discrimination patterns 16A to 16D shown in (a) have line shapes of different lengths and are arranged in the blank area BA of the unit pattern 10 (see reference). Figure 1(a) However, the discrimination patterns 160A to 160D differ from the discrimination patterns 16A to 16D in that they are connected to the line 10B of the unit pattern 10. Thus, even when connected to the unit pattern 10, the discrimination patterns 160A to 160D can be distinguished based on their length, thereby enabling the discrimination of unit patterns 10 each equipped with discrimination patterns 160A to 160D. Furthermore, if the discrimination patterns 160A to 160D are connected to the unit pattern 10, which is a wiring pattern, circuit constants such as parasitic capacitance may deviate, potentially causing deviations in the operation of the semiconductor device. Therefore, it is preferable to use discrimination patterns 160A to 160D when the impact of deviations in circuit constants, etc., is minimal.

[0039] like Figure 3 As shown in (c), circuit pattern 131 has a unit pattern 10 and a discrimination pattern 140 that are repeatedly arranged in the X direction. Discrimination pattern 140 has discrimination patterns 140A, 140B, 140C, and 140D, which respectively have... Figure 1 The discrimination patterns 14A to 14D shown in (c) have the same shape. However, discrimination patterns 14A to 14D are separate from the unit pattern 10, while discrimination patterns 140A to 140D are connected to the unit pattern 10. Even in this case, discrimination patterns 140A to 140D have different shapes, so they can be distinguished, and therefore the unit pattern 10 to which discrimination patterns 140A to 140D are assigned can also be discriminated. In addition, discrimination patterns 140A to 140D and Figure 3 Similarly, the discrimination graphs 160A to 160D shown in (b) are useful when the influence of deviations in circuit constants, etc., is minimal.

[0040] Next, refer to Figures 4 to 6 Other variations of the circuit pattern will be described. In the previously described circuit patterns 120, 121, 130, and 131, the repeatedly configured unit pattern 10 is assigned a different discrimination pattern 14, 16, 140, and 160, respectively. In contrast, in the subsequent variations, the unit pattern 10 is modified to form a discrimination pattern.

[0041] like Figure 4 As shown in (a), the unit pattern 100 has a plurality of lines 100A extending in the Y direction and a line 100B having a width (length in the X direction) wider than the lines 100A. Furthermore, a connecting portion C is provided in the unit pattern 100, through which two lines 100A are connected. That is, these two lines 100A are electrically connected to each other. If such a unit pattern 100 is simply repeated, it forms... Figure 4The circuit pattern 110 shown in (b) is as follows. As shown, in the circuit pattern 110, as indicated by dashed lines L1 and L2, the connecting portions C of each unit pattern 100 are arranged at the same position in the Y direction.

[0042] On the other hand, in the circuit pattern 114 of the modified example, such as Figure 4 As shown in (c), connecting portions C, C1, C2, and C3 are provided. While connecting portions C1 and C2 have approximately the same shape as connecting portion C, their relative positions to the dashed lines L1 and L2 in the figure indicate that they are positioned differently in the Y direction relative to connecting portion C. Furthermore, connecting portion C3 is longer than connecting portions C, C1, and C2 in the Y direction. Moreover, two connecting portions C3 are formed in the unit pattern 100 at the right end of the figure. The connecting portions C to C3 in circuit pattern 114 differ in position and / or shape, thus allowing them to be distinguished from each other. Therefore, these connecting portions C to C3 can have the same function as the aforementioned discrimination pattern 14A, etc. In other words, the discrimination pattern is constructed using connecting portions C to C3. That is, by changing the position and shape of a portion of the unit pattern 100 (the connecting portion in the illustrated example), a discrimination pattern can also be obtained. Furthermore, it goes without saying that such changes should be made in a manner that does not affect the characteristics of the semiconductor device.

[0043] Next, refer to Figure 5 (a) The unit pattern 101 has multiple lines 101A extending along the Y direction and lines 101B having a width wider than the lines 100A. Two openings, OPL and OPU, are formed on the line 101B. If such a unit pattern 101 is simply repeated, it forms Figure 5 The circuit pattern 111 shown in (b) is as follows. As shown in the figure, in the circuit pattern 111, as indicated by the dashed lines L3 and L4, the two openings OPL and OPU of each unit pattern 101 are respectively arranged at the same position in the Y direction.

[0044] On the other hand, in the circuit pattern 150 of the modified example, an opening OPL and an opening OPU are arranged in one unit pattern 101 (the left end in the figure), while different openings are arranged in the other unit patterns 101. Specifically, an opening OPL1 and an opening OPU1 are arranged in line 101B of the second unit pattern 101 from the left in the figure, an opening OPL2 and an opening OPU2 are arranged in line 101B of the third unit pattern 101 from the left, an opening OPL3 and an opening OPU3 are arranged in line 101B of the fourth unit pattern 101 from the left, an opening OPL4 and an opening OPU4 are arranged in line 101B of the fifth unit pattern 101 from the left, an opening OPL5 and an opening OPU5 are arranged in line 101B of the sixth unit pattern 101 from the left, and an opening OPL6, an opening OPM, and an opening OPU6 are arranged in line 101B of the rightmost unit pattern 101.

[0045] As shown by dashed line L3, open OPU1 and open OPU2 are positioned at the same location in the Y direction relative to the open OPU. However, relative to the open OPL, open OPL1 and open OPL2 are offset downwards in the diagram. Furthermore, open OPL2 is offset downwards more significantly than open OPL1. Similarly, as shown by dashed line L4, open OPL3 and open OPL4 are positioned at the same location in the Y direction relative to the open OPL. However, relative to the open OPU, open OPU3 and open OPU4 are offset upwards in the diagram. Furthermore, open OPU4 is offset upwards more significantly than open OPU3. Based on these different configurations, combinations of open OPL and open OPU, and combinations of open OPLx and open OPUx (where x is an integer from 1 to 4) can be distinguished.

[0046] Furthermore, although the lower end of open OPU5 is positioned in the same Y direction as the lower end of open OPU, its upper end is offset downwards in the figure compared to the upper end of open OPU. That is, open OPU5 is shorter than open OPU in the Y direction. Therefore, the combination of open OPL5 and open OPU5 can be distinguished from the above-mentioned combinations of openings. The combinations of open OPL6, open OPM, and open OPU6 can also be distinguished from other combinations. That is, due to differences in shape and / or position, these combinations of openings can have the same function as the aforementioned discrimination pattern 14A, and can be used to construct discrimination patterns.

[0047] Additionally, refer to Figure 6 (a) The unit pattern 102 has multiple lines 102A and two lines 102B extending in the Y direction. The lines 102B are opposite each other across the cut-off portion DP and all extend in the Y direction. If such a unit pattern 102 is simply repeated, it forms Figure 6 The circuit pattern 112 shown in (b) is as follows. As shown in the figure, in the circuit pattern 112, as indicated by the dashed lines L5 and L6, the cut-off portions DP of each unit pattern 102 are arranged at the same position in the Y direction.

[0048] On the other hand, in the circuit pattern 161 of the modified example, such as Figure 6 As shown in (c), cut-off portions DP, DP1, DP2, DP3, and DP4 are provided. Although cut-off portions DP1 and DP2 have approximately the same length as cut-off portion DP along the Y direction, they are positioned at different locations relative to cut-off portion DP in the Y direction, as can be seen from their relative positions to the dashed lines L5 and L6 in the figure. Furthermore, cut-off portion DP3 is longer in the Y direction than cut-off portions DP, DP1, and DP2. Moreover, two cut-off portions DP4 are formed in the unit pattern 100 at the right end of the figure. The cut-off portions DP to DP4 in circuit pattern 161 differ in position and / or shape, and can therefore be distinguished from each other. Thus, these cut-off portions DP to DP4 can have the same function as the discrimination pattern 14A described above, and a discrimination pattern is formed by the cut-off portions DP to DP4.

[0049] Furthermore, while previous studies focused on the repetitive arrangement of unit patterns in the X direction, there are also cases where unit patterns extending considerably in the Y direction are repeatedly arranged in the X direction. In such cases, it is possible to... Figure 7 As shown, a series of discrimination patterns are arranged at predetermined intervals in the Y direction. Figure 7 It is a schematic representation Figure 4 (a) is a top view of the circuit pattern when the unit pattern 100 extends relatively long in the Y direction. As shown, two columns of connecting portions C, C1, C2, and C3 are provided on the circuit pattern 170, arranged periodically along the dashed lines L7 and L8 extending approximately in the X direction. Here, the interval between the two columns (the interval between the dashed lines L7 and L8) can be determined, for example, by taking into account the imaging range IR of the SEM and the positional error based on the die-to-die method.

[0050] (Other variations)

[0051] Previously, the case of repeatedly configuring unit patterns formed by wiring was described, but this embodiment can also be applied when repeatedly configuring unit patterns formed by through holes and through contacts. Hereinafter, refer to... Figure 8 For example, another variation will be described using the case where a unit pattern is formed by a through hole provided in the insulating film and a hole used to penetrate the contact element, and the pattern is repeatedly arranged. Figure 8 This is an explanatory diagram illustrating the circuit pattern of another variation.

[0052] Reference Figure 8 (a) forms a wiring pattern 104 including wiring 104A and wiring 104B, which is wider than wiring 104A. Wiring 104A and 104B can be formed, for example, from a metal such as Cu or conductive polysilicon. Figure 8 (a) is a cross-sectional view along line AA. Figure 8 As shown in (b), wiring 104B (and wiring 104A as well) is formed on insulating film 51, and insulating film 53 is formed to cover them. That is, wiring 104A and 104B are lower layer wirings. Figure 8 (a) indicates wiring 104A, 104B whose shape can be visually identified through the insulating film 53 based on the material and thickness of the insulating film 53.

[0053] like Figure 8 (a) and Figure 8 As shown in (b), a plurality of holes H are formed that penetrate the insulating film 53 and reach the wiring 104B, with the wiring 104B exposed on the bottom surface of the plurality of holes H. These holes H can be formed, for example, by photolithography and etching processes. In addition, a metal such as Cu is then filled into the holes H to form through holes (or contacts) connected to the wiring 104B.

[0054] like Figure 8 As shown in (a), multiple holes H are divided into two groups, GH1 and GH2. Group GH1 has five holes H arranged in a roughly pentagonal shape. Specifically, three of the five holes H are located at the vertices of an isosceles triangle whose base extends along the X direction. The remaining two holes H are arranged offset in the Y direction from the two holes located at the two vertices at the ends of the base. Group GH2 also has five holes H, which are also arranged in the same roughly pentagonal shape as the holes H in group GH1. However, in the illustrated example, the holes H in group GH1 and group GH2 are arranged symmetrically with respect to the X-axis.

[0055] If such a pair of hole groups GH1, GH2 are taken as the unit pattern GH( Figure 8 (a)) If the unit pattern GH is repeated together with the lower layer wiring pattern 104 in the X direction, then as follows Figure 8 As shown in (c), circuit pattern 141 is formed. In this case, since the unit pattern GH, which is arranged in the same way as the hole H, is repeated, it is similar to the reference. Figure 2 Similarly, even if defects such as particles are observed on the insulating film 53, it is not easy to determine the location in the design data for the circuit pattern 12 described.

[0056] Furthermore, when observing defects such as particles on the insulating film 53, the wirings 104A and 104B can be identified through the insulating film 53 based on its material and thickness. However, since the wiring pattern 104 containing them is also repeated, it is still not easy to determine the location of the defects such as particles in the design data from the position of the wirings 104A and 104B. In addition, when the insulating film 53 is thick, the shape of the wirings 104A and 104B cannot be identified.

[0057] On the other hand, refer to Figure 8 In the circuit diagram 151 of this modified example, (d) replaces... Figure 8 Hole groups GH2, GH21, GH22, GH23, GH24, and GH25 in (c) are arranged in pairs with hole group GH1. Hole groups GH21 to GH25, like hole group GH2, have 5 holes H, but their arrangement is different. Specifically, in hole groups GH21 to GH25, the holes H are not approximately pentagonal; instead, holes H are arranged at 5 out of 6 positions in a 2x3 matrix in the XY plane, excluding position 1. Moreover, the position of this single location is different in each of hole groups GH21 to GH25. More specifically, the single location where no hole H is arranged corresponds to positions 1x3, 1x2, 1x1, 2x1, and 2x2 in each of hole groups GH21, GH22, GH23, GH24, and GH25. Depending on the different configurations, the hole groups GH21 to GH25 can have the same function as the discrimination pattern 14A mentioned above, and it can be said that the discrimination pattern is formed by the deformation of the unit pattern GH.

[0058] Furthermore, as mentioned above, it is not easy to clearly identify wirings 104A and 104B through the insulating film 53. Therefore, even if a prescribed discrimination pattern is assigned to wirings 104A and 104B, it is still not easy to determine the location of defects on the insulating film 53 in the design data based on the discrimination pattern. In contrast, in the case of hole H, wirings 104A and 104B exposed on its bottom surface can be clearly identified by SEM or the like, thus making it easy to determine the location of defects in the design data.

[0059] Furthermore, even if the configurations of each hole group GH21 to GH25 are different, since the number of holes H is the same, the resistance between the vias formed by filling the holes H with metal and the wiring 104B can be approximately the same in any configuration. Also, although hole groups GH1 and GH2, each with 5 holes H, are shown as examples, the number of holes H is not limited to 5, and can be appropriately determined by considering the imaging range, magnification, and positional error based on the die-to-die method in observation devices such as SEMs. Furthermore, alternatives can be used... Figure 8(c) shows hole group GH2, and hole groups GH21 to GH25 with different hole H configurations are used instead of hole group GH1, and multiple hole groups with different hole H configurations are used. Furthermore, in Figure 8 In (d), for example, hole groups GH21 and GH1 can be interchanged in the Y direction (the up-down direction in the figure), and hole groups GH24 and GH1 can be interchanged in the Y direction. That is, it is also possible to... Figure 8 The configuration of hole H is changed in either (or both) of hole groups GH1 and GH2 contained in the unit pattern GH in (c).

[0060] Furthermore, the observation (inspection) of defects, etc., after forming holes H on the insulating film 53 has been described. However, it is also possible to observe defects, etc., after filling the holes H with metal (e.g., Cu) and forming through holes, etc. Even in this case, the location of defects on the substrate can be determined based on the hole groups GH21 to GH25, as described above, using design data. Additionally, as described above, the circuit pattern 120, etc., is formed by filling trenches, etc., with conductive materials such as metal. However, defects, etc., can also be observed after the trenches (grooves) before the conductive material is filled are formed. That is, the circuit pattern to be observed is not limited to wiring, through holes, etc., but can also be holes or grooves. Furthermore, in Figure 8 In the previous example, the case where the bottom surface of the hole was made of a different material than the interlayer insulating film was explained. However, SEM images are excellent at observing surface irregularities, so even when the bottom surface of the hole or groove is made of the same material as other areas, the location of the hole or groove can be identified on the SEM image.

[0061] Next, a semiconductor device having a circuit pattern formed by repeating multiple unit patterns of the same shape in one direction will be described. Figure 9 This is a block diagram schematically representing the structure of a NAND flash memory. Figure 10 This is a block diagram schematically representing the structure of a DRAM memory. Figure 11 It is a block diagram that schematically represents the structure of a camera element.

[0062] Reference Figure 9 A NAND flash memory (NM), as a semiconductor storage device, includes a core (COR), input / output (IO) sections, and peripheral circuitry (PER). The core (COR) houses a memory cell array (MCA), a row decoder (RD), and a sense amplifier (SA). Within the MCA, there are multiple blocks (BLKs) (BLK0, BLK1, BLK2, ...) each containing multiple memory cells. Specifically, each block (BLK) has multiple string units (SU0, SU1, SU2, ...), and each string unit (SU) has multiple NAND strings (NS). Within each NAND string, the memory cells are connected in series.

[0063] The memory cell array MCA includes multiple word lines (WL) and multiple bit lines (BL) (in the diagram, one word line and one bit line are shown). The word lines (WL) extend along the X-direction and connect to the row decoder (RD). Additionally, each word line (WL) is commonly connected to the nth memory cell in the multiple NAND strings (NS) of each string cell (SU) within its corresponding block (BLK). Conversely, each bit line (BL) extends along the Y-direction and connects to the sense amplifier (SA). Furthermore, one of the bit lines (BL) is commonly connected to the mth NAND string (NS) between the multiple blocks (BLK). Memory cells are positioned at the points where the word lines (WL) and bit lines (BL) intersect.

[0064] The row decoder RD decodes the block address received from a designated control unit outside the NAND memory NM, selecting the block BLK and the word line WL within that block BLK. The sense amplifier SA reads the data from the memory cell and amplifies it during data reading. Then, it outputs the read data to the designated control unit as needed. Additionally, during data programming, the write data received from the designated control unit is transferred to the memory cell.

[0065] The Input / Output (IO) unit communicates with designated control units to send and receive various commands or data. The IO unit includes, for example, data input / output terminals DQ0-DQ7, toggle signal input / output terminals DQS, / DQS, and external control terminals / CEn, CLE, ALE, / WE, RE, / RE, receiving signals corresponding to these terminals from an external controller. The Peripheral Circuit (PER) includes a sequence generator (SEQ), a charge pump (CHP), a register (REG), and a driver (DRV). The driver (DRV) supplies the voltage required for data programming, reading, and erasing to the line decoder (RD) and the sense amplifier (SA). This voltage is applied to various wiring within the memory cell array (MCA). The charge pump (CHP) boosts the externally supplied power voltage and supplies the necessary voltage to the driver (DRV). The register (REG) holds various signals, such as the status of data programming and erasing operations, thereby notifying the designated control unit whether the operation has been completed correctly. The sequencer (SEQ) controls the overall operation of the NAND memory (NM).

[0066] In a NAND flash memory (NM) as described above, within the memory cell array (MCA), transistors constituting memory cells and various circuit elements, primarily word lines (WL) and bit lines (BL), are periodically arranged in the same circuit layout. Therefore, in the row decoder (RD) that connects to each word line (WL), it also becomes a circuit pattern formed by repeatedly arranging unit patterns of the same shape in one direction through multiple word lines (WL) or other wiring. The same applies to the sense amplifier (SA) that connects to multiple bit lines (BL). The circuit pattern 120 described above can be applied to such a row decoder (RD) and sense amplifier (SA).

[0067] Next, refer to Figure 10 The DRAM memory 80, as a semiconductor memory device, includes a memory cell array MA. The memory cell array MA has multiple word lines WL and multiple bit lines BL, with memory cells MC arranged at their intersections. The word lines WL are selected by a row decoder 83R, and the bit lines BL are selected by a column decoder 83C. Additionally, the DRAM memory 80 is provided with a command address terminal T1, a clock terminal T2, a data terminal T3, and power supply terminals T4 and T5. Clock signals CK and / CK are input to the clock terminal T2. A power supply voltage is supplied to the power supply terminal T5, and this power supply voltage is further supplied to an internal voltage generation circuit 88. The internal voltage generation circuit 88 generates various internal voltages based on the power supply voltage and outputs them to each unit from the terminal T1. Furthermore, in... Figure 10 For ease of explanation, the refresh circuitry and other features in the DRAM memory have been omitted.

[0068] Address signals and command signals are input externally to the command address terminal T1. The address signal input to the command address terminal T1 is supplied to the address decoder 82A via the command address input circuit 81. The address decoder 82A supplies the address signal AS to the row decoder 83R or the column decoder 83C. On the other hand, the command signal input to the command address terminal T1 is supplied to the command decoder 82C via the command address input circuit 81. The command decoder 82C generates various internal command signals by decoding the input command signals. The internal command signals include the active signal ATS and the column signal CS.

[0069] When the command signal is an activation command, the activation signal ATS is activated. When the activation signal ATS is activated, the address signal AS is supplied from the address decoder 82A to the row decoder 83R. Consequently, the word line WL specified by the address signal AS is selected. When the command signal is a read command or a write command, the column signal CS is activated. When the column signal CS is activated, the address signal AS is supplied from the address decoder 82A to the column decoder 83C. Consequently, the bit line BL specified by the address signal AS is selected.

[0070] Therefore, when an activation command and a read command are input, read data is read from the memory cell MC defined by the word line WL and bit line BL specified by the address signal AS. The read data is output to the outside via the sense amplifier 84, the input / output circuit 85, and the data terminal T3. On the other hand, when an activation command and a read command are input, and write data is input to the data terminal T3, write data is supplied to the memory cell array MA defined by the word line WL and bit line BL specified by the address signal AS via the data terminal T3, the input / output circuit 85, and the sense amplifier 15, and then written.

[0071] In a DRAM memory 80 as described above, within the memory cell array MA, transistors constituting memory cells and various circuit elements, primarily word lines WL and bit lines BL, are periodically arranged in the same circuit layout. Therefore, in the row decoder 83R, which connects each word line WL, a circuit pattern is formed by repeating unit patterns of the same shape in one direction through multiple word lines WL or other wiring. The same applies to the column decoder 83C with multiple bit lines BL. The aforementioned circuit pattern 120, etc., can be applied to such a row decoder 83R or column decoder 83C.

[0072] Next, refer to Figure 11 The image sensor 90 has a pixel array PA and peripheral circuitry, and the peripheral circuitry includes a row scanning circuit 91, a column processing circuit 92, a column scanning circuit 93, a system control unit 94, and a signal processing unit 96.

[0073] The pixel array PA has multiple pixels PXL. These pixels PXL are arranged in a 2D lattice pattern in both the row and column directions. Here, the row direction refers to the horizontal direction in the figure, and the column direction refers to the vertical direction. Each pixel PXL has a photoelectric conversion element that generates and stores a charge corresponding to the amount of received light. A predefined filter can be placed on the light incident surface of each pixel PXL. Such a filter can be, for example, a Bayer filter.

[0074] In the pixel array PA, pixel drive lines PDL are commonly connected to pixels PXL arranged in the row direction, and vertical signal lines VSL are commonly connected to pixels PXL arranged in the column direction. One end of the pixel drive line PDL is connected to the row scanning circuit 91. The row scanning circuit 91 generates drive signals for driving the signal readout from the pixels, and drives all pixels PDL of the pixel array PA simultaneously or in row units through the pixel drive lines PDL.

[0075] The signal output from the pixel PDL driven by the row scanning circuit 91 is input to the column processing circuit 92 through each vertical signal line VSL of each pixel PDS arranged in the row direction. The column processing circuit 92 can perform prescribed signal processing on the signal input through the vertical signal line VSL to generate a pixel signal and temporarily hold the pixel signal. For example, the column processing circuit 92 performs noise removal processing, analog-to-digital conversion (AD conversion) processing, etc. The digital signal obtained by the AD conversion is output to the signal processing unit 96. The column scanning circuit 93 sequentially selects the readout circuit corresponding to the pixel column of the column processing circuit 92. Through the selective scanning of the column scanning circuit 93, the column processing circuit 92 sequentially outputs the signal-processed pixel signal for each pixel circuit.

[0076] The system control unit 94 receives the system clock SYSCLK signal and other signals from an external controller. The system control unit 94 includes a timing generator, which drives the row scanning circuit 91, column processing circuit 92, and column scanning circuit 93 based on various timing signals generated therefrom. The signal processing unit 96 has at least arithmetic processing functions, performing various signal processing operations, such as arithmetic processing, on the pixel signals output from the column processing circuit 92. Furthermore, the digital signals output from the signal processing unit 96 are sent to the image processing unit, where prescribed processing is performed to generate image signals used for displaying images on a specified display.

[0077] In the image sensor 90 configured as described above, various circuit elements constituting photoelectric conversion elements, such as photodiodes, pixel drive lines (PDLs), and vertical signal lines (VSLs), are periodically arranged in the same circuit layout within the pixel array PA. Therefore, in the row scanning circuit 91, which connects to each pixel drive line (PDL), a circuit pattern is formed by repeatedly arranging multiple pixel drive lines (PDLs) or other wirings in one direction using unit patterns of the same shape. The same applies to the column processing circuit 92, which connects to multiple vertical signal lines (VSL). The aforementioned circuit pattern 120, etc., can be applied to such a row scanning circuit 91, column processing circuit 92, and column scanning circuit 93 connected to the column processing circuit 92.

[0078] Furthermore, in addition to NAND memory, DRAM, and camera elements mentioned above, circuit patterns formed by repeating unit patterns of the same shape in one direction are sometimes used in FPGA (Field Programmable Gate Array) and cross-point memory. Moreover, even semiconductor devices having a circuit equivalent to one of the line decoder RD and sense amplifier SA in the aforementioned NAND memory NM can have the aforementioned circuit pattern 120 applied to that circuit.

[0079] Several embodiments (modifications) of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0080] Furthermore, while particulate PCL is illustrated as a defect in this specification, it is not limited thereto. The circuit pattern of the embodiment is useful in cases where defects such as broken wires or short circuits that may occur during etching are identified in a circuit pattern with repeating unit patterns.

Claims

1. A semiconductor device, comprising: A circuit pattern comprising multiple unit patterns that are repeated in at least one direction; as well as A discrimination pattern, set within the circuit pattern, is capable of discriminating the unit pattern. The discrimination pattern comprises a corresponding discrimination pattern from a plurality of distinct discrimination graphics, each of the plurality of discrimination graphics corresponding to a corresponding unit pattern from the plurality of unit patterns. The plurality of discriminant patterns are arranged along a second direction different from the first direction, and the corresponding lengths of the plurality of discriminant patterns in the second direction are different from each other.

2. The semiconductor device according to claim 1, wherein, The discrimination pattern comprises multiple different discrimination graphics, which are assigned one by one to the unit pattern.

3. The semiconductor device according to claim 1, wherein, The discrimination pattern comprises multiple different discrimination graphics, which are set in proportion to assign one discrimination graphic to multiple unit patterns that are repeated within the circuit pattern.

4. The semiconductor device according to claim 2 or 3, wherein, The various discrimination graphics are respectively arranged in the gap area within the unit pattern.

5. The semiconductor device according to claim 2 or 3, wherein, The multiple discrimination graphics are separated from the unit pattern.

6. The semiconductor device according to claim 2 or 3, wherein, The various discrimination graphics are connected to the unit pattern.

7. The semiconductor device according to claim 1, wherein, The circuit pattern and the discrimination pattern are set on the same layer.

8. The semiconductor device according to claim 1, wherein, The circuit pattern is defined by wiring, and the discrimination pattern is formed of the same material as the wiring.

9. The semiconductor device according to claim 1, wherein, The circuit pattern is defined by wiring, and the discrimination pattern is set by deformation of the unit pattern.

10. The semiconductor device according to claim 1, wherein, The circuit pattern is defined by slots or holes, and the discrimination pattern is set by deformation of the unit pattern.

11. The semiconductor device according to claim 1, wherein, It also includes an additional discrimination pattern, which is separated from the original discrimination pattern by a predetermined interval and is arranged in the same direction.

12. A method for manufacturing a semiconductor device, comprising: The process of forming a circuit pattern, wherein the circuit pattern comprises a plurality of unit patterns repeatedly arranged in at least one direction, and is provided with a discrimination pattern capable of discriminating the unit patterns; as well as The process of observing the circuit pattern, The discrimination pattern comprises a corresponding discrimination pattern from a plurality of distinct discrimination graphics, each of the plurality of discrimination graphics corresponding to a corresponding unit pattern from the plurality of unit patterns. The plurality of discriminant patterns are arranged along a second direction different from the first direction, and the corresponding lengths of the plurality of discriminant patterns in the second direction are different from each other.

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