A semiconductor structure and a method of fabricating the same

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a method for fabricating the same. The method comprises: providing a substrate; forming an insulating layer and a plurality of contact plugs penetrating through the insulating layer above the substrate; forming an isolation layer above the insulating layer, the isolation layer having a plurality of capacitor holes filled with sacrificial layers, a projection of the capacitor holes on a substrate plane overlapping a projection of the contact plugs on the substrate plane; removing part of the sacrificial layers in the capacitor holes to form first sacrificial layers, the first sacrificial layers exposing upper surfaces of part of the contact plugs; forming spacers on sidewalls of the first sacrificial layers; removing the first sacrificial layers, the spacers separating the capacitor holes into at least two sub-capacitor holes; and forming capacitor structures in the sub-capacitor holes.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] As manufacturing processes continue to evolve, device integration levels increase, and component sizes shrink, the difficulty of capacitor fabrication increases. Current manufacturing processes often result in capacitors with problems such as high leakage current, low charge storage capacity, and relatively high structural density.

[0003] Therefore, optimizing capacitor manufacturing technology is a pressing technical problem that needs to be solved at this stage. Summary of the Invention

[0004] This disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate; forming an insulating layer and a plurality of contact plugs penetrating the insulating layer above the substrate; forming an isolation layer above the insulating layer, the isolation layer having a plurality of capacitor holes filled with a sacrificial layer, the orthographic projection of the capacitor holes on a substrate plane overlapping the orthographic projection of the contact plugs on a substrate plane; removing a portion of the sacrificial layer located within the capacitor holes to form a first sacrificial layer, the first sacrificial layer exposing a portion of the upper surface of the contact plugs; forming spacers on the sidewalls of the first sacrificial layer; removing the first sacrificial layer, the spacers dividing the capacitor holes into at least two sub-capacitor holes; and forming a capacitor structure within the sub-capacitor holes.

[0005] In some embodiments, an isolation layer is formed above the insulating layer, the isolation layer having a plurality of capacitive vias filled with a sacrificial layer, comprising: depositing a first isolation layer on the surface of the insulating layer; etching the first isolation layer along a first direction to form a plurality of first isolation barriers extending along the first direction, the first isolation barriers exposing the upper surface of the contact plug; depositing a sacrificial layer covering the first isolation barriers and filling the gaps between adjacent first isolation barriers; etching the sacrificial layer and portions of the first isolation barriers along a second direction intersecting the first direction to form a plurality of wall-like structures extending along the second direction, the plurality of wall-like structures exposing the upper surface of the insulating layer; depositing a second isolation layer filling the gaps between adjacent wall-like structures to form a plurality of second isolation barriers extending along the second direction; the first isolation barriers and the second isolation barriers intersecting each other to define a plurality of capacitive vias.

[0006] In some embodiments, removing a portion of the sacrificial layer located within a capacitor via to form a first sacrificial layer includes: depositing a mask layer over the sacrificial layer and the isolation layer; patterning the mask layer to form a first mask layer, the first mask layer exposing a portion of the upper surface of the sacrificial layer located within the capacitor via; and etching the sacrificial layer using the first mask layer as a mask.

[0007] In some embodiments, an isolation layer is formed above the insulating layer, the isolation layer having a plurality of capacitive holes filled with a sacrificial layer, comprising: depositing the isolation layer on the surface of the insulating layer; patterning the isolation layer to form capacitive holes that expose the upper surface of the contact plug; and filling the capacitive holes with a sacrificial layer.

[0008] In some embodiments, the projected area of ​​the first sacrificial layer on the substrate plane is half the projected area of ​​the capacitor hole on the substrate plane.

[0009] In some embodiments, forming a spacer on the sidewall of the first sacrificial layer includes forming the spacer using a plasma sputtering process, wherein the spacer comprises a nitride and the plasma precursor comprises N2 or NH3.

[0010] In some embodiments, forming a capacitor structure within the sub-capacitor hole, the capacitor structure being electrically connected to the contact plug, includes: depositing a lower electrode layer covering the sidewalls of the capacitor hole, the sidewalls of the spacer, and the upper surface of the contact plug; depositing a capacitor dielectric layer covering the surface of the lower electrode, the upper surface of the insulating layer, and the upper surface of the spacer; and depositing an upper electrode layer covering the surface of the capacitor dielectric layer and filling the capacitor hole.

[0011] In some embodiments, depositing a lower electrode layer covering the sidewalls of the capacitor aperture and the spacer, as well as the upper surface of the contact plug, includes: depositing the lower electrode layer over the substrate, the lower electrode layer covering the isolation layer, the spacer, and the contact plug; and removing the lower electrode layer located on the upper surface of the isolation layer and the upper surface of the spacer.

[0012] This disclosure also provides a semiconductor structure, including: a substrate; an insulating layer above the substrate and a plurality of contact plugs penetrating the insulating layer; an isolation layer above the insulating layer, the isolation layer having a plurality of capacitor holes exposing the upper surfaces of the contact plugs; at least one spacer located within the capacitor holes, the spacer dividing the capacitor holes into at least two sub-capacitor holes; and a capacitor structure filling the sub-capacitor holes, the capacitor structure being electrically connected to the contact plugs.

[0013] In some embodiments, the orthographic projection of the capacitor aperture onto the substrate plane is an axisymmetric figure, and the orthographic projection of the spacer onto the substrate plane is located on the axis of symmetry of the orthographic projection of the capacitor aperture onto the substrate plane.

[0014] In some embodiments, the capacitor structure includes a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer, wherein the lower electrode layer covers the sidewalls of the capacitor hole, the sidewalls of the spacer, and the upper surface of the contact plug; the capacitor dielectric layer covers the surface of the lower electrode, the upper surface of the insulating layer, and the upper surface of the spacer; and the upper electrode layer covers the surface of the capacitor dielectric layer and fills the capacitor hole.

[0015] In some embodiments, the orthographic projection of the sub-capacitor aperture onto the substrate plane comprises a triangle.

[0016] In some embodiments, the spacer is made of a nitride.

[0017] In some embodiments, the material of the isolation layer includes a low dielectric constant material, which includes carbon-doped oxides or nitrides; the material of the capacitor dielectric layer includes a high dielectric constant material, which includes one or more of the group consisting of zirconium oxide, aluminum oxide, hafnium oxide, silicon oxide, niobium oxide, and silicon nitride.

[0018] In some embodiments, the aspect ratio of the capacitor hole is less than 30:1.

[0019] In some embodiments, the contact plug includes a contact hole located in an insulating layer and extending through a substrate. The contact hole includes a first through-hole segment and a second through-hole segment, the second through-hole segment being located above the first through-hole segment. The contact plug includes a first conductive material layer, a second conductive material layer, and a third conductive material layer. The first conductive material layer fills the first through-hole segment, the second conductive material layer covers the sidewall of the second through-hole segment and the upper surface of the first conductive material layer, and the third conductive material layer covers the second conductive material layer and fills the second through-hole segment.

[0020] In some embodiments, the substrate includes a transistor, the transistor including a buried gate word line and source and drain regions located on both sides of the gate word line; the insulating layer further includes a bit line plug; the contact plug is electrically connected to the source region of the transistor, and the bit line plug is electrically connected to the drain region of the transistor.

[0021] This embodiment of the invention first forms a spacer in the capacitor hole above the contact plug, and the subsequently deposited capacitor dielectric layer can cover the surface of the spacer, thereby increasing the surface area of ​​the upper and lower electrodes of the capacitor. Then, a parallel capacitor stack structure is formed, which increases the spatial density of the capacitor unit. Thus, the height of the capacitor is reduced while the capacitor energy remains unchanged, and the difficulty of etching and coating is reduced.

[0022] Additional aspects and advantages of this disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this disclosure. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0025] Figures 2a-2w This is a schematic diagram of a semiconductor structure during the fabrication process provided in an embodiment of the present disclosure, wherein all I figures are top views and all II figures are cross-sectional views taken along line AA' in the I figures;

[0026] Figures 3a-3c This is a schematic diagram of another semiconductor structure provided in the embodiment of this disclosure during the fabrication process; wherein all Figure I are top views and all Figure II are cross-sectional views taken along line AA' in Figure I;

[0027] Figures 4a-4c This is a top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure.

[0028] Figure label:

[0029] 21-Substrate; 22-Insulating layer; 23-Contact plug; 231-First conductive material layer; 232-Second conductive material layer; 233-Third conductive material layer; 234-Contact hole; 2341-First through-hole segment; 2342-Second through-hole segment; 24-Isolation layer; 241-First isolation layer; 2411-First isolation fence; 242-Second isolation layer; 2421-Second isolation fence; 25-Sacrificial layer; 251-First sacrificial layer; 2511-Wall structure; 26-Capacitor hole; 261-Sub-capacitor hole; 27-Mask layer; 271-First mask layer; 28-Patterned photoresist layer; 29-Spacer; 30-Capacitor structure; 301-Lower electrode layer; 302-Capacitor dielectric layer; 303-Upper electrode layer; 3031-First upper electrode layer; 3232-Second upper electrode layer. Detailed Implementation

[0030] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0031] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0032] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0033] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0035] To meet the demands of memory capacitors, and given the miniaturization of semiconductors, the structural design of capacitors requires deep trenches and uniform deposition of upper and lower electrode plates and high-K dielectric films on the surface. This imposes certain limitations on etching and deposition capabilities. Furthermore, capacitors manufactured using current processes often suffer from problems such as high leakage current, low charge storage capacity, and high structural density.

[0036] Based on the above, in order to improve the aforementioned problems, this disclosure provides a method for fabricating a semiconductor structure, as shown in the attached figure. Figure 1 The preparation methods include:

[0037] Step 101: Provide a substrate;

[0038] Step 102: Form an insulating layer and a plurality of contact plugs penetrating the insulating layer above the substrate;

[0039] Step 103: An isolation layer is formed above the insulating layer. The isolation layer has multiple capacitor holes filled with sacrificial layers. The orthographic projection of the capacitor holes on the substrate plane overlaps with the orthographic projection of the contact plugs on the substrate plane.

[0040] Step 104: Remove part of the sacrificial layer located inside the capacitor hole to form a first sacrificial layer, which exposes part of the upper surface of the contact plug;

[0041] Step 105: Form spacers on the sidewalls of the first sacrificial layer;

[0042] Step 106: Remove the first sacrificial layer, and the spacer divides the capacitor hole into at least two sub-capacitor holes;

[0043] Step 107: Form a capacitor structure inside the sub-capacitor hole.

[0044] This embodiment of the invention first forms a spacer in the capacitor hole above the contact plug, and the subsequently deposited capacitor dielectric layer can cover the surface of the spacer, thereby increasing the surface area of ​​the upper and lower electrodes of the capacitor. Then, a parallel capacitor stack structure is formed, which increases the spatial density of the capacitor unit. Thus, the height of the capacitor is reduced while the capacitor energy remains unchanged, and the difficulty of etching and coating is reduced.

[0045] Figures 2a-2w This is a schematic diagram of a semiconductor structure during its fabrication process, provided as an embodiment of the present disclosure. Figure 2g-Figure 2r In the accompanying drawings, all Figure I are top views, and all Figure II are cross-sectional views taken along line AA' in Figure I. The following description, in conjunction with the accompanying drawings, further details the fabrication method of the semiconductor structure provided in the embodiments of this disclosure. For ease of explanation, the schematic diagrams may be partially enlarged beyond the general scale during the detailed description of the embodiments of this disclosure, and these schematic diagrams are merely examples and should not limit the scope of protection of this application.

[0046] Perform step 101, see appendix. Figure 2a A substrate 21 is provided. The substrate 21 may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, the substrate 21 is a silicon substrate, which may be doped or undoped.

[0047] In some embodiments, substrate 21 may further include transistors (not shown), the transistors including buried gate word lines and source and drain regions located on both sides of the gate word lines.

[0048] Next, refer to the appendix Figure 2b - Appendix Figure 2g Step 102 is performed to form an insulating layer 22 and a plurality of contact plugs 23 penetrating the insulating layer 22 above the substrate 21.

[0049] Specifically, firstly, as shown in the attached document... Figure 2bAs shown, an insulating layer 22 is formed above the substrate 21. The insulating layer 22 can be formed using one or more thin-film deposition processes, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), etc. The material of the insulating layer includes, but is not limited to, nitrides, such as silicon nitride.

[0050] Next, as attached Figure 2c As shown, the insulating layer 22 is patterned to form a contact hole 234 extending through the substrate. Here, the contact hole 234 can be formed by photolithography or multiple patterning.

[0051] In some embodiments, before forming a contact hole extending through the substrate, the method further includes: forming a bit line plug (not shown) and a bit line extending along a first direction within an insulating layer, the bit line being electrically connected to the drain region of a transistor via the bit line plug, wherein the first direction is a direction parallel to line AA'.

[0052] Next, as attached Figure 2d As shown, a first conductive material layer 231 is deposited, which fills the contact hole 234. In actual operation, the first conductive material layer 231 is electrically connected to the source or drain region of the transistor.

[0053] Then, see appendix. Figure 2e The first conductive material layer 231 is etched back to form a first through-hole segment 2341 and a second through-hole segment 2342 in the contact hole 234. The second through-hole segment 2342 is located above the first through-hole segment 2341, and the first conductive material layer 231 fills the first through-hole segment 2341.

[0054] Next, as attached Figure 2f As shown, a second conductive material layer 232 is deposited, which covers the sidewall of the second through-hole segment 2342 and the upper surface of the first conductive material layer 231.

[0055] Then, as attached Figure 2g As shown, a third conductive material layer 233 is deposited, which covers the second conductive material layer 232 and fills the second via segment 2342.

[0056] The first conductive material layer, the second conductive material layer, and the third conductive material can be formed using processes such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, and sputtering. The first conductive material layer, the second conductive material layer, and the third conductive material include, but are not limited to, tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), polycrystalline silicon, doped silicon, metal silicides, metal alloys, or any combination thereof. In one specific embodiment, the first conductive material layer is polycrystalline silicon, the second conductive material is titanium nitride, and the third conductive material is tungsten. In this embodiment, a capacitor hole is subsequently formed directly above the contact plug, eliminating the need for a separate metal redistribution layer, thereby effectively reducing the fabrication height of the contact plug and facilitating the filling of polycrystalline silicon within the contact plug.

[0057] Next, step 103 is performed, forming an isolation layer 24 above the insulating layer 22. The isolation layer 24 has a plurality of capacitor holes 26 filled with sacrificial layers 25. The orthographic projection of the capacitor holes 26 on the substrate plane overlaps with the orthographic projection of the contact plug 23 on the substrate plane. In actual operation, the orthographic projection of the capacitor holes 26 on the substrate plane can coincide with the orthographic projection of the contact plug 23 on the substrate plane.

[0058] In some embodiments, an isolation layer is formed above an insulating layer, the isolation layer having a plurality of capacitor vias filled with a sacrificial layer, comprising: depositing a first isolation layer on the surface of the insulating layer; etching the first isolation layer along a first direction to form a plurality of first isolation barriers extending along the first direction, the first isolation barriers exposing the upper surface of the contact plug; depositing a sacrificial layer covering the first isolation barriers and filling the gaps between adjacent first isolation barriers; etching the sacrificial layer and portions of the first isolation barriers along a second direction intersecting the first direction to form a plurality of wall-like structures extending along the second direction, the plurality of wall-like structures exposing the upper surface of the insulating layer; depositing a second isolation layer filling the gaps between adjacent wall-like structures to form a plurality of second isolation barriers extending along the second direction; the first isolation barriers and the second isolation barriers intersect each other to define a plurality of capacitor vias, wherein the second direction is a direction perpendicular to line AA'.

[0059] Specifically, first, see the appendix. Figure 2h A first isolation layer 241 is deposited on the surface of the insulating layer 22. The material of the first isolation layer includes a low dielectric constant material, which includes, but is not limited to, carbon-doped oxides or nitrides.

[0060] Next, see the appendix. Figure 2iThe first isolation layer 241 is etched along a first direction to form a plurality of first isolation barriers 2411 extending along the first direction, the first isolation barriers 2411 exposing the upper surface of the contact plug 23. Here, the first isolation layer 241 can be etched by wet etching, dry etching, or a combination thereof. In practice, a bit line mask (BL mask) can be used to pattern the first isolation layer 241 to form a plurality of first isolation barriers 2411 extending along the first direction.

[0061] Next, see the appendix. Figure 2j A sacrificial layer 25 is deposited, which covers the first isolation fence 2411 and fills the gaps between adjacent first isolation fences 2411. The formation process of the sacrificial layer 25 includes, but is not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or combinations thereof. In one specific embodiment, the sacrificial layer 25 is formed by spin-on dielectric (SOD). The material of the sacrificial layer 25 includes, but is not limited to, oxides, such as silicon oxide.

[0062] Then, see appendix. Figure 2k The sacrificial layer 25 and a portion of the first isolation fence 2411 are etched along a second direction intersecting the first direction to form a plurality of wall-like structures 2511 extending along the second direction, exposing the upper surface of the insulating layer 22. In actual operation, the first and second directions can be perpendicular.

[0063] Next, see the appendix. Figure 2l A second isolation layer 242 is deposited, filling the gaps between adjacent wall-like structures 2511 to form a plurality of second isolation fences 2421 extending along a second direction; the first isolation fences 2411 and the second isolation fences 2421 intersect to define a plurality of capacitive vias 26. The material of the second isolation layer 242 includes a low dielectric constant material, including but not limited to carbon-doped oxides or nitrides. In practice, the materials of the first isolation layer 241 and the second isolation layer 242 can be the same.

[0064] Then, as attached Figure 2m As shown, a planarization process is performed so that the upper surface of the second isolation barrier 2421 is flush with the upper surface of the first isolation barrier 2411 and the sacrificial layer 25. The planarization process can be, for example, chemical mechanical polishing (CMP) and / or etching processes.

[0065] The above is one embodiment of step 103, in which a square capacitor aperture is formed by the first isolation barrier 2411 and the second isolation barrier 2421. The photomask used in the patterning process can be fabricated using a photomask for BL (bit line) / NC (capacitor contact plug) fabrication, thus saving on the number of photomasks. It should be understood that the embodiment of step 103 is not limited to this; in other embodiments, see the appendix. Figure 3a - Appendix Figure 3c An isolation layer is formed above an insulating layer, and the isolation layer has multiple capacitor holes filled with a sacrificial layer. This involves: depositing the isolation layer on the surface of the insulating layer; patterning the isolation layer to form the capacitor holes, which expose the upper surface of the contact plug; and filling the capacitor holes with a sacrificial layer. This simplifies the process flow, allowing the capacitor holes to be formed in one step, and the shape of the capacitor holes can be controlled through the patterning process.

[0066] Specifically, first, see the appendix. Figure 3a An isolation layer 24 is deposited on the surface of the insulating layer 22. The material of the isolation layer 24 includes a low dielectric constant material, which includes, but is not limited to, carbon-doped oxides or nitrides.

[0067] Next, see the appendix. Figure 3b The patterned isolation layer 24 forms a capacitor hole 26, which exposes the upper surface of the contact plug 23. Here, the orthographic projection of the capacitor hole onto the substrate plane can be, for example, a triangle, rectangle, or other polygon. In one specific embodiment, the orthographic projection of the capacitor hole onto the substrate plane is circular or elliptical. The capacitor hole 26 can be formed by photolithography or multiple patterning.

[0068] Then, see appendix. Figure 3c A sacrificial layer 25 is filled within the capacitor via 26. The formation process of the sacrificial layer 25 includes, but is not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or combinations thereof. In one specific embodiment, the sacrificial layer 25 is formed by spin-on dielectric (SOD). The material of the sacrificial layer 25 includes, but is not limited to, oxides, such as silicon oxide. Optionally, after filling the sacrificial layer 25, planarization processes, such as chemical mechanical polishing (CMP) and / or etching processes, may be used to make the upper surface of the sacrificial layer 25 coplanar with the upper surface of the capacitor via 26.

[0069] Next, step 104 is performed to remove part of the sacrificial layer 25 located in the capacitor hole 26 to form a first sacrificial layer 251, which exposes part of the upper surface of the contact plug 23.

[0070] In some embodiments, see Appendix Figure 2n - Appendix Figure 2pThe process of removing a portion of the sacrificial layer located within the capacitor via to form a first sacrificial layer includes: depositing a mask layer over the sacrificial layer and an isolation layer; patterning the mask layer to form a first mask layer, the first mask layer exposing a portion of the upper surface of the sacrificial layer located within the capacitor via; and etching the sacrificial layer using the first mask layer as a mask.

[0071] Specifically, first, see the appendix. Figure 2n A mask layer 27 is deposited above the sacrificial layer 25 and the isolation layer 24. The material of the mask layer includes, but is not limited to, nitrides, oxides, carbon, silicon, anti-reflective coatings, or combinations thereof. Here, the mask layer can be reactively deposited using a CVD single-wafer or furnace tube apparatus.

[0072] Next, see the appendix. Figure 2n and attached Figure 2o A patterned mask layer forms a first mask layer 271, which exposes a portion of the upper surface of the sacrificial layer 25 located within the capacitor via. In practice, a photoresist layer (PR) can be formed above the mask layer 27; a patterned photoresist layer is then formed to create a patterned photoresist layer 28, which exposes the mask layer 27; the mask layer 27 is etched using the patterned photoresist layer 28 as a mask to form the first mask layer 271.

[0073] Then, see appendix. Figure 2p Using the first mask layer 271 as a mask, the sacrificial layer 25 is etched to form the first sacrificial layer 251. Here, a dry etching process can be used to etch the sacrificial layer 25. The gases used in dry etching include, but are not limited to, sulfur hexafluoride, carbon fluoride, chlorine, argon, or combinations thereof. In actual operation, the etching can be performed using a bias voltage.

[0074] In some embodiments, the projected area of ​​the first sacrificial layer 251 on the substrate plane is half the projected area of ​​the capacitor aperture 26 on the substrate plane. This reduces the complexity of patterning the sacrificial layer and improves the efficiency of sacrificial layer removal compared to arrayed capacitor apertures. Furthermore, removing too much or too little sacrificial layer is detrimental to the subsequent formation of a stable parallel capacitor structure.

[0075] Next, as attached Figure 2q As shown, step 105 is performed to form a spacer 29 on the sidewall of the first sacrificial layer 251.

[0076] In some embodiments, a spacer is formed on the sidewall of the first sacrificial layer, comprising: forming the spacer using a plasma sputtering process, wherein the spacer comprises a nitride, and the plasma precursor comprises N2 or NH3. Nitride spacers formed by plasma sputtering have advantages such as high modulus, excellent insulation, and resistance to collapse.

[0077] Next, see the appendix. Figure 2rIn step 106, the first sacrificial layer 251 is removed, and the spacer 29 divides the capacitor hole 26 into at least two sub-capacitor holes 261. Here, the first sacrificial layer can be removed by wet etching, dry etching, or a combination thereof.

[0078] Finally, see appendix. Figure 2s - Appendix Figure 2v Step 107 is executed to form a capacitor structure 30 within the sub-capacitor hole 261.

[0079] In some embodiments, see Appendix Figure 2s - Appendix Figure 2v A capacitor structure is formed within the sub-capacitor hole, and the capacitor structure is electrically connected to the contact plug. The process includes: depositing a lower electrode layer, which covers the sidewalls of the capacitor hole, the sidewalls of the spacer, and the upper surface of the contact plug; depositing a capacitor dielectric layer, which covers the surface of the lower electrode, the upper surface of the insulating layer, and the upper surface of the spacer; and depositing an upper electrode layer, which covers the surface of the capacitor dielectric layer and fills the capacitor hole.

[0080] In some embodiments, see Appendix Figure 2s-2w The process includes depositing a lower electrode layer that covers the sidewalls of the capacitor aperture and the spacer, as well as the upper surface of the contact plug, comprising: depositing a lower electrode layer over a substrate, the lower electrode layer covering the isolation layer, the spacer, and the contact plug; and removing the lower electrode layer located on the upper surface of the isolation layer and the upper surface of the spacer.

[0081] Specifically, first, see the appendix. Figure 2s A lower electrode layer 301 is deposited, which covers the isolation layer 24, spacer 29, and contact plug 23. The materials of the lower electrode 301 include, but are not limited to, tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), polycrystalline silicon, doped silicon, metal silicides, metal alloys, or any combination thereof. In one specific embodiment, the material of the lower electrode is titanium nitride (TiN). In practice, the lower electrode 301 can be formed using a CVD or ALD apparatus.

[0082] Next, see the appendix. Figure 2t Remove the lower electrode layer 301 located on the upper surface of the isolation layer 24 and the upper surface of the spacer 29.

[0083] Next, see the appendix. Figure 2uA capacitor dielectric layer 302 is deposited, covering the surface of the lower electrode layer 301, the upper surface of the insulating layer 24, and the upper surface of the spacer 29. The dielectric layer 302 is made of a high-dielectric-constant material, including one or more materials from the group consisting of zirconium oxide, alumina, hafnium oxide, silicon oxide, niobium oxide, and silicon nitride. In practice, the dielectric layer 302 can be formed using either furnace-tube or monolithic atomic layer deposition.

[0084] Then, see appendix. Figure 2v - Appendix Figure 2w A top electrode layer 303 is deposited, covering the surface of the capacitor dielectric layer 302 and filling the capacitor holes 26. This allows the capacitor stack structures within the segmented sub-capacitor holes to be connected in parallel, forming a parallel dual-capacitor structure. The material of the top electrode layer 303 includes, but is not limited to, tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), polycrystalline silicon, doped silicon, metal silicides, metal alloys, or any combination thereof. Here, the top electrode layer 303 can be reacted using a CVD or ALD apparatus. In practice, a first top electrode layer 3031 can be deposited to cover the surface of the capacitor dielectric layer 302, followed by the deposition of a second top electrode layer 3032 to fill the capacitor holes 26. The first top electrode layer 3031 can be, for example, titanium nitride (TiN), and the second top electrode layer 3032 can be, for example, polycrystalline silicon germanium (SiGe poly). It should be noted that, for ease of explanation and understanding, Figure 2w Figure I in the diagram only shows the portion of the second upper electrode layer 3032 that fills the capacitor holes. In actual operation, see... Figure 2w In Figure II, the second upper electrode layer 3032 can cover the upper surface of the first upper electrode layer 3031.

[0085] This disclosure also provides a semiconductor structure, see appendix. Figure 2w The device includes: a substrate 21; an insulating layer 22 above the substrate and a plurality of contact plugs 23 penetrating the insulating layer; an isolation layer 24 above the insulating layer 22, the isolation layer 24 having a plurality of capacitor holes 26, the capacitor holes 26 exposing the upper surface of the contact plugs 23; at least one spacer 29 located within the capacitor holes 26, the spacer 29 dividing the capacitor holes 26 into at least two sub-capacitor holes 261; and a capacitor structure 30 filling the sub-capacitor holes, the capacitor structure 30 being electrically connected to the contact plugs 23.

[0086] In some embodiments, see Appendix Figure 2w The orthographic projection of the capacitor aperture onto the substrate plane is an axisymmetric figure, and the orthographic projection of the spacer onto the substrate plane lies on the axis of symmetry of the orthographic projection of the capacitor aperture onto the substrate plane. This helps to reduce the difficulty of the manufacturing process and makes the subsequent parallel capacitor structure more stable.

[0087] In some embodiments, see Appendix Figure 2w The orthographic projection of the sub-capacitor aperture 261 onto the substrate plane comprises a triangle. In one specific embodiment, the orthographic projection of the capacitor aperture 261 onto the substrate plane comprises a rectangle, and the orthographic projection of the spacer 29 onto the substrate plane lies on the diagonal of the rectangle, thereby making the orthographic projection of the sub-capacitor aperture 261 onto the substrate plane a triangle. Compared to capacitor apertures of other shapes, the triangular capacitor aperture allows the subsequently deposited capacitor dielectric layer to cover a larger area of ​​the spacer surface, resulting in a higher spatial density of the capacitor cells.

[0088] In some embodiments, see Appendix Figure 4a The orthographic projection of capacitor hole 26 on the substrate plane is a circle, and the orthographic projection of sub-capacitor hole 261 on the substrate plane is a semicircle.

[0089] In some embodiments, see Appendix Figure 4b The orthographic projection of capacitor hole 26 onto the substrate plane is square, and the orthographic projection of sub-capacitor hole 261 onto the substrate plane is square.

[0090] In some embodiments, see Appendix Figure 4c The spacer 29 divides the capacitor hole 26 into multiple sub-capacitor holes 261; for example, the spacer 29 divides the capacitor hole 26 into three sub-capacitor holes 261. In this way, the spatial density of the capacitor cell is further increased.

[0091] In some embodiments, see Appendix Figure 2w The capacitor structure includes a lower electrode layer 301, a capacitor dielectric layer 302, and an upper electrode layer 303. The lower electrode layer 301 covers the sidewalls of the capacitor hole 26, the sidewalls of the spacer 29, and the upper surface of the contact plug 23. The capacitor dielectric layer 302 covers the surface of the lower electrode 301, the upper surface of the isolation layer 24, and the upper surface of the spacer 29. The upper electrode layer 303 covers the surface of the capacitor dielectric layer 302 and fills the capacitor hole 26.

[0092] In some embodiments, the material of the spacer 29 includes nitrides. Here, nitride spacers have advantages such as high modulus, excellent insulation, and resistance to collapse.

[0093] In some embodiments, the insulating layer is made of a low-dielectric-constant material, including carbon-doped oxides or nitrides; the capacitor dielectric layer is made of a high-dielectric-constant material, including one or more of the group consisting of zirconium oxide, aluminum oxide, hafnium oxide, silicon oxide, niobium oxide, and silicon nitride. The low-dielectric-constant material insulating layer can prevent leakage current. For capacitor dielectric layers of the same thickness, the high-dielectric-constant material dielectric layer can increase the capacitance.

[0094] In some embodiments, the aspect ratio of the capacitor aperture is less than 30:1. In practice, the aspect ratio of the capacitor aperture can be, for example, 25:1, 15:1, or 10:1. This disclosure increases the surface area of ​​the upper and lower electrodes of the capacitor by providing spacers within the capacitor apertures, allowing the subsequently deposited capacitor dielectric layer to cover the surface of the spacers. This reduces the height of the capacitor without changing the capacitor energy, thereby reducing the difficulty of etching and coating, and simultaneously reducing the product's package size.

[0095] In some embodiments, see Appendix Figure 2w The contact plug includes a contact hole 234 located in the insulating layer and extending through to the substrate (see Appendix). Figure 2c The contact hole 234 includes a first through-hole section 2341 (see Appendix). Figure 2e ) and second through-hole section 2342 (see appendix) Figure 2e The second through-hole segment 2342 is located above the first through-hole segment 2341; the contact plug 23 includes a first conductive material layer 231, a second conductive material layer 232 and a third conductive material layer 233; wherein, the first conductive material layer 231 fills the first through-hole segment 2341, the second conductive material layer 232 covers the sidewall of the second through-hole segment 2342 and the upper surface of the first conductive material layer 231, and the third conductive material layer 233 covers the second conductive material layer 232 and fills the second through-hole segment 2342.

[0096] In some embodiments, the substrate includes a transistor (not shown), the transistor including a buried gate word line and source and drain regions located on both sides of the gate word line; the insulating layer also includes a bit line plug (not shown); the contact plug is electrically connected to the source region of the transistor, and the bit line plug is electrically connected to the drain region of the transistor.

[0097] This embodiment of the invention first forms a spacer in the capacitor hole above the contact plug, and the subsequently deposited capacitor dielectric layer can cover the surface of the spacer, thereby increasing the surface area of ​​the upper and lower electrodes of the capacitor. Then, a parallel capacitor stack structure is formed, which increases the spatial density of the capacitor unit. Thus, the height of the capacitor is reduced while the capacitor energy remains unchanged, and the difficulty of etching and coating is reduced.

[0098] It should be noted that the semiconductor structure and its fabrication method provided in this disclosure can be applied to any integrated circuit including this structure. The technical features described in each embodiment can be arbitrarily combined without conflict. Those skilled in the art can change the order of the above-described forming method steps without departing from the scope of protection of this disclosure. In the embodiments of this disclosure, some steps can be executed simultaneously or sequentially without conflict.

[0099] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; An insulating layer and a plurality of contact plugs extending through the insulating layer are formed above the substrate; An isolation layer is formed above the insulating layer, and the isolation layer has a plurality of capacitor holes filled with a sacrificial layer. The orthographic projection of the capacitor holes on the substrate plane overlaps with the orthographic projection of the contact plug on the substrate plane. A portion of the sacrificial layer located within the capacitor hole is removed to form a first sacrificial layer, which exposes a portion of the upper surface of the contact plug; A spacer is formed on the sidewall of the first sacrificial layer, and the spacer is connected to a portion of the contact plug; After removing the first sacrificial layer, the spacer divides the capacitor aperture into at least two sub-capacitor apertures; A capacitor structure is formed within the sub-capacitor hole, and the capacitor structure is electrically connected to the contact plug.

2. The preparation method according to claim 1, characterized in that, An isolation layer is formed above the insulating layer, the isolation layer having a plurality of capacitor vias filled with a sacrificial layer, including: A first insulating layer is deposited on the surface of the insulating layer; The first isolation layer is etched along a first direction to form a plurality of first isolation barriers extending along the first direction, the first isolation barriers exposing the upper surface of the contact plug; A sacrificial layer is deposited, which covers the first isolation fence and fills the gaps between adjacent first isolation fences; The sacrificial layer and a portion of the first isolation fence are etched along a second direction intersecting the first direction to form a plurality of wall-like structures extending along the second direction, the plurality of wall-like structures exposing the upper surface of the insulating layer; A second isolation layer is deposited, which fills the gaps between adjacent wall-like structures to form a plurality of second isolation fences extending along a second direction; the first isolation fences and the second isolation fences intersect each other to define a plurality of capacitive apertures.

3. The preparation method according to claim 1, characterized in that, Removing a portion of the sacrificial layer located within the capacitor via to form a first sacrificial layer includes: A mask layer is deposited above the sacrificial layer and the isolation layer; The mask layer is patterned to form a first mask layer, which exposes a portion of the upper surface of the sacrificial layer located within the capacitor aperture; The sacrificial layer is etched using the first mask layer as a mask.

4. The preparation method according to claim 1, characterized in that, An isolation layer is formed above the insulating layer, the isolation layer having a plurality of capacitor vias filled with a sacrificial layer, including: An insulating layer is deposited on the surface of the insulating layer; The isolation layer is patterned to form a capacitive aperture, which exposes the upper surface of the contact plug; A sacrificial layer is filled inside the capacitor hole.

5. The preparation method according to claim 1, characterized in that, The projected area of ​​the first sacrificial layer on the substrate plane is half the projected area of ​​the capacitor hole on the substrate plane.

6. The preparation method according to claim 1, characterized in that, A spacer is formed on the sidewall of the first sacrificial layer, including: The spacer is formed using a plasma sputtering process, and the spacer includes a nitride, with the plasma precursor including N2 or NH3.

7. The preparation method according to claim 1, characterized in that, A capacitor structure is formed within the sub-capacitor hole, and the capacitor structure is electrically connected to the contact plug, including: A lower electrode layer is deposited, which covers the sidewalls of the capacitor orifice, the sidewalls of the spacer, and the upper surface of the contact plug; A capacitor dielectric layer is deposited, which covers the surface of the lower electrode, the upper surface of the insulating layer, and the upper surface of the spacer; An upper electrode layer is deposited, which covers the surface of the capacitor dielectric layer and fills the capacitor orifice.

8. The preparation method according to claim 7, characterized in that, A lower electrode layer is deposited, the lower electrode layer covering the sidewalls of the capacitor orifice, the sidewalls of the spacer, and the upper surface of the contact plug, comprising: A lower electrode layer is deposited above the substrate, the lower electrode layer covering the isolation layer, the spacer, and the contact plug; Remove the lower electrode layer located on the upper surface of the insulating layer and the upper surface of the spacer.

9. A semiconductor structure, characterized in that, include: Substrate; An insulating layer located above the substrate and a plurality of contact plugs penetrating the insulating layer; An isolation layer located above the insulating layer, the isolation layer having a plurality of capacitive holes, the capacitive holes exposing the upper surface of the contact plug; At least one spacer located within the capacitor hole, the spacer dividing the capacitor hole into at least two sub-capacitor holes, the spacer being connected to a portion of the contact plug; A capacitor structure that fills the sub-capacitor hole, the capacitor structure being electrically connected to the contact plug.

10. The semiconductor structure according to claim 9, characterized in that, The orthographic projection of the capacitor aperture onto the substrate plane is an axisymmetric figure, and the orthographic projection of the spacer onto the substrate plane is located on the axis of symmetry of the orthographic projection of the capacitor aperture onto the substrate plane.

11. The semiconductor structure according to claim 9, characterized in that, The capacitor structure includes a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer. The lower electrode layer covers the sidewalls of the capacitor hole, the sidewalls of the spacer, and the upper surface of the contact plug. The capacitor dielectric layer covers the surface of the lower electrode, the upper surface of the insulating layer, and the upper surface of the spacer. The upper electrode layer covers the surface of the capacitor dielectric layer and fills the capacitor hole.

12. The semiconductor structure according to claim 9, characterized in that, The orthographic projection of the sub-capacitor aperture onto the substrate plane comprises a triangle.

13. The semiconductor structure according to claim 9, characterized in that, The spacer is made of nitride.

14. The semiconductor structure according to claim 11, characterized in that, The material of the isolation layer includes a low dielectric constant material, which includes carbon-doped oxides or nitrides; The material of the capacitor dielectric layer includes a high dielectric constant material, which includes one or more of the group consisting of zirconium oxide, aluminum oxide, hafnium oxide, silicon oxide, niobium oxide, and silicon nitride.

15. The semiconductor structure according to claim 9, characterized in that, The aspect ratio of the capacitor aperture is less than 30:

1.

16. The semiconductor structure according to claim 9, characterized in that, The contact plug includes a contact hole located in the insulating layer and extending through the substrate. The contact hole includes a first through-hole section and a second through-hole section, with the second through-hole section located above the first through-hole section. The contact plug includes a first conductive material layer, a second conductive material layer, and a third conductive material layer; The first conductive material layer fills the first through-hole segment, the second conductive material layer covers the sidewall of the second through-hole segment and the upper surface of the first conductive material layer, and the third conductive material layer covers the second conductive material layer and fills the second through-hole segment.

17. The semiconductor structure according to claim 9, characterized in that, The substrate includes a transistor, the transistor including a buried gate word line and source and drain regions located on both sides of the gate word line; The insulating layer also includes bit line plugs; The contact plug is electrically connected to the source region of the transistor, and the bit line plug is electrically connected to the drain region of the transistor.

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