Semiconductor structure and method of manufacturing a semiconductor structure

Abstract

This application provides a semiconductor structure and a method for fabricating the semiconductor structure. The semiconductor structure includes a substrate having a first region and a second region arranged adjacent to each other. The substrate in the first region has a groove, within which a first connector and a storage structure are disposed. The first connector extends along a first direction, and the storage structure extends along a second direction. The first connector is electrically connected to the storage structure. A first circuit layer is disposed on the substrate in the second region, and a plurality of first contact structures are disposed on the first circuit layer at intervals along the first direction. The first connector is electrically connected to the first contact structures. The first direction and the second direction are perpendicular to each other. By placing the storage structure within the groove in the first region, the distance between the top surface of the storage structure and the top surface of the second region can be reduced, and the length of the first contact structures can be shortened, thereby facilitating the miniaturization of the circuit in the second region.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for fabricating the semiconductor structure. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in computers and other electronic devices, typically consisting of a core region and a peripheral region. The core region comprises multiple memory cells, each usually including a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source of the transistor is electrically connected to the bit line, and the drain of the transistor is electrically connected to the capacitor. The peripheral region contains peripheral circuitry. The word line and bit line are electrically connected to the peripheral circuitry through contact structures, allowing the word line voltage to control the switching on and off of the transistor. This enables the reading of data stored in the capacitor or the writing of data to the capacitor via the bit line.

[0003] However, the structure of the related technology is not conducive to the miniaturization of the peripheral circuits in the peripheral area. Summary of the Invention

[0004] This application provides a semiconductor structure and a method for manufacturing the semiconductor structure, in order to solve the technical problem that the structure of the related technology is not conducive to the miniaturization of the peripheral circuit of the peripheral area.

[0005] In a first aspect, embodiments of this application provide a semiconductor structure including a substrate, the substrate having a first region and a second region, the second region being arranged adjacent to the first region, the substrate located in the first region having a groove, a first connector and a storage structure being disposed in the groove, the first connector extending along a first direction, the storage structure extending along a second direction, the first connector being electrically connected to the storage structure;

[0006] A first circuit layer is disposed on the substrate located in the second region, and a plurality of first contact structures are disposed on the first circuit layer at intervals along the first direction. The first connector is electrically connected to the first contact structure; the first direction is perpendicular to the second direction.

[0007] In one possible implementation, the groove includes a first groove area and a second groove area that are interconnected. The first groove area extends along the first direction, and the second groove area extends along the second direction. The first connector is located in the first groove area. The first connector includes a plurality of stepped structures stacked along a third direction and distributed in a stepped manner. Each of the stepped structures extends along the first direction.

[0008] The storage structure is located in the second slot area, and the storage structure includes a plurality of capacitors stacked along a third direction, with each step structure electrically connected to its corresponding capacitor;

[0009] The first direction, the second direction, and the third direction are perpendicular to each other.

[0010] In one possible implementation, the sidewalls of the groove are covered with a protective layer, the material of which includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0011] In one possible implementation, when the top surface of the substrate located in the second region is lower than the top surface of the memory structure, the height difference between the two ranges from 0 to 100 nm; when the top surface of the substrate located in the second region is higher than or flush with the top surface of the memory structure, the height difference between the two ranges from 0 to 150 nm.

[0012] In one possible implementation, the depth of the groove ranges from 400 nm to 1000 nm.

[0013] In one possible implementation, a plurality of bit line connection structures are spaced apart on the substrate, the bit line connection structures extend along the second direction, conductive pillars are provided on the stepped structure, the conductive pillars are in contact with and electrically connected to the stepped structure, the top of the conductive pillars are electrically connected to the bit line connection structures, and the bit line connection structures are electrically connected to the corresponding first contact structures.

[0014] In one possible implementation, word line connection structures are spaced apart on the substrate and extend along the second direction. A gate conductive structure is disposed in the groove. The gate conductive structure is electrically connected to a plurality of capacitors stacked along the third direction. The top end of the gate conductive structure is electrically connected to the word line connection structure. The word line connection structure is electrically connected to the corresponding first contact structure.

[0015] In one possible implementation, the substrate has a third region, the second region and the third region are respectively located on opposite sides of the first region, and a second connector extending along a first direction is disposed in the groove, the second connector being electrically connected to one end of the storage structure opposite to the first connector;

[0016] A second circuit layer is disposed on the substrate located in the third region, and a second contact structure is disposed on the second circuit layer. The second contact structure extends along the third direction, and the second connector is electrically connected to the second circuit layer through the second contact structure.

[0017] Secondly, embodiments of this application also provide a method for fabricating a semiconductor structure, comprising:

[0018] A substrate is provided, the substrate having a first region and a second region, the second region being arranged adjacent to the first region, and the substrate located in the first region having a groove;

[0019] A first connector and a storage structure are formed in the groove, the first connector extending along a first direction and the storage structure extending along a second direction, and the first connector being electrically connected to the storage structure.

[0020] A first circuit layer and a first contact structure are formed on the substrate located in the second region. A plurality of the first contact structures are spaced apart along the first direction. The first connector is electrically connected to the first circuit layer through the first contact structure. The first direction is perpendicular to the second direction.

[0021] In one possible implementation, after the substrate is provided but before the first connector and storage structure are formed, the method further includes:

[0022] An intermediate layer is formed on the groove wall and the groove bottom;

[0023] The intermediate layer covering the bottom of the groove is removed to form a protective layer covering the sidewalls of the groove. The material of the protective layer includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0024] In one possible implementation, removing the intermediate layer covering the bottom of the groove includes:

[0025] The intermediate layer covering the bottom of the groove is removed using a plasma etching process.

[0026] In one possible implementation, after the protective layer is formed and before the first connector and storage structure are formed, the method further includes:

[0027] An oxide is formed on the bottom of the groove;

[0028] The oxides are removed using a cleaning solution.

[0029] In one possible implementation, a substrate is provided, the substrate located in the first region having a groove, including:

[0030] A mask layer is formed on the substrate;

[0031] The substrate is etched using the mask layer as a mask to form the groove. The groove includes a first groove region and a second groove region that are interconnected. The first groove region extends along the first direction, and the second groove region extends along the second direction. The depth of the groove ranges from 400nm to 1000nm.

[0032] In one possible implementation, the first connector and the storage structure are formed within the groove, including:

[0033] Multiple sacrificial layers are formed in the groove;

[0034] Remove a portion of the sacrificial layer to form a first filling space;

[0035] Multiple support columns are formed within the first filling space;

[0036] Remove part of the sacrificial layer, retaining the support column, to form a second filling space;

[0037] Multiple step structures are formed in the second filling space located in the first groove area. The multiple step structures are stacked along the third direction and distributed in a stepped manner. The multiple step structures constitute the first connector. Each step structure extends along the first direction.

[0038] Multiple capacitors are formed in the second filling space located in the second trench area, stacked along a third direction. The multiple capacitors constitute the storage structure, and each step structure is electrically connected to its corresponding capacitor.

[0039] The first direction, the second direction, and the third direction are perpendicular to each other.

[0040] In one possible implementation, the first connector and the storage structure are formed within the groove, and the method further includes:

[0041] Multiple conductive pillars are formed in the first groove area, and the multiple conductive pillars are spaced apart along a first direction. The conductive pillars are in contact with and electrically connected to the corresponding stepped structure.

[0042] Multiple spaced bit line connection structures are formed on the conductive post, each bit line connection structure extends along the second direction, the top end of the conductive post is electrically connected to the bit line connection structure, and the bit line connection structure is electrically connected to the corresponding first contact structure.

[0043] In one possible implementation, the first connector and the storage structure are formed within the groove, and the method further includes:

[0044] A gate conductive structure is formed in the second trench region, and the gate conductive structure is electrically connected to a plurality of capacitors stacked along the third direction;

[0045] A word line connection structure is formed on the gate conductive structure, the word line connection structure extends along the second direction, the top end of the gate conductive structure is electrically connected to the word line connection structure, and the word line connection structure is electrically connected to the corresponding first contact structure.

[0046] In one possible implementation, the substrate is provided, further comprising: the substrate having a third region, wherein the second region and the third region are located on opposite sides of the first region;

[0047] Forming the first connector and the storage structure within the groove includes: forming a second connector extending along a first direction in the groove, wherein the second connector is electrically connected to one end of the storage structure opposite to the first connector;

[0048] Forming a first circuit layer and a first contact structure on the substrate located in the second region includes: forming a second circuit layer and a second contact structure on the substrate located in the third region, the second contact structure extending along the third direction, and the second connector being electrically connected to the second circuit layer through the second contact structure.

[0049] This application provides a semiconductor structure and a method for fabricating the semiconductor structure. The semiconductor structure includes a substrate with a first region and a second region, the second region being adjacent to the first region. The substrate in the first region has a groove, within which a first connector and a storage structure are disposed. The first connector extends along a first direction, and the storage structure extends along a second direction, with the first connector electrically connected to the storage structure. A first circuit layer is disposed on the substrate in the second region, and a plurality of first contact structures spaced apart along the first direction are disposed on the first circuit layer, with the first connector electrically connected to the first contact structures. The first direction and the second direction are perpendicular to each other. By placing the storage structure within the groove in the first region, this application reduces the distance between the top surface of the storage structure and the top surface of the second region, shortens the length of the first contact structures, and thus facilitates the miniaturization of the circuitry in the second region. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1A schematic diagram of a semiconductor structure provided in this application embodiment. Figure 1 ;

[0052] Figure 2 This application provides a schematic diagram of the structure of a first connector and a memory structure in a semiconductor structure.

[0053] Figure 3 A schematic diagram of a semiconductor structure provided in this application embodiment. Figure 2 ;

[0054] Figure 4 A schematic diagram of a semiconductor structure provided in this application embodiment. Figure 3 ;

[0055] Figure 5 A flowchart illustrating a method for fabricating a semiconductor structure, as provided in this application embodiment;

[0056] Figure 6 This is a schematic diagram of the structure for forming a mask layer in a method for fabricating a semiconductor structure according to an embodiment of this application;

[0057] Figure 7 This is a schematic diagram of the structure for forming a photoresist layer in a method for fabricating a semiconductor structure according to an embodiment of this application;

[0058] Figure 8 for Figure 7 Cross-sectional view at point AA;

[0059] Figure 9 This is a schematic diagram of a method for forming a groove in the fabrication of a semiconductor structure provided in an embodiment of this application;

[0060] Figure 10 for Figure 9 Cross-sectional view at point BB;

[0061] Figure 11 This is a schematic diagram of the structure for forming a protective layer in a method for fabricating a semiconductor structure according to an embodiment of this application;

[0062] Figure 12 This is a schematic diagram of the structure for forming a sacrificial layer in a method for fabricating a semiconductor structure according to an embodiment of this application. Detailed Implementation

[0063] In DRAM of related technologies, there are core and peripheral regions. The core region consists of multiple memory cells, each typically including a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source of the transistor is electrically connected to the bit line, and the drain of the transistor is electrically connected to the capacitor. The peripheral region is provided with peripheral circuitry, and the word and bit lines are electrically connected to the peripheral circuitry through contact structures. During actual research, the inventors of this application discovered that stacking multiple capacitors in the core region results in a large distance between the top surface of the capacitors and the top surface of the peripheral region, leading to a long contact structure. However, as the integration density of DRAM continues to increase, the long contact structure is detrimental to the miniaturization of the peripheral circuitry in the peripheral region.

[0064] In view of this, embodiments of this application provide a semiconductor structure and a method for fabricating the semiconductor structure. The semiconductor structure includes a substrate, which has a first region and a second region. The second region is arranged adjacent to the first region. The substrate in the first region has a groove, and a first connector and a storage structure are disposed in the groove. The first connector extends along a first direction and is electrically connected to the storage structure. A first circuit layer is disposed on the substrate in the second region, and a plurality of first contact structures are disposed on the first circuit layer at intervals along the first direction. The first connector is electrically connected to the first contact structures. The first direction and the second direction are perpendicular to each other. By placing the storage structure in the groove in the first region, embodiments of this application can reduce the distance between the top surface of the storage structure and the top surface of the second region, shorten the length of the first contact structures, and thus facilitate the miniaturization of the circuit in the second region.

[0065] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be described in more detail below with reference to the accompanying drawings. In the drawings, the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout. The described embodiments are some, but not all, embodiments of this application. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application. The embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0066] Reference Figure 1 , Figure 2 as well as Figure 3This application provides a semiconductor structure. It should be noted that the semiconductor structure provided in this application can be a memory device or a non-memory device. Memory devices may include, for example, Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), flash memory, Electrically Erasable Programmable Read-Only Memory (EEPROM), Phase Change Random Access Memory (PRAM), or Magnetoresistive Random Access Memory (MRAM). Non-memory devices may be logic devices (e.g., microprocessors, digital signal processors, or microcontrollers) or similar devices. This application uses a DRAM memory device as an example for illustration.

[0067] The semiconductor structure includes a substrate 10. The substrate 10 provides the structural basis for subsequent structures and processes. The material of the substrate 10 may include any one or more of silicon, germanium, silicon-germanium, silicon carbide, silicon-on-insulator substrate 10, and germanium-on-insulator substrate 10. In this embodiment, the substrate 10 may be made of silicon.

[0068] In this embodiment, the substrate 10 has a first region 101 and a second region 102. The first region 101 can be a core region, and the second region 102 can be a peripheral region. The first region 101 and the second region 102 are arranged adjacent to each other. It is worth noting that the first direction X and the second direction Y described below are both parallel to the surface of the substrate 10, and the first direction X and the second direction Y are perpendicular to each other; the third direction Z is a direction perpendicular to the surface of the substrate 10, and the first direction X, the second direction Y, and the third direction Z are all perpendicular to each other.

[0069] Reference Figure 3 The substrate 10 located in the first region 101 has a groove 11, which includes a first groove region and a second groove region that are interconnected. The first groove region extends along a first direction X, and the second groove region extends along a second direction Y. A first connector 31 and a storage structure 32 are disposed within the groove 11. The first connector 31 is located within the first groove region and extends along the first direction X, while the storage structure 32 is located within the second groove region and extends along the second direction Y. The first connector 31 and the storage structure 32 are electrically connected. It is worth noting that the shape of the groove 11 can be configured according to the shapes of the first connector 31 and the storage structure 32; this embodiment does not impose specific limitations on this.

[0070] In this embodiment, the first connector 31 may include a plurality of stepped structures 311 stacked along the third direction Z and distributed in a stepped manner, each stepped structure 311 extending along the first direction X; the storage structure 32 includes a plurality of capacitors 321 stacked along the third direction Z, each stepped structure 311 being electrically connected to its corresponding capacitor 321. For example, each stepped structure 311 and its corresponding capacitor 321 are located in the same plane, which helps improve the regularity of the semiconductor structure and reduces the fabrication difficulty of the semiconductor structure.

[0071] A first circuit layer 20 is disposed on the substrate 10 located in the second region 102. The first circuit layer 20 can be the peripheral circuit of the peripheral region. Multiple first contact structures 21 are disposed on the first circuit layer 20 at intervals along a first direction X. A first connector 31 is electrically connected to the first circuit layer 20 through the first contact structures 21. The first contact structures 21 extend along a third direction Z. The top end of the first contact structure 21 is electrically connected to the corresponding step structure 311 in the first connector 31, and the bottom end of the first contact structure 21 contacts and is connected to the first circuit layer 20. Therefore, the peripheral circuit can be electrically connected to the corresponding capacitor 321 in the storage structure 32 through different first contact structures 21 and step structures 311, enabling the first circuit layer 20 to store or retrieve data from the corresponding capacitor 321.

[0072] The semiconductor structure provided in this application includes a substrate 10, which has a first region 101 and a second region 102. The second region 102 is arranged adjacent to the first region 101. The substrate 10 in the first region 101 has a groove 11, in which a first connector 31 and a storage structure 32 are disposed. The first connector 31 extends along a first direction X, and the storage structure 32 extends along a second direction Y. The first connector 31 and the storage structure 32 are electrically connected. A first circuit layer 20 is disposed on the substrate 10 in the second region 102. A plurality of first contact structures 21 are disposed on the first circuit layer 20 at intervals along the first direction X. The first connector 31 and the first circuit layer 20 are electrically connected through the first contact structures 21. The first direction X and the second direction Y are perpendicular to each other. By placing the storage structure 32 in the groove 11 in the first region 101, this application can reduce the distance between the top surface of the storage structure 32 and the top surface of the second region 102, shorten the length of the first contact structure 21, and thus facilitate further miniaturization of the circuit in the second region.

[0073] Reference Figure 2In some embodiments, the first connector 31 is a bit line connector. Multiple bit line connection structures 51 may also be spaced apart on the substrate 10, extending along the second direction Y. Conductive posts 41 may also be provided on the stepped structure 311. The first connector 31 is electrically connected to the bit line connection structure 51 through the conductive posts 41. For example, multiple conductive posts 41 are spaced apart along the first direction X, each extending along the third direction Z, and each stepped structure 311 has a corresponding conductive post 41. The conductive post 41 contacts and is electrically connected to the stepped structure 311. The end of the conductive post 41 facing away from the stepped structure 311 is electrically connected to the corresponding bit line connection structure 51. The bit line connection structure 51 is electrically connected to the corresponding first contact structure 21, so that the first circuit layer 20 can control data to be stored in the corresponding capacitor 321 through different bit line connection structures 51, or control data to be read out of the corresponding capacitor 321 through different bit line connection structures 51.

[0074] Furthermore, since each step structure 311 in the first connector 31 extends along the first direction X, and multiple first contact structures 21 are also spaced apart along the first direction X, it is beneficial to reduce the distance between the step structure 311 and the first contact structure 21, and to reduce the length of the bit line connecting structure 51 between the step structure 311 and the first contact structure 21, which is beneficial for the miniaturization of the semiconductor structure.

[0075] Continue to refer to Figure 2The first connector 31 can be a bit line connector. Word line output structures 52 can be spaced apart on the substrate 10, and the word line output structures 52 extend along the second direction Y. The memory structure 32 also includes a gate conductive structure 42. The top end of the gate conductive structure 42 is connected to the word line output structure 52, and the gate conductive structure 42 is electrically connected to a plurality of capacitors 321 arranged along the third direction Z. For example, the plurality of gate conductive structures 42 are spaced apart along the first direction X, each gate conductive structure 42 extends along the third direction Z, and each word line output structure 52 is correspondingly provided with a gate conductive structure 42. In some embodiments, a plurality of active structures 33 are stacked along the third direction Z. One end of the active structure 33 is electrically connected to the corresponding step structure, and the other end of the active structure 33 is electrically connected to the corresponding capacitor 321. The gate conductive structure 42 can surround all or part of the plurality of active structures 33 arranged along the third direction Z so that the gate conductive structure 42 is electrically connected to the plurality of capacitors 321 arranged along the third direction Z. It is worth noting that the gate conductive structure 42 and the active structure 33 together constitute the transistor structure. The top end of the gate conductive structure 42, that is, the end opposite to the bottom of the groove 11, is electrically connected to the word line connection structure 52. The word line connection structure 52 is electrically connected to the corresponding first contact structure 21, so that the first circuit layer 20 can control the corresponding gate conductive structure 42 to turn the transistor structure on or off through the voltage of different word line connection structures 52.

[0076] In some other embodiments, the first connector may also be a word line connector, and the storage structure further includes a plurality of active pillars stacked along a third direction Y, and a plurality of bit line structures spaced apart along a first direction X. Each active pillar extends along a second direction Y, with one end of the active pillar near the substrate of the second region electrically connected to the corresponding bit line structure, and the other end of the active pillar electrically connected to the corresponding capacitor. Each active pillar is at least partially covered by the corresponding stepped structure in the word line connector. In some embodiments, the word line output structure is electrically connected to the first connector so that the first circuit layer connects different stepped structures through the word line output structure, thereby controlling the corresponding active pillar to be turned on or off. The bit line output structure is electrically connected to the bit line structure so that the first circuit layer connects different bit line structures through the bit line output structure, thereby controlling the data to be stored in the corresponding capacitor or controlled to be read from the corresponding capacitor through the corresponding active pillar.

[0077] like Figure 3As shown, a protective layer 61 can also be provided on the sidewall of the groove 11. The protective layer 61 is made of one or more of silicon nitride, silicon oxide, and silicon oxynitride. By providing a protective layer 61 on the sidewall of the groove 11, the storage structure 32 within the groove 11 can be isolated from the first circuit layer 20, thereby improving the performance of the semiconductor structure. Simultaneously, providing a protective layer 61 on the sidewall of the groove 11 also helps to protect the substrate 10 during the formation of the storage structure 32 within the groove 11, thereby further improving the performance of the semiconductor structure.

[0078] In some embodiments, the top surface of the substrate 10 located in the second region 102 may be lower than the top surface of the memory structure 32, with a height difference ranging from 0 to 100 nm. The height difference H can be 0 nm, 50 nm, or 100 nm. In other embodiments, the top surface of the substrate 10 located in the second region 102 may be higher than the top surface of the memory structure 32, with a height difference ranging from 0 to 150 nm. For example, the height difference can be 0 nm, 75 nm, or 150 nm. By limiting the height difference, it is beneficial to further reduce the distance between the top surface of the memory structure 32 and the top surface of the second region 102, further shorten the length of the first contact structure 21, and thus facilitate further miniaturization of the circuitry in the second region.

[0079] It is worth noting that the depth of the groove 11 should be set according to the number of capacitors 321 stacked in the storage structure 32. In this embodiment, the depth of the groove 11 ranges from 400nm to 1000nm. For example, the depth of the groove 11 can be 400nm, 700nm, or 1000nm, so as to further reduce the distance between the top surface of the storage structure 32 and the top surface of the second region 102 within the groove 11, thereby facilitating further miniaturization of the circuit in the second region. Correspondingly, the width and length of the groove 11 should also be set according to the size of the storage structure 32 within the groove 11. In this embodiment, the width or length of the groove 11 can range from 5μm to 100μm. For example, the width or length of the groove 11 can be 5μm, 50μm, or 100μm. Here, the width and length of the groove 11 refer to the distance of the groove 11 along the first direction X and the second direction Y, respectively.

[0080] Reference Figure 3 and Figure 4In some embodiments, the substrate 10 may have a third region 103, with the second region 102 and the third region 103 located on opposite sides of the first region 101. For example, the third region 103 is a peripheral region, and the third region 103 is also arranged adjacent to the first region 101. Correspondingly, the groove 11 may also include a third groove region communicating with the first groove region, and a second connector extending along the first direction X is disposed in the third groove region. The second connector is electrically connected to one end of the storage structure 32 opposite to the first connector 31. In some embodiments, the second connector and the first connector 31 may be symmetrically arranged with respect to the center line L of the groove 11.

[0081] In some embodiments, the capacitor includes a plurality of first capacitors stacked along a third direction and a plurality of second capacitors stacked along a third direction. The first capacitors and second capacitors extend along a second direction and are disposed opposite to each other. A first connector is electrically connected to one end of the plurality of first capacitors away from the second capacitors, and a second connector is electrically connected to one end of the plurality of second capacitors away from the first capacitors.

[0082] Furthermore, a second circuit layer 70 can be disposed on the substrate 10 located in the third region 103. A second contact structure 71 is disposed on the second circuit layer 70, extending in the third direction Z. The storage structure 32 is electrically connected to the second contact structure 71. In some embodiments, the second circuit layer 70 and the first circuit layer 20, and the second contact structure 71 and the first contact structure 21, can all be symmetrically arranged with respect to the center line L of the groove 11. This implementation method helps to reduce the distance between the top surface of the storage structure 32 and the top surface of the third region 103, shortens the length of the second contact structure 71, and thus facilitates the miniaturization of the second circuit layer 70. Furthermore, the symmetrical arrangement method helps to improve the regularity of the semiconductor structure and reduce the fabrication difficulty of the semiconductor structure.

[0083] Based on the above embodiments, referring to Figure 5 As shown, a second aspect of this application provides a method for fabricating a semiconductor structure, comprising the following steps:

[0084] S101: Provide a substrate having a first region and a second region, the second region being arranged adjacent to the first region, and the substrate located in the first region having a groove.

[0085] As described in the above embodiments, refer to Figure 6The substrate 10 provides a structural basis for subsequent structures and processes. The material of the substrate 10 may include silicon, germanium, silicon-germanium, silicon carbide, silicon-on-insulator (SiI) substrate 10, and germanium-on-insulator (GDI) substrate 10, or any one or more of these. In this embodiment, the substrate 10 may be made of silicon. The first region 101 of the substrate 10 is the core region, and the second region 102 is the peripheral region. The substrate 10 may also have a third region 103, which is also a peripheral region. The second region 102 and the third region 103 are located on opposite sides of the first region 101.

[0086] In this embodiment, the step of providing the substrate 10 further includes: forming a mask layer 60 on the substrate 10, the mask layer 60 having mask openings that expose the substrate in the first region. Exemplarily, the mask layer 60 may include a first mask layer 601 and a second mask layer 602, the first mask layer 601 covering the top surface of the substrate 10, and the second mask layer 602 covering the top surface of the first mask layer 601. The material of the first mask layer 601 and the second mask layer 602 may include, for example, one or more of oxides, nitrides, or oxynitrides.

[0087] like Figure 7 and Figure 8 As shown, in some embodiments, a photoresist layer 80 can be formed on the top surface of the second mask layer 602. The photoresist layer 80 has a photolithographic pattern. A portion of the mask layer 60 is removed by a photolithography process to create a mask opening that exposes the substrate located in the first region. The photoresist layer 80 can be, for example, a positive photoresist, whose projection on the substrate 10 coincides with the second region 102 and the third region 103.

[0088] In this embodiment, refer to Figure 9 and Figure 10 After forming the mask layer 60, the process further includes etching the substrate 10 using the mask layer 60 as a mask to form a groove 11. The groove 11 includes a first groove region and a second groove region that are interconnected. The first groove region extends along a first direction X, and the second groove region extends along a second direction Y. The depth of the groove 11 ranges from 400 nm to 1000 nm. The groove 11 may also include a third groove region that extends along the second direction Y and is connected to the first groove region. The length of the second groove region in the first direction X is greater than the length of the first groove region in the first direction X, and the length of the third groove region in the first direction X is greater than the length of the first groove region in the first direction X. The lengths of the second groove region and the third groove region in the first direction X may be equal.

[0089] It is worth noting that the depth of the groove 11 should be set according to the number of stacked structures in the internal structure. In this embodiment, the depth of the groove 11 ranges from 400nm to 1000nm. The depth of the groove 11 can be 400nm, 700nm, or 1000nm to reduce the distance between the top surface of the structure inside the groove 11 and the top surface of the second region 102. Correspondingly, the width and length of the groove 11 should also be set according to the dimensions of the structure inside the groove 11. In this embodiment, the width or length of the groove 11 can range from 5μm to 100μm. For example, the width or length of the groove 11 can be 5μm, 50μm, or 100μm. Here, the width and length of the groove 11 refer to the distance of the groove 11 along the first direction X and the second direction Y, respectively.

[0090] In this embodiment, refer to Figure 11 After forming the groove 11, the process further includes: forming an intermediate layer on the groove wall and the bottom of the groove 11; removing the intermediate layer covering the bottom of the groove 11 to form a protective layer 61 covering the sidewalls of the groove 11. The protective layer 61 is made of one or more of silicon nitride, silicon oxide, and silicon oxynitride. The thickness of the protective layer 61 in the second direction Y is less than the width of the second and third groove regions in the second direction Y. By providing the protective layer 61 on the sidewalls of the groove 11, the storage structure 32 within the groove 11 can be isolated from the first circuit layer 20, thereby improving the performance of the semiconductor structure. Simultaneously, providing the protective layer 61 on the sidewalls of the groove 11 also helps to protect the substrate 10 during the formation of the storage structure 32 within the groove 11, thereby further improving the performance of the semiconductor structure.

[0091] In this embodiment, the step of removing the intermediate layer covering the bottom of the groove 11 may include: removing the intermediate layer covering the bottom of the groove 11 using a plasma etching process. It is worth noting that plasma etching is a type of dry etching, characterized by high selectivity and high etching rate, which is beneficial for improving the fabrication efficiency of semiconductor structures.

[0092] In this embodiment, after forming the protective layer 61, the process further includes: forming an oxide on the bottom of the groove 11; and removing the oxide using a cleaning solution to repair the surface of the bottom of the groove 11. It is worth noting that plasma etching is a type of dry etching, and during the etching process to remove the intermediate layer located on the bottom of the groove, the silicon lattice within the substrate 10 may be damaged. While forming the oxide on the bottom of the groove 11, the oxide consumes the damaged silicon on the bottom surface. Removing the oxide using a cleaning solution repairs the surface of the bottom of the groove 11, which is beneficial for improving the performance of the semiconductor structure. In some embodiments, the oxide can be formed using in-situ steam generation (ISSG), PED, CVD, etc., and the cleaning solution may include, for example, an acid solution such as hydrofluoric acid.

[0093] In this embodiment, after repairing the bottom of the groove 11, the method further includes:

[0094] S102: A first connector and a storage structure are formed in the groove. The first connector extends along a first direction, and the storage structure extends along a second direction. The first connector and the storage structure are electrically connected.

[0095] In this embodiment, as Figure 12 As shown, a first connector 31 and a storage structure 32 are formed within a groove 11, including: forming a plurality of stacked sacrificial layers within the groove 11. The sacrificial layers may include a first sacrificial layer 301 and a second sacrificial layer 302, which are sequentially stacked within the groove 11. The material of the first sacrificial layer 301 may include silicon, and the material of the second sacrificial layer 302 may include silicon germanium.

[0096] The step of forming the first connector 31 and the storage structure 32 in the groove 11 after forming multiple sacrificial layers further includes: removing part of the sacrificial layers to form a first filling space; and forming multiple support columns in the first filling space.

[0097] Reference Figure 2 The step of forming a first connector 31 and a storage structure 32 in the groove 11 after forming multiple support columns further includes: removing part of the sacrificial layer and retaining the support columns to form a second filling space; forming multiple step structures 311 in the second filling space located in the first groove area, the multiple step structures 311 being stacked along the third direction Z and distributed in a stepped manner, the multiple step structures 311 constituting the first connector 31, and each step structure 311 extending along the first direction X.

[0098] After forming multiple support pillars, the step of forming the first connector 31 and the storage structure 32 within the groove 11 further includes: forming multiple capacitors 321 stacked along the third direction Z within the second filling space located in the second groove region. The multiple capacitors 321 constitute the storage structure 32, and each step structure 311 is electrically connected to its corresponding capacitor 321. It is worth noting that the first direction X and the second direction Y are both parallel to the surface of the substrate 10, and the first direction X and the second direction Y are perpendicular to each other; the third direction Z is perpendicular to the surface of the substrate 10, and the first direction X, the second direction Y, and the third direction Z are all perpendicular to each other.

[0099] For example, each step structure 311 is connected to a capacitor 321, and each step structure 311 and its corresponding capacitor 321 are located in the same plane, which helps to improve the regularity of the semiconductor structure and reduce the manufacturing difficulty of the semiconductor structure.

[0100] In this embodiment, in addition to forming the first connector 31, a second connector extending along the first direction X is also formed within the groove 11. The second connector is electrically connected to the end of the storage structure 32 opposite to the first connector 31. Accordingly, the second connector may be located in a third groove region of the groove 11. In some embodiments, the second connector and the first connector 31 may be symmetrically arranged with respect to the center line L of the groove 11.

[0101] In this embodiment, a first connector 31 and a storage structure 32 are formed within the groove 11. The embodiment also includes forming a plurality of conductive posts 41 within the first groove area. These conductive posts 41 are spaced apart along a first direction X, and each conductive post 41 contacts and is electrically connected to a corresponding stepped structure 311. For example, the plurality of conductive posts 41 are spaced apart along the first direction X, each conductive post 41 extends along a third direction Z, and each stepped structure 311 is correspondingly provided with one conductive post 41.

[0102] In some embodiments, the first connector 31 is a bit line connector. After forming multiple conductive posts 41, the connector further includes: forming multiple spaced bit line connection structures 51 on the conductive posts 41. Each bit line connection structure 51 extends along the second direction Y. The end of the conductive post 41 facing away from the step structure 311 is electrically connected to the corresponding bit line connection structure 51. The bit line connection structure 51 is electrically connected to the corresponding first contact structure 21. For example, the conductive post 41 is in contact with and electrically connected to the step structure 311. The end of the conductive post 41 facing away from the step structure 311 is electrically connected to the corresponding bit line connection structure 51. The bit line connection structure 51 is electrically connected to the corresponding first contact structure 21, so that data can be controlled to be stored in the corresponding capacitor 321 through different bit line connection structures 51, or data can be controlled to be read out of the corresponding capacitor 321 through different bit line connection structures 51.

[0103] In an embodiment where the first connector 31 is a bit line connector, the first connector 31 and the storage structure 32 are formed within the groove 11, and the method further includes: forming a gate conductive structure 42 within the second groove region, the gate conductive structure 42 being electrically connected to a plurality of capacitors 321 arranged along a third direction Z. Exemplarily, the plurality of gate conductive structures 42 are spaced apart along a first direction X, each gate conductive structure 42 extending along a third direction Z, and each word line connection structure 52 correspondingly has one gate conductive structure 42.

[0104] After forming the gate conductive structure 42, the method further includes: forming a word line connection structure 52 on the gate conductive structure 42, the word line connection structure 52 extending along the second direction Y, one end of the gate conductive structure 42 away from the bottom of the groove 11 being electrically connected to the word line connection structure 52, and the word line connection structure 52 being electrically connected to the corresponding first contact structure 21. In some embodiments, before forming the gate conductive structure 42, the method further includes forming a plurality of active structures 33 stacked along the third direction Y. One end of the active structure 33 is electrically connected to the corresponding step structure, and the other end of the active structure 33 is electrically connected to the corresponding capacitor 321. The gate conductive structure 42 may surround all or part of the plurality of active structures 33 arranged along the third direction Z, so that the gate conductive structure 42 is electrically connected to the plurality of capacitors 321 arranged along the third direction Z. It is worth noting that the gate conductive structure 42 and the active structures 33 together constitute a transistor structure. One end of the gate conductive structure 42 away from the bottom of the groove 11 is electrically connected to the word line connection structure 52. The word line connection structure 52 is electrically connected to the corresponding first contact structure 21 so that the voltage of different word line connection structures 52 can control the corresponding gate conductive structure 42 to turn the transistor structure on or off.

[0105] In other embodiments, the first connector 31 may also be a word line connector. The first connector 31 and the storage structure 32 are formed within the groove 11, and the groove 11 further includes: a plurality of active pillars stacked along a third direction Y, and a plurality of bit line structures spaced apart along a first direction X. Each active pillar extends along a second direction Y, with one end electrically connected to the corresponding bit line structure and the other end electrically connected to the corresponding capacitor. The active pillars are also sandwiched between the top surfaces of two adjacent stepped structures 311.

[0106] In embodiments where the first connector 31 is a word line connector, after forming the active pillars and bit line structures, the method further includes forming a word line connection structure 52 and a bit line connection structure 51 extending along the second direction Y. In some embodiments, the word line connection structure 52 is electrically connected to the first connector 31 so that the first circuit layer 20 connects to different step structures 311 through the word line connection structure 52, thereby controlling the corresponding active pillars to be turned on or off. The bit line connection structure 51 is electrically connected to the bit line structure so that the first circuit layer 20 connects to different bit line structures through the bit line connection structure 51, thereby controlling the data to be stored in the corresponding capacitor 321 or controlled to be read out of the corresponding capacitor 321 through the corresponding active pillars.

[0107] In this embodiment, after the first connector 31 and the storage structure 32 are formed in the groove 11, the following is also included:

[0108] S103: A first circuit layer and a first contact structure are formed on a substrate located in the second region, a plurality of first contact structures are spaced apart along a first direction, and a first connector is electrically connected to the first contact structure; the first direction and the second direction are perpendicular to each other.

[0109] For example, refer to Figure 1 The first circuit layer 20 can be the peripheral circuit of the peripheral area. The first circuit layer 20 is provided with multiple first contact structures 21 spaced apart along the first direction X. The first connector 31 is electrically connected to the first circuit layer 20 through the first contact structures 21. The first contact structure 21 extends along the third direction Z. The top end of the first contact structure 21 is electrically connected to the corresponding step structure 311 in the first connector 31, and the bottom end of the first contact structure 21 contacts and is connected to the first circuit layer 20. Therefore, the peripheral circuit can be electrically connected to the corresponding capacitor 321 in the storage structure 32 through different first contact structures 21 and step structures 311, enabling the first circuit layer 20 to store or retrieve data from the corresponding capacitor 321.

[0110] This application provides a method for fabricating a semiconductor structure, including: providing a substrate 10, the substrate 10 having a first region 101 and a second region 102, the second region 102 being arranged adjacent to the first region 101, and the substrate 10 located in the first region 101 having a groove 11; forming a first connector 31 and a storage structure 32 within the groove 11, the first connector 31 extending along a first direction X, the storage structure 32 extending along a second direction Y, and the first connector 31 being electrically connected to the storage structure 32; forming a first circuit layer 20 and a first contact structure 21 on the substrate 10 located in the second region 102, a plurality of first contact structures 21 being spaced apart along the first direction X, and the first connector 31 being electrically connected to the first circuit layer 20 through the first contact structure 21; the first direction X and the second direction Y are perpendicular to each other. By forming the storage structure 32 within the groove 11, this application can reduce the distance between the top surface of the storage structure 32 and the top surface of the second region 102, shorten the length of the first contact structure 21, and thus facilitate further miniaturization of the circuit in the second region.

[0111] Furthermore, since each step structure 311 in the first connector 31 extends along the first direction X, and multiple first contact structures 21 are also spaced apart along the first direction X, it is beneficial to reduce the distance between the step structure 311 and the first contact structure 21, and to reduce the length of the bit line connecting structure 51 between the step structure 311 and the first contact structure 21, which is beneficial for the miniaturization of the semiconductor structure.

[0112] As described in the above embodiments, when the top surface of the substrate in the second region is lower than the top surface of the memory structure, the height difference between the two ranges from 0 to 100 nm. Figure 3 As shown, the height difference H between the two can be 0 nm, 50 nm, or 100 nm. In some other embodiments, when the top surface of the substrate in the second region is higher than or flush with the top surface of the memory structure, the height difference between the two ranges from 0 to 150 nm. For example, the height difference between the two can be 0 nm, 75 nm, or 150 nm. By limiting the height difference between the two, it is beneficial to further reduce the distance between the top surface of the memory structure 32 and the top surface of the second region 102, further shorten the length of the first contact structure 21, and thus facilitate further miniaturization of the circuitry in the second region.

[0113] In this embodiment, refer to Figure 4In addition to forming the first circuit layer 20 and the first contact structure 21, the method also includes forming a second circuit layer 70 and a second contact structure 71 on the substrate 10 located in the third region 103. The second contact structure 71 extends along the third direction Z, and the storage structure 32 is electrically connected to the second contact structure 71. In some embodiments, the second circuit layer 70 and the first circuit layer 20, and the second contact structure 71 and the first contact structure 21, can all be symmetrically arranged with respect to the center line L of the groove 11. This implementation method helps to reduce the distance between the top surface of the storage structure 32 and the top surface of the third region 103, shortens the length of the second contact structure 71, and thus facilitates the miniaturization of the second circuit layer 70. Furthermore, the symmetrical arrangement method helps to improve the regularity of the semiconductor structure and reduce the fabrication difficulty of the semiconductor structure.

[0114] In the above description, it should be understood that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection or an indirect connection through an intermediate medium, or the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances. The terms "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In the description of this application, "multiple" means two or more, unless otherwise precisely specified.

[0115] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0116] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor structure, characterized by, The substrate includes a first region and a second region, the second region being arranged adjacent to the first region. The substrate located in the first region has a groove, in which a first connector and a storage structure are disposed. The first connector extends along a first direction, and the storage structure extends along a second direction. The first connector is electrically connected to the storage structure. A first circuit layer is disposed on the substrate located in the second region, and a plurality of first contact structures are disposed on the first circuit layer at intervals along the first direction. The first connector is electrically connected to the first contact structure; the first direction is perpendicular to the second direction.

2. The semiconductor structure of claim 1, wherein, The groove includes a first groove area and a second groove area that are interconnected. The first groove area extends along the first direction, and the second groove area extends along the second direction. The first connector is located in the first groove area. The first connector includes a plurality of stepped structures stacked along a third direction and distributed in a stepped manner. Each of the stepped structures extends along the first direction. The storage structure is located in the second slot area, and the storage structure includes a plurality of capacitors stacked along a third direction, with each step structure electrically connected to its corresponding capacitor; The first direction, the second direction, and the third direction are perpendicular to each other.

3. The semiconductor structure of claim 2, wherein, The sidewalls of the groove are covered with a protective layer, the material of which includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.

4. The semiconductor structure of claim 2, wherein, When the top surface of the substrate located in the second region is lower than the top surface of the memory structure, the height difference between the two ranges from 0 to 100 nm; when the top surface of the substrate located in the second region is higher than or flush with the top surface of the memory structure, the height difference between the two ranges from 0 to 150 nm.

5. The semiconductor structure according to claim 2, characterized in that, The depth of the groove ranges from 400nm to 1000nm.

6. The semiconductor structure according to any one of claims 2-5, characterized in that, Multiple bit line connection structures are spaced apart on the substrate and extend along the second direction; conductive pillars are provided on the stepped structure, the conductive pillars are in contact with and electrically connected to the stepped structure, the top of the conductive pillars are electrically connected to the bit line connection structures, and the bit line connection structures are electrically connected to the corresponding first contact structures.

7. The semiconductor structure according to any one of claims 2-5, characterized in that, Word line connection structures are spaced apart on the substrate and extend along the second direction. A gate conductive structure is disposed in the groove. The gate conductive structure is electrically connected to a plurality of capacitors stacked along the third direction. The top end of the gate conductive structure is electrically connected to the word line connection structure. The word line connection structure is electrically connected to the corresponding first contact structure.

8. The semiconductor structure according to any one of claims 2-5, characterized in that, The substrate has a third region, and the second region and the third region are respectively located on opposite sides of the first region. A second connector extending along a first direction is disposed in the groove, and the second connector is electrically connected to one end of the storage structure opposite to the first connector. A second circuit layer is disposed on the substrate located in the third region, and a second contact structure is disposed on the second circuit layer. The second contact structure extends along the third direction, and the second connector is electrically connected to the second circuit layer through the second contact structure.

9. A method for fabricating a semiconductor structure, characterized in that, A substrate is provided, the substrate having a first region and a second region, the second region being arranged adjacent to the first region, and the substrate located in the first region having a groove; A first connector and a storage structure are formed in the groove. The first connector extends along a first direction, and the storage structure extends along a second direction. The first connector is electrically connected to the storage structure. A first circuit layer and a first contact structure are formed on the substrate located in the second region, a plurality of the first contact structures are spaced apart along the first direction, and the first connector is electrically connected to the first contact structure; the first direction is perpendicular to the second direction.

10. The method for fabricating a semiconductor structure according to claim 9, characterized in that, After the substrate is provided, but before the first connector and storage structure are formed, the method further includes: An intermediate layer is formed on the groove wall and the groove bottom; The intermediate layer covering the bottom of the groove is removed to form a protective layer covering the sidewalls of the groove. The material of the protective layer includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.

11. The method for fabricating a semiconductor structure according to claim 10, characterized in that, Removing the intermediate layer covering the bottom of the groove includes: The intermediate layer covering the bottom of the groove is removed using a plasma etching process.

12. The method for fabricating a semiconductor structure according to claim 11, characterized in that, After the protective layer is formed, but before the first connector and storage structure are formed, the method further includes: An oxide is formed on the bottom of the groove; The oxides are removed using a cleaning solution.

13. The method for fabricating a semiconductor structure according to any one of claims 9-12, characterized in that, Provide a substrate, including: A mask layer is formed on the substrate; The substrate is etched using the mask layer as a mask to form the groove. The groove includes a first groove region and a second groove region that are interconnected. The first groove region extends along the first direction, and the second groove region extends along the second direction. The depth of the groove ranges from 400nm to 1000nm.

14. The method for fabricating a semiconductor structure according to claim 13, characterized in that, The first connector and storage structure are formed within the groove, including: Multiple sacrificial layers are formed in the groove; Remove a portion of the sacrificial layer to form a first filling space; A support column is formed within the first filling space; Remove a portion of the sacrificial layer to form a second filling space; Multiple step structures are formed in the second filling space located in the first groove area. The multiple step structures are stacked along the third direction and distributed in a stepped manner. The multiple step structures constitute the first connector. Each step structure extends along the first direction. Multiple capacitors are formed in the second filling space located in the second trench area, stacked along a third direction. The multiple capacitors constitute part of the storage structure, and each step structure is electrically connected to its corresponding capacitor. The first direction, the second direction, and the third direction are perpendicular to each other.

15. The method for fabricating a semiconductor structure according to claim 14, characterized in that, The first connector and storage structure are formed within the groove, and the method further includes: Multiple conductive pillars are formed in the first groove area, and the multiple conductive pillars are spaced apart along a first direction. The conductive pillars are in contact with and electrically connected to the corresponding stepped structure. Multiple spaced bit line connection structures are formed on the conductive post, each bit line connection structure extends along the second direction, the top end of the conductive post is electrically connected to the bit line connection structure, and the bit line connection structure is electrically connected to the corresponding first contact structure.

16. The method for fabricating a semiconductor structure according to claim 14, characterized in that, The first connector and storage structure are formed within the groove, and the method further includes: A gate conductive structure is formed in the second trench region, and the gate conductive structure is electrically connected to a plurality of capacitors stacked along the third direction; A word line connection structure is formed on the gate conductive structure, the word line connection structure extends along the second direction, the top end of the gate conductive structure is electrically connected to the word line connection structure, and the word line connection structure is electrically connected to the corresponding first contact structure.

17. The method for fabricating a semiconductor structure according to claim 14, characterized in that, The substrate has a third region, and the second region and the third region are located on opposite sides of the first region; The method further includes: forming a second connector extending in a first direction in the groove, the second connector being electrically connected to one end of the storage structure opposite to the first connector; A second circuit layer and a second contact structure are formed on the substrate located in the third region, the second contact structure extending along the third direction, and the second connector is electrically connected to the second circuit layer through the second contact structure.

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