Memory system, three-dimensional memory and method of manufacturing the same, and photolithographic mask

Abstract

The application provides a three-dimensional memory, a manufacturing method thereof, and a photolithography mask. The application also provides a storage system. The manufacturing method of the three-dimensional memory comprises: forming a stack structure comprising a plurality of channel structures on a substrate; forming a mask layer on a side of the stack structure away from the substrate; forming a gate slit opening comprising a trench on the mask layer via a photolithography mask, wherein the trench comprises a strip-shaped main body and two protruding portions protruding from the strip-shaped main body and arranged along a width direction of the trench; and etching the stack structure via the gate slit opening.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, and more specifically, to memory systems, three-dimensional memories and methods for manufacturing the same, and photomasks. Background Technology

[0002] As the number of stacked layers in a 3D memory structure increases, the structure becomes increasingly unstable, leading to distortion of deep trenches. Within a single memory block, an H-Cut is typically introduced to break the central Gate Line Slit (GLS) into multiple smaller segments to ensure structural stability. However, due to factors such as manufacturing processes, the shape and size of the GLS segments at the H-Cut are difficult to guarantee, potentially causing slower programming speeds for some word lines or short circuits and leakage in some word lines, thus affecting device performance. Summary of the Invention

[0003] This application provides a storage system, a three-dimensional memory, a method for manufacturing the same, and a photomask that can at least partially solve the aforementioned problems existing in the related art.

[0004] According to one aspect, this application provides a method for manufacturing a three-dimensional memory, the method comprising: forming a stacked structure including a plurality of channel structures on a substrate; forming a mask layer on a side of the stacked structure away from the substrate; forming a gate slot opening including trenches on the mask layer via a photomask, wherein the trench includes a strip-shaped body and two protrusions, the two protrusions extending from the strip-shaped body and arranged along the width direction of the trench; and etching the stacked structure via the gate slot opening.

[0005] In one embodiment, along the width direction of the groove, the two protrusions protrude from the two apex corners of the corresponding end sides of the strip-shaped body.

[0006] In one embodiment, the groove has a minimum width at the junction of the strip body and the two protrusions.

[0007] In one embodiment, the two protrusions are partially adjacent to each other along the width direction of the groove.

[0008] In one embodiment, the mask layer includes a photoresist layer, the photomask has a gate slit pattern, the gate slit pattern includes at least one pair of extended patterns, the at least one pair of extended patterns includes a first extended pattern and a second extended pattern, and wherein forming a gate slit opening including a trench on the mask layer via the photomask includes: correspondingly providing sub-resolution auxiliary lines at the periphery of adjacent ends of the first extended pattern and the second extended pattern; exposing the photoresist layer with a first light beam via the photomask; and forming the gate slit opening on the photoresist layer.

[0009] In one embodiment, the sub-resolution auxiliary lines include a first auxiliary line and a second auxiliary line, the first auxiliary line and the second auxiliary line having an "L" shape, forming a configuration around the end of the corresponding extended pattern.

[0010] In one embodiment, the first beam has a light intensity capable of exposing the sub-resolution auxiliary lines.

[0011] In one embodiment, the minimum width of the first and second extended graphics is located at the adjacent end (F) in a direction perpendicular to the extension direction of the first and second extended graphics.

[0012] In one embodiment, the mask layer includes a photoresist layer, and the photomask has a gate gap correction pattern. The gate gap correction pattern includes at least one pair of extended patterns, the at least one pair of extended patterns including a first extended pattern and a second extended pattern, and each of the adjacent ends of the first extended pattern and the second extended pattern has two protruding patterns. Forming a gate gap opening including a trench on the mask layer via the photomask includes: exposing the photoresist layer with a second light beam via the photomask; and forming the gate gap opening on the photoresist layer.

[0013] In one embodiment, each of the protruding shapes (T1'; T2') extends from the end (F) along the direction of extension of the extension shape and the width direction of the extension shape, respectively. The width direction of the extension shape is perpendicular to the direction of extension of the extension shape, and the two protruding shapes are spaced apart along the width direction of the extension shape.

[0014] In one embodiment, in the width direction of the extended pattern, the minimum width of the first extended pattern and the second extended pattern is located at the adjacent end (F).

[0015] In one embodiment, sub-resolution auxiliary lines are respectively provided on the periphery of the two protruding shapes, wherein each of the sub-resolution auxiliary lines includes a first auxiliary line and a second auxiliary line, the first auxiliary line and the second auxiliary line having an "L" shape, forming a structure around the end of the corresponding extended shape.

[0016] In one embodiment, the second beam has a light intensity lower than that capable of exposing the sub-resolution auxiliary lines.

[0017] According to another aspect, this application provides a photomask including a gate slit pattern, the gate slit pattern including at least a pair of extended patterns, the at least a pair of extended patterns including a first extended pattern and a second extended pattern, and sub-resolution auxiliary lines are respectively provided on the periphery of the adjacent ends of the first extended pattern and the second extended pattern.

[0018] In one embodiment, each of the adjacent ends of the first and second extended graphics has two protruding graphics, wherein each of the protruding graphics (T1'; T2') extends and protrudes from the end (F) along the direction of extension of the extended graphics and the width direction of the extended graphics, respectively. The width direction of the extended graphics is perpendicular to the direction of extension of the extended graphics, and the two protruding graphics are spaced apart along the width direction of the extended graphics. The sub-resolution auxiliary lines are respectively located on the periphery of the two protruding graphics.

[0019] In one embodiment, in the width direction of the extended pattern, the minimum width of the first extended pattern and the second extended pattern is located at the adjacent end (F).

[0020] In one embodiment, each of the sub-resolution auxiliary lines includes a first auxiliary line and a second auxiliary line, the first auxiliary line and the second auxiliary line having an "L" shape, forming a configuration around the end of the corresponding extended pattern.

[0021] According to another aspect, this application provides a three-dimensional memory comprising: a stacked structure including alternating gate layers and insulating layers; a channel structure extending through the stacked structure; and a gate line slot structure extending through the stacked structure along a first direction, the gate line slot structure being broken into a plurality of segments in the first direction; and at least one end of each of the segments being flattened in any plane parallel to the gate layer or the insulating layer.

[0022] In one embodiment, in the contour of at least one end of each of the segments, the included angle between the tangents of any two adjacent contours is less than 30°.

[0023] According to yet another aspect, this application also provides a storage system comprising: at least one three-dimensional memory as described above; and a controller electrically connected to at least one of the three-dimensional memories for controlling at least one of the three-dimensional memories.

[0024] According to the embodiments of this application, by forming a gate slot opening with an irregularly shaped end including two protrusions on the mask layer, and etching the stacked structure through the gate slot opening, the ends of each gate slot segment formed can have a flatter shape, which helps to avoid the formation of "large heads" or "sharp corners". Furthermore, the flatter shape of the ends of each gate slot segment structure can effectively reduce problems such as slower programming / erasing speeds for corresponding word lines caused by the fusion of "large heads" with adjacent channel structures, or leakage current in the common source and channel structures. Simultaneously, it can also effectively reduce problems such as short circuits and leakage current in adjacent word lines located at the bottom of the memory caused by "sharp corners", which is beneficial to improving the performance of the 3D memory. Attached Figure Description

[0025] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0026] Figure 1 This is a scanning electron microscope image showing the sharp point at the bottom of the stacked structure of the gate gap end in the three-dimensional memory manufacturing method according to the relevant technology.

[0027] Figure 2 This is a flowchart of a method for manufacturing a three-dimensional memory according to an exemplary embodiment of this application;

[0028] Figure 3A and Figure 3B These are, respectively, scanning electron microscope images and schematic diagrams of gate slot openings formed in a photoresist layer according to exemplary embodiments of this application;

[0029] Figure 4A and Figure 4B These are, respectively, scanning electron microscope images and schematic diagrams of the gate slit openings formed in the hard mask layer according to exemplary embodiments of this application;

[0030] Figure 5A and Figure 5B These are scanning electron microscope images and schematic diagrams of the grid gaps formed in the stacked structure according to exemplary embodiments of this application;

[0031] Figure 6A and Figure 6B These are scanning electron microscope images of the maximum CD and minimum CD of the end of the gate gap formed in the stacked structure according to an exemplary embodiment of this application;

[0032] Figure 7 This is a schematic diagram of different types of gate openings formed in a photoresist layer by two types of light with different intensities via a photomask according to an exemplary embodiment of this application;

[0033] Figure 8 This is a schematic diagram of forming a gate slot opening with irregular ends on a photoresist layer via a photomask with a gate slot correction pattern according to an exemplary embodiment of this application;

[0034] Figure 9 This is a schematic diagram of a storage system according to an exemplary embodiment of this application; and

[0035] Figure 10 This is a schematic diagram of a storage system according to another exemplary embodiment of this application. Detailed Implementation

[0036] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0037] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first insulating layer discussed herein may also be referred to as the second insulating layer, and the first filling material may also be referred to as the second filling material, and vice versa.

[0038] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0039] Furthermore, in this text, when describing a part as being "on" another part, such as "on," "above," and "above," the meaning should be interpreted in the broadest possible sense, such that "on" not only means "directly on" something, but also includes the meaning of "on" something with intermediate features or layers in between. Moreover, "above" or "above" does not absolutely mean being above something with respect to the direction of gravity, nor does it only mean "on" something or "above" something, but can also include the meaning of "on" something or "above" something without intermediate features or layers in between (i.e., directly on) something.

[0040] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0041] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0042] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0043] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0044] As the number of stacked layers in 3D memory structures increases, the stability of the structure deteriorates, easily leading to deep trench distortion. Within the same memory block, an H-Cut is typically introduced to break the central Gate Line Slit (GLS) into multiple smaller segments to ensure structural stability. However, due to factors such as manufacturing processes, the shape and size of the GLS ends at the H-Cut are difficult to guarantee. For example, the ends of the broken GLS are prone to developing "large heads." Because the CD (critical dimension) of these "large heads" is large, they are prone to contacting / merging with the external memory channel structure after subsequent processes such as W Recess, resulting in slower programming speeds at the corresponding word lines and affecting the storage performance of the 3D memory. In more severe cases, it may cause leakage current due to contact between the common source and the channel structure, leading to device failure. To reduce the CD of the "large heads," the CD near the break point of the GLS is usually reduced during design. However, this approach results in a "sharp corner" morphology at the end of the GLS at the H-Cut, located at the bottom of the stacked structure. Figure 1 As shown in the image. This situation can easily lead to incomplete tungsten etching in subsequent steps, leaving tungsten residue at sharp corners. This can cause leakage current at the connection between upper and lower word lines, affecting device performance.

[0045] To address the aforementioned problems, this application achieves the formation of gate slot openings with irregularly shaped ends in the photoresist layer after exposure and development. This reduces or eliminates the "sharp corners" at the H-Cut points of the gate slots formed by subsequent etching of the stacked structure, resulting in a nearly flattened morphology at the ends of the broken gate slots. The solution of this application facilitates the improvement or elimination of incomplete tungsten etching back caused by "sharp corners" during the subsequent formation of the common source electrode (ACS) in the gate slots. This, in turn, helps avoid leakage current between upper and lower word lines caused by residual tungsten, thereby improving the device performance of the 3D memory. The application will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0046] Figure 2 This is a flowchart illustrating a method for manufacturing a three-dimensional memory according to an exemplary embodiment of this application. Figure 2 As shown, the manufacturing method 1000 of the three-dimensional memory according to an exemplary embodiment of this application may include the following steps:

[0047] S1, a stacked structure including multiple channel structures is formed on the substrate;

[0048] S2, a mask layer is formed on the side of the stacked structure away from the substrate;

[0049] S3, forming a gate slot opening including a trench on a photomask layer, wherein the trench includes a strip-shaped body and two protrusions, the two protrusions extending from the strip-shaped body and arranged along the width direction of the trench; and

[0050] S4, the stacked structure is etched through the gate slot opening.

[0051] Next, we will combine Figures 3A to 8 The steps of method 1000 described above are described in detail.

[0052] According to step S1 of method 1000, a plurality of channel structures 110 are formed on a substrate (not shown) (see [reference]). Figure 6A The stacked structure 100 (see) Figure 6A ).

[0053] In this step, a substrate is first prepared, which can be used to support the device structure thereon. The substrate may include, for example, at least one of single-crystal silicon (Si), single-crystal germanium (Ge), III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. In one embodiment, the substrate is, for example, a doped single-crystal silicon substrate. The substrate may be a P-type substrate or an N-type substrate, and may further include N-wells and / or P-wells. In other embodiments, the substrate may also be a composite substrate. It is understood that the substrate can be prepared and selected according to actual needs, and this application does not specifically limit it.

[0054] Next, a stacked structure 100 may be formed on the substrate using a thin-film deposition process including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The stacked structure 100 may include multiple insulating layers and multiple gate sacrificial layers alternately stacked on the substrate. The insulating layers may be made of, for example, silicon oxide. The gate sacrificial layers may be made of, for example, silicon nitride. See also Figure 6A and Figure 6B This is a partial top view of the stacked structure 100 cut along the plane containing one of the stacks.

[0055] Figure 6A and Figure 6BThe channel structure 110 shown can serve as a string of memory cells in a three-dimensional memory. Its formation method may include: first, forming a plurality of channel holes in the stacked structure 100 using, for example, a dry / wet etching process. These channel holes may penetrate the stacked structure 100 and extend into the substrate in a direction perpendicular or substantially perpendicular to the substrate. Then, a memory dielectric layer and a channel layer are sequentially formed on the inner walls of the formed channel holes. In this step, a charge barrier layer, a charge trapping layer, a tunneling layer, and the channel layer are sequentially deposited along the inner walls of the channel holes using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. The charge barrier layer, charge trapping layer, and tunneling layer may be referred to as the memory dielectric layer. The materials of the charge barrier layer, charge trapping layer, and tunneling layer may, for example, sequentially include silicon oxide, silicon nitride, and silicon oxide to form an "ONO" (Oxide-Nitride-Oxide) structure. The material of the channel layer may, for example, include polysilicon.

[0056] According to step S2 in method 1000, a mask layer is formed on the side of the stacked structure 100 away from the substrate.

[0057] In one embodiment, the mask layer formed on the side of the stacked structure 100 away from the substrate can be, for example, a photoresist layer. In one embodiment, before forming the photoresist layer on the side of the stacked structure 100 away from the substrate, a hard mask layer 300 can be formed on the stacked structure first. Figure 4A ), Figure 4A The image shown is a scanning electron microscope (SEM) image of the gate slot opening 300-1 formed in the hard mask layer 300. The hard mask layer 300 may include, for example, carbon, silicon nitride, silicon oxide, or combinations thereof. In this embodiment, an amorphous carbon hard mask layer is used. Then, a photoresist layer 400 can be formed on the formed hard mask layer 300 using, for example, spin coating. Figure 3A Spin coating can be divided into static coating methods or dynamic coating methods. Static coating methods involve dripping adhesive, accelerating rotation, spinning adhesive, and evaporating solvent while the silicon wafer is stationary. Dynamic coating methods involve dripping adhesive, accelerating rotation, spinning adhesive, and evaporating solvent while the silicon wafer is rotating at a low speed.

[0058] According to step S3 of method 1000, a photomask 200 is disposed on the side of the formed photoresist layer 400 away from the substrate, such as... Figure 7 The diagram shows a partial schematic of a photomask 200 according to one embodiment. A gate slot opening, including, for example, an elongated trench, is formed on the mask layer via the photomask 200. The elongated trench includes, for example, an elongated body M and irregularly shaped ends. The irregularly shaped ends include two protrusions T1 and T2 extending from the elongated body M and arranged along the width direction of the trench. See [reference needed]. Figure 3A and 3B .

[0059] Figure 3A This is a scanning electron microscope image of a gate slot opening 400-1 formed in a photoresist layer 400 according to an exemplary embodiment of this application. Figure 3B yes Figure 3A A partial schematic diagram of the elongated groove including the irregularly shaped end of the central grid slot opening 400-1.

[0060] like Figure 3B As shown, in an exemplary embodiment, along the width direction of the elongated groove (i.e., the Y direction in the figure), two protrusions T1 and T2 may protrude from the two apex angles D1 and D2 of the elongated body M at that end, respectively. In an exemplary embodiment, the two protrusions T1 and T2 may be symmetrical or approximately symmetrical about the centerline C1 of the elongated groove along its length direction. In an exemplary embodiment, the maximum distance W2 between the outer contours of the two protrusions T1 and T2 in the width direction of the elongated groove may be greater than the minimum width of the elongated body M in the width direction. The minimum width may be located at the connection between the elongated body M and the irregular end, that is, the end E of the elongated body M may have the minimum width W1. Therefore, it can be understood that W2 is greater than W1. In an exemplary embodiment, along the width direction of the elongated groove, the two protrusions T1 and T2 may be partially adjacent to each other, such as... Figure 3B In this case, the two protrusions T1 and T2 can be considered to be adjacent to each other at the location of the center line C1.

[0061] In an exemplary embodiment, two protrusions T1 and T2 may protrude from the end E of the main body M of the elongated groove along the length direction of the elongated groove. Figure 3B (As shown by the dashed line in the middle), the maximum dimension L1 of the outlines of the two protrusions T1 and T2 in the length direction (i.e., the X direction in the figure) of the elongated groove can be less than the minimum width W1 of the elongated body M in its width direction. In an exemplary embodiment, the maximum dimension L1 of the outlines of the two protrusions T1 and T2 in the length direction (i.e., the X direction in the figure) of the elongated groove can, for example, be approximately equal to half the minimum width W1 of the elongated body M in its width direction.

[0062] Based on the foregoing, it can be understood that the end E of the elongated body M has the minimum width in the width direction, which helps to avoid the gate gap formed by the etched stacked structure from having a "large head" at the end E. On this basis, forming an irregular end, for example including two protrusions T1 and T2, at the end E with the minimum width can help to avoid the gate gap formed by the etched stacked structure from having a "sharp corner" at the end E with the minimum width. Specifically, along the width direction of the elongated body M, two protrusions T1 and T2 protrude from the two apex corners D1 and D2 of the elongated body M at that end, respectively. The maximum distance W2 between the outer contours of the two protrusions T1 and T2 in the width direction is greater than the minimum width W1 of the elongated body M in its width direction. Furthermore, along the length direction of the elongated body M, the two protrusions T1 and T2 have appropriate lengths, for example, approximately equal to half the minimum width W1 of the elongated body M in its width direction. This allows for a certain modification of the shape and size at the end E with the minimum width. It can be considered that the local shape and size at the two apex corners of the end E are appropriately enlarged, thereby helping to avoid the formation of "sharp corners" at the end E with the minimum width due to the subsequent etching of the stacked structure.

[0063] In contrast, if the gate slot opening formed in the mask layer (e.g., photoresist layer) does not include the irregular ends as described above, i.e., it does not include protrusions T1 and T2, and in order to reduce the "big head" phenomenon at the ends of the segmented gate slots, the formed gate slot opening has a reduced critical dimension (width dimension) only at the end at H-Cut and within a length adjacent to the end. For example, the end of the gate slot opening at H-Cut has its minimum width dimension along the width direction. It is understood that etching the hard mask layer and the stacked structure through such gate slot openings with reduced end dimensions will also result in elongated trenches with reduced end dimensions in the opening formed in the hard mask layer and in the gate slots formed in the stacked structure. However, at the bottom of the stacked structure, due to the influence of the etching depth, the size reduction of the end dimension of the formed gate slot is more extreme, resulting in the "sharp corner" shape described above. According to the embodiments of this application, the gate slot opening formed on the photoresist layer has two protrusions T1 and T2 at the end of the elongated trench with a contracted dimension, which are referred to herein as irregular ends. Because of these irregular ends, the gate slot opening formed on the photoresist layer according to the embodiments of this application allows for etching of the hard mask layer and ultimately the stacked structure via the gate slot opening, ensuring that the ends of the gate slots located at each layer in the stacked structure have a relatively flat morphology at the H-Cut. Figure 6A A scanning electron microscope image of the gate slot joint with the largest critical dimension, located in the fifth layer at the top of the stacked structure, is shown. Figure 6BA scanning electron microscope image of the gate slot joint with the smallest critical size located at the bottom layer of the stacked structure is shown.

[0064] Depend on Figure 6A As can be seen, the critical dimension (width) of the gate slot end, which has the largest critical dimension in the fifth layer at the top of the stacked structure, does not significantly exceed the overall critical dimension (width) of the gate slot, and has a relatively ideal distance from the adjacent channel structure 110. This effectively avoids the problem of slower programming speed at the corresponding word line due to contact / fusion with the adjacent channel structure, as mentioned earlier. It also helps to avoid leakage current caused by contact between the common source electrode (formed in the gate slot in subsequent processes) and the channel structure. Furthermore, the end of the gate slot H-Cut, which has the largest critical dimension in the fifth layer at the top of the stacked structure, has a flattened morphology. Figure 6B As can be seen, the end of the gate slot H-Cut, which has the smallest critical size at the bottom layer of the stacked structure, also has a flat shape and does not produce a "sharp corner". This helps to avoid incomplete tungsten etching back and residual tungsten causing leakage current at the connection between the upper and lower word lines. In short, in the embodiments of this application, by forming a gate slot opening with the aforementioned irregular end on the mask layer (e.g., photoresist layer), and etching the stacked structure through the gate slot opening, it is beneficial to avoid the situation where the gate slot formed in the stacked structure produces a "large head" or a "sharp corner" at the end of H-Cut. This can effectively reduce problems such as affecting the programming / erasing speed of the channel structure, leakage current in the common source and channel structure, and leakage current at the connection between the lower and upper word lines, which is beneficial to improving the performance of the three-dimensional memory.

[0065] The following describes an exemplary implementation method for forming a gate slot opening with the aforementioned irregular end on a mask layer (e.g., a photoresist layer) according to this application.

[0066] According to one embodiment of this application, a photomask 200 is provided with a gate slit pattern, which includes at least one pair of extended patterns, including a first extended pattern 210-1 and a second extended pattern 210-2. Sub-resolution assist features (SRAFs) 220 are respectively provided around the periphery of the adjacent ends (F1 and F2) of the first extended pattern 210-1 and the second extended pattern 210-2 on the photomask. In one embodiment, the sub-resolution assist features 220 provided at the ends of each extended pattern may include the first assist feature 220-1 and the second assist feature 220-2, which may be symmetrically or approximately symmetrically arranged along the centerline or approximately the centerline of the length direction of the extended pattern (210-1 or 210-2). See [reference needed]. Figure 7A schematic diagram showing the arrangement of the first extended pattern 210-1, the second extended pattern 210-2, and the sub-resolution auxiliary lines 220 on the photomask 200. Then, the photoresist layer is exposed through the photomask 200 with a first light beam, followed by a development operation to form the gate slot openings on the photoresist layer. See [reference needed]. Figure 7 The process flow is indicated by the dashed box A. A1 is a schematic diagram of simulated exposure, and A2 is a schematic diagram showing the formation of gate openings in the photoresist layer.

[0067] like Figure 7 As shown, in an exemplary embodiment, the SRAF (Structured Reflective Aspects) provided on the photomask 200 can be L-shaped auxiliary lines. The L-shaped auxiliary lines can be arranged symmetrically or approximately symmetrically along the center line of the elongated pattern on the photomask, and are located at the periphery of the two apex corners of the respective ends of the elongated patterns (first extended pattern 210-1, second extended pattern 210-2). In an exemplary embodiment, the minimum width of the first extended pattern 210-1 and the second extended pattern 210-2 on the photomask along the width direction (perpendicular to their extension direction) can be located at their adjacent ends (F1 and F2). Figure 7 In the exemplary embodiment shown by the dashed box A, a first light beam is used to expose the photoresist layer via a photomask 200. This first light beam has, for example, an intensity capable of exposing the provided SRAF. That is, in this case, the sub-resolution auxiliary line 220 not only serves an optical correction function, but more importantly, it can be exposed onto the photoresist layer to form a pattern, thereby forming the gate slot opening with irregularly shaped ends on the photoresist layer. In one embodiment, for example, the critical dimension (width) of the gate slot is 120 nm, and a light intensity greater than 33 mJ / cm² can be used. 2 The first beam of light exposes the photoresist layer through a photomask 200 (including a strip pattern and an SRAF pattern), and then a pattern can be formed on the photoresist layer by development. Figure 7 As shown in Figure A2, the gate slot opening with an irregularly shaped end, as described above, allows for further etching of the stacked structure via this opening. This results in a gate slot with a flatter shape at the H-Cut point, reducing the likelihood of "large heads" or "sharp corners." This is beneficial for improving the performance of 3D memory.

[0068] exist Figure 7In the exemplary embodiment shown in the dashed box B, the photoresist layer is exposed via a second light beam through a photomask 200. This second light beam has a normal light intensity, for example, insufficient to expose the sub-resolution auxiliary lines 220 disposed on the photomask 200. That is, in this case, the sub-resolution auxiliary lines 220 only serve an optical correction function and are not exposed onto the photoresist layer to form a pattern. In one embodiment, for example, the critical dimension (width) of the gate gap is 120 nm, and the second light beam used has, for example, an intensity below 30 mJ / cm². 2 Ordinary beams of light with light intensity, via Figure 7 The photomask 200 shown (including the strip pattern and the SRAF pattern) can form patterns on the photoresist layer such as... Figure 7 The grille slot opening shown in B2, which lacks the irregularly shaped ends, clearly does not have the two protrusions with irregularly shaped ends as described above. Instead, it has one protrusion at the center or approximately the center along the width direction of the strip. It can be understood that, via... Figure 7 The gate slot opening shown in B2 further etches the stacked structure, making it easier for the gate slot to produce a "sharp corner" shape as described above, which is not conducive to ensuring the performance of the three-dimensional memory.

[0069] It is understood that the key dimensions of the gate gap and the light intensity of the light beam used in the above embodiments are only examples. In other embodiments, the key dimensions of the gate gap may be different from the above values, and the light beam used may be selected with a corresponding light intensity value according to the size of the key dimensions of the gate gap in the specific embodiment, so as to achieve the exposure of SRAF and enable SRAF to form a pattern on the photoresist layer; or only achieve the optical correction function of SRAF without exposing SRAF to the photoresist layer, which can be determined according to the specific implementation.

[0070] See Figure 8 According to another embodiment of this application, the photomask 200 may include a gate gap correction pattern. Specifically, the gate gap correction pattern may include at least a pair of extended patterns, combined with... Figure 7 The at least one pair of extended patterns includes, for example, a first extended pattern 210-1 and a second extended pattern 210-2. Each adjacent end of the first extended pattern 210-1 and the second extended pattern 210-2 may have two protruding patterns T1' and T2'. Then, a photoresist layer is exposed via a second beam through the photomask 200 including the gate gap correction pattern, and a gate gap opening with irregular ends is formed on the photoresist layer, such as... Figure 8 As shown in A4.

[0071] The protruding figures (T1' and T2') at adjacent ends of each pair of extended figures (strip figures) may extend and protrude from the end (F1 or F2) of the corresponding extended figure, respectively, along the extension direction (or length direction) and in a direction perpendicular to the extension direction (or width direction). See also Figure 8 The first extended pattern 210-1 shown in the figure has an extension direction (or length direction) that is the X direction shown in the figure, and a direction perpendicular to the extension direction (or width direction) that is the Y direction shown in the figure. Furthermore, each pair of protruding patterns (T1' and T2') corresponding to each extended pattern may have a gap along the width direction of the extended pattern. Figure 8 Only one extended shape 210-1 is schematically shown. In one embodiment, along the width direction of the extended shape 210-1 (i.e., the Y direction shown in the figure), two protruding shapes T1' and T2' may protrude from the two apex corners of the end F1, respectively. Along the length direction of the extended shape 210-1 (i.e., the X direction shown in the figure), two protruding shapes T1' and T2' may protrude from the end F1, respectively. Figure 8 As shown, in the width direction of the extension pattern 210-1, the distance between the outer contours of the two protruding patterns T1' and T2' that are far apart from each other is greater than the minimum width dimension of the extension pattern 210-1. The end F1 of the extension pattern 210-1 may have its minimum width in the width direction. Furthermore, in the length direction of the extension pattern 210-1, the length of the two protruding patterns T1' and T2' may be less than the minimum width dimension of the extension pattern 210-1, for example, approximately equal to or less than half of the minimum width dimension of the extension pattern 210-1. In one embodiment, the two protruding patterns T1' and T2' may be symmetrical or approximately symmetrical about the centerline of the extension pattern 210-1 in the length direction.

[0072] As mentioned above, in order to reduce the critical size of the "big head" generated at the grid slot joint, the minimum width of each pair of extended patterns along the width direction (perpendicular to its extension direction) can be set to be located at the adjacent ends of the two extended patterns (F1 and F2).

[0073] In one embodiment, SRAFs (Self-Range Apparatus) are symmetrically arranged on the photomask 200 along the centerline of the elongated pattern, located on the periphery of the two protruding patterns T1' and T2'. The arrangement of the SRAFs serves as Optical Proximity Correction (OPC). In one embodiment, the arranged SRAFs have an L-shape. In one embodiment, the second beam may have a light intensity lower than that required to expose the SRAFs. The photoresist layer is exposed using the second beam through a photomask with a gate slit correction pattern, and then a gate slit opening with irregularly shaped ends can be formed on the photoresist layer by development, such as... Figure 8 As shown in A4. Figure 8 Figure A3 shows a simulation diagram of the exposure of the photoresist layer by the second light beam through the gate gap correction pattern, obtained through simulation. As can be seen from Figures A3 and A4, by setting a gate gap correction pattern including the shown protruding patterns T1' and T2' on the photomask 200, and setting, for example, L-shaped auxiliary lines SRAF around the protruding patterns T1' and T2', the photoresist layer is exposed with a light beam of normal intensity, i.e., a light beam with an intensity lower than that sufficient to expose the SRAF. Then, through development, a gate gap opening with irregularly shaped ends can be formed on the photoresist layer. In conjunction with the foregoing, continuing to etch the stacked structure through this gate gap opening with irregularly shaped ends allows the formed gate gap (and the gate gap structure subsequently formed in the gate gap) to have a flatter shape at the H-Cut, which helps avoid the generation of "large heads" or "sharp corners," thus ensuring the performance of the 3D memory.

[0074] Those skilled in the art will understand that the above-described method for forming a gate slot opening with the irregular end on a photoresist layer is merely exemplary and not limiting; other methods may also be used to achieve the same result.

[0075] According to step S4 of method 1000, the hard mask layer and the stacked structure are etched through the gate slot opening with irregular ends formed.

[0076] See Figures 4A to 5B ,in, Figure 4A and Figure 4B They are like the sutra Figure 3A The image shown is a scanning electron microscope image and schematic diagram of the gate slot opening 400-1 formed on the photoresist layer 400 by etching the hard mask layer 300. Figure 5A and Figure 5B They are formed on the hard mask layer 300, such as Figure 4AThe image shows a scanning electron microscope (SEM) image of the gate slot 100-1 formed in the stacked structure 100 after further etching of the gate slot opening 300-1, and a schematic diagram of the end structure of the formed gate slot 100-1. In one embodiment, plasma etching may be used to etch the hard mask layer and the stacked structure, for example. It is understood that in other embodiments, other different methods may be used to etch the hard mask layer and the stacked structure, and this application is not limited thereto.

[0077] Another aspect of this application provides a photomask 200, which can be applied to any of the related embodiments or three-dimensional memory fabrication methods described above.

[0078] In one embodiment, the gate slit pattern on the photomask 200 includes at least one pair of extended patterns, such as a first extended pattern 210-1 and a second extended pattern 210-2. Sub-resolution auxiliary lines 220 are respectively provided on the periphery of adjacent ends of the first extended pattern 210-1 and the second extended pattern 210-2. Figure 7 As shown. In one embodiment, for example, the photoresist layer can be exposed via the photomask 200 using a light beam capable of exposing sub-resolution auxiliary lines 220, followed by development to form a gate slot opening with the irregularly shaped ends as described above on the photoresist layer. That is, in this case, the sub-resolution auxiliary lines 220 not only serve an optical correction function, but more importantly, the sub-resolution auxiliary lines 220 can be exposed onto the photoresist layer to form a pattern, thereby forming the gate slot opening with the irregularly shaped ends on the photoresist layer. The formation of this gate slot opening with irregularly shaped ends facilitates subsequent etching of the stacked structure to obtain a gate slot with a flattened morphology at the H-Cut end, which is beneficial for improving the performance of the three-dimensional memory.

[0079] In one embodiment, the adjacent ends of the first extended pattern 210-1 and the second extended pattern 210-2 may each have two protruding patterns T1' and T2', wherein each protruding pattern (T1' and T2') may extend from the corresponding end (F1 or F2) along the length direction of the extended pattern and the width direction of the extended pattern (the direction perpendicular to the length direction), respectively. The two protruding patterns (T1' and T2') at the corresponding ends (e.g., F1 or F2) of each extended pattern may be spaced apart along the width direction. The sub-resolution auxiliary lines 220 may be respectively located on the periphery of each protruding pattern. In one embodiment, for example, the photoresist layer may be exposed via the photomask 200 using a light beam with an intensity lower than that capable of exposing the sub-resolution auxiliary lines 220, and then developed to form a gate slot opening with the irregular ends as described above on the photoresist layer. That is, in this case, the sub-resolution auxiliary lines 220 only serve an optical correction function and are not exposed on the photoresist layer to form a pattern. Forming gate slot openings with irregular ends on the photoresist layer can facilitate subsequent etching of the stacked structure to obtain gate slots with flattened ends at the H-Cut, which is beneficial to improving the performance of three-dimensional memory.

[0080] In one implementation, see Figure 7 or Figure 8 Each pair of extended graphics, such as the first extended graphic 210-1 and the second extended graphic 210-2, may have their respective minimum widths located at their adjacent ends (F1 and F2) along their width direction.

[0081] In one embodiment, the sub-resolution auxiliary lines 220 located at the respective ends of each extended pattern may include a first auxiliary line 220-1 and a second auxiliary line 220-2. The first auxiliary line 220-1 and the second auxiliary line 220-2 may have an "L" shape, forming a structure around the respective ends of each extended pattern.

[0082] Furthermore, it is understood that the photomask according to the embodiments of this application may also have other specific features, which can be learned from the detailed description of the method 1000 for preparing a three-dimensional memory above, and will not be repeated here for the sake of brevity.

[0083] Another aspect of this application provides a three-dimensional memory. This three-dimensional memory can be manufactured according to at least a portion of the three-dimensional memory manufacturing method provided in this application. The three-dimensional memory according to this application may include a stacked structure 100 having alternating gate layers and insulating layers, and a channel structure 110 penetrating the stacked structure 100, and a channel structure 110 penetrating the stacked structure 100 and along a first direction (e.g., Figure 6A or Figure 6BThe gate line slot structure 120 extends in the X direction (as shown in the diagram). The gate line slot structure 120 can be broken into multiple segments in its extending direction. In any plane parallel to the gate layer or insulating layer, at least one end of each segment of the gate line slot structure can have a relatively flat shape. For example, according to one embodiment, in the profile of at least one end of each segment of the gate line slot structure, the included angle between the tangents of any two adjacent segments is less than 30°.

[0084] It is understood that further features of the three-dimensional memory according to the embodiments of this application can also be learned from the detailed description of the method 1000 for preparing the three-dimensional memory above, and will not be repeated here.

[0085] In summary, this application achieves gate gap correction development with irregularly shaped ends in the photoresist layer after exposure and development, thereby reducing or eliminating the generation of "sharp corners" at the junctions of gate gaps subsequently formed in the stacked structure, making the morphology at the gate gap junctions nearly flat. This helps to improve or eliminate the problem of incomplete tungsten etch-back caused by "sharp corners" during the subsequent formation of the common source electrode (ACS) in the gate gap, and thus helps to avoid leakage current between upper and lower word lines caused by residual tungsten metal. Furthermore, according to the embodiments of this application, it helps to reduce or eliminate the generation of "large head" defects at the junctions of gate gaps, thereby reducing or eliminating the adverse effects of the common source electrode formed in the gate gap on the adjacent channel structure, eliminating the possibility of leakage current caused by the contact between the common source electrode and the channel structure, and improving the device performance of the three-dimensional memory.

[0086] In another aspect, this application also provides a storage system. Figure 9 and Figure 10 These are schematic diagrams of storage systems 2000a and 2000b according to embodiments of this application. Figure 9 and Figure 10 As shown, storage system 2000a or 2000b may include at least one three-dimensional memory 2100 and controller 2200, wherein the three-dimensional memory 2100 may be a three-dimensional memory provided according to any of the embodiments described above in this application, and may accordingly include the structure described according to any of the exemplary embodiments described above in this application, which will not be repeated here.

[0087] The controller 2200 can be electrically connected to and control the three-dimensional memory 2100 via, for example, a channel (not shown), and the three-dimensional memory 2100 can perform operations based on the control of the controller 2200. Exemplarily, the three-dimensional memory 2100 can receive commands and addresses from the controller 2200 via, for example, a channel and access a region of a channel structure in response to the address. In other words, the three-dimensional memory 2100 can perform internal operations corresponding to commands on a region selected by an address.

[0088] In some examples, the controller 2200 and one or more three-dimensional memories 2100 can be integrated into various types of storage devices; in other words, storage systems 2000a and 2000b can be implemented and packaged into different types of final electronic products. Figure 9 In one example shown, the controller 2200 and a single three-dimensional memory 2100 may be integrated into a memory card-based storage system 2200a. The memory card may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a universal flash memory card (UFS), etc. The memory card-based storage system 2200a may also include a memory card connector 2300a that couples it to a host (not shown).

[0089] In such Figure 10 In another example shown, the controller 2200 and multiple three-dimensional memories 2100 may be integrated into a storage system 2000b, such as a solid-state drive (SSD). The solid-state drive (SSD) may also include an SSD connector 2300b that couples it to the host.

[0090] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for manufacturing a three-dimensional memory, characterized in that, The method includes: A multilayer structure including multiple channel structures is formed on a substrate; A mask layer is formed on the side of the stacked structure away from the substrate; A gate slot opening, including a trench, is formed on the mask layer using a photolithography mask. The trench includes a strip-shaped body and two protrusions extending from the strip-shaped body and arranged along the width direction of the trench. The stacked structure is etched through the gate slot opening; The photomask has a gate slit pattern, which includes at least one pair of extended patterns. The at least one pair of extended patterns includes a first extended pattern and a second extended pattern. The adjacent ends of the first extended pattern and the second extended pattern each have two protruding patterns. Sub-resolution auxiliary lines are respectively provided around the adjacent ends of the first extended pattern and the second extended pattern. Each of the protruding shapes (T1'; T2') extends from the end (F) along the direction of extension of the extension shape and the width direction of the extension shape, respectively. The width direction of the extension shape is perpendicular to the direction of extension of the extension shape, and the two protruding shapes are spaced apart along the width direction of the extension shape. The sub-resolution auxiliary lines are respectively located on the periphery of the two protruding shapes.

2. The method according to claim 1, wherein, Along the width direction of the groove, the two protruding portions protrude from the two apex corners of the corresponding end sides of the strip-shaped body.

3. The method according to claim 1, wherein, The groove has a minimum width at the junction of the strip-shaped body and the two protrusions.

4. The method according to claim 1, wherein, Along the width direction of the groove, the two protrusions are partially adjacent to each other.

5. The method according to any one of claims 1-4, wherein, The mask layer includes a photoresist layer. The process of forming a gate slot opening, including a trench, on the mask layer via the photolithographic mask includes: The photoresist layer is exposed by a first light beam through the photomask; and The gate slot opening is formed on the photoresist layer.

6. The method according to claim 5, wherein, The sub-resolution auxiliary lines include a first auxiliary line and a second auxiliary line, the first auxiliary line and the second auxiliary line having an "L" shape, forming a structure around the end of the corresponding extended pattern.

7. The method according to claim 5, wherein, The first beam has an intensity capable of exposing the sub-resolution auxiliary lines.

8. The method according to claim 5, wherein, In a direction perpendicular to the extension direction of the first and second extended shapes, the minimum width of the first and second extended shapes is located at the adjacent ends (F).

9. The method according to claim 1, wherein, In the width direction of the extended pattern, the minimum width of the first extended pattern and the second extended pattern is located at the adjacent end (F).

10. A photomask, comprising a gate slit pattern, the gate slit pattern comprising at least a pair of extended patterns, the at least a pair of extended patterns comprising a first extended pattern and a second extended pattern, characterized in that, Sub-resolution auxiliary lines are respectively provided on the periphery of the adjacent ends of the first extended shape and the second extended shape. Both the first and second extended shapes have two protruding shapes at their adjacent ends. Each of the protruding shapes (T1'; T2') extends from the end (F) along the direction of extension of the extended shape and along the width direction of the extended shape, respectively. The width direction of the extended shape is perpendicular to the direction of extension of the extended shape, and the two protruding shapes are spaced apart along the width direction of the extended shape. The sub-resolution auxiliary lines are respectively located on the periphery of the two protruding shapes.

11. The photomask according to claim 10, wherein, In the width direction of the extended pattern, the minimum width of the first extended pattern and the second extended pattern is located at the adjacent end (F).

12. The photomask according to any one of claims 10-11, wherein, Each of the sub-resolution auxiliary lines includes a first auxiliary line and a second auxiliary line, the first auxiliary line and the second auxiliary line having an "L" shape, forming a structure around the end of the corresponding extended pattern.

13. A three-dimensional memory manufactured using the manufacturing method of a three-dimensional memory as described in any one of claims 1-9, characterized in that, include: A stacked structure, comprising alternating gate layers and insulating layers; A channel structure that penetrates the stacked structure; as well as A grid line slot structure penetrates the stacked structure and extends along a first direction, wherein the grid line slot structure is broken into multiple segments in the first direction; In any plane parallel to the gate layer or the insulating layer, at least one end of each segment is flattened.

14. The three-dimensional memory according to claim 13, wherein, In the profile of at least one end of each of the segments, the included angle between the tangents of any two adjacent profiles is less than 30°.

15. A storage system, characterized in that, include: At least one three-dimensional memory as described in claim 13 or 14; as well as A controller, electrically connected to at least one of the three-dimensional memories, is used to control at least one of the three-dimensional memories.

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