Semiconductor device and method of manufacturing the same

Abstract

Embodiments provide a semiconductor device in which a semiconductor layer can be appropriately formed in an opening portion and a method for manufacturing the same. According to one embodiment, a semiconductor device includes a first stacked film including a plurality of first electrode layers separated from each other, an insulating layer provided over the first stacked film, and a second stacked film provided over the insulating layer and including a plurality of second electrode layers separated from each other. The device also includes a columnar portion including a first insulating film, a charge storage layer, a second insulating film, and a semiconductor layer provided in this order in the first stacked film, the insulating layer, and the second stacked film, and extending in a first direction from the first stacked film toward the second stacked film. The columnar portion in the insulating layer includes a first portion having a first width in a second direction intersecting the first direction, and a second portion provided at a position higher than the first portion and having a second width larger than the first width in the second direction and larger than a width of the columnar portion in the second stacked film in the second direction.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2021-32083 (filed on March 1, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to semiconductor devices and methods for manufacturing the same. Background Technology

[0004] When a memory hole is formed that connects the lower, intermediate, and upper layers of the stacked film and a channel semiconductor layer is formed within the memory hole, defects such as the channel semiconductor layer being blocked within the intermediate film may occur. Summary of the Invention

[0005] The embodiments provide a semiconductor device and a method for manufacturing the same, which are capable of forming a semiconductor layer appropriately within an opening.

[0006] According to one embodiment, a semiconductor device includes: a first laminated film comprising a plurality of first electrode layers spaced apart from each other; an insulating layer disposed on the first laminated film; and a second laminated film disposed on the insulating layer, comprising a plurality of second electrode layers spaced apart from each other. The device further includes a columnar portion comprising a first insulating film, a charge storage layer, a second insulating film, and a semiconductor layer sequentially disposed within the first laminated film, the insulating layer, and the second laminated film, and extending along a first direction from the first laminated film toward the second laminated film. Furthermore, the columnar portion within the insulating layer includes a first portion and a second portion. The first portion has a first width in a second direction intersecting the first direction, and the second portion is disposed at a position higher than the first portion and has a second width in the second direction. The second width is larger than the first width and larger than the width of the columnar portion within the second laminated film in the second direction. Attached Figure Description

[0007] Figure 1 This is a perspective view showing the structure of the semiconductor device according to the first embodiment.

[0008] Figure 2 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0009] Figure 3 This is a cross-sectional view showing the structure of a semiconductor device according to a comparative example of the first embodiment.

[0010] Figure 4 (a)~ Figure 8(b) is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment.

[0011] Figure 9 (a)~ Figure 13 (b) is a cross-sectional view showing a method for manufacturing a semiconductor device according to a comparative example of the first embodiment.

[0012] Figure 14 This is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment.

[0013] Figure 15 This is a cross-sectional view showing the structure of a semiconductor device according to a modified example of the second embodiment.

[0014] Figure 16 This is a cross-sectional view showing the structure of a semiconductor device according to another variation of the second embodiment.

[0015] Figure 17 (a)~ Figure 20 (b) is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0016] Figure 21 This is a cross-sectional view showing the structure of a memory device 100, which is an example of a semiconductor device according to the first embodiment.

[0017] Figure 22 This is a circuit diagram showing the configuration of the storage device 100.

[0018] Figure 23 This is a block diagram showing the structure associated with the memory cell array 70. Detailed Implementation

[0019] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Figures 1 to 23 In this context, identical components are assigned the same symbols, and repetitive explanations are omitted.

[0020] (First Implementation)

[0021] Figure 1 This is a perspective view showing the structure of the semiconductor device according to the first embodiment. Figure 1 Semiconductor devices, for example, are three-dimensional NAND memories.

[0022] Figure 1 The semiconductor device includes a core insulating film 1, a channel semiconductor layer 2, a tunnel insulating film 3, a charge storage layer 4, a barrier insulating film 5, and an electrode layer 6. Furthermore, the barrier insulating film 5 includes an insulating film 5a and an insulating film 5b, and the electrode layer 6 includes a barrier metal layer 6a and an electrode material layer 6b. The insulating film 5a is an example of a first insulating film. The tunnel insulating film 3 is an example of a second insulating film.

[0023] exist Figure 1 In this process, multiple electrode layers and multiple insulating layers are alternately stacked on the substrate, and memory holes H are provided within these electrode layers and insulating layers. Figure 1 One of these electrode layers, electrode layer 6, is shown. These electrode layers function, for example, as word lines in NAND memory. Figure 1 The X and Y directions, which are parallel to and perpendicular to the surface of the substrate, and the Z direction, which is perpendicular to the surface of the substrate, are shown. In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may or may not be aligned with the direction of gravity.

[0024] A core insulating film 1, a channel semiconductor layer 2, a tunnel insulating film 3, a charge storage layer 4, and an insulating film 5a are formed within a memory aperture H, constituting a memory cell of a NAND flash memory. The insulating film 5a is formed on the surface of both the electrode layer and the insulating layer within the memory aperture H, and the charge storage layer 4 is formed on the surface of the insulating film 5a. The charge storage layer 4 is capable of storing charge between its outer and inner sides. The tunnel insulating film 3 is formed on the surface of the charge storage layer 4, and the channel semiconductor layer 2 is formed on the surface of the tunnel insulating film 3. The channel semiconductor layer 2 functions as the channel for the memory cell. The core insulating film 1 is formed within the channel semiconductor layer 2.

[0025] The insulating film 5a is, for example, a SiO2 film (silicon oxide film). The charge storage layer 4 is, for example, a SiN film (silicon nitride film). The tunnel insulating film 3 is, for example, a SiO2 film, a SiON film (silicon oxide nitride film), or a stacked film containing them. The channel semiconductor layer 2 is, for example, a polycrystalline silicon layer. The core insulating film 1 is, for example, a SiO2 film.

[0026] An insulating film 5b, a barrier metal layer 6a, and an electrode material layer 6b are formed between adjacent insulating layers, sequentially on the lower surface of the upper insulating layer, the upper surface of the lower insulating layer, and the side surface of the insulating film 5a. The insulating film 5b is, for example, a metallic insulating film such as an Al2O3 film (aluminum oxide film). The barrier metal layer 6a is, for example, a TiN film (titanium nitride film). The electrode material layer 6b is, for example, a W (tungsten) layer.

[0027] Figure 1 Also shown is a columnar portion CL disposed within a memory aperture H and extending along the Z direction. The columnar portion CL includes an insulating film 5a, a charge storage layer 4, a tunnel insulating film 3, a channel semiconductor layer 2, and a core insulating film 1 sequentially disposed within the memory aperture H. Figure 1As shown, the columnar portion CL has a columnar shape extending in the Z direction. Furthermore, the insulating film 5a, charge storage layer 4, tunnel insulating film 3, channel semiconductor layer 2, and core insulating film 1 within the columnar portion CL also have columnar shapes extending in the Z direction. The insulating film 5a, charge storage layer 4, tunnel insulating film 3, and channel semiconductor layer 2 have tubular shapes, with inner and outer peripheral surfaces. On the other hand, the core insulating film 1 has a non-tubular shape, but may also have a tubular shape. Further details regarding the columnar portion CL will be described later.

[0028] Figure 2 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment. Figure 2 The XZ section of the columnar portion CL, etc., is shown.

[0029] like Figure 2 As shown, the semiconductor device of this embodiment includes a substrate 11, a lower laminated film 12, an intermediate film 13, an upper laminated film 14, and a columnar portion CL. The lower laminated film 12 is an example of a first laminated film. The intermediate film 13 is an example of an insulating layer. The upper laminated film 14 is an example of a second laminated film.

[0030] Substrate 11 is the substrate described above. Substrate 11 is, for example, a semiconductor substrate such as a silicon substrate.

[0031] The lower laminate 12 includes a plurality of electrode layers 6 and a plurality of insulating layers 7 alternately disposed on the substrate 11. Thus, these electrode layers 6 are separated from each other by these insulating layers 7. As described above, each electrode layer 6 includes a barrier metal layer 6a and an electrode material layer 6b. Each insulating layer 7 is, for example, a SiO2 film. Furthermore, in... Figure 2 The illustration of the insulating film 5b mentioned above is omitted. The lower laminated film 12 is in Figure 2 It contains two electrode layers 6 and two insulating layers 7, but it may also contain three or more electrode layers 6 and three or more insulating layers 7. Furthermore, the lower laminate 12 may be formed directly on the substrate 11, or it may be formed on the substrate 11 with other films in between. The electrode layer 6 within the lower laminate 12 is an example of a first electrode layer.

[0032] The intermediate film 13 comprises insulating layers 13a, 13b, and 13c sequentially formed on the lower laminated film 12. Insulating layer 13a is, for example, a SiO2 film. Insulating layer 13b is, for example, a SiON film. Insulating layer 13c is, for example, a SiO2 film. Thus, in this embodiment, insulating layer 13b is formed of a material (SiON) different from the material (SiO2) of insulating layer 13a and insulating layer 13c. Insulating layer 13b is an example of a first insulating layer. Insulating layer 13a is an example of a second insulating layer. Insulating layer 13c is an example of a third insulating layer.

[0033] Furthermore, the insulating layer 13b of this embodiment may also have a density different from that of the insulating layer 13a and the insulating layer 13c. For example, the density of the insulating layer 13b may be higher than that of the insulating layers 13a and 13c. In this case, the material of the insulating layer 13b may be the same as, or different from, at least one of the materials of the insulating layers 13a and 13c. Further details of these insulating layers 13a, 13b, and 13c will be described later.

[0034] The upper laminated film 14 includes a plurality of electrode layers 6 and a plurality of insulating layers 7 alternately disposed on the intermediate film 13. Thus, these electrode layers 6 are separated from each other by these insulating layers 7. Similar to the lower laminated film 12, each electrode layer 6 in the upper laminated film 14 includes a barrier metal layer 6a and an electrode material layer 6b, and each insulating layer 7 in the upper laminated film 14 is, for example, a SiO2 film. Furthermore, in Figure 2 In the diagram above, the insulating film 5b is also omitted in the upper laminate 14. The upper laminate 14 is... Figure 2 It contains two electrode layers 6 and two insulating layers 7, but it may also contain three or more electrode layers 6 and three or more insulating layers 7. The electrode layer 6 in the lower laminate 14 is an example of a second electrode layer.

[0035] A columnar portion CL is disposed within the lower laminated film 12, the intermediate film 13, and the upper laminated film 14, extending along the lamination direction (Z direction) of the lower laminated film 12, the intermediate film 13, and the upper laminated film 14. The columnar portion CL includes a memory insulating film 8, a channel semiconductor layer 2, and a core insulating film 1, which are sequentially disposed within the lower laminated film 12, the intermediate film 13, and the upper laminated film 14. The memory insulating film 8 is a laminated film that sequentially includes the aforementioned insulating film 5a, the charge storage layer 4, and the tunnel insulating film 3. Thus, within the columnar portion CL, the insulating film 5a, the charge storage layer 4, the tunnel insulating film 3, the channel semiconductor layer 2, and the core insulating film 1 are sequentially formed on the side surfaces of the lower laminated film 12, the intermediate film 13, and the upper laminated film 14. In this embodiment, the columnar portion CL is disposed within a memory hole H that penetrates the lower laminated film 12, the intermediate film 13, and the upper laminated film 14. The above-mentioned stacking direction is an example of a first direction from the first stacked film toward the second stacked film.

[0036] The memory hole H includes a lower memory hole HL, a connecting hole HJ, and an upper memory hole HU. The connecting hole HJ is disposed between the lower memory hole HL and the upper memory hole HU, connecting the lower memory hole HL and the upper memory hole HU. In this embodiment, the connecting hole HJ protrudes radially relative to the side of the lower memory hole HL and the upper memory hole HU. The aforementioned radial direction is an example of a second direction intersecting the first direction.

[0037] Similarly, the columnar portion CL includes a lower columnar portion PL, a connecting portion PJ, and an upper columnar portion PU. The connecting portion PJ is disposed between the lower columnar portion PL and the upper columnar portion PU, connecting the lower columnar portion PL and the upper columnar portion PU. The lower columnar portion PL, the connecting portion PJ, and the upper columnar portion PU are respectively disposed within the lower memory hole HL, the connecting hole HJ, and the upper memory hole HU. Thus, in this embodiment, the connecting portion PJ protrudes radially relative to the side surface of the lower columnar portion PL and the upper columnar portion PU.

[0038] In this embodiment, the lower columnar portion PL is disposed within the lower laminated film 12, the junction portion PJ is disposed within the intermediate film 13, and the upper columnar portion PU is disposed within the upper laminated film 14. A portion of the lower columnar portion PL is also disposed within the intermediate film 13. The lower columnar portion PL and the upper columnar portion PU form NAND memory cells within the lower memory hole HL and the upper memory hole HU, respectively.

[0039] Figure 2 The width WL of the lower columnar portion PL in the X direction and the width WU of the upper columnar portion PU in the X direction are shown. Specifically, the width WL represents the width near the upper end of the lower columnar portion PL, and the width WU represents the width near the lower end of the upper columnar portion PL. The columnar portion CL of this embodiment has a generally circular cross-sectional shape in any XY section. Therefore, the widths WL and WU of this embodiment are the diameters of the lower columnar portion PL and the upper columnar portion PU, respectively. The same applies to the widths W1, W2, W3, Wa, and Wb, which will be described later.

[0040] The following continues to refer to Figure 2 Further details of the joint PJ in this embodiment will be explained.

[0041] The joint PJ includes a middle joint P1, an upper joint P2, and a lower joint P3. The upper joint P2 is positioned higher than the middle joint P1, and the lower joint P3 is positioned lower than the middle joint P1. In this embodiment, the upper joint P2 and the lower joint P3 protrude radially relative to the side of the middle joint P1. The middle joint P1, the upper joint P2, and the lower joint P3 are examples of the first part, the second part, and the third part, respectively.

[0042] In this embodiment, the intermediate joint P1 is disposed within the insulating layer 13b, the upper joint P2 is disposed within the insulating layer 13c, and the lower joint P3 is disposed within the insulating layer 13a. A portion of the upper joint P2 and a portion of the lower joint P3 are also disposed within the insulating layer 13b. In this embodiment, the lower surface of the memory insulating film 8 included in the upper joint P2 contacts the upper surface of the insulating layer 13b, and these lower and upper surfaces are inclined relative to the Z direction. Similarly, the upper surface of the memory insulating film 8 included in the lower joint P3 contacts the lower surface of the insulating layer 13b, and these upper and lower surfaces are inclined relative to the Z direction.

[0043] Figure 2 The widths W1 in the X direction of the intermediate joint P1, W2 in the X direction of the upper joint P2, and W3 in the X direction of the lower joint P3 are shown. Specifically, width W2 indicates the width near the upper end of the upper joint P2, and width W3 indicates the width near the lower end of the lower joint P3. As described above, in this embodiment, the joint PJ protrudes radially relative to the side surfaces of the lower columnar part PL and the upper columnar part PU. Therefore, the widths W1, W2, and W3 in this embodiment are larger than the widths WL and WU (W1, W2, W3 > WL, WU). Furthermore, in this embodiment, the upper joint P2 and the lower joint P3 protrude radially relative to the side surfaces of the intermediate joint P1. Therefore, the widths W2 and W3 in this embodiment are larger than the width W1 (W2, W3 > W1). Widths W1, W2, and W3 are examples of the first width, the second width, and the third width, respectively.

[0044] The difference between width W1 and widths W2 and W3 in this embodiment is, for example, due to the difference between the etching rate of insulating layer 13b and the etching rate of insulating layers 13c and 13a. Details of these etching rates will be described later.

[0045] Figure 2 The thickness DU in the Z direction of the upper joint P2, the thickness DL in the Z direction of the lower joint P3, and the film thickness T of the memory insulating film 8 are also shown. Specifically, the thickness DU indicates the thickness of the upper joint P2 above the side of the intermediate joint P1, and the thickness DL indicates the thickness of the lower joint P3 below the side of the intermediate joint P1. Furthermore, the film thickness T indicates the total film thickness of the insulating film 5a, the charge storage layer 4, and the tunnel insulating film 3. In this embodiment, the thicknesses DU and DL are set to be less than or equal to twice the film thickness T (DU, DL ≤ 2T).

[0046] In this embodiment, since widths W2 and W3 are larger than width W1, the sides of the joining hole HJ protrude radially near the upper and lower ends of the joining hole HJ. That is, the joining hole HJ has two protrusions near the upper and lower ends of the joining hole HJ. Thus, the memory insulating film 8 of the upper joining portion P2 and the memory insulating film 8 of the lower joining portion P3 enter these protrusions. Figure 2 As shown, two memory insulating films 8 are inserted into each protrusion. In this embodiment, since the thickness DU of the upper joint P2 and the thickness DL of the lower joint P3 are set to less than twice the film thickness T of the memory insulating film 8, each protrusion is filled with the memory insulating film 8. Thus, according to this embodiment, by setting the thickness DU (or thickness DL) to less than twice the film thickness T, the protrusions near the upper end (or lower end) of the joint hole HJ can be filled with the memory insulating film 8.

[0047] Figure 2 The width Wa of the outer peripheral surface of the channel semiconductor layer 2 and the width Wb of the inner peripheral surface of the channel semiconductor layer 2 are also shown. As described above, in this embodiment, the junction PJ protrudes radially relative to the side surface of the lower columnar portion PL and the upper columnar portion PU. Therefore, in this embodiment, the widths Wa and Wb are larger in the junction PJ than in the lower columnar portion PL and the upper columnar portion PU. The same applies to the width of the outer peripheral surface and the width of the inner peripheral surface of the memory insulating film 8.

[0048] However, in the intermediate joint P1, upper joint P2, and lower joint P3, the width of the outer peripheral surface of the memory insulating film 8 is greatest in the upper joint P2 or the lower joint P3. This is because protrusions exist near the upper and lower ends of the bonding hole HJ, and the memory insulating film 8 enters these protrusions. On the other hand, in the intermediate joint P1, upper joint P2, and lower joint P3, the width Wa of the outer peripheral surface and the width Wb of the inner peripheral surface of the channel semiconductor layer 2 are greatest in the intermediate joint P1. This is because the aforementioned protrusions are filled by the memory insulating film 8, and the channel semiconductor layer 2 does not enter these protrusions. Thus, according to this embodiment, the width Wa of the outer peripheral surface and the width Wb of the inner peripheral surface of the channel semiconductor layer 2 can be maximized in the intermediate joint P1.

[0049] Figure 3 This is a cross-sectional view showing the structure of a semiconductor device according to a comparative example of the first embodiment.

[0050] Figure 3 The semiconductor device of the comparative example shown has the same characteristics as... Figure 2a structure identical to that of the semiconductor device according to the first embodiment shown. However, the bonding portion PJ of the columnar portion CL in this comparative example has the same width (diameter) from the lower end to the upper end of the bonding portion PJ. In this comparative example, the width W1 of the central portion of the bonding portion PJ is the same as the width W2 near the upper end of the bonding portion PJ and the width W3 near the lower end of the bonding portion PJ (W1=W2=W3).

[0051] Figure 3 shows a corner portion K of the channel semiconductor layer 2 near the boundary between the bonding portion PJ and the upper columnar portion PU. Near this boundary, the width of the columnar portion CL changes greatly from the width WU to the width W1, so the shape of the channel semiconductor layer 2 is greatly bent near the corner portion K. As a result, the channel semiconductor layer 2 may be disconnected near the corner portion K. With the progress of integration of semiconductor devices, the film thickness of the channel semiconductor layer 2 becomes thinner, which makes such disconnection more likely to occur.

[0052] Such disconnection may also occur at the corner portion of the channel semiconductor layer 2 near the boundary between the bonding portion PJ and the lower columnar portion PL. However, since the width WU near the lower end of the upper columnar portion PU is often smaller than the width WL near the upper end of the lower columnar portion PL (WU<WL), such disconnection is more likely to occur at the corner portion K of the channel semiconductor layer 2 near the boundary between the bonding portion PJ and the upper columnar portion PU.

[0053] Figure 2 also shows the corner portion K of the channel semiconductor layer 2 near the boundary between the bonding portion PJ and the upper columnar portion PU. However, Figure 2 the bending of the channel semiconductor layer 2 at the corner portion K shown in is gentler than that of the channel semiconductor layer 2 at the corner portion K shown in Figure 3 . The reason is that since the memory insulating film 8 enters the above-mentioned convex portion of the bonding hole HJ, the widths Wa and Wb of the channel semiconductor layer 2 do not change greatly near the corner portion K. As a result, disconnection of the channel semiconductor layer 2 near the corner portion K can be suppressed. As described above, according to the present embodiment, by providing the intermediate bonding portion P1 and the upper bonding portion P2 in the bonding portion PJ, disconnection of the channel semiconductor layer 2 near the corner portion K can be suppressed. In addition, according to the present embodiment, by further providing the lower bonding portion P3 in the bonding portion PJ, disconnection of the channel semiconductor layer 2 at the corner portion near the boundary between the bonding portion PJ and the lower columnar portion PL can be suppressed.

[0054] These effects are further enhanced by setting the thickness DU and the thickness DL to be 2 times or less of the film thickness T. The reason therefor is that this allows the memory insulating film 8 to fill the above-mentioned convex portion of the bonding hole HJ, and can make the curvature of the channel semiconductor layer 2 more gentle. In addition, the width WU near the lower end of the upper pillar portion PU is often smaller than the width WL near the upper end of the lower pillar portion PL (WU<WL), therefore, in most cases, the advantage of setting the thickness DU to be 2 times or less of the film thickness T is greater than the advantage of setting the thickness DL to be 2 times or less of the film thickness T.

[0055] Figures 4-8 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

[0056] First, a lower stacked film 12 and an intermediate film 13 are sequentially formed on a substrate 11 ( Figure 4 (a)). However, Figure 4 the lower stacked film 12 shown in (a) is different from the lower stacked film 12 shown in Figure 2 , and is formed by alternately stacking a plurality of sacrifice layers 9 and a plurality of insulating layers 7 on the substrate 11. These sacrifice layers 9 are replaced with a plurality of electrode layers 6 in a process described later. On the other hand, Figure 4 the intermediate film 13 shown in (a) is the same as the intermediate film 13 shown in Figure 2 , and is formed by sequentially stacking an insulating layer 13a, an insulating layer 13b, and an insulating layer 13c on the lower stacked film 12. The sacrifice layer 9 is, for example, a SiN film. In Figure 4 (a), the sacrifice layers 9 are spaced apart from each other by the insulating layers 7. The sacrifice layer 9 is an example of the first layer.

[0057] Next, a hole H1 penetrating through the intermediate film 13 and the lower stacked film 12 is formed by etching ( Figure 4 (b)). As will be described later, the hole H1 becomes a part of the memory hole H.

[0058] Next, a resist film 21 is formed on the entire surface of the substrate 11 ( Figure 5 (a)). As a result, the upper surface of the intermediate film 13 is covered with the resist film 21, and the hole H1 is filled with the resist film 21.

[0059] Next, a part of the resist film 21 is removed by etching ( Figure 5 (b)). As a result, the resist film 21 is removed from the upper surface of the intermediate film 13, and a part of the resist film 21 inside the hole H1 is removed. Figure 5 The hole H2 shown in (b) is a region obtained by removing the resist film 21 from the hole H1. The hole H2 is formed in such a manner that the side surface of the insulating layer 13c, the side surface of the insulating layer 13b, and a part of the side surface of the insulating layer 13a are exposed.

[0060] Next, the intermediate film 13 is processed by etching. Figure 6 (a)). In this embodiment, insulating layers 13a and 13c are, for example, SiO2 films, and insulating layer 13b is, for example, a SiON film. Therefore, insulating layer 13b is processed at an etching rate different from that of insulating layers 13a and 13c. In this embodiment, the etching rate of insulating layer 13b is low, while the etching rates of insulating layers 13a and 13c are high. As a result, the sides of insulating layers 13a and 13c are etched faster than the sides of insulating layer 13b, and hole H2 changes to the aforementioned bonding hole HJ. On the other hand, hole H1 other than hole H2 becomes the aforementioned lower memory hole HL.

[0061] Furthermore, the insulating layer 13b in this embodiment may also be formed of the same material as the insulating layer 13a and the insulating layer 13c, and have a density different from that of the insulating layer 13a and the insulating layer 13c. For example, the density of the insulating layer 13b may be higher than that of the insulating layer 13a and the insulating layer 13c. Thus, even if the materials of the insulating layers 13a, 13b, and 13c are the same, it is possible to reduce the etching rate of the insulating layer 13b and increase the etching rates of the insulating layers 13a and 13c.

[0062] Next, a resist film 22 is formed on the entire surface of the substrate 11. Figure 6 (b) As a result, the upper surface of the intermediate film 13 is covered by the resist film 22, and the pore H2 is filled with the resist film 22.

[0063] Next, the resist film 22 is removed from the upper surface of the intermediate film 13. Figure 7 (a) As a result, the upper surface of the intermediate film 13 is exposed from the resist film 22.

[0064] Next, an upper laminate 14 is formed on the intermediate film 13 and the resist film 22, and a hole H3 penetrating the upper laminate 14 is formed by etching. Then, the resist films 22 and 21 are removed. Figure 7 (b)). However, Figure 7 The upper laminated film 14 shown in (b) and Figure 2 The upper laminated film 14 shown is different, formed by alternately laminating multiple sacrificial layers 9 and multiple insulating layers 7 on the intermediate film 13. These sacrificial layers 9 are replaced with multiple electrode layers 6 in a process described later. The sacrificial layers 9 of the upper laminated film 14 are the same as those of the lower laminated film 12, for example, SiN films. Figure 7 In (b), the sacrificial layers 9 of the upper laminate 14 are separated from each other by the insulating layer 7 of the upper laminate 14. The sacrificial layers 9 of the upper laminate 14 are an example of the second layer.

[0065] Figure 7As shown in (b), hole H3 is formed on hole H2, becoming the aforementioned upper memory hole HU. Thus, a memory hole H comprising the lower memory hole HL, the junction hole HJ, and the upper memory hole HU is formed within the lower laminate 12, the intermediate film 13, and the upper laminate 14. The memory hole H is an example of an opening.

[0066] Next, a memory insulating film 8, a channel semiconductor layer 2, and a core insulating film 1 are sequentially formed within the memory hole H. Then, the sacrificial layer 9 of the lower stacked film 12 and the upper stacked film 14 is removed by etching. Figure 8 (a) As a result, a columnar portion CL is formed within the memory hole H. The columnar portion CL is formed by comprising an insulating film 5a, a charge storage layer 4, a tunnel insulating film 3, a channel semiconductor layer 2, and a core insulating film 1 sequentially formed on the side and bottom surfaces of the memory hole H. In addition, the sacrificial layer 9 is removed from the slits formed within the upper laminated film 14, the intermediate film 13, and the lower laminated film 12. As a result, a recess C is formed in the region after the sacrificial layer 9 is removed.

[0067] Figure 8 (a) shows a lower columnar portion PL formed within the lower memory hole HL, a junction portion PJ formed within the junction hole HJ, and an upper columnar portion PU formed within the upper memory hole HU. Thus, a columnar portion CL comprising the lower columnar portion PL, the junction portion PJ, and the upper columnar portion PU is formed within the lower laminate 12, the intermediate film 13, and the upper laminate 14. Figure 8 In (a), the aforementioned protrusion within the junction hole HJ is filled with the memory insulating film 8.

[0068] Next, an electrode layer 6 is formed in each recess C. Figure 8 (b)). As a result, a lower laminated film 12 and an upper laminated film 14, including the electrode layer 6, are formed on the substrate 11. In this embodiment, the aforementioned insulating film 5b, barrier metal layer 6a, and electrode material layer 6b are sequentially formed on the surfaces of the insulating layer 7, insulating layer 13, and memory insulating film 8 within each recess C. In this way, a... Figure 1 The structure shown includes an insulating film 5b, a barrier metal layer 6a, and an electrode material layer 6b. Furthermore, an illustration of the insulating film 5b is provided. Figure 8 (b) is omitted.

[0069] In this way, it creates Figure 2 The semiconductor device shown. Additionally, in Figure 4 of (a), Figure 7 In process (b), if the electrode layer 6 is formed without forming the sacrificial layer 7, it is not necessary to... Figure 8 (a) and Figure 8In process (b), the sacrificial layer 7 is replaced with the electrode layer 6. In this case, the electrode layer 6 is an example of the first layer and the second layer.

[0070] Figures 9-13 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to a comparative example of the first embodiment. In the description of the method for manufacturing a semiconductor device in this comparative example, descriptions of commonalities with the method for manufacturing a semiconductor device according to the first embodiment are appropriately omitted.

[0071] First, a lower laminated film 12 and an intermediate film 13 are sequentially formed on a substrate 11. Figure 9 (a)). The lower laminate 12 is formed by alternately stacking multiple sacrificial layers 9 and multiple insulating layers 7 on the substrate 11. The intermediate film 13 is formed by forming an insulating layer 13b on the lower laminate 12. Then, a hole H1 penetrating the intermediate film 13 and the lower laminate 12 is formed by etching. Figure 9 (b)

[0072] Next, a resist film 21 is formed on the entire surface of the substrate 11. Figure 10 (a)). As a result, the hole H1 is filled with resist film 21. Then, a portion of the resist film 21 is removed by etching. Figure 10 (b) As a result, a portion of the resist film 21 within the hole H1 was removed. Figure 10 (b) shows the area after the resist film 21 has been removed from the hole H1. The hole H2 is formed in such a way that a portion of the side of the insulating layer 13b is exposed.

[0073] Next, the intermediate film 13 is processed by etching. Figure 11 (a)). As a result, hole H2 changes to the aforementioned bonding hole HJ. On the other hand, hole H1 other than hole H2 becomes the aforementioned lower memory hole HL. Next, a resist film 22 is formed on the entire surface of the substrate 11. Figure 11 (b)). As a result, the pore H2 is filled with the resist film 22.

[0074] Next, the resist film 22 is removed from the upper surface of the intermediate film 13. Figure 12 (a)). As a result, the upper surface of the intermediate film 13 is exposed from the resist film 22. Next, an upper laminate 14 is formed on the intermediate film 13 and the resist film 22, and a hole H3 penetrating the upper laminate 14 is formed by etching. Then, the resist films 22 and 21 are removed. Figure 12 (b) The upper laminated film 14 is formed by alternately laminating multiple sacrificial layers 9 and multiple insulating layers 7 on the intermediate film 13.

[0075] Figure 12The hole H3 shown in (b) is formed on the hole H2, becoming the upper memory hole HU described above. In this way, a memory hole H including the lower memory hole HL, the bonding hole HJ and the upper memory hole HU are formed in the lower laminate 12, the intermediate film 13 and the upper laminate 14.

[0076] Next, a memory insulating film 8, a channel semiconductor layer 2, and a core insulating film 1 are sequentially formed within the memory hole H. Then, the sacrificial layer 9 of the lower stacked film 12 and the upper stacked film 14 is removed by etching. Figure 13 (a) As a result, a columnar portion CL is formed within the memory hole H. The sacrificial layer 9 is removed from the slits formed within the upper laminate 14, the intermediate film 13, and the lower laminate 12. As a result, a recess C is formed in the region after the sacrificial layer 9 is removed.

[0077] Figure 13 (a) shows a lower columnar portion PL formed in the lower memory hole HL, a joint portion PJ formed in the joint hole HJ, and an upper columnar portion PU formed in the upper memory hole HU. In this way, a columnar portion CL containing the lower columnar portion PL, the joint portion PJ, and the upper columnar portion PU is formed in the lower laminate 12, the intermediate film 13, and the upper laminate 14.

[0078] Next, an electrode layer 6 is formed in each recess C. Figure 13 (b)). As a result, a lower laminate 12 containing the electrode layer 6 and an upper laminate 14 are formed on the substrate 11. In this way, a [material / structure] is manufactured. Figure 3 The semiconductor device shown.

[0079] In the manufacturing method of the semiconductor device in this comparative example, the intermediate film 13 is formed in a manner that includes only the insulating layer 13b. Figure 9 (a)). Thus, the joint hole HJ in this comparative example is formed in such a way that it has the same width (diameter) from the lower end to the upper end of the joint hole HJ. Figure 11 (a) Therefore, near the boundary between the junction PJ and the upper columnar portion PU, the shape of the channel semiconductor layer 2 is significantly curved ( Figure 13 (a) As a result, the channel semiconductor layer 2 may be isolated near the corner.

[0080] On the other hand, in the manufacturing method of the semiconductor device in the first embodiment, the intermediate film 13 is formed in such a way that it sequentially includes insulating layers 13a, 13b, and 13c. Figure 4 (a)). Therefore, the joining hole HJ in this embodiment is formed in a manner that includes the above-described protrusion. Figure 6 (a)). As a result, near the boundary between the junction PJ and the upper columnar portion PU, the significant bending of the channel semiconductor layer 2 is suppressed. Figure 8 (a)). Thus, it is possible to suppress the situation where the channel semiconductor layer 2 is blocked near the corner.

[0081] Figure 21 This is a cross-sectional view showing the structure of a memory device 100, an example of a semiconductor device according to a first embodiment. The memory device 100 is, for example, a NAND-type non-volatile memory device, comprising memory cells MC arranged in three dimensions. Furthermore, in Figure 21 The diagram of the insulating layer that electrically insulates the various components of the storage device 100 is omitted.

[0082] like Figure 21 As shown, the storage device 100 includes a substrate 10 and wirings D0, D1, and D2. The substrate 10 is, for example, a silicon substrate, and a driving circuit DC for a storage cell MC is disposed on its upper surface. Wirings D0, D1, and D2 are sequentially stacked on the substrate 10, for example, electrically connecting circuit elements such as transistors. Wiring D0 is connected to the circuit elements on the substrate 10 via a contact plug C0. Wiring D1 is connected to wiring D0 via a contact plug C1. Wiring D2 is connected to wiring D1 via a contact plug C2. The substrate 10 is an example of the substrate 11 described above.

[0083] The storage device 100 also includes a laminated film 200, which includes a source line SL, a word line 20, select gates 30 and 40, and a channel layer 50. The source line SL is disposed on the wiring D2. The source line SL is, for example, a plate-shaped conductor extending in the X and Y directions. The word line 20, select gate 30, and select gate 40 are laminated on the source line SL. The word line 20 is located between the select gates 30 and 40. The channel layer 50 passes through the word line 20, select gate 30, and select gate 40 and extends in the Z direction. The lower end of the channel layer 50 is electrically connected to the source line SL. The laminated film 200 is an example of the lower laminated film 12, the intermediate film 13, and the upper laminated film 14 described above.

[0084] like Figure 21 As shown, word line 20, select gate 30, and select gate 40 have stepped ends and are connected to the M0 wiring via contact plug C3. The M0 wiring is connected to the line decoder in the drive circuit DC, for example, via a contact plug (not shown).

[0085] The memory cell MC is disposed at the intersection of the word line 20 and the channel layer 50. An insulating layer 60 is disposed between the word line 20 and the channel layer 50. The insulating layer 60 extends along the channel layer 50 in the Z direction and functions as a charge retention layer in the portion located between the word line 20 and the channel layer 50. The channel layer 50 corresponds to an example of the channel semiconductor layer 2 described above.

[0086] A source-side selection transistor (STS) is provided at the intersection of the channel layer 50 and the selection gate 30. Additionally, a drain-side selection transistor (STD) is provided at the intersection of the channel layer 50 and the selection gate 40.

[0087] The storage device 100 also includes a contact plug C4 that passes through the word line 20, the select gates 30 and 40, and the source line SL and extends in the Z direction. The contact plug C4 is provided, for example, in the central part of the word line 20, and its lower end is connected to the wiring D2.

[0088] The storage device 100 also includes M1 wiring and M2 wiring. M1 wiring is disposed above the select gate 40, for example, including multiple bit lines BL. M2 wiring is disposed above M1 wiring.

[0089] Bit lines BL are electrically connected to one of the channels 50. Additionally, bit line BL is connected to the M2 wiring at a location not shown. The M2 wiring is electrically connected to the M1 wiring. That is, bit line BL is electrically connected, for example, to the sense amplifier located in the drive circuit DC via the M2 wiring and contact plug C4.

[0090] Figure 22 This is a circuit diagram showing the configuration of the storage device 100.

[0091] like Figure 22 As shown, the storage device 100 includes a storage cell array 70, an I / O (Input / Output) control circuit 71, a logic control circuit 72, a status register 73, an address register 74, a command register 75, a control circuit 76, a ready / busy circuit 77, a voltage generator 78, a row decoder 81, a sense amplifier 82, a data register 83, and a column decoder 84.

[0092] The I / O control circuit 71 transmits and receives input and output signals with the controller (not shown) via data lines DQ0-0 to DQ7-0. The logic control circuit 72 receives the chip enable signal BCE-0, the command latch enable signal CLE-0, the address latch enable signal ALE-0, the write enable signal BWE-0, the read enable signals RE-0 and BRE-0, and controls the operation of the I / O control circuit 71 and the control circuit 76 according to these signals.

[0093] Status register 73 stores the status of read, write, and erase operations, and notifies the controller of the completion of these operations. Address register 74 stores the address signals received by the I / O control circuit 71 from the controller. Command register 75 stores the command signals received by the I / O control circuit 71 from the controller.

[0094] The control circuit 76 controls the status register 73, ready / busy circuit 77, voltage generator 78, row decoder 81, sense amplifier 82, data register 83 and column decoder 84 according to the instruction signal of the command register 75 to perform read operations, write operations, erase operations and so on.

[0095] The ready / busy circuit 77 sends a ready / busy signal RY / BBY-0 to the controller based on the operating conditions of the control circuit 76. Thus, the control circuit 76 can indicate whether an instruction can be accepted or not. The voltage generator 78 generates the voltages required for read, write, and erase operations.

[0096] Row decoder 81 applies voltage to the word line WL of memory cell array 70. Sensing amplifier 82 detects data read onto bit line BL of memory cell array 70. Data register 83 stores data from I / O control circuit 71 and sensing amplifier 82. Column decoder 84 decodes the column address and selects the latch circuit in data register 83 based on the decoding result. Row decoder 81, sensing amplifier 82, data register 83, and column decoder 84 function as interfaces for read, write, and erase operations on memory cell array 70.

[0097] Figure 23 This is a block diagram showing the configuration associated with the memory cell array 70 within the storage device 100.

[0098] Figure 23 The diagram shows multiple layers 61 constituting the memory cell array 70, multiple row decoders 62 (=81) provided for these layers 61, multiple SA / DL units 63, multiple XDL units 64, and multiple YLOG units 65. Figure 23 Also shown are serial circuit 66, I / O (Input / Output) circuit 67, low voltage generation circuit 51, high voltage generation circuit 52, row control circuit 53, and column control circuit 54. Figure 23 The controller 300 included in the storage device 100 is also shown.

[0099] Each layer 61 consists of multiple memory cells, multiple word lines (WL), multiple bit lines (BL), etc. Each row decoder 62 applies control voltages to the control wiring such as the word lines (WL). Examples of such control voltages include write voltage (VPRG), erase voltage (VERASE), intermediate voltage (VPASS), and source voltage (VSL). Each SA / DL section 63 is a sense amplifier circuit and a data latch circuit that detects the data read from the bit line (BL). Each XDL section 64 is a data latch circuit that stores the data sent from the SA / DL section 63 and the I / O circuit 67. Each YLOG section 65 decodes the column address and selects the latch circuit within the XDL section 64 based on the decoding result. The serial circuit 66 provides a serial bus shared by multiple layers 61, and the I / O circuit 67 transmits and receives input signals and output signals with the controller 300.

[0100] The low-voltage generation circuit 51 and the high-voltage generation circuit 52 constitute a control voltage generation circuit, generating low voltage and high voltage respectively for use as control voltage. The row control circuit 53 and the column control circuit 54 respectively implement control related to the rows and columns of each layer 61.

[0101] As described above, in this embodiment, the joint PJ of the columnar portion CL is formed in such a way that it includes an intermediate joint P1 and an upper joint P2 having a width greater than that of the intermediate joint P1. Furthermore, in this embodiment, the joint PJ is formed in such a way that it includes a lower joint P3 having a width greater than that of the intermediate joint P1. Therefore, according to this embodiment, it is possible to suppress situations such as the channel semiconductor layer 2 being isolated within the joint PJ, and the channel semiconductor layer 2 can be appropriately formed within the memory hole H.

[0102] (Second Implementation)

[0103] Figure 14 This is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment.

[0104] The semiconductor device of this embodiment, like the semiconductor device of the first embodiment, includes a substrate 11, a lower laminate 12, an intermediate film 13, an upper laminate 14, and a columnar portion CL. However, the intermediate film 13 of this embodiment includes insulating layers 13d, 13e, 13f, and 13g sequentially formed on the lower laminate 12. Insulating layer 13d is, for example, a SiON film. Insulating layer 13e is, for example, a SiO2 film. Insulating layer 13f is, for example, a SiON film. Insulating layer 13g is, for example, a metal insulating film. Thus, the insulating layer 13e of this embodiment is formed of a material (SiO2) different from the material (SiON) of insulating layer 13f, the material (SiON) of insulating layer 13d, and the material (metal insulating material) of insulating layer 13g. Furthermore, the insulating layer 13g of this embodiment is formed of a material (metal insulating material) different from the material (SiON) of insulating layer 13f. Insulating layer 13e is an example of a fourth insulating layer. Insulating layer 13f is an example of a fifth insulating layer. Insulating layer 13d is an example of the sixth insulating layer. Insulating layer 13g is an example of the seventh insulating layer.

[0105] Furthermore, the insulating layer 13e of this embodiment may also have a density different from that of the insulating layer 13f, the insulating layer 13d, and the insulating layer 13g. For example, the density of the insulating layer 13e of this embodiment may be lower than that of the insulating layer 13f, the insulating layer 13d, and the insulating layer 13g. In this case, the material of the insulating layer 13e may be the same as, or different from, at least one of the materials of the insulating layer 13f, the insulating layer 13d, and the insulating layer 13g.

[0106] Furthermore, the insulating layer 13g of this embodiment may also have a density different from that of the insulating layer 13f. For example, the density of the insulating layer 13g of this embodiment may be higher than that of the insulating layer 13f. In this case, the material of the insulating layer 13g may be the same as or different from that of the insulating layer 13f. Further details regarding the insulating layers 13d, 13e, 13f, and 13g will be described later.

[0107] Next, continue to refer to Figure 14 This section will provide further details about the joint PJ in this embodiment.

[0108] In the present embodiment, the joint PJ includes an intermediate joint P4, an upper joint P5, and a lower joint P6. The upper joint P5 is provided at a position higher than the intermediate joint P4, and the lower joint P6 is provided at a position lower than the intermediate joint P4. In the present embodiment, the side surface of the intermediate joint P4 is located further in the radial direction than the side surfaces of the upper joint P5 and the lower joint P6. The intermediate joint P4, the upper joint P5, and the lower joint P6 are examples of the fourth portion, the fifth portion, and the sixth portion, respectively.

[0109] In the present embodiment, the intermediate joint P4 is provided in the insulating layer 13e, the upper joint P5 is provided in the insulating layers 13f and 13g, and the lower joint P6 is provided in the insulating layer 13d. In the present embodiment, the side surface of the memory insulating film 8 included in the upper joint P5 is in contact with the side surface of the insulating layer 13f, and these side surfaces are inclined with respect to the Z direction. Similarly, the side surface of the memory insulating film 8 included in the lower joint P6 is in contact with the side surface of the insulating layer 13d, and these side surfaces are inclined with respect to the Z direction.

[0110] Figure 14 The width W4 in the X direction of the intermediate joint P4, the width W5 in the X direction of the upper joint P5, and the width W6 in the X direction of the lower joint P6 are shown. Specifically, the width W5 represents the width near the upper end of the upper joint P5, and the width W6 represents the width near the lower end of the lower joint P6. As Figure 14 shown, the joint PJ of the present embodiment protrudes in the radial direction relative to the side surface of the lower columnar portion PL and the side surface of the upper columnar portion PU within the insulating layers 13d, 13e, and 13f. Therefore, in the present embodiment, the widths W4 and W6 are larger than the widths WL and WU (W4, W6>WL, WU), but the width W5 of the present embodiment is the same as the width WU (W5=WU). However, the width of the upper joint P5 is also larger than the width WU within the insulating layer 13f. In addition, as described above, the side surface of the intermediate joint P4 of the present embodiment is located further in the radial direction than the side surfaces of the upper joint P5 and the lower joint P6. Therefore, in the present embodiment, the widths W5 and W6 are smaller than the width W4 (W5, W6<W4). The widths W4, W5, and W6 are examples of a fourth width, a fifth width, and a sixth width, respectively.

[0111] The difference between the width W4 and the widths W5 and W6 in the present embodiment is caused, for example, by the difference between the etching rate of the insulating layer 13e and the etching rates of the insulating layers 13f, 13d, and 13g. Details of these etching rates will be described later.

[0112] Figure 14The corner K of the channel semiconductor layer 2 within the upper junction P5 is shown. In the upper junction P5 of this embodiment, the width of the columnar portion CL changes smoothly from the width W4 of the central junction P4 to the width WU of the upper columnar portion PU. Therefore, the curvature of the channel semiconductor layer 2 at the corner K of this embodiment is as gentle as the curvature of the channel semiconductor layer 2 at the corner K of the first embodiment. As a result, the possibility of the channel semiconductor layer 2 being interrupted near the corner K can be suppressed. Thus, according to this embodiment, by providing the middle junction P4 and the upper junction P5 in the junction PJ, the possibility of the channel semiconductor layer 2 being interrupted near the corner K can be suppressed. Furthermore, according to this embodiment, by further providing the lower junction P6 in the junction PJ, the possibility of the channel semiconductor layer 2 being interrupted at the corner near the boundary between the junction PJ and the lower columnar portion PL can be suppressed.

[0113] Figure 15 This is a cross-sectional view showing the structure of a semiconductor device according to a modified example of the second embodiment.

[0114] In this modified example, the upper memory hole HU is offset in the X direction relative to the bonding hole HJ. That is, the central axis of the upper memory hole HU is not located on the central axis of the bonding hole HJ, but is located further in the X direction than the central axis of the bonding hole HJ. As a result, when the upper memory hole HU is formed by etching within the upper laminate 14, a portion of the insulating layer 13 is also removed by the etching. Consequently, the planar shape of the upper bonding portion P5 in this modified example is slightly deformed from a circle. For example, through this deformation, the width W5 of the upper bonding portion P5 in this modified example becomes larger than the width WU of the upper columnar portion PU (W5>WU).

[0115] In the upper joint P5 of this modified example, the width of the columnar portion CL changes smoothly from width W4 to width W5. Therefore, the curvature of the channel semiconductor layer 2 at the corner K of this modified example is also as smooth as the curvature of the channel semiconductor layer 2 at the corner K of the first and second embodiments. As a result, it is possible to suppress the situation where the channel semiconductor layer 2 of this modified example is interrupted near the corner K. Such interruption of the channel semiconductor layer 2 is also suppressed at the corner near the boundary between the joint PJ and the lower columnar portion PL.

[0116] Figure 16 This is a cross-sectional view showing the structure of a semiconductor device according to another variation of the second embodiment.

[0117] In this modified example, the intermediate film 13 includes insulating layers 13e, 13f, and 13g, but does not include insulating layer 13d. Therefore, the joint PJ in this modified example does not include the lower joint P6. The width W6 in this modified example shows the width near the lower end of the intermediate joint P4. The width W6 in this modified example is the same as the width W4 (W6 = W4).

[0118] In the upper joint P5 of this modified example, the width of the columnar portion CL changes smoothly from width W4 to width W5. Therefore, the curvature of the channel semiconductor layer 2 at corner K in this modified example is also as gentle as the curvature of the channel semiconductor layer 2 at corner K in the first and second embodiments. As a result, it is possible to suppress the situation where the channel semiconductor layer 2 of this modified example is interrupted near corner K.

[0119] On the other hand, such a barrier in the channel semiconductor layer 2 may occur at the corner near the boundary between the junction PJ and the lower columnar portion PL. However, as described above, the width WL near the upper end of the lower columnar portion PL is often larger than the width WU near the lower end of the upper columnar portion PU (WL>WU). In this case, even if the lower junction P6 is not provided in the junction PJ, the barrier in the channel semiconductor layer 2 can be suppressed at this corner.

[0120] in addition, Figure 15 and Figure 16 The variations shown can also be applied to the semiconductor device of the first embodiment. That is, in the first embodiment, a positional offset of the upper memory hole HU can be generated, and the lower joint P3 can be omitted from the joint PJ in the first embodiment. In these cases, references can also be obtained. Figure 15 and Figure 16 The effect of the explanation.

[0121] Figures 17-20 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment. In the description of the method for manufacturing a semiconductor device according to this embodiment, descriptions of commonalities with the method for manufacturing a semiconductor device according to the first embodiment are appropriately omitted.

[0122] First, a lower laminated film 12 and an intermediate film 13 are sequentially formed on a substrate 11. Figure 17 (a)). The lower laminate 12 is formed by alternately stacking multiple sacrificial layers 9 and multiple insulating layers 7 on the substrate 11. The intermediate film 13 is formed by sequentially stacking insulating layers 13d, 13e, 13f, and 13g on the lower laminate 12. Then, a hole H4 penetrating the intermediate film 13 and the lower laminate 12 is formed by etching. Figure 17 (b)). As described later, hole H4 becomes part of memory hole H.

[0123] Next, a resist film 23 is formed on the entire surface of the substrate 11. Figure 18 (a)). As a result, the hole H4 is filled with resist film 23. Then, a portion of the resist film 23 is removed by etching. Figure 18 (b)). As a result, a portion of the resist film 23 within the hole H4 was removed. Figure 18 (b) shows that hole H5 is the area after the resist film 21 has been removed from hole H4. Hole H5 is formed in such a way that the side surface of insulating layer 13g, the side surface of insulating layer 13f, the side surface of insulating layer 13e, and a portion of the side surface of insulating layer 13d are exposed.

[0124] Next, the intermediate film 13 is processed by etching. Figure 19 (a)). In this embodiment, insulating layers 13d and 13f are, for example, SiON films, insulating layer 13e is, for example, a SiO2 film, and insulating layer 13g is, for example, a metal insulating film. Therefore, insulating layer 13e is processed at an etching rate different from that of insulating layers 13d, 13f, and 13g, and insulating layers 13d and 13f are processed at an etching rate different from that of insulating layer 13g. In this embodiment, the etching rate of insulating layer 13e is high, the etching rates of insulating layers 13d and 13f are low, and the etching rate of insulating layer 13g is even lower. As a result, the sidewalls of insulating layer 13e are etched faster than the sidewalls of insulating layers 13d and 13f, and the sidewalls of insulating layers 13d and 13f are etched faster than the sidewalls of insulating layer 13g, and hole H5 changes to the aforementioned bonding hole HJ. On the other hand, hole H4 other than hole H5 becomes the aforementioned lower memory hole HL.

[0125] Furthermore, the insulating layer 13e in this embodiment may also be formed of the same material as the insulating layer 13d and the insulating layer 13f, and have a density different from that of the insulating layer 13d and the insulating layer 13f. For example, the density of the insulating layer 13e may be lower than that of the insulating layers 13d and 13f. Thus, even if the materials of the insulating layers 13d, 13e, and 13f are the same, it is possible to increase the etching rate of the insulating layer 13e and decrease the etching rates of the insulating layers 13d and 13e.

[0126] Furthermore, the insulating layer 13f in this embodiment may also be formed of the same material as the insulating layer 13g, and have a density different from that of the insulating layer 13g. For example, the density of the insulating layer 13f may be lower than that of the insulating layer 13g. Thus, even if the materials of the insulating layers 13f and 13g are the same, it is possible to increase the etching rate of the insulating layer 13f and decrease the etching rate of the insulating layer 13g.

[0127] Next, the hole H5 is filled with a resist film (not shown), and an upper laminate 14 is formed on the intermediate film 13 and the resist film. A hole H6 penetrating the upper laminate 14 is formed by etching. Then, the resist film and resist film 23 are removed. Figure 19 (b) The upper laminated film 14 is formed by alternately laminating multiple sacrificial layers 9 and multiple insulating layers 7 on the intermediate film 13.

[0128] Figure 19 The hole H6 shown in (b) is formed on the hole H5, becoming the aforementioned upper memory hole HU. In this way, a memory hole H including the lower memory hole HL, the bonding hole HJ, and the upper memory hole HU is formed in the lower laminate 12, the intermediate film 13, and the upper laminate 14.

[0129] Next, a memory insulating film 8, a channel semiconductor layer 2, and a core insulating film 1 are sequentially formed within the memory hole H. Then, the sacrificial layer 9 of the lower stacked film 12 and the upper stacked film 14 is removed by etching. Figure 20 (a) As a result, a columnar portion CL is formed within the memory hole H. The sacrificial layer 9 is removed from the slits formed in the upper laminate 14, the intermediate film 13, and the lower laminate 12. As a result, a recess C is formed in the region after the sacrificial layer 9 is removed.

[0130] Figure 20 (a) shows a lower columnar portion PL formed in the lower memory hole HL, a joint portion PJ formed in the joint hole HJ, and an upper columnar portion PU formed in the upper memory hole HU. In this way, a columnar portion CL containing the lower columnar portion PL, the joint portion PJ, and the upper columnar portion PU is formed in the lower laminate 12, the intermediate film 13, and the upper laminate 14.

[0131] Next, an electrode layer 6 is formed in each recess C. Figure 20 (b)). As a result, a lower laminate 12 containing the electrode layer 6 and an upper laminate 14 are formed on the substrate 11. In this way, a [material / structure] is manufactured. Figure 14 The semiconductor device shown.

[0132] in addition, Figure 15 The semiconductor device shown is in Figure 19 This was manufactured under conditions where the position of hole H6 was offset during the process shown in (b). Additionally, Figure 16 The semiconductor device shown is in Figure 17 It is manufactured without the formation of the insulating layer 13d in the process shown in (a).

[0133] As described above, in this embodiment, the joint PJ of the columnar portion CL is formed in such a way that it includes an intermediate joint P4 and an upper joint P5 having a width smaller than that of the intermediate joint P4. Furthermore, in this embodiment, the joint PJ is formed in such a way that it includes a lower joint P6 having a width smaller than that of the intermediate joint P4. Therefore, according to this embodiment, it is possible to suppress situations such as the channel semiconductor layer 2 being isolated within the joint PJ, and the channel semiconductor layer 2 can be appropriately formed within the memory hole H.

[0134] The above describes several embodiments, but these embodiments are merely examples and do not imply limitation of the scope of the invention. The novel apparatus and method described in this specification can be implemented in various other ways. Furthermore, various omissions, substitutions, and modifications can be made to the apparatus and method described in this specification without departing from the spirit of the invention. The scope of the appended claims and their equivalents is intended to cover the scope of the invention, such embodiments, and modifications as encompassed in its spirit.

[0135] Explanation of symbols

[0136] 1: Core insulating film, 2: Channel semiconductor layer, 3: Tunnel insulating film.

[0137] 4: Charge storage layer; 5: Barrier insulating film; 5a: Insulating film; 5b: Insulating film.

[0138] 6: Electrode layer, 6a: Barrier metal layer, 6b: Electrode material layer

[0139] 7: Insulating layer, 8: Memory insulating film, 9: Sacrificial layer

[0140] 11: Substrate; 12: Lower laminated film; 13: Intermediate film.

[0141] 13a: Insulating layer, 13b: Insulating layer, 13c: Insulating layer, 13d: Insulating layer

[0142] 13e: Insulating layer, 13f: Insulating layer, 13g: Insulating layer, 14: Upper laminate.

[0143] 21: Anti-corrosion film, 22: Anti-corrosion film, 23: Anti-corrosion film.

Claims

1. A semiconductor device comprising: The first layer of the film includes a plurality of first electrode layers spaced apart from each other; An insulating layer is disposed on the first laminated film; A second laminated film, disposed on the insulating layer, includes a plurality of second electrode layers spaced apart from each other; and The columnar portion comprises a first insulating film, a charge storage layer, a second insulating film, and a semiconductor layer sequentially disposed within the first laminated film, the insulating layer, and the second laminated film, and extends along a first direction from the first laminated film toward the second laminated film. The columnar portion within the insulating layer comprises a first portion and a second portion. The first portion has a first width in a second direction intersecting the first direction. The second portion is positioned higher than the first portion and has a second width in the second direction. The second width is larger than the first width and larger than the width of the columnar portion within the second laminate in the second direction. The thickness of the second portion in the first direction is less than twice the combined thickness of the first insulating film, the charge storage layer, and the second insulating film.

2. The semiconductor device according to claim 1, wherein, The first width is greater than the width of the columnar portion within the second laminated film.

3. The semiconductor device according to claim 1, wherein, The columnar portion within the insulating layer further includes a third portion, which is positioned lower than the first portion and has a third width, which is larger than the first width and larger than the width of the columnar portion within the first laminated film.

4. The semiconductor device according to claim 3, wherein, The thickness of the third portion in the first direction is less than twice the combined thickness of the first insulating film, the charge storage layer, and the second insulating film.

5. The semiconductor device according to claim 3, wherein, The first width is greater than the width of the columnar portion within the first laminated film.

6. The semiconductor device according to claim 3, wherein, In the first part, the second part, and the third part, the width of the outer peripheral surface of the semiconductor layer is the largest in the first part.

7. The semiconductor device according to claim 3, wherein, In the first part, the second part, and the third part, the width of the inner peripheral surface of the semiconductor layer is the largest in the first part.

8. The semiconductor device according to claim 3, wherein, The insulating layer includes a first insulating layer, a second insulating layer disposed on the first insulating layer, and a third insulating layer disposed below the first insulating layer. At least a portion of the first part is disposed within the first insulating layer, at least a portion of the second part is disposed within the second insulating layer, and at least a portion of the third part is disposed within the third insulating layer.

9. The semiconductor device according to claim 8, wherein, The first insulating layer is formed of a material different from the material of the second insulating layer and the material of the third insulating layer.

10. The semiconductor device according to claim 8, wherein, The first insulating layer has a density that is different from the density of the second insulating layer and the density of the third insulating layer.

11. A semiconductor device comprising: The first layer of the film includes a plurality of first electrode layers spaced apart from each other; An insulating layer is disposed on the first laminated film; A second laminated film, disposed on the insulating layer, includes a plurality of second electrode layers spaced apart from each other; and The columnar portion comprises a first insulating film, a charge storage layer, a second insulating film, and a semiconductor layer sequentially disposed within the first laminated film, the insulating layer, and the second laminated film, and extends along a first direction from the first laminated film toward the second laminated film. The columnar portion within the insulating layer comprises a fourth portion and a fifth portion. The fourth portion has a fourth width in a second direction intersecting the first direction. The fifth portion is positioned higher than the fourth portion and has a fifth width in the second direction. The fifth width is smaller than the fourth width but larger than the width of the columnar portion within the second laminate in the second direction. The side of the columnar portion is inclined relative to the first direction at the fifth part.

12. The semiconductor device according to claim 11, wherein, The columnar portion within the insulating layer further includes a sixth portion, which is positioned lower than the fourth portion and has a sixth width, which is smaller than the fourth width but larger than the width of the columnar portion within the first laminated film.

13. The semiconductor device according to claim 12, wherein, The side of the columnar portion is inclined relative to the first direction at the sixth part.

14. The semiconductor device according to claim 12, wherein, The insulating layer includes a fourth insulating layer, a fifth insulating layer disposed on the fourth insulating layer, and a sixth insulating layer disposed below the fourth insulating layer. At least a portion of the fourth part is disposed within the fourth insulating layer, at least a portion of the fifth part is disposed within the fifth insulating layer, and at least a portion of the sixth part is disposed within the sixth insulating layer.

15. The semiconductor device according to claim 14, wherein, The insulating layer further includes a seventh insulating layer disposed on the fifth insulating layer. At least a portion of the fifth part is disposed within the fifth insulating layer and the seventh insulating layer.

16. A method for manufacturing a semiconductor device, comprising the following steps: A first laminated film is formed, the first laminated film comprising a plurality of first layers spaced apart from each other; An insulating layer is formed on the first laminated film; A second laminated film is formed on the insulating layer, the second laminated film comprising a plurality of second layers spaced apart from each other; An opening is formed in the first laminated film, the insulating layer and the second laminated film, extending in a first direction from the first laminated film toward the second laminated film; as well as A columnar portion is formed, which includes a first insulating film, a charge storage layer, a second insulating film, and a semiconductor layer sequentially disposed within the opening. The columnar portion within the insulating layer is formed comprising a first portion and a second portion. The first portion has a first width in a second direction intersecting the first direction. The second portion is positioned higher than the first portion and has a second width in the second direction. The second width is larger than the first width and larger than the width of the columnar portion within the second laminate in the second direction. The thickness of the second portion in the first direction is less than twice the combined thickness of the first insulating film, the charge storage layer, and the second insulating film. or The columnar portion within the insulating layer is formed in a manner comprising a fourth portion and a fifth portion, the fourth portion having a fourth width in the second direction, the fifth portion being disposed at a position higher than the fourth portion and having a fifth width in the second direction, the fifth width being smaller than the fourth width and larger than the width of the columnar portion within the second laminate in the second direction, and the side of the columnar portion being inclined relative to the first direction at the fifth portion.

17. The method of manufacturing a semiconductor device according to claim 16, wherein, The columnar portion within the insulating layer is formed further comprising a third portion, which is positioned lower than the first portion and has a third width in the second direction. This third width is larger than the first width and also larger than the width of the columnar portion within the first laminated film in the second direction. or The columnar portion within the insulating layer is formed to further include a sixth portion, which is positioned lower than the fourth portion and has a sixth width in the second direction. The sixth width is smaller than the fourth width and larger than the width of the columnar portion within the first laminate in the second direction.

18. The method of manufacturing a semiconductor device according to claim 16, wherein, It also includes the following steps: replacing the plurality of first layers in the first layered film with a plurality of first electrode layers, and replacing the plurality of second layers in the second layered film with a plurality of second electrode layers.

Images