Depletion self-conducting uniform field low resistance device and method of manufacture

Abstract

The present application provides a kind of depletion self-continuous uniform field low resistance device and manufacturing method, comprising: first conductive type semiconductor substrate, first conductive type well region, first conductive type semiconductor contact area, second conductive type drift region, second conductive type well region, second conductive type semiconductor contact area, first dielectric oxide layer, second dielectric oxide layer, third dielectric oxide layer, fourth dielectric oxide layer, floating field plate polysilicon electrode, control gate polysilicon electrode, via, metal strip;First dielectric oxide layer and polysilicon electrode constitute longitudinal floating field plate, form a kind of continuous depletion cell.When the drain is energized, floating potential will be coupled out on the polysilicon electrode to clamp potential, because there is overlapping area between depletion cells, drift region can be depleted simultaneously.Due to the shape of the first dielectric oxide layer in the depletion cell is adjusted, the depletion continuity is enhanced, and the withstand voltage is improved. The drift region injection dose can also be increased to reduce the specific on-resistance.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor devices, and mainly proposes a depletion self-continuous uniform low-resistivity device and its manufacturing method. Background Technology

[0002] In my country, power semiconductor devices are widely used in consumer electronics, computers and peripherals, network communications, electronic equipment and instruments, automotive electronics, LED displays, and electronic lighting. Among these, lateral devices, with their source, gate, and drain all located on the chip surface, are easily integrated with other devices and circuits through internal connections and possess excellent characteristics, making them widely used in power integrated circuits. The main electrical characteristics of lateral devices are reverse breakdown voltage and specific on-resistance. In device design, achieving high breakdown voltage and low specific on-resistance is a major research focus. However, in high-voltage integrated circuits, optimizing these two indicators presents a certain contradiction, namely R... on,sp ∝ V B 2.5 Silicon limits.

[0003] Therefore, improving the breakdown voltage of devices while reducing their specific on-resistance has always been a mainstream research area in lateral device development. Some researchers have introduced dielectric trenches into lateral power devices. In this structure, for the same length, the dielectric trench can withstand a larger electric field than a silicon layer. Therefore, introducing a dielectric trench can improve the breakdown voltage of the device while shortening its lateral dimensions and reducing the chip area. However, a drawback is that the specific on-resistance of traditional dielectric trench LDMOS devices remains relatively high. Summary of the Invention

[0004] The purpose of this invention is to propose a depletion-self-continuous uniform low-resistivity device and its manufacturing method based on the working mechanism of longitudinal field plate structure and MIS structure. The device introduces continuous depletion cells in the drift region, exhibiting higher breakdown voltage and lower specific on-resistance than conventional dielectric trench lateral devices, and its manufacturing method is also relatively simple.

[0005] To achieve the above-mentioned objectives, the technical solution of this invention is as follows:

[0006] A self-continuous uniform low-resistivity device, comprising:

[0007] A first conductivity type semiconductor substrate 11, a first conductivity type well region 12, a first conductivity type semiconductor contact region 13, a second conductivity type drift region 21, a second conductivity type well region 22, a second conductivity type semiconductor contact region 23, a first dielectric oxide layer 31, a second dielectric oxide layer 32, a third dielectric oxide layer 33, a fourth dielectric oxide layer 34, a floating field plate polysilicon electrode 41, a control gate polysilicon electrode 42, a source via 51, a drain via 52, a drift region metal via 53, a source metal 61, a drain metal 62, and a metal strip 63;

[0008] In this design, the second conductivity type drift region 21 is located above the first conductivity type semiconductor substrate 11; the first conductivity type well region 12 is located to the left of the second conductivity type drift region 21; the second conductivity type well region 22 is located to the right of the second conductivity type drift region 21; the first conductivity type semiconductor contact region 13 and the second conductivity type semiconductor contact region 23 are located within the first conductivity type well region 12; the source via 51 is located on the upper surface of the first conductivity type semiconductor contact region 13 and the second conductivity type semiconductor contact region 23; and the source metal 61 is located on the upper surface of the source via 51. The second conductivity type semiconductor contact region 23 is located within the second conductivity type well region 22; the drain via 52 is located on the upper surface of the second conductivity type semiconductor contact region 23; and the drain metal 62 is located on the upper surface of the drain via 52. The second dielectric oxide layer 32 is located above the first conductivity type well region 12, with its left end in contact with the second conductivity type semiconductor contact region 23 and its right end in contact with the second conductivity type drift region 21. Region 21 is in contact; the third dielectric oxide layer 33 is located on the upper surface of the second conductivity type drift region 21 between the second dielectric oxide layer 32 on the left and the second conductivity type semiconductor contact region 23 on the right; the fourth dielectric oxide layer 34 is located above the third dielectric oxide layer 33 and covers the first conductivity type semiconductor contact region 13 and the second conductivity type semiconductor contact region 23; the control gate polysilicon electrode 42 covers the upper surface of the second dielectric oxide layer 32 and partially extends to the upper surface of the fourth dielectric oxide layer 34; the first dielectric oxide layer 31 and the floating field plate polysilicon electrode 41 constitute a longitudinal floating field plate, forming a continuous depletion cell, and the first dielectric oxide layer 31 surrounds the floating field plate polysilicon electrode 41. The longitudinal floating field plate is distributed throughout the second conductivity type drift region 21, forming a pressure-resistant layer with equipotential floating grooves; the drift region metal via 53 is located in the third dielectric oxide layer 33 and the fourth dielectric oxide layer 34, and a metal strip 63 is connected above the floating field plate polysilicon electrode 41.

[0009] As a preferred embodiment, the first dielectric oxide layer 31 and the floating field plate polysilicon electrode 41 therein include two identical circular grooves, and the direction of the circular grooves is parallel to the source-drain direction, wherein the floating field plate polysilicon electrode 41 near the drain end is connected to the upper metal strip.

[0010] In a preferred embodiment, when the depth of the longitudinal floating field plate is less than the depth of the second conductivity type drift region 21, it depletes the entire drift region; when the longitudinal floating field plate is inserted into the substrate, it simultaneously depletes the first conductivity type semiconductor substrate 11 and the second conductivity type drift region 21.

[0011] As a preferred embodiment, the floating field plate polycrystalline silicon electrode 41 is made of polycrystalline silicon or metal; the first conductivity type semiconductor substrate 11 is made of bulk silicon, gallium nitride, silicon carbide, or SOI; and the first dielectric oxide layer 31 is an oxide layer or a low-k dielectric.

[0012] As a preferred embodiment, the first dielectric oxide layer 31 of the continuously depleted cells is composed of two connected circular grooves of different sizes, and the floating field plate polycrystalline silicon electrode 41 is located only in the larger circular groove.

[0013] As a preferred embodiment, the first dielectric oxide layer 31 of the continuous depletion cell is a number of circular grooves of the same size and connected to each other, perpendicular to the source and drain directions. In each circular groove, the floating field plate polysilicon electrode 41 is located in the first dielectric oxide layer 31, and the polysilicon electrode at the center of the continuous depletion cell is connected to the metal strip on the upper layer.

[0014] As a preferred embodiment, the first dielectric oxide layer 31 is a structure formed by multiple elongated ellipses, wherein the polycrystalline silicon electrode 41 is an elongated elliptical structure inside the first dielectric oxide layer 31.

[0015] As a preferred embodiment, the first dielectric oxide layer 31 is a dumbbell-shaped structure composed of larger circular grooves at both ends and a smaller circular groove in the middle. The floating field plate polycrystalline silicon electrode 41 is located in the larger circular grooves at both ends. The dumbbell-shaped floating field plate structure is arranged alternately along the source-drain direction. The adjacent floating field plate polycrystalline silicon electrodes 41 in the direction perpendicular to the source-drain direction are connected to the upper metal strip. The dumbbell-shaped dielectric layer has one or more smaller circular grooves in the middle.

[0016] As a preferred embodiment, the voltage-resistant layer with equipotential floating grooves formed by the longitudinal floating field plate is applied to diodes, Schottky diodes, MOS devices, IGBT devices, and JBS devices.

[0017] As a preferred embodiment, the device introduces a first conductive type buried layer 02, and the longitudinal floating field plate simultaneously depletes the first conductive type buried layer 02 and the second conductive type drift region 21. The first conductive type buried layer 02 is located on the surface, in the middle or at the bottom of the groove of the second conductive type drift region 21.

[0018] As a preferred embodiment, the device incorporates a first conductivity type independent deep buried layer 01, which is obtained by injection through slots after grooving, forming an independent buried layer surrounding the bottom of each longitudinal floating field plate.

[0019] To achieve the above-mentioned objective, the present invention also provides a method for manufacturing a depletion-self-continuous uniform low-resistivity device, comprising the following steps:

[0020] Step 1: Select a semiconductor substrate 11 of the first type of conductivity;

[0021] Step 2: Ion implantation of impurities of the second conductivity type is performed, and the thermal process is used to advance the formation of the drift region 21 of the second conductivity type;

[0022] Step 3: Select the spacing of the groove structure, and form two adjacent cylindrical groove structures through photolithography and etching;

[0023] Step 4: Generate the first dielectric oxide layer 31 within the groove structure;

[0024] Step 5: Deposit polycrystalline silicon and etch it onto the silicon plane to form the floating field plate polycrystalline silicon electrode 41;

[0025] Step 6: Form the second dielectric oxide layer 32, and then form the third dielectric oxide layer 33;

[0026] Step 7: Ion implantation of a first type of conductivity impurity and push-junction to form a first type of conductivity well region 12, and then ion implantation of a second type of conductivity impurity and push-junction to form a second type of conductivity well region 22;

[0027] Step 8: Deposit and etch polysilicon to form the control gate polysilicon electrode 42;

[0028] Step 9: Ion implantation forms a first conductivity type semiconductor contact region 13 and a second conductivity type semiconductor contact region 23;

[0029] Step 10: Deposit and planarize an oxide layer on the surface to form the fourth dielectric oxide layer 34;

[0030] Step 11: Etch the third dielectric oxide layer 33 and the fourth dielectric oxide layer 34 to form the drift region metal via 53, and then etch the fourth dielectric oxide layer 34 to form the source via 51 and the drain via 52.

[0031] Step 12: Deposit and etch to form source metal 61, drain metal 62, and metal strip 63.

[0032] As a preferred method, the first conductivity type well region 12 and the second conductivity type well region 22 obtained by ion implantation and push-junction in step 7 are formed by multiple ion implantations and activations with different energies.

[0033] As a preferred embodiment, all of the dielectric oxide layers are formed by thermal growth or by deposition and etching.

[0034] The beneficial effects of this invention are as follows: The first dielectric oxide layer 31 and the polycrystalline silicon electrode 41 therein constitute a longitudinal floating field plate, forming a continuous depletion cell, which is distributed throughout the entire second conductivity type drift region 21. Since the dielectric constant of the dielectric layer is lower than that of the silicon layer, the dielectric layer can withstand a higher voltage for the same length. The first dielectric oxide layer with a double-elliptical or long-elliptical structure, along with the floating field plate polycrystalline silicon electrode 41, forms a continuous depletion cell. Compared to the discrete depletion cells formed by the first dielectric oxide layer and the floating field plate polycrystalline silicon electrode 41 in a single-slot structure, when a high voltage is applied to the drain, a floating potential is coupled out on the polycrystalline silicon electrode in the continuous depletion cell to clamp the potential. Furthermore, since there is an overlapping region between the continuous depletion cells, they can simultaneously deplete the second conductivity type drift region. Because the continuous depletion cell can effectively deplete the silicon layer, it enhances the depletion continuity, thereby improving the device's withstand voltage and providing a low-resistance current path. Furthermore, the floating field plate polysilicon electrode can modulate the electric field in the drift region, resulting in a more uniform electric field distribution and further improving the device's breakdown voltage. It can also increase the injection dose in the drift region, reducing the specific on-resistance. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the depletion-self-continuous uniform low-resistivity device structure of Example 1;

[0036] Figure 2 This is a top view of the depletion-self-continuous uniform low-resistivity device structure of Example 1;

[0037] Figure 3 This is a top view of the depletion-self-continuous uniform low-resistivity device structure of Example 2;

[0038] Figure 4 This is a top view of the depletion-self-continuous uniform low-resistivity device structure of Example 3;

[0039] Figure 5 This is a top view of the depletion-self-continuous uniform low-resistivity device structure of Example 4;

[0040] Figure 6 This is a top view of the depletion-self-continuous uniform low-resistivity device structure of Example 5;

[0041] Figure 7 This is a top view of the depletion-self-continuous uniform low-resistivity device structure of Example 6;

[0042] Figure 8 This is a schematic diagram of the depletion-self-continuous uniform low-resistivity device structure in Example 7;

[0043] Figure 9 This is a schematic diagram of the depletion-self-continuous uniform low-resistivity device structure in Example 8;

[0044] Figure 10 This is a schematic diagram of the depletion-self-continuous uniform low-resistivity device structure in Example 9;

[0045] Figure 11 This is a schematic diagram of the depletion-self-continuous uniform low-resistivity device structure of Example 10;

[0046] Figures 12(a)-12(l) are schematic diagrams of the process flow of the device described in Example 1;

[0047] Figure 13 (a) and (b) in the figure are the depletion region distribution diagrams of the device described in Example 1 and the single-slot device when they break down, respectively.

[0048] 11 is a semiconductor substrate of the first conductivity type, 12 is a well region of the first conductivity type, 13 is a semiconductor contact region of the first conductivity type, 21 is a drift region of the second conductivity type, 22 is a well region of the second conductivity type, 23 is a semiconductor contact region of the second conductivity type, 31 is a first dielectric oxide layer, 32 is a second dielectric oxide layer, 33 is a third dielectric oxide layer, 34 is a fourth dielectric oxide layer, 41 is a polysilicon electrode of the floating field plate, 42 is a polysilicon electrode of the control gate, 51 is a source via, 52 is a drain via, 53 is a metal via of the drift region, 61 is a source metal, 62 is a drain metal, 63 is a metal strip, 02 is a buried layer of the first conductivity type, and 01 is an independent deep buried layer of the first conductivity type. Detailed Implementation

[0049] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0050] Example 1

[0051] Example 1 describes a self-depleting, continuous, uniform low-resistivity device, such as... Figure 1 As shown, it specifically includes:

[0052] A first conductivity type semiconductor substrate 11, a first conductivity type well region 12, a first conductivity type semiconductor contact region 13, a second conductivity type drift region 21, a second conductivity type well region 22, a second conductivity type semiconductor contact region 23, a first dielectric oxide layer 31, a second dielectric oxide layer 32, a third dielectric oxide layer 33, a fourth dielectric oxide layer 34, a floating field plate polysilicon electrode 41, a control gate polysilicon electrode 42, a source via 51, a drain via 52, a drift region metal via 53, a source metal 61, a drain metal 62, and a metal strip 63;

[0053] In this design, the second conductivity type drift region 21 is located above the first conductivity type semiconductor substrate 11; the first conductivity type well region 12 is located to the left of the second conductivity type drift region 21; the second conductivity type well region 22 is located to the right of the second conductivity type drift region 21; the first conductivity type semiconductor contact region 13 and the second conductivity type semiconductor contact region 23 are located within the first conductivity type well region 12; the source via 51 is located on the upper surface of the first conductivity type semiconductor contact region 13 and the second conductivity type semiconductor contact region 23; and the source metal 61 is located on the upper surface of the source via 51. The second conductivity type semiconductor contact region 23 is located within the second conductivity type well region 22; the drain via 52 is located on the upper surface of the second conductivity type semiconductor contact region 23; and the drain metal 62 is located on the upper surface of the drain via 52. The second dielectric oxide layer 32 is located above the first conductivity type well region 12, with its left end in contact with the second conductivity type semiconductor contact region 23 and its right end in contact with the second conductivity type drift region 21. Region 21 is in contact; the third dielectric oxide layer 33 is located on the upper surface of the second conductivity type drift region 21 between the second dielectric oxide layer 32 on the left and the second conductivity type semiconductor contact region 23 on the right; the fourth dielectric oxide layer 34 is located above the third dielectric oxide layer 33 and covers the first conductivity type semiconductor contact region 13 and the second conductivity type semiconductor contact region 23; the control gate polysilicon electrode 42 covers the upper surface of the second dielectric oxide layer 32 and partially extends to the upper surface of the fourth dielectric oxide layer 34; the first dielectric oxide layer 31 and the floating field plate polysilicon electrode 41 constitute a longitudinal floating field plate, forming a continuous depletion cell, and the first dielectric oxide layer 31 surrounds the floating field plate polysilicon electrode 41. The longitudinal floating field plate is distributed throughout the second conductivity type drift region 21, forming a pressure-resistant layer with equipotential floating grooves; the drift region metal via 53 is located in the third dielectric oxide layer 33 and the fourth dielectric oxide layer 34, and a metal strip 63 is connected above the floating field plate polysilicon electrode 41.

[0054] When the depth of the longitudinal floating field plate is less than the depth of the second conductive type drift region 21, it depletes the entire drift region.

[0055] In this embodiment, the first dielectric oxide layer 31 and the floating field plate polysilicon electrode 41 therein include two identical circular grooves, and the direction of the circular grooves is parallel to the source-drain direction, wherein the floating field plate polysilicon electrode 41 near the drain end is connected to the upper metal strip.

[0056] Its basic working principle is as follows: Taking the first conductivity type semiconductor substrate 11 as a P-type as an example, under the gate bias voltage V G When the voltage is 0, a large voltage V is applied across the drain metal 62. D At this time, the PN junction formed by the second conductivity type drift region 21, the first conductivity type well region 12, and the first conductivity type semiconductor substrate 11 is at the drain voltage V D Under the influence of the depletion effect, depletion begins. A first dielectric oxide layer 31 and a floating field plate polysilicon electrode 41 are uniformly distributed within the second conductivity type drift region 21, forming a vertical floating field plate. During reverse breakdown, the dielectric oxide layer bears the majority of the voltage. Since the dielectric constant of silicon dioxide is less than that of silicon, the device's breakdown voltage is significantly improved. Simultaneously, when voltage is applied to the drain, a floating potential is coupled out on the polysilicon electrode in the vertical floating field plate to clamp the potential. Furthermore, due to the overlapping regions between depletion cells, the depletion cells can simultaneously deplete the second conductivity type drift region, enhancing the depletion continuity of the silicon layer and improving the device's breakdown voltage. The electrodes in the floating field plate allow for a more uniform electric field distribution in the drift region, further improving the device's breakdown voltage. Enhanced depletion continuity also allows for an increase in the injection dose into the drift region, reducing the specific on-resistance.

[0057] When the gate bias voltage V G When the voltage exceeds the threshold voltage, inversion electrons will appear on the surface of the first conductivity type well region 12 near the second dielectric oxide layer 32. A bias voltage V is applied to the drain metal 62. D Inverted electrons move from the source to the drain along the surface of the longitudinal drift region. Because the longitudinal floating field plate provides a current path in the lateral direction, electrons can flow rapidly across the surface of the drift region, and the specific on-resistance can be reduced by increasing the injection dose into the drift region. In summary, the self-continuous, depletion-based, uniform low-resistance device proposed in this invention exhibits a higher breakdown voltage and a lower specific on-resistance than conventional devices.

[0058] Figure 12 shows a schematic diagram of the process flow of Embodiment 1 of the present invention, which specifically includes the following steps:

[0059] Step 1: Select a semiconductor substrate 11 of the first type of conductivity, as shown in Figure 12(a);

[0060] Step 2: Perform high-energy ion implantation of impurities of the second conductivity type, and promote the formation of the second conductivity type drift region 21 through thermal process, as shown in Figure 12(b);

[0061] Step 3: Select the spacing of the groove structure, and form periodically arranged adjacent cylindrical groove structures through photolithography and etching, as shown in Figure 12(c);

[0062] Step 4: Generate the first dielectric oxide layer 31 within the groove structure, as shown in Figure 12(d);

[0063] Step 5: Deposit polycrystalline silicon and etch it onto the silicon plane to form a floating field plate polycrystalline silicon electrode 41, as shown in Figure 12(e);

[0064] Step 6: Form the second dielectric oxide layer 32, and then form the third dielectric oxide layer 33, as shown in Figure 12(f);

[0065] Step 7: Ion implantation of a first type of conductivity impurity and push-junction to form a first type of conductivity well region 12, and then ion implantation of a second type of conductivity impurity and push-junction to form a second type of conductivity well region 22, as shown in Figure 12(g);

[0066] Step 8: Deposit and etch polysilicon to form the control gate polysilicon electrode 42, as shown in Figure 12(h);

[0067] Step 9: Ion implantation forms a first conductivity type semiconductor contact region 13 and a second conductivity type semiconductor contact region 23, as shown in Figure 12(i);

[0068] Step 10: Deposit and planarize an oxide layer on the surface to form a fourth dielectric oxide layer 34, as shown in Figure 12(j);

[0069] Step 11: Etch the third dielectric oxide layer 33 and the fourth dielectric oxide layer 34 to form the drift region metal via 53, and then etch the fourth dielectric oxide layer 34 to form the source via 51 and the drain via 52, as shown in Figure 12(k);

[0070] Step 12: Deposit and etch to form source metal 61, drain metal 62, and metal strip 63, as shown in Figure 12(l).

[0071] It is important to note that:

[0072] In the manufacturing method described above, the second conductivity type drift region 21 formed by high-energy ion implantation and push-junction in step 2 can also be obtained by epitaxy.

[0073] In the manufacturing method described above, the first conductive type well region 12 and the second conductive type well region 22 obtained by ion implantation and push-junction in step 7 can also be formed by multiple high-energy implantations and activations of different energies.

[0074] All of the aforementioned dielectric oxide layers are formed by thermal growth or by deposition and etching.

[0075] The voltage-resistant layer with equipotential floating grooves formed by the longitudinal floating field plate is used in diodes, Schottky diodes, MOS devices, IGBT devices, and JBS devices.

[0076] The floating field plate polycrystalline silicon electrode 41 is made of polycrystalline silicon or metal; the first conductivity type semiconductor substrate 11 is made of bulk silicon, gallium nitride, silicon carbide, or SOI; the first dielectric oxide layer 31 is an oxide layer or a low-k dielectric.

[0077] Example 2

[0078] like Figure 3 The diagram shows a top view of the depletion-self-continuous uniform low-resistivity device structure of Example 2. The difference between this example and Example 1 is that the first dielectric oxide layer 31 of the continuous depletion cell is composed of two connected circular slots of different sizes, with the floating field plate polysilicon electrode 41 located only in the larger circular slot. Compared to the dielectric oxide layer composed of two circles, the current path is larger, further reducing device resistance and increasing device current. Its working principle is basically the same as that of Example 1.

[0079] Example 3

[0080] like Figure 4 The diagram shows a top view of the depletion-self-continuous uniform low-resistivity device structure of Example 3. The difference between this example and Example 1 is that the first dielectric oxide layer 31 of the continuous depletion cell consists of several interconnected circular grooves of the same size perpendicular to the source / drain direction. In each circular groove, a floating field plate polysilicon electrode 41 is located within the first dielectric oxide layer 31. The polysilicon electrode at the center of the continuous depletion cell is connected to the upper metal strip. Its working principle is basically the same as in Example 1.

[0081] Example 4

[0082] like Figure 5 The diagram shows a top view of the depletion-self-continuous uniform low-resistivity device structure of Example 4. The difference between this example and Example 1 is that the first dielectric oxide layer 31 is a structure formed by multiple elongated ellipses, wherein the polycrystalline silicon electrode 41 is an elongated elliptical structure inside the first dielectric oxide layer 31. Its working principle is basically the same as that of Example 1.

[0083] Example 5

[0084] like Figure 6The diagram shows a top view of the depletion-self-continuous uniform low-resistivity device structure of Example 5. The difference between this example and Example 1 is that the first dielectric oxide layer 31 is a dumbbell-shaped structure composed of larger circular grooves at both ends and a smaller circular groove in the middle. The floating field plate polysilicon electrode 41 is located in the larger circular grooves at both ends. The dumbbell-shaped floating field plate structure is arranged alternately along the source-drain direction. The adjacent floating field plate polysilicon electrodes 41 in the direction perpendicular to the source-drain direction are connected to the upper metal strip. There is one or more smaller circular grooves in the middle of the dumbbell-shaped dielectric layer.

[0085] This structure enhances the modulation effect of the dielectric layer on the electric field through the connection between electrodes, thereby improving the device's withstand voltage and reducing its specific on-resistance. Its working principle is basically the same as that of Example 1.

[0086] Example 6

[0087] like Figure 7 The diagram shows a top view of the depletion-self-continuous uniform low-resistivity device structure of Example 6. The difference between this example and Example 1 is that the first dielectric oxide layer 31 is a dumbbell-shaped structure composed of large circular grooves at both ends and multiple smaller circular grooves in the middle. The floating field plate polycrystalline silicon electrode 41 is located in the larger circular grooves at both ends. Its working principle is basically the same as that of Example 1.

[0088] Example 7

[0089] like Figure 8 The diagram shown is a schematic of the depletion self-continuous uniform low-resistivity device structure of Example 7. The difference between this example and Example 1 is that the longitudinal floating field plate is inserted into the substrate, which simultaneously depletes the first conductivity type semiconductor substrate 11 and the second conductivity type drift region 21. Its working principle is basically the same as that of Example 1.

[0090] Example 8

[0091] like Figure 9 The diagram shown is a schematic of the depletion self-continuous uniform low-resistivity device structure of Example 8. The difference between this example and Example 1 is that the device is an SOI device rather than a bulk silicon device. The longitudinal floating field plate is uniformly distributed in the second conductivity type drift region 21. Its working principle is basically the same as that of Example 1.

[0092] Example 9

[0093] like Figure 10The diagram shows a depletion-self-continuous uniform low-resistivity device structure of Example 9. The difference between this example and Example 1 is that the device introduces a first conductivity type buried layer 02. The longitudinal floating field plate simultaneously depletes the first conductivity type buried layer 02 and the second conductivity type drift region 21. The first conductivity type buried layer 02 is located on the surface, in the middle or at the bottom of the groove of the second conductivity type drift region 21. Its working principle is basically the same as that of Example 1.

[0094] Example 10

[0095] like Figure 11 The diagram shows a depletion-self-continuous uniform low-resistivity device structure of Example 10. The difference between this example and Example 1 is that the device introduces a discrete first conductive type buried layer 01, which is obtained by injection through slots after grooving. The resulting structure is an independent buried layer surrounding the bottom of each longitudinal floating field plate. Its working principle is basically the same as that of Example 1.

[0096] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A self-continuous uniform low-resistivity device, characterized in that... include: First conductivity type semiconductor substrate (11), first conductivity type well region (12), first conductivity type semiconductor contact region (13), second conductivity type drift region (21), second conductivity type well region (22), second conductivity type semiconductor contact region (23), first dielectric oxide layer (31), second dielectric oxide layer (32), third dielectric oxide layer (33), fourth dielectric oxide layer (34), floating field plate polysilicon electrode (41), control gate polysilicon electrode (42), source via (51), drain via (52), drift region metal via (53), source metal (61), drain metal (62), metal strip (63); Among them, the second conductivity type drift region (21) is located above the first conductivity type semiconductor substrate (11), the first conductivity type well region (12) is located to the left of the second conductivity type drift region (21), the second conductivity type well region (22) is located to the right of the second conductivity type drift region (21), the first conductivity type semiconductor contact region (13) and the second conductivity type semiconductor contact region (23) are located in the first conductivity type well region (12), the source via (51) is located on the upper surface of the first conductivity type semiconductor contact region (13) and the second conductivity type semiconductor contact region (23), and the source metal (61) is located on the upper surface of the source via (51); The second conductivity type semiconductor contact region (23) is located in the second conductivity type well region (22), the drain via (52) is located on the upper surface of the second conductivity type semiconductor contact region (23), and the drain metal (62) is located on the upper surface of the drain via (52); the second dielectric oxide layer (32) is located above the first conductivity type well region (12), and the left end of the second dielectric oxide layer (32) is in contact with the second conductivity type semiconductor contact region (23), and the right end is in contact with the second conductivity type drift region (21); the third dielectric oxide layer (33) is located on the upper surface of the second conductivity type drift region (21) between the second dielectric oxide layer (32) on the left and the second conductivity type semiconductor contact region (23) on the right; the fourth dielectric oxide layer (34) is located above the third dielectric oxide layer (33), and The first conductivity type semiconductor contact area (13) and the second conductivity type semiconductor contact area (23) are covered; the control gate polysilicon electrode (42) is covered on the upper surface of the second dielectric oxide layer (32) and partially extends to the upper surface of the fourth dielectric oxide layer (34); the first dielectric oxide layer (31) and the floating field plate polysilicon electrode (41) constitute a vertical floating field plate, forming a continuous depletion cell, and the first dielectric oxide layer (31) surrounds the floating field plate polysilicon electrode (41), the vertical floating field plate is distributed in the entire second conductivity type drift area (21), forming a pressure-resistant layer with equipotential floating grooves; the drift area metal via (53) is located in the third dielectric oxide layer (33) and the fourth dielectric oxide layer (34), and a metal strip (63) is connected above the floating field plate polysilicon electrode (41). The first dielectric oxide layer (31) and the floating field plate polysilicon electrode (41) therein include two identical circular grooves, and the direction of the circular grooves is parallel to the source-drain direction, wherein only the floating field plate polysilicon electrode (41) near the drain end is connected to the upper metal strip.

2. The self-continuous uniform low-resistivity device according to claim 1, characterized in that: When the depth of the longitudinal floating field plate is less than the depth of the second conductivity type drift region (21), it depletes the entire drift region; the longitudinal floating field plate is inserted into the substrate, which simultaneously depletes the first conductivity type semiconductor substrate (11) and the second conductivity type drift region (21).

3. The depletion-self-continuous uniform low-resistivity device according to claim 1, characterized in that: The floating field plate polycrystalline silicon electrode (41) is made of polycrystalline silicon or metal; the first conductivity type semiconductor substrate (11) is made of bulk silicon, gallium nitride, silicon carbide or SOI; the first dielectric oxide layer (31) is an oxide layer or a low-k dielectric.

4. The depletion-self-continuous uniform low-resistivity device according to claim 1, characterized in that: The first dielectric oxide layer (31) of the continuous depletion cell consists of several circular grooves of the same size and connected to each other, perpendicular to the source and drain directions. In each circular groove, the floating field plate polysilicon electrode (41) is located in the first dielectric oxide layer (31). Only the polysilicon electrode at the center of the continuous depletion cell is connected to the metal strip on the upper layer.

5. A depletion-self-continuous uniform low-resistivity device according to claim 1, characterized in that: The first dielectric oxide layer (31) is a structure formed by multiple elongated ellipses, wherein the polycrystalline silicon electrode (41) is an elongated elliptical structure inside the first dielectric oxide layer (31).

6. The depletion-self-continuous uniform low-resistivity device according to claim 1, characterized in that: The first dielectric oxide layer (31) is a dumbbell-shaped structure composed of larger circular grooves at both ends and a smaller circular groove in the middle. The floating field plate polycrystalline silicon electrode (41) is located in the larger circular grooves at both ends. The dumbbell-shaped floating field plate structure is arranged alternately along the source-drain direction. The adjacent floating field plate polycrystalline silicon electrodes (41) in the direction perpendicular to the source-drain direction are connected to the upper metal strip. There is one or more smaller circular grooves in the middle of the dumbbell-shaped dielectric layer.

7. The depletion-self-continuous uniform low-resistivity device according to claim 1, characterized in that: The voltage-resistant layer with equipotential floating grooves formed by the longitudinal floating field plate is used in diodes, Schottky diodes, MOS devices, IGBT devices, and JBS devices.

8. A depletion-self-continuous uniform low-resistivity device according to claim 1, characterized in that: The device introduces a first conductive type buried layer (02), and the longitudinal floating field plate simultaneously depletes the first conductive type buried layer (02) and the second conductive type drift region (21). The first conductive type buried layer (02) is located on the surface, in the middle or at the bottom of the second conductive type drift region (21).

9. A depletion-self-continuous uniform low-resistivity device according to claim 1, characterized in that: The device introduces a first conductivity type independent deep buried layer (01), which is obtained by injection through a slot after grooving, forming an independent buried layer surrounding the bottom of each longitudinal floating field plate.

10. A method for manufacturing a depleted self-continuous uniform low-resistivity device according to any one of claims 1 to 9, characterized in that... Includes the following steps: Step 1: Select a semiconductor substrate of the first type of conductivity (11); Step 2: Ion implantation of impurities of the second conductivity type is performed, and thermal processes are used to advance the formation of drift regions of the second conductivity type (21). Step 3: Select the spacing of the groove structure, and form two adjacent cylindrical groove structures through photolithography and etching; Step 4: Generate the first dielectric oxide layer (31) within the groove structure; Step 5: Deposit polycrystalline silicon and etch it onto the silicon plane to form a floating field plate polycrystalline silicon electrode (41). Step 6: Form the second dielectric oxide layer (32), and then form the third dielectric oxide layer (33); Step 7: Ion implantation of a first type of conductivity impurity and push-junction to form a first type of conductivity well region (12), and then ion implantation of a second type of conductivity impurity and push-junction to form a second type of conductivity well region (22). Step 8: Deposit and etch polysilicon to form a control gate polysilicon electrode (42). Step 9: Ion implantation forms a first conductivity type semiconductor contact region (13) and a second conductivity type semiconductor contact region (23); Step 10: Deposit and planarize an oxide layer on the surface to form a fourth dielectric oxide layer (34). Step 11: Etch the third dielectric oxide layer (33) and the fourth dielectric oxide layer (34) to form a drift region metal via (53), and then etch the fourth dielectric oxide layer (34) to form a source via (51) and a drain via (52). Step 12: Deposit and etch to form source metal (61), drain metal (62), and metal strip (63).

11. A method for manufacturing a depleted self-continuous uniform low-resistivity device according to claim 10, characterized in that: The first conductivity type well region (12) and the second conductivity type well region (22) obtained by ion implantation and push-junction in step 7 are formed by ion implantation and activation at different energies multiple times.

12. The method for manufacturing a depleted self-continuous uniform low-resistivity device according to claim 10, characterized in that: All of the aforementioned dielectric oxide layers are formed by thermal growth or by deposition and etching.

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