Semiconductor device structure

Abstract

A semiconductor device structure includes a first nitride semiconductor layer, a second nitride semiconductor layer, a first gate structure, a second gate structure, a first electrode, a field plate, and a temperature sensitive component. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The first gate structure is disposed on the second nitride semiconductor layer. The second gate structure is disposed on the second nitride semiconductor layer. The first electrode is disposed on the second nitride semiconductor layer and between the first gate structure and the second gate structure. The field plate extends from the first electrode over the first gate structure and the second gate structure. The temperature sensitive component is directly above the first electrode. The temperature sensitive component has a height greater than a height of the first gate structure and the second gate structure, and the temperature sensitive component is lower than a height of an upper surface of the field plate.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 202080002805.3, entitled “Semiconductor Device Structure and Method of Manufacturing Thereof”, filed on August 28, 2020. Technical Field

[0002] This disclosure relates to a semiconductor device structure, and more specifically to a semiconductor device structure including a temperature-sensitive component. Background Technology

[0003] Components containing direct bandgap semiconductors, such as semiconductor components containing III-V materials or III-V compounds (category: III-V compounds), can operate or function under a variety of conditions or in a variety of environments (e.g., at different voltages and frequencies).

[0004] Semiconductor components may include heterojunction bipolar transistors (HBTs), heterojunction field effect transistors (HFETs), high-electron-mobility transistors (HEMTs), and modulation-doped FETs (MODFETs). Summary of the Invention

[0005] According to one aspect of this disclosure, a semiconductor device structure includes a first nitride semiconductor layer, a second nitride semiconductor layer, a first gate structure, a second gate structure, a first electrode, a field plate, and a temperature-sensitive component. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer, and the bandgap of the second nitride semiconductor layer is greater than the bandgap of the first nitride semiconductor layer. The first gate structure is disposed on the second nitride semiconductor layer. The second gate structure is disposed on the second nitride semiconductor layer. The first electrode is disposed on the second nitride semiconductor layer and located between the first gate structure and the second gate structure. The field plate extends from the first electrode over the first gate structure and the second gate structure. The temperature-sensitive component is disposed on the second nitride semiconductor layer, directly above the first electrode, wherein the height of the temperature-sensitive component relative to the second nitride semiconductor layer is greater than the height of the first gate structure and the second gate structure relative to the second nitride semiconductor layer, and the height of the temperature-sensitive component relative to the second nitride semiconductor layer is lower than the height of the upper surface of the field plate relative to the second nitride semiconductor layer.

[0006] According to one aspect of this disclosure, a semiconductor device structure includes a first nitride semiconductor layer, a second nitride semiconductor layer, a first gate structure, a second gate structure, a first electrode, a first temperature-sensitive component, and a second temperature-sensitive component. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer, and the bandgap of the second nitride semiconductor layer is greater than the bandgap of the first nitride semiconductor layer. The first gate structure is disposed on the second nitride semiconductor layer. The second gate structure is disposed on the second nitride semiconductor layer. The first electrode is disposed on the second nitride semiconductor layer and located between the first gate structure and the second gate structure. The first temperature-sensitive component is disposed above the first gate structure. The second temperature-sensitive component is disposed above the second gate structure, and the distance between the first temperature-sensitive component and the second temperature-sensitive component is less than the distance between the first gate structure and the second gate structure. Attached Figure Description

[0007] When with attachment Figure 1 When reading the following detailed description, various aspects of this disclosure can be readily understood from it. It should be noted that the various features may not be drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figure 1 This is a top view of a semiconductor device structure according to some embodiments of the present disclosure.

[0009] Figure 2 According to some embodiments of this disclosure Figure 1 A cross-sectional view of the semiconductor device structure along line A-A'.

[0010] Figure 3 This is a cross-sectional view of a semiconductor device structure according to some embodiments of the present disclosure.

[0011] Figure 4 This is a top view of the layout of a plurality of semiconductor devices according to some embodiments of the present disclosure.

[0012] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F and Figure 5G Various stages of a method for manufacturing a semiconductor device structure according to some embodiments of the present disclosure are illustrated.

[0013] Throughout the accompanying drawings and detailed embodiments, common reference numerals are used to indicate the same or similar components. This disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. In this disclosure, references to forming or placing a first feature on or over a second feature may include embodiments in which the first and second features are formed or placed in direct contact, and may also include embodiments in which an additional feature may be formed or placed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] Embodiments of this disclosure are discussed in detail below. However, it should be understood that this disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of this disclosure.

[0016] This disclosure provides a semiconductor device structure including a temperature-sensitive component. The temperature-sensitive component can be integrated into the semiconductor device structure, thereby facilitating accurate temperature measurement of the semiconductor device structure. The semiconductor device structure disclosed herein can be applied to, but is not limited to, HEMT devices, particularly low-voltage HEMT devices, high-voltage HEMT devices, and radio frequency (RF) HEMT devices.

[0017] Figure 1 This is a top view of a semiconductor device structure 1a according to some embodiments of the present disclosure. For clarity, some components are omitted and some are shown with dashed lines to clearly depict the positional relationship between the temperature-sensitive element and other components. The semiconductor device structure 1a may include a gate structure 61, a gate structure 62, electrodes 71, 72, and 73, a temperature-sensitive component 90, metal layers 111, 112, and 113, and a pad 114. Electrode 71 may be disposed between gate structure 61 and gate structure 62. Gate structure 61 may be disposed between electrodes 71 and 72. Gate structure 62 may be disposed between electrodes 71 and 73. Metal layer 111 (or a first metal layer, M1) may span across gate structure 61, gate structure 62, electrodes 71, 72, and 73. Metal layer 112 (or a second metal layer, M2) 112 may be disposed on metal layer 111. Metal layer 112 may extend in a direction substantially perpendicular to metal layer 111. Temperature-sensitive component 90 may overlap with electrode 71. Temperature-sensitive component 90 may be disposed outside the region between gate structure 61 and electrode 72. Temperature-sensitive component 90 may be disposed outside the region between gate structure 62 and electrode 73. Temperature-sensitive component 90 may be electrically connected to pad 114 via metal layer 113. Metal layer 113 may be disposed at the same height as metal layer 111. Metal layer 113 may be disposed at a different height than metal layer 111.

[0018] Figure 2 According to some embodiments of this disclosure Figure 1 The image shows a cross-sectional view of a semiconductor device structure 1a along line A-A'. The semiconductor device structure 1a may include a substrate 10, a buffer layer 20, a nitride semiconductor layer 30, a nitride semiconductor layer 40, a nitride semiconductor layer 50, a gate structure 61, a gate structure 62, electrodes 71, 72, and 73, dielectric layers 81, 82, and 83, a temperature-sensitive component 90, and metal layers 111 and 112.

[0019] The substrate 10 may contain, but is not limited to, silicon (Si), doped Si, silicon carbide (SiC), germanium silicide (SiGe), gallium arsenide (GaAs), or other semiconductor materials. The substrate 10 may contain, but is not limited to, sapphire, silicon-on-insulator (SOI), or other suitable materials.

[0020] A buffer layer 20 may be disposed on the substrate 10. The buffer layer 20 may be configured to reduce defects caused by dislocations between the substrate 10 and the nitride semiconductor layer 30. The buffer layer 20 may contain, but is not limited to, nitrides such as AlN, AlGaN, etc.

[0021] A nitride semiconductor layer 30 (or channel layer) may be disposed on the buffer layer 20. The nitride semiconductor layer 30 may comprise a III-V group layer. The nitride semiconductor layer 30 may comprise, but is not limited to, group III nitrides, such as the compound In. a Al b Ga 1-a- b N, where a+b≦1. The group III nitrides further comprise, but are not limited to, for example, the compound Al. a Ga (1-a) N, where a≦1. The nitride semiconductor layer 30 may comprise a gallium nitride (GaN) layer. The bandgap of GaN is approximately 3.4 eV. The thickness of the nitride semiconductor layer 30 may range from, but is not limited to, approximately 0.5 μm to approximately 10 μm.

[0022] A nitride semiconductor layer 40 (or barrier layer) may be disposed on the nitride semiconductor layer 30. The nitride semiconductor layer 40 may comprise a III-V group layer. The nitride semiconductor layer 40 may comprise, but is not limited to, group III nitrides, such as the compound In. a Al b Ga 1-a-b N, where a+b≦1. The group III nitrides may further include, but are not limited to, compounds such as Al. a Ga (1-a) N, where a≦1. The bandgap of the nitride semiconductor layer 40 can be greater than that of the nitride semiconductor layer 30. The nitride semiconductor layer 40 may contain an aluminum gallium nitride (AlGaN) layer. The bandgap of AlGaN is approximately 4.0 eV. The thickness of the nitride semiconductor layer 40 can range from, but is not limited to, approximately 10 nm to approximately 100 nm.

[0023] A heterojunction is formed between the nitride semiconductor layer 40 and the nitride semiconductor layer 30, and the polarization of the heterojunction forms a two-dimensional electron gas (2DEG) region in the nitride semiconductor layer 30.

[0024] A nitride semiconductor layer 50 (or depletion layer) may be disposed on the nitride semiconductor layer 40. The nitride semiconductor layer 50 may be in direct contact with the nitride semiconductor layer 40. The nitride semiconductor layer 50 may be doped with impurities. The nitride semiconductor layer 50 may contain p-type dopants. It is contemplated, with careful consideration, that the nitride semiconductor layer 50 may contain a p-type doped GaN layer, a p-type doped AlGaN layer, a p-type doped AlN layer, or other suitable III-V group layers. The p-type dopants may include magnesium (Mg), beryllium (Be), zinc (Zn), and cadmium (Cd).

[0025] The nitride semiconductor layer 50 can be configured to control the concentration of 2DEG in the nitride semiconductor layer 30. The nitride semiconductor layer 50 can be used to deplete the 2DEG directly beneath the nitride semiconductor layer 50.

[0026] Gate structure 61 may be disposed on nitride semiconductor layer 50. Gate structure 61 may be disposed between electrode 71 and electrode 72. Gate structure 61 may comprise a gate metal. The gate metal may comprise titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), cobalt (Co), copper (Cu), nickel (Ni), platinum (Pt), lead (Pb), molybdenum (Mo) and its compounds (such as, but not limited to, titanium nitride (TiN), tantalum nitride (TaN), other conductive nitrides or conductive oxides), metal alloys (such as aluminum-copper alloys (Al-Cu)), or other suitable materials. Gate structure 61 may have a surface 61a (or side surface) facing electrode 72. Gate structure 61 may have a surface 61b (or side surface) opposite to surface 61a.

[0027] Gate structure 62 may be disposed on nitride semiconductor layer 50. The material of gate structure 62 may be the same as or similar to the material of gate structure 61. Gate structure 62 may have a surface 62a (or side surface) facing surface 61b. Gate structure 62 may have a surface 62b (or side surface) opposite to surface 62a.

[0028] Electrode 71 (or source electrode) may be disposed on nitride semiconductor layer 40. Electrode 71 may be in contact with nitride semiconductor layer 40. Electrode 71 may comprise, for example, but not limited to, a conductive material. The conductive material may comprise metals, alloys, doped semiconducting materials (e.g., doped crystalline silicon), or other suitable conductive materials such as Ti, Al, Ni, Cu, Au, Pt, Pd, W, TiN, or other suitable materials. Electrode 71 may comprise a multilayer structure. For example, electrode 71 may comprise a structure of two layers of different materials. Electrode 71 may comprise a three-layer structure, wherein two adjacent layers are made of different materials. Electrode 71 may be electrically connected to ground. Electrode 71 may be electrically connected to virtual ground. Electrode 71 may be electrically connected to real ground.

[0029] Electrode 72 (or drain electrode) may be disposed on nitride semiconductor layer 40. Electrode 72 may be in contact with nitride semiconductor layer 40. Electrode 72 may comprise, for example, but not limited to, a conductive material. The conductive material may comprise metals, alloys, doped semiconducting materials (e.g., doped crystalline silicon) or other suitable conductive materials, such as Ti, Al, Ni, Cu, Au, Pt, Pd, W, TiN, or other suitable materials. The structure of electrode 72 may be similar to or the same as the structure of electrode 71.

[0030] Electrode 73 (or drain electrode) may be disposed on nitride semiconductor layer 40. Electrode 71 may be disposed between electrode 72 and electrode 73. The structure of electrode 73 may be similar to or the same as the structure of electrode 71.

[0031] Dielectric layer 81 may be disposed on nitride semiconductor layer 40. Dielectric layer 81 may be disposed on gate structure 61. Gate structure 61 may be separated from electrode 71 by dielectric layer 81. Gate structure 61 may be separated from electrode 72 by dielectric layer 81. Dielectric layer 81 may be disposed on gate structure 62. Gate structure 62 may be separated from electrode 71 by dielectric layer 81. Gate structure 62 may be separated from electrode 73 by dielectric layer 81. Dielectric layer 81 may comprise oxide, nitride, oxynitride, or other suitable materials.

[0032] Extension 74 may be disposed on dielectric layer 81. Extension 74 may cover gate structure 61. Extension 74 may overlap with gate structure 61. Extension 74 may extend from electrode 71. Extension 74 may extend into region R between gate structure 61 and electrode 72. Extension 74 may be electrically connected to electrode 71. Extension 74 may be configured to act as, for example, a field plate that can control the electric field between electrodes such as gate structure 61 and electrode 72. The structure of extension 74 may be similar to or the same as the structure of electrode 71.

[0033] Extension 75 may be disposed on dielectric layer 81. Extension 75 may cover gate structure 62. Extension 75 may overlap with gate structure 62. Extension 75 may extend from electrode 71. Extension 75 may extend into the region between gate structure 62 and electrode 73. Extension 75 may be electrically connected to electrode 71. Extension 75 may be configured to act as, for example, a field plate that can control the electric field between electrodes such as gate structure 62 and electrode 73. The structure of extension 75 may be similar to or the same as the structure of electrode 71.

[0034] Dielectric layer 82 may be disposed on dielectric layer 81. The material of dielectric layer 82 may be the same as or similar to the material of dielectric layer 81. The material of dielectric layer 82 may be different from the material of dielectric layer 81.

[0035] Temperature-sensitive component 90 may be disposed on dielectric layer 82. Temperature-sensitive component 90 may have temperature-responsive characteristics, such as resistance, volume, or profile. For example, when the temperature changes, the resistance of temperature-sensitive component 90 may change, the volume of temperature-sensitive component 90 may change, or the profile of temperature-sensitive component 90 may change.

[0036] Temperature-sensitive component 90 can be disposed on electrode 71. Temperature-sensitive component 90 can be disposed above electrode 71. Temperature-sensitive component 90 can be spaced apart from electrode 71. Temperature-sensitive component 90 can be spaced apart from electrode 71 by dielectric layer 82. Temperature-sensitive component 90 can be disposed between extension 74 and extension 75. Temperature-sensitive component 90 can be disposed between gate structure 61 and gate structure 62.

[0037] The temperature-sensitive component 90 can be disposed outside the region R between the gate structure 61 and the electrode 72 along an axis (or direction) parallel to the interface between the nitride semiconductor layer 30 and the nitride semiconductor layer 40. Region R can be defined as the region between the surface 61a of the gate structure 61 and the electrode 72. The temperature-sensitive component 90 may not overlap with region R. The temperature-sensitive component 90 can be disposed outside the region between the gate structure 62 and the electrode 73. The temperature-sensitive component 90 can be disposed between the surface 61a of the gate structure 61 and the surface 62b of the gate structure 62. The temperature-sensitive component 90 can be disposed between the surface 61b of the gate structure 61 and the surface 62a of the gate structure 62. The height of the surface 74a (or upper surface) of the extension 74 can exceed the height of the surface 90a (or upper surface) of the temperature-sensitive component 90. The height of the surface 74a of the extension 74 can be the same as the height of the surface 90a of the temperature-sensitive component 90.

[0038] Temperature-sensitive component 90 can be configured to sense the temperature, for example, that of a semiconductor device structure 1a. Temperature-sensitive component 90 may comprise a temperature-sensitive material. For example, temperature-sensitive component 90 may comprise a thermistor whose resistance changes with temperature. The resistance change of temperature-sensitive component 90 may be proportional to the temperature change. There may be a linear relationship between the resistance change of temperature-sensitive component 90 and the temperature change. For example, temperature-sensitive component 90 may comprise a positive thermal coefficient material, where the resistance increases with increasing temperature. Positive thermal coefficient material may comprise, for example, TiN or other materials. Temperature-sensitive component 90 may comprise a negative thermal coefficient material, where the resistance decreases with increasing temperature. Negative thermal coefficient material may comprise, for example, polycrystalline silicon or other materials. Temperature-sensitive component 90 may comprise titanium nitride (TiN). Temperature-sensitive component 90 may comprise titanium (Ti). Temperature-sensitive component 90 may comprise aluminum (Al). Temperature-sensitive component 90 may comprise a single-layer structure. For example, the temperature-sensitive component 90 may comprise a monolayer of TiN. The temperature-sensitive component 90 may comprise a monolayer of Ti. The temperature-sensitive component 90 may comprise a monolayer of Al. The material of the temperature-sensitive component 90 may be different from the material of the extension 74. The material of the temperature-sensitive component 90 may be different from the material of the electrode 71.

[0039] Temperature-sensitive component 90 can be electrically isolated from gate structure 61. Temperature-sensitive component 90 can be electrically isolated from gate structure 62. Temperature-sensitive component 90 can be electrically isolated from electrode 71. Temperature-sensitive component 90 can be electrically isolated from electrode 72. Temperature-sensitive component 90 can be electrically isolated from electrode 73.

[0040] Metal layer 111 (or M1 layer) can be disposed on dielectric layer 82. Metal layer 111 can be electrically connected to electrode 71 through via 101. Although Figure 2 Not shown, but after careful consideration, electrode 72 can be electrically connected to layer M1 via a via existing in another cross-section. Similarly, gate structure 61 can be electrically connected to layer M1 via a via existing in another cross-section. Temperature-sensitive component 90 can be positioned between metal layer 111 and electrode 71 along an axis perpendicular to the interface between nitride semiconductor layer 30 and nitride semiconductor layer 40.

[0041] The dielectric layer 83 can be placed on the metal layer 111.

[0042] Metal layer 112 (or M2 layer) can be disposed on dielectric layer 83. Metal layer 112 can be electrically connected to metal layer 111 through via 102.

[0043] In conventional semiconductor device structures, temperature-sensitive components are external components located outside the semiconductor device structure. However, external temperature-sensitive components cannot reflect the true temperature of the device because the heat generated by the device is transferred to the external temperature-sensitive component through a relatively long conductive path. In this embodiment, the temperature-sensitive component 90 can be integrated within the semiconductor device structure 1a. The heat generated by the semiconductor device structure 1a can be transferred to the temperature-sensitive component 90 along a relatively short conductive path, thereby reflecting the accurate temperature of the semiconductor device structure 1a. Therefore, the semiconductor device structure 1a can be turned off in time before it overheats.

[0044] Since the highest temperature of the device typically occurs at the gate corner facing the drain, the temperature-sensitive component can more accurately reflect the temperature when it is positioned close to the gate structure. In this embodiment, the temperature-sensitive component 90 is positioned between the metal layer 111 and the electrode 71, minimizing the distance between the gate structure 61 and the temperature-sensitive component 90.

[0045] However, when the temperature-sensitive component is placed too close to the electrodes, especially too close to the region between the gate structure and the drain, the temperature-sensitive component may disturb the electric field. In this embodiment, the temperature-sensitive component 90 is placed outside the region R to prevent adverse effects on the electrical parameters of the semiconductor device structure 1a.

[0046] Furthermore, the temperature-sensitive component 90 is electrically isolated from the electrodes (such as the gate structure 61, electrode 71, and electrode 72) to ensure that the electrical parameters remain intact during the operation of the temperature-sensitive component 90.

[0047] After careful consideration, a layered field plate for controlling the electric field cannot serve as an effective temperature-sensitive component because there may be a non-linear relationship between the resistance change and the temperature change of such a structure. In this embodiment, the temperature-sensitive component 90 may comprise a single-layer structure, thereby ensuring a linear relationship between the resistance change and the temperature change.

[0048] Figure 3 This is a cross-sectional view of a semiconductor device structure 1b according to some embodiments of the present disclosure. Except that a temperature-sensitive component can be disposed on top of the gate structure, the structure of semiconductor device structure 1b can be similar to that of semiconductor device structure 1a.

[0049] Temperature-sensitive component 91 can be disposed on gate structure 61. Temperature-sensitive component 91 can be directly disposed on gate structure 61. Temperature-sensitive component 91 can cover extension 74. Extension 74 can be disposed between gate structure 61 and temperature-sensitive component 91 along an axis perpendicular to the interface between nitride semiconductor layer 30 and nitride semiconductor layer 40. The height of surface 91a of temperature-sensitive component 91 can exceed the height of surface 74a of extension 74. Temperature-sensitive component 92 can be disposed on gate structure 62. Temperature-sensitive component 92 can be directly disposed on gate structure 62. Extension 75 can be disposed between gate structure 62 and temperature-sensitive component 92.

[0050] Figure 4 This is a top view of the layout of device 2 according to some embodiments of the present disclosure.

[0051] Device 2 may include multiple semiconductor device structures, such as semiconductor device structure 1a.

[0052] Pad 61' can be a pad electrically connected to multiple gate structures, such as gate structure 61 and gate structure 62. Pad 71' can be a pad electrically connected to multiple source electrodes, such as electrode 71. Pad 72' can be a pad electrically connected to multiple drain electrodes, such as electrodes 72 and 73. Temperature-sensitive component 90', via 101', metal layer 111', metal layer 112', metal layer 113', and pad 114' can be similar to temperature-sensitive component 90, via 101, metal layer 111, metal layer 112, metal layer 113, and pad 114, respectively. Temperature-sensitive component 90' can be electrically connected to metal layer 113' through via 115'. Temperature-sensitive component 90' can be electrically connected to pad 114'. Metal layer 113' can be electrically isolated from metal layer 111'. Pad 114' can be electrically isolated from pad 61'. Pad 114' can be electrically isolated from pad 71'. Gasket 114' can be electrically isolated from gasket 72'.

[0053] Multiple temperature-sensitive components 90' can be housed within the device 2. The temperature-sensitive components 90' can be positioned between pads 71' and 72'. When more temperature-sensitive components 90' are distributed within the device 2, the temperature of the device 2 can be measured more accurately.

[0054] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F and Figure 5G Various stages of a method for manufacturing a semiconductor device structure according to some embodiments of the present disclosure are illustrated.

[0055] refer to Figure 5AA substrate 10 is provided. A buffer layer 20, a nitride semiconductor layer 30, a nitride semiconductor layer 40, a nitride semiconductor layer 50, a gate structure 61, and a gate structure 62 can be formed on the substrate 10. For example, the buffer layer 20, the nitride semiconductor layer 30, and the nitride semiconductor layer 40 can be formed by metal-organic chemical vapor deposition (MOCVD), epitaxial growth, or other suitable deposition steps. The nitride semiconductor layer 50 can be formed by epitaxial technology.

[0056] refer to Figure 5B A dielectric layer 81 can be formed on the nitride semiconductor layer 40, the nitride semiconductor layer 50, the gate structure 61, and the gate structure 62. The dielectric layer 81 can be conformally formed on the nitride semiconductor layer 40, the nitride semiconductor layer 50, the gate structure 61, and the gate structure 62.

[0057] refer to Figure 5C Electrodes 71, 72, and 73 can be formed on the nitride semiconductor layer 40 and the dielectric layer 81. For example, the dielectric layer 81 can be patterned to expose a portion of the nitride semiconductor layer 40, and a conductive material can then be deposited to cover the nitride semiconductor layer 40 and the dielectric layer 81. Next, the conductive material is patterned to form electrodes 71, 72, and 73.

[0058] refer to Figure 5D A dielectric layer 82' can be formed to cover electrodes 71, 72, and 73. A temperature-sensitive component 90 can be formed on the dielectric layer 82'.

[0059] refer to Figure 5E This can form a dielectric layer 82, allowing the temperature-sensitive component 90 to be embedded in the dielectric layer 82.

[0060] refer to Figure 5F Via 101 and metal layer 111 can be formed on dielectric layer 82. For example, a plurality of openings defined by dielectric layer 82 can be formed, and conductive material can then be deposited to fill the openings to form via 101 and metal layer 111.

[0061] refer to Figure 5G It can form dielectric layer 83, via 102 and metal layer 112 to create a .... Figure 2 The semiconductor device structure described and shown is the same as or similar to the semiconductor device structure 1a.

[0062] In this document, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” “lower,” “left,” and “right” are used for ease of description to describe the relationship between one element or feature as shown in the accompanying drawings and one or more other elements or features. In addition to the orientations depicted in the drawings, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 80 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly. It should be understood that when an element is referred to as “connected to” or “coupled to” another element, the element may be directly connected to or coupled to the other element, or there may be an intermediate element present.

[0063] As used herein, the terms “approximately,” “substantially,” “basically,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to instances where the event or situation occurs precisely or instances where the event or situation is close to occurring. As used herein with respect to a given value or range, the term “about” generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. A range may be expressed herein as from one endpoint to another or between two endpoints. All ranges disclosed herein include endpoints unless otherwise specified. The term “substantially coplanar” may mean that the positional difference between two surfaces located along the same plane is within a few micrometers (μm), such as within 10 μm, 5 μm, 1 μm, or 0.5 μm when located along the same plane. When a numerical value or characteristic is referred to as “substantially” the same, the term may refer to a value within ±10%, ±5%, ±1%, or ±0.5% of the average of said values.

[0064] The foregoing has summarized the features of several embodiments and detailed aspects of this disclosure. The embodiments described in this disclosure can readily serve as the basis for designing or modifying other processes and structures to achieve the same or similar purposes and / or realize the same or similar advantages of the embodiments described herein. Such equivalent constructions do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device structure, characterized in that, include: First nitride semiconductor layer; A second nitride semiconductor layer is disposed on the first nitride semiconductor layer, and the band gap of the second nitride semiconductor layer is greater than that of the first nitride semiconductor layer; the first nitride semiconductor layer includes a gallium nitride layer, and the second nitride semiconductor layer includes an aluminum gallium nitride layer; A first gate structure is disposed on the second nitride semiconductor layer; The second gate structure is disposed on the second nitride semiconductor layer; A first electrode is disposed on the second nitride semiconductor layer and located between the first gate structure and the second gate structure; The field plate extends from the first electrode to the top of the first gate structure and the second gate structure; as well as A temperature-sensitive component is disposed on the second nitride semiconductor layer and is located directly above the first electrode. The height of the temperature-sensitive component relative to the second nitride semiconductor layer is greater than the height of the first gate structure and the height of the second gate structure relative to the second nitride semiconductor layer, and the height of the temperature-sensitive component relative to the second nitride semiconductor layer is lower than the height of the upper surface of the field plate relative to the second nitride semiconductor layer. The temperature-sensitive component is disposed outside the region between the first gate structure and the drain electrode along an axis parallel to the interface between the first nitride semiconductor layer and the second nitride semiconductor layer, the drain electrode being disposed on the second nitride semiconductor layer.

2. The semiconductor device structure according to claim 1, characterized in that, It also includes a dielectric layer disposed on the first electrode and located between the first electrode and the temperature-sensitive component.

3. The semiconductor device structure according to claim 2, characterized in that, The dielectric layer is located between the field plate and the temperature-sensitive component.

4. The semiconductor device structure according to claim 1, characterized in that, The temperature-sensitive component described herein comprises a single-layer structure.

5. The semiconductor device structure according to claim 1, characterized in that, It also includes a metal layer disposed above the field plate and the temperature-sensitive component.

6. The semiconductor device structure according to claim 5, characterized in that, It also includes through holes that extend upward from the field plate to connect to the metal layer.

7. The semiconductor device structure according to claim 1, characterized in that, It also includes a pair of second electrodes, wherein the first gate structure, the second gate structure, and the first electrode are located between the pair of second electrodes.

8. The semiconductor device structure according to claim 1, characterized in that, The temperature-sensitive component is electrically isolated from the first gate structure and the second gate structure.

9. The semiconductor device structure according to claim 1, characterized in that, The temperature-sensitive component is electrically isolated from the first electrode.

10. The semiconductor device structure according to claim 1, characterized in that, The field plate includes a first extension located above the first gate structure and a second extension located above the second gate structure, and the temperature-sensitive component is located between the first extension and the second extension.

11. A semiconductor device structure, characterized in that, include: First nitride semiconductor layer; A second nitride semiconductor layer is disposed on the first nitride semiconductor layer, and the band gap of the second nitride semiconductor layer is greater than that of the first nitride semiconductor layer; the first nitride semiconductor layer includes a gallium nitride layer, and the second nitride semiconductor layer includes an aluminum gallium nitride layer; A first gate structure is disposed on the second nitride semiconductor layer; The second gate structure is disposed on the second nitride semiconductor layer; A first electrode is disposed on the second nitride semiconductor layer and located between the first gate structure and the second gate structure; A first temperature-sensitive component is disposed above the first gate structure; as well as The second temperature-sensitive component is disposed above the second gate structure, and the distance between the first temperature-sensitive component and the second temperature-sensitive component is less than the distance between the first gate structure and the second gate structure; The first temperature-sensitive component and the second temperature-sensitive component are disposed outside the region between the first gate structure and the drain electrode along an axis parallel to the interface between the first nitride semiconductor layer and the second nitride semiconductor layer, wherein the drain electrode is disposed on the second nitride semiconductor layer.

12. The semiconductor device structure according to claim 11, characterized in that, It also includes a field plate extending from the first electrode to between the first gate structure and the first temperature-sensitive component, and extending to between the second gate structure and the second temperature-sensitive component.

13. The semiconductor device structure according to claim 12, characterized in that, It also includes a dielectric layer disposed between the field plate and the first temperature-sensitive component and between the field plate and the second temperature-sensitive component.

14. The semiconductor device structure according to claim 11, characterized in that, The first temperature-sensitive component and the second temperature-sensitive component each include a single-layer structure.

15. The semiconductor device structure according to claim 11, characterized in that, It also includes a metal layer disposed above the first temperature-sensitive component and the second temperature-sensitive component.

16. The semiconductor device structure according to claim 15, characterized in that, It also includes through holes that extend upward from the first electrode to connect to the metal layer.

17. The semiconductor device structure according to claim 16, characterized in that, The through-hole is located between the first temperature-sensitive component and the second temperature-sensitive component.

18. The semiconductor device structure according to claim 11, characterized in that, It also includes a pair of second electrodes, wherein the first gate structure, the second gate structure, and the first electrode are located between the pair of second electrodes.

19. The semiconductor device structure according to claim 11, characterized in that, The first temperature-sensitive component is electrically isolated from the first gate structure, and the second temperature-sensitive component is electrically isolated from the second gate structure.

20. The semiconductor device structure according to claim 11, characterized in that, The first temperature-sensitive component and the second temperature-sensitive component are electrically isolated from the first electrode.

Images