Method of manufacturing a semiconductor structure, semiconductor structure and memory

Abstract

The application provides a semiconductor structure preparation method, a semiconductor structure and a memory. The semiconductor structure preparation method comprises the following steps: providing a substrate; sequentially forming a magnetic composite layer and a transfer mask layer on the substrate; performing a first mask etching process and a second mask etching process on the transfer mask layer to form a plurality of transfer patterns arranged in an array in the transfer mask layer; the shape of a mask pattern of the first mask etching process comprises a strip shape, and the shape of a mask pattern of the second mask etching process comprises a dot shape; etching the magnetic composite layer along the transfer patterns to form a plurality of columnar structures arranged in an array, and the columnar structures form magnetic tunnel junctions; and the adjacent columnar structures are separated by a gap. The application can facilitate the preparation of a semiconductor structure with high-density magnetic tunnel junctions, and can effectively adjust the size of the magnetic tunnel junctions and reduce the preparation difficulty of the semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a semiconductor structure, a semiconductor structure, and a memory. Background Technology

[0002] MRAM (Magnetic Random Access Memory) is a type of non-volatile magnetic random access memory. It features high-speed read and write capabilities, high integration density, and can be repeatedly written to an unlimited number of times.

[0003] MRAM comprises an array of multiple magnetic tunnel junctions (MTJs). An MTJ device can change its resistance state based on the magnetic material within it. It consists of two ferromagnetic layers and a thin insulating layer between them. When a voltage is applied across the junction of an MTJ device, the magnetic moments of the two ferromagnetic layers are aligned, allowing electrons to tunnel through the thin insulating layer, thus turning the MTJ device on. In related technologies, arrayed MTJ devices are fabricated using strip mask patterns and photolithography.

[0004] However, the above-mentioned fabrication methods are difficult to use to fabricate high-density MTJ devices and to adjust the size of MTJ devices. Summary of the Invention

[0005] This application provides a method for fabricating a semiconductor structure, a semiconductor structure, and a memory, which facilitates the fabrication of a semiconductor structure with high-density magnetic tunnel junctions and can effectively adjust the size of the magnetic tunnel junctions, thereby reducing the difficulty of fabricating the semiconductor structure.

[0006] To achieve the above objectives, in a first aspect, this application provides a method for fabricating a semiconductor structure, comprising:

[0007] Provide substrate;

[0008] A magnetic composite layer and a transfer mask layer are sequentially formed on the substrate;

[0009] A first mask etching process and a second mask etching process are performed on the transfer mask layer to form multiple transfer patterns arranged in an array in the transfer mask layer; the shape of the mask pattern in the first mask etching process includes stripes, and the shape of the mask pattern in the second mask etching process includes dots.

[0010] A magnetic composite layer is etched along a transfer pattern to form multiple columnar structures arranged in an array, which form magnetic tunnel junctions; adjacent columnar structures are separated by gaps.

[0011] In the above-described method for fabricating the semiconductor structure, optionally, the first mask etching process on the transfer mask layer includes:

[0012] A second composite mask layer, a first composite mask layer, and a first initial mask layer are sequentially formed on the transfer mask layer;

[0013] The first composite mask layer is etched along the first initial mask layer to form a plurality of initial patterns spaced apart in the first composite mask layer;

[0014] A first sacrificial mask layer is formed on the initial pattern;

[0015] The second composite mask layer is etched along the sidewall of the initial pattern to form a plurality of spaced first spacers in the second composite mask layer.

[0016] A second sacrificial mask layer is formed on the first spacer;

[0017] The transfer mask layer is etched along the second sacrificial mask layer located on the sidewall of the first spacer to form a plurality of second spacers spaced apart in the transfer mask layer;

[0018] Both the first and second spacers have strip-shaped forms.

[0019] In the above-described method for fabricating the semiconductor structure, optionally, the etching process for forming a second mask on the transfer mask layer includes:

[0020] At least one second initial mask layer is formed on the second spacer;

[0021] The second spacer is etched along the second initial mask layer to form multiple transfer patterns arranged in an array;

[0022] The transfer pattern is a transfer column.

[0023] In the above-described method for fabricating a semiconductor structure, optionally, the second initial mask layer includes a plurality of second mask patterns arranged in an array, and the shape of the second mask patterns includes dots.

[0024] In the above-described method for fabricating a semiconductor structure, it is optional to form a second initial mask layer on the second spacer.

[0025] Multiple transfer patterns are arranged at intervals to form multiple rows, and multiple transfer patterns in two adjacent rows are set in a one-to-one correspondence.

[0026] In the above-described method for fabricating a semiconductor structure, it is optional to form two second initial mask layers on the second spacer.

[0027] Forming a second initial mask layer on a second spacer includes: forming a first second initial mask layer on the second spacer; and forming a second second initial mask layer on the first second initial mask layer.

[0028] Etching the second spacer along the second initial mask layer includes: etching the second spacer along the second initial mask layer to form a plurality of first transfer patterns arranged in an array; and etching the second spacer along the first initial mask layer to form a plurality of second transfer patterns arranged in an array.

[0029] The first transfer pattern and the second transfer pattern are arranged alternately along the diagonal direction. The first transfer pattern in the same row and the second transfer pattern in the adjacent row are staggered. The first transfer pattern and the second transfer pattern together form a transfer pattern.

[0030] In the above-described method for fabricating a semiconductor structure, optionally, before etching the second composite mask layer along the first sacrificial mask layer located on the sidewall of the initial pattern, the method further includes:

[0031] Remove the first sacrificial mask layer located on the top surface of the initial pattern and the second composite mask layer, and retain the first sacrificial mask layer located on the sidewall of the initial pattern;

[0032] Remove the initial pattern;

[0033] And / or, before etching the transfer mask layer along the second sacrificial mask layer located on the sidewall of the first spacer, the method further includes:

[0034] Remove the second sacrificial mask layer located on the top surface of the first spacer and the transfer mask layer, and retain the second sacrificial mask layer located on the sidewall of the first spacer;

[0035] Remove the first spacer.

[0036] In the above-described method for fabricating the semiconductor structure, optionally, before forming at least one second initial mask layer on the second spacer, the method further includes:

[0037] A third composite mask layer is formed on the second spacer; at least one second initial mask layer is formed on the third composite mask layer;

[0038] Etching the second spacer along the second initial mask layer includes:

[0039] The third composite mask layer is etched along the second initial mask layer; the second spacer is etched along the second initial mask layer.

[0040] In the above-described method for fabricating the semiconductor structure, optionally, etching the second spacer along the second initial mask layer includes:

[0041] The second spacer is etched along the second mask pattern of the second initial mask layer until a cutting point is formed on the second spacer. The cutting point is located at the orthogonal projection position of the second mask pattern on the second spacer.

[0042] The cutting points are etched to cut the second spacer, forming multiple discrete transfer patterns.

[0043] In the above-described method for fabricating a semiconductor structure, optionally, the first composite mask layer, the second composite mask layer, and the third composite mask layer each include a hard mask layer and a fill mask layer, with the fill mask layer located on the side of the hard mask layer away from the substrate.

[0044] In the above-described method for fabricating the semiconductor structure, optionally, after forming the magnetic composite layer on the substrate and before forming the transfer mask layer, the following steps are also included:

[0045] An intermediate mask layer is formed, which is located between the magnetic composite layer and the transfer mask layer;

[0046] Before etching the magnetic composite layer along the transfer pattern, the following steps are also included:

[0047] The intermediate mask layer is etched along the transfer pattern.

[0048] In the above-described method for fabricating a semiconductor structure, optionally, the magnetic composite layer includes a second magnetic layer, an insulating layer, and a first magnetic layer stacked sequentially; the first magnetic layer is located on the side of the second magnetic layer away from the substrate.

[0049] Forming a magnetic composite layer on a substrate includes: forming a second magnetic layer on the substrate; forming an insulating layer on the second magnetic layer; and forming a first magnetic layer on the insulating layer.

[0050] Etching the magnetic composite layer along the transfer pattern includes: sequentially etching the first magnetic layer, the insulating layer, and the second magnetic layer along the transfer pattern.

[0051] In the above-described method for fabricating a semiconductor structure, optionally, the shape of the second mask pattern includes dots, and the dots of the plurality of second mask patterns are all of equal diameter.

[0052] Secondly, this application provides a semiconductor structure, which is prepared by the above-described preparation method.

[0053] Thirdly, this application provides a memory including the semiconductor structure described above.

[0054] In the aforementioned memory, optionally, there are multiple semiconductor structures arranged in an array, and an isolation structure is provided between the magnetic tunnel junctions of two adjacent semiconductor structures.

[0055] The semiconductor structure fabrication method, semiconductor structure, and memory provided in this application involve forming a magnetic composite layer and a transfer mask layer on a substrate. Two mask etching processes are performed on the transfer mask layer. The mask pattern in the first etching process includes a strip shape, and the mask pattern in the second etching process includes a dot shape. Strip-shaped second spacers are formed in the transfer mask layer using the first etching process. The second etching process then etches the second spacers, breaking them and forming multiple discrete transfer patterns. These transfer patterns are used as masks to etch the magnetic composite layer, thereby forming a magnetic tunnel junction. The two-stage mask etching process effectively increases the density of the formed magnetic tunnel junction. By adjusting the dimensions of the two etched mask patterns, the dimensions of the formed magnetic tunnel junction can be adjusted, thus effectively reducing the fabrication difficulty of the semiconductor structure with a magnetic tunnel junction.

[0056] The structure of this application, as well as its other inventive objectives and beneficial effects, will become more apparent from the description of the preferred embodiments taken in conjunction with the accompanying drawings. Attached Figure Description

[0057] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0058] Figure 1 A schematic flowchart illustrating the method for fabricating a semiconductor structure provided in this application embodiment;

[0059] Figure 2 This is a schematic diagram of the structure for forming the first initial mask layer of the semiconductor structure provided in an embodiment of this application;

[0060] Figure 3 This is a schematic diagram of the magnetic composite layer of the semiconductor structure provided in the embodiments of this application;

[0061] Figure 4 for Figure 2 Top view;

[0062] Figure 5 This is a schematic diagram of the initial pattern for forming a semiconductor structure provided in an embodiment of this application;

[0063] Figure 6 for Figure 5 Top view;

[0064] Figure 7 This is a schematic diagram of the structure for forming the first sacrificial mask layer in a semiconductor structure provided in an embodiment of this application;

[0065] Figure 8 A schematic diagram of the structure of the first sacrificial mask layer that retains the initial pattern sidewalls of the semiconductor structure provided in this application embodiment;

[0066] Figure 9 for Figure 8 Top view;

[0067] Figure 10 This is a schematic diagram of the semiconductor structure forming the first spacer provided in an embodiment of the present application;

[0068] Figure 11 for Figure 10 Top view;

[0069] Figure 12 This is a schematic diagram of the semiconductor structure used to form the second sacrificial mask layer, provided in an embodiment of this application.

[0070] Figure 13 A schematic diagram of the second sacrificial mask layer for retaining the sidewalls of the first spacer in the semiconductor structure provided in this application embodiment;

[0071] Figure 14 for Figure 13 Top view;

[0072] Figure 15 This is a schematic diagram of the semiconductor structure forming the second spacer provided in an embodiment of this application;

[0073] Figure 16 for Figure 15 Top view;

[0074] Figure 17 This is a schematic diagram of the structure for forming the second initial mask layer of the semiconductor structure provided in an embodiment of this application;

[0075] Figure 18 This is a schematic diagram of the structure of the second spacer in the semiconductor structure provided in the embodiments of this application;

[0076] Figure 19 A schematic diagram of the second spacer and the second mask pattern of the semiconductor structure provided in an embodiment of this application;

[0077] Figure 20 This is a schematic diagram of the transfer pattern of the semiconductor structure provided in the embodiments of this application;

[0078] Figure 21 This is a schematic diagram of the columnar structure of the semiconductor structure provided in the embodiments of this application;

[0079] Figure 22This is a schematic diagram of the magnetic tunnel junction of the semiconductor structure provided in the embodiments of this application;

[0080] Figure 23 A schematic diagram of the second spacer and the second mask pattern of another semiconductor structure provided in an embodiment of this application;

[0081] Figure 24 A schematic diagram of the transfer pattern of another structure of the semiconductor structure provided in the embodiments of this application;

[0082] Figure 25 A schematic diagram of a columnar structure, which is another type of semiconductor structure provided in this application embodiment;

[0083] Figure 26 This is a schematic diagram of a magnetic tunnel junction, which is another structure of the semiconductor structure provided in this application embodiment.

[0084] Explanation of reference numerals in the attached figures:

[0085] 100, Substrate; 200, Magnetic Composite Layer; 200a, Columnar Structure; 201, First Magnetic Layer; 202, Insulating Layer; 203, Second Magnetic Layer; 203a, Magnetic Base Layer; 203b, First Composite Layer; 203c, First Magnetic Intermediate Layer; 203d, Second Composite Layer; 203e, Second Magnetic Intermediate Layer; 203f, Magnetic Body Layer; 300, Transfer Mask Layer; 301, Second Spacer; 302, Transfer Pattern; 302a, First Transfer Pattern; 302b, Second Transfer Pattern; 400, First Composite Mask Layer; 400a, First Hard Mask Layer; 400 b. First filling mask layer; 401. Initial pattern; 402. First sacrificial mask layer; 500. Second composite mask layer; 500a. Second hard mask layer; 500b. Second filling mask layer; 501. First spacer; 502. Second sacrificial mask layer; 600. Third composite mask layer; 600a. Third hard mask layer; 600b. Third filling mask layer; 700. First initial mask layer; 700a. First mask pattern; 701. Second initial mask layer; 701a, 701b, 701c. Second mask pattern; 800. Intermediate mask layer; 900. Gap isolation. Detailed Implementation

[0086] The inventors of this application discovered during their research that MRAM comprises multiple memory cells arranged in an array, each memory cell containing an MTJ and a transistor. Therefore, in MRAM, the multiple magnetic tunnel junctions of the multiple memory cells are also arranged in an array. The MTJ can change its resistance state according to the magnetic material within the device. It comprises two ferromagnetic layers and a thin insulating layer between the two ferromagnetic layers, which are a reference layer and a free layer, respectively. The MTJ is connected to an external circuit via a transistor. When the transistor is turned on, a voltage signal from the external circuit is applied across the junction of the MTJ device through the transistor. This reverses the magnetic moment direction of the free layer. When the magnetic moments of the free layer and the reference layer are in the same direction, electrons can tunnel through the thin insulating layer, and the MTJ device becomes conductive.

[0087] In related technologies, arrayed MTJ devices are fabricated using strip mask patterns and photolithography. The strip mask pattern can consist of two layers, stacked together with their extension directions intersecting. At the intersection, a mask pattern for etching the MTJs is formed. This mask pattern is then transferred to the MTJ prefabrication layer via photolithography, thereby forming an array of multiple MTJs within the MTJ prefabrication layer.

[0088] In the above-described methods, the density of the fabricated MTJ is increased by increasing the density of the strip mask pattern. Alternatively, the size of the fabricated MTJ is adjusted by adjusting the size of the strip mask pattern. However, increasing the density or adjusting the size of the strip mask pattern will cause diffraction during photolithography, resulting in lower imaging accuracy during strip mask pattern transfer. This makes it difficult to fabricate high-density MTJs or to adjust the size of the MTJ, thus making MTJ fabrication quite challenging.

[0089] In view of this, the semiconductor structure fabrication method, semiconductor structure, and memory provided in this application form a magnetic composite layer and a transfer mask layer on a substrate. Two mask etching processes are performed on the transfer mask layer. The mask pattern in the first etching process includes a strip shape, and the mask pattern in the second etching process includes a dot shape. Strip-shaped second spacers are formed in the transfer mask layer using the first etching process. The second etching process etches the second spacers, breaking them and forming multiple discrete transfer patterns. The transfer patterns are used as masks to etch the magnetic composite layer, thereby forming a magnetic tunnel junction. Through the above two mask etching processes, the density of the formed magnetic tunnel junction can be effectively increased. By adjusting the size of the two mask etching patterns, the size of the formed magnetic tunnel junction can be adjusted, thus effectively reducing the fabrication difficulty of the semiconductor structure with a magnetic tunnel junction.

[0090] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be described in more detail below with reference to the accompanying drawings. In the drawings, the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout. The described embodiments are some, but not all, embodiments of this application. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application. The embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0091] Figure 1 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application. (Refer to...) Figure 1 As shown, in a first aspect, embodiments of this application provide a method for fabricating a semiconductor structure, comprising:

[0092] S100: Providing a substrate. The substrate 100 provides a structural basis for subsequent structures and processes. The material of the substrate 100 may include any or more of silicon, germanium, silicon-germanium, silicon carbide, silicon-on-insulator substrate, and germanium-on-insulator substrate. In this embodiment, at least a portion of the substrate 100 is a silicon substrate, and the silicon material may be single-crystal silicon. The substrate 100 can be prepared by chemical vapor deposition (CVD).

[0093] S200: A magnetic composite layer and a transfer mask layer are sequentially formed on the substrate.

[0094] Figure 2 This is a schematic diagram of the structure for forming the first initial mask layer of the semiconductor structure provided in an embodiment of this application. Figure 3 This is a schematic diagram of the magnetic composite layer of the semiconductor structure provided in an embodiment of this application. (Combined with...) Figure 2 and Figure 3 As shown, the transfer mask layer 300 is located on the side of the magnetic composite layer 200 away from the substrate 100. Both the magnetic composite layer 200 and the transfer mask layer 300 can be formed by deposition.

[0095] The material of the transfer mask layer 300 can be polycrystalline silicon.

[0096] Reference Figure 3As shown, the magnetic composite layer 200 includes a second magnetic layer 203, an insulating layer 202, and a first magnetic layer 201 stacked sequentially; the first magnetic layer 201 is located on the side of the second magnetic layer 203 away from the substrate 100. Forming the magnetic composite layer 200 on the substrate 100 includes: forming the second magnetic layer 203 on the substrate 100; forming the insulating layer 202 on the second magnetic layer 203; and forming the first magnetic layer 201 on the insulating layer 202. The first magnetic layer 201 can serve as a free layer, and the second magnetic layer 203 can serve as a pinned layer. Along the direction away from the substrate 100, the second magnetic layer 203 may include a magnetic base layer 203a (seed layer), a first composite layer 203b, a first magnetic intermediate layer 203c, a second composite layer 203d, a second magnetic intermediate layer 203e, and a magnetic body layer 203f stacked sequentially.

[0097] The first composite layer 203b and the second composite layer 203d can both be Co and Pt composite layers ([Co(x) / Pt(y)]m Multilayer). The material of the first magnetic intermediate layer 203c can be, but is not limited to, Ru or Ir, and the material of the second magnetic intermediate layer 203e can be, but is not limited to, Ta. The materials of the magnetic body layer 203f and the first magnetic layer 201 can both be, but are not limited to, CoFeB composite layers. The insulating layer 202 can serve as a tunnel barrier to isolate the first magnetic layer 201 and the second magnetic layer 203, and its material can be, but is not limited to, MgO.

[0098] As one feasible implementation method, refer to Figure 2 As shown, after forming the magnetic composite layer 200 on the substrate 100 and before forming the transfer mask layer 300, the process further includes forming an intermediate mask layer 800, which is located between the magnetic composite layer 200 and the transfer mask layer 300. This intermediate mask layer 800 serves as a transition layer during the etching process of the magnetic composite layer 200. It not only protects the magnetic composite layer 200 from damage during the etching of the transfer mask layer 300, but also allows the mask pattern formed by multiple mask etching processes to be transferred onto the transfer mask layer 300 in a single etching process, reducing the difficulty of etching the magnetic composite layer 200 along the mask pattern formed by multiple mask etching processes.

[0099] The intermediate mask layer 800 can be a mask layer including oxides, which can be formed by deposition. The oxide material can be, but is not limited to, silicon oxide, germanium oxide, or silicon-germanium oxide.

[0100] S300: A first mask etching process and a second mask etching process are performed on the transfer mask layer to form multiple transfer patterns arranged in an array in the transfer mask layer; the shape of the mask pattern in the first mask etching process includes stripes, and the shape of the mask pattern in the second mask etching process includes dots.

[0101] It should be noted that the mask etching process in this embodiment includes two steps. The mask pattern in the first mask etching process is strip-shaped, which can form strip-shaped second spacers 301 in the transfer mask layer 300. The first mask etching process can include multiple etching steps to increase the arrangement density of the second spacers 301, which is beneficial to increasing the density of the final magnetic tunnel junction. The mask pattern in the second mask etching process is dot-shaped, which can etch away at least a portion of each second spacer 301 to break the second spacers 301 and form multiple discrete transfer patterns 302.

[0102] The etching process of the first mask is described in detail below:

[0103] Specifically, the first mask etching process on the transfer mask layer 300 includes:

[0104] Figure 4 for Figure 2 Top view, Figure 5 This is a schematic diagram of the initial pattern for forming a semiconductor structure provided in an embodiment of this application. Figure 6 for Figure 5 A top view. Combined with... Figure 2 , Figure 4 and Figure 5 As shown, a second composite mask layer 500, a first composite mask layer 400, and a first initial mask layer 700 are sequentially formed on the transfer mask layer 300.

[0105] Both the first composite mask layer 400 and the second composite mask layer 500 include a hard mask layer and a filler mask layer, with the filler mask layer located on the side of the hard mask layer away from the substrate 100. That is, Figure 2 and Figure 5The first composite mask layer 400 shown includes a first hard mask layer 400a and a first filler mask layer 400b, with the first filler mask layer 400b located on the side of the first hard mask layer 400a away from the substrate 100. The second composite mask layer 500 includes a second hard mask layer 500a and a second filler mask layer 500b, with the second filler mask layer 500b located on the side of the second hard mask layer 500a away from the substrate 100. The first hard mask layer 400a, the first filler mask layer 400b, the second hard mask layer 500a, and the second filler mask layer 500b can all be formed by deposition. The material of the first hard mask layer 400a and the second hard mask layer 500a can be a spin-on hard mask (SOH), and the material of the first filler mask layer 400b and the second filler mask layer 500b can be SiON.

[0106] Combination Figure 2 and Figure 4 As shown, the first mask pattern 700a of the first initial mask layer 700 includes a strip shape, and multiple strip-shaped first mask patterns 700a are arranged at intervals. The size of the strip-shaped first mask patterns 700a can be adjusted as needed, thereby adjusting the size of the final magnetic tunnel junction.

[0107] Reference Figure 5 and Figure 6 As shown, the first composite mask layer 400 is etched along the first initial mask layer 700 to form a plurality of initial patterns 401 spaced apart in the first composite mask layer 400. Specifically, etching the first composite mask layer 400 along the first initial mask layer 700 may include: sequentially etching a first filling mask layer 400b and a first hard mask layer 400a along the first mask pattern 700a. The formed initial pattern 401 also includes two layers: the bottom layer near the substrate 100 is formed by the first hard mask layer 400a retained during the etching process, and the top layer away from the substrate 100 is formed by the first filling mask layer 400b retained during the etching process. The formed initial pattern 401 is also strip-shaped, and the plurality of initial patterns 401 are spaced apart on the second composite mask layer 500. The size of the initial pattern 401 depends on the size of the first mask pattern 700a.

[0108] Figure 7 This is a schematic diagram of the structure for forming the first sacrificial mask layer of the semiconductor structure provided in an embodiment of this application, with reference to... Figure 7 As shown, after forming the initial pattern 401, the method further includes forming a first sacrificial mask layer 402 on the initial pattern 401. The first sacrificial mask layer 402 can be formed by deposition, and its material can include oxides, including but not limited to silicon oxide. The first sacrificial mask layer 402 can cover the sidewalls and topwalls of the initial pattern 401.

[0109] Figure 8 This is a schematic diagram of the first sacrificial mask layer for preserving the initial pattern sidewalls of the semiconductor structure provided in an embodiment of this application. Figure 9 for Figure 8 Top view. (Refer to...) Figure 8 and Figure 9 As shown, before etching the second composite mask layer 500 along the first sacrificial mask layer 402 located on the sidewall of the initial pattern 401, the process further includes:

[0110] Remove the first sacrificial mask layer 402 located on the top surface of the initial pattern 401 and the second composite mask layer 500, retain the first sacrificial mask layer 402 located on the sidewall of the initial pattern 401, and remove the initial pattern 401.

[0111] It should be noted that the first sacrificial mask layer 402 is etched, retaining only the first sacrificial mask layer 402 located on the sidewall of the initial pattern 401. This process can be completed using photomask etching. Afterwards, the initial pattern 401 is removed, a process that can be completed using wet etching, thereby forming... Figure 8 The structure is as follows. The retained first sacrificial mask layer 402 is also a strip structure, and its arrangement density is higher than that of the initial pattern 401. By using the retained first sacrificial mask layer 402 as a mask to continue etching the second composite mask layer 500, the arrangement density of the first spacer 501 subsequently formed in the second composite mask layer 500 can be increased.

[0112] Figure 10 This is a schematic diagram of the semiconductor structure forming the first spacer provided in an embodiment of this application. Figure 11 for Figure 10 A top view. Combined with... Figure 10 and Figure 11 As shown, the second composite mask layer 500 is etched along the sidewall of the initial pattern 401 using the first sacrificial mask layer 402 to form a plurality of spacers 501 spaced apart in the second composite mask layer 500. The formed first spacers 501 are also strip-shaped structures, and each first spacer 501 comprises two layers: a bottom layer near the substrate 100 is a second hard mask layer 500a retained during the etching process, and a top layer away from the substrate 100 is a second filler mask layer 500b retained during the etching process.

[0113] After the first spacer 501 is formed, the process of forming the sacrificial mask layer and etching is repeated again, specifically:

[0114] Figure 12 This is a schematic diagram of the semiconductor structure used to form the second sacrificial mask layer, provided in an embodiment of this application. Figure 13 This is a schematic diagram of the second sacrificial mask layer that retains the sidewalls of the first spacer in the semiconductor structure provided in this application embodiment. Figure 14 for Figure 13 A top view. Combined with... Figures 12 to 14 As shown, a second sacrificial mask layer 502 is formed on the first spacer 501. The material and formation method of the second sacrificial mask layer 502 and the first sacrificial mask layer 402 can be the same, which will not be described in detail in this embodiment. The second sacrificial mask layer 502 covers the sidewalls and top wall of the first spacer 501.

[0115] Before etching the transfer mask layer 300 along the second sacrificial mask layer 502 located on the sidewall of the first spacer 501, the process further includes: removing the second sacrificial mask layer located on the top surface of the first spacer 501 and the transfer mask layer 300, retaining the second sacrificial mask layer located on the sidewall of the first spacer 501, and removing the first spacer 501.

[0116] It should be noted that the second sacrificial mask layer 502 is etched, leaving only the second sacrificial mask layer 502 located on the sidewall of the first spacer 501. This process can be completed using photomask etching. Then, the first spacer 501 is removed, which can be completed using wet etching, thereby forming... Figure 13 The structure is as follows. The retained second sacrificial mask layer 502 is also a strip structure, and its arrangement density is higher than that of the first spacer 501. By using the retained second sacrificial mask layer 502 as a mask to continue etching the transfer mask layer 300, the arrangement density of the second spacer 301 subsequently formed in the transfer mask layer 300 can be increased.

[0117] Figure 15 This is a schematic diagram of the semiconductor structure forming the second spacer provided in an embodiment of this application. Figure 16 for Figure 15 Top view. (Refer to...) Figure 15 and Figure 16 As shown, the transfer mask layer 300 is etched along the sidewall of the first spacer 501 by the second sacrificial mask layer 502 to form a plurality of second spacers 301 spaced apart in the transfer mask layer 300. The formed second spacers 301 are all strip-shaped. The second spacers 301 are formed by the transfer mask layer 300 retained by the etching.

[0118] It should be noted that the two processes of forming the sacrificial mask layer and etching performed in this embodiment constitute the self-aligned quadruple patterning (SAQP) process. During this process, the mask pattern density can be increased by etching the sacrificial mask layer to regenerate the mask pattern. In some embodiments, the processes of forming the sacrificial mask layer and etching can be performed multiple times, and this embodiment does not limit this.

[0119] The etching process for the second mask is described in detail below:

[0120] The etching process for forming a second mask on the transfer mask layer 300 includes:

[0121] Figure 17 This is a schematic diagram of the structure for forming the second initial mask layer of the semiconductor structure provided in an embodiment of this application, with reference to... Figure 17 As shown, at least one second initial mask layer 701 is formed on the second spacer 301.

[0122] It should be noted that before forming at least one second initial mask layer 701 on the second spacer 301, the process further includes:

[0123] A third composite mask layer 600 is formed on the second spacer 301; at least one second initial mask layer 701 is formed on the third composite mask layer 600. The third composite mask layer 600 includes a third hard mask layer 600a and a third filler mask layer 600b, with the third filler mask layer 600b located on the side of the third hard mask layer 600a away from the substrate 100. The material of the third hard mask layer 600a can be spin-coated hard mask SOH, and the material of the third filler mask layer 600b can be SiON.

[0124] After forming the second initial mask layer 701, the process further includes: etching the second spacer 301 along the second initial mask layer 701 to form a plurality of transfer patterns 302 arranged in an array. The transfer patterns 302 are transfer pillars. Specifically, etching the second spacer 301 along the second initial mask layer 701 includes: etching the third composite mask layer 600 along the second initial mask layer 701; and etching the second spacer 301 along the second initial mask layer 701.

[0125] It should be noted that etching the second spacer 301 along the second initial mask layer 701 includes:

[0126] The second spacer 301 is etched along the second mask pattern of the second initial mask layer 701 until a cutting point is formed on the second spacer 301. The cutting point is located at the orthogonal projection position of the second mask pattern on the second spacer 301. The cutting point is etched to cut the second spacer 301, forming multiple discrete transfer patterns 302. This cutting point can serve as a pre-etching position point in the etching process, reducing the difficulty of etching and improving the etching accuracy of the discrete transfer patterns 302.

[0127] As a first feasible mask pattern, the second initial mask layer 701 includes multiple arrayed second mask patterns, the shapes of which include dot-like shapes. These dot-like second mask patterns can not only form cutting points on the strip-shaped second spacer 301 during etching, breaking the second spacer 301 to form discrete transfer patterns 302, but also adjust the size of the dot-like second mask patterns to adjust the cutting positions, thereby adjusting the size of the formed transfer pattern 302 and ultimately adjusting the size of the formed magnetic tunnel junction. Since the second spacer 301 is strip-shaped, and multiple cutting points are formed on the second spacer 302, the resulting transfer pattern 302 is columnar, i.e., a transfer column.

[0128] In this embodiment, the second mask pattern can be a dot. The size of the transfer pattern 302 can be adjusted by adjusting the diameter of the dot, the distance between adjacent dots, and the width of the strip-shaped second spacer 301.

[0129] After forming the transfer pattern 302, the process further includes: S400: etching a magnetic composite layer along the transfer pattern to form multiple columnar structures arranged in an array, the columnar structures forming a magnetic tunnel junction; and gaps separating adjacent columnar structures.

[0130] It should be noted that, based on this embodiment, the magnetic tunnel junction includes a stacked second magnetic layer 203, an insulating layer 202 and a first magnetic layer 201. Therefore, etching the magnetic composite layer 200 along the transfer pattern 302 includes: sequentially etching the first magnetic layer 201, the insulating layer 202 and the second magnetic layer 203 along the transfer pattern 302.

[0131] It should be noted that the gap isolation 900 between adjacent columnar structures 200a can be formed by spacing adjacent columnar structures 200a apart, with a gap between them. Alternatively, an insulating material can be filled between adjacent columnar structures 200a, forming the gap isolation 900. This embodiment does not limit the specific structure of the gap isolation 900. The gap isolation 900 can effectively block the transmission of electrical signals between adjacent columnar structures 200a, thereby ensuring the stability of electrical signal transmission within the columnar structures 200a and improving the performance stability of the semiconductor structure. Furthermore, when the gap isolation 900 is formed of an insulating material, the gap material can provide supporting force for the columnar structures 200a, preventing them from tilting or collapsing, thereby improving the structural stability of the columnar structures 200a and the semiconductor structure.

[0132] In this embodiment, two achievable mask patterns for the second initial mask layer 701 are provided:

[0133] Figure 18 This is a schematic diagram of the structure of the second spacer in the semiconductor structure provided in an embodiment of this application. Figure 19 This is a schematic diagram of the second spacer and the second mask pattern of the semiconductor structure provided in an embodiment of this application. Figure 20 This is a schematic diagram of the transfer pattern of the semiconductor structure provided in the embodiments of this application. Figure 21 This is a schematic diagram of the columnar structure of the semiconductor structure provided in the embodiments of this application. Figure 22 This is a schematic diagram of the magnetic tunnel junction of the semiconductor structure provided in the embodiments of this application.

[0134] Combination Figures 18 to 22 As shown, as a first feasible mask pattern, a second initial mask layer 701 is formed on the second spacer 301; multiple transfer patterns 302 are arranged at intervals to form multiple rows, and multiple transfer patterns 302 in adjacent rows are set in a one-to-one correspondence.

[0135] It should be noted that the structure of the second spacer 301 before the second mask etching process can be referred to Figure 18 The second initial mask layer 701 has a second mask pattern 701a. The orthographic projection of the second mask pattern 701a onto the second spacer 301 overlaps with at least a portion of the second spacer 301. The second mask pattern 701a includes a plurality of dots arranged in an array. The plurality of dots are spaced apart along the extension direction of the second spacer 301. After etching, a plurality of breakpoints are formed on the second spacer 301, thereby forming a plurality of discrete transfer patterns 302. The dots in adjacent rows or adjacent columns are all set in a one-to-one correspondence, thereby ensuring that the arrangement of the plurality of transfer patterns 302 formed is the same as the arrangement of the dots, that is, the transfer patterns 302 in adjacent rows or adjacent columns are set in a one-to-one correspondence. Figure 19 In the diagram, x indicates the column direction and y indicates the row direction, both of which lie in the same plane.

[0136] Reference Figure 20 As shown, among the multiple transfer patterns 302, at least some of the transfer patterns 302 can form a quadrilateral. When the distance between two adjacent rows of transfer patterns 302 is equal to the distance between two adjacent columns of transfer patterns 302, the quadrilateral can be a square. The magnetic composite layer 200 is etched along the transfer patterns 302 to form a columnar structure 200a, which is a magnetic tunnel junction. Figure 21 and Figure 22 The arrangement of the magnetic tunnel junction is shown. The distance between any two adjacent columnar structures 200a is 'a'. Four adjacent columnar structures 200a1, 200a2, 200a3, and 200a4 in the plurality of columnar structures 200a form a unit, and the area occupied by the unit is 'a'. 2 .

[0137] This arrangement of magnetic tunnel structures results in a relatively regular structure, which can effectively reduce the difficulty of fabricating semiconductor structures with this magnetic tunnel junction.

[0138] Figure 23 This is a schematic diagram of the second spacer and the second mask pattern, representing another structure of the semiconductor structure provided in this application embodiment. Figure 24 This is a schematic diagram of the transfer pattern of another semiconductor structure provided in an embodiment of this application. Figure 25 This is a schematic diagram of a columnar structure, which is another type of semiconductor structure provided in this application embodiment. Figure 26 This is a schematic diagram of another structure of a magnetic tunnel junction, which is a semiconductor structure provided in an embodiment of this application.

[0139] Combination Figures 23 to 26 As shown, as a second achievable mask pattern, two second initial mask layers 701 are formed on the second spacer 301.

[0140] Forming a second initial mask layer 701 on the second spacer 301 includes: forming a first second initial mask layer 701 on the second spacer 301; and forming a second second initial mask layer 701 on the first second initial mask layer 701.

[0141] Etching the second spacer 301 along the second initial mask layer 701 includes: etching the second spacer 301 along the second initial mask layer 701 to form a plurality of first transfer patterns 302a arranged in an array; and etching the second spacer 301 along the first initial mask layer 701 to form a plurality of second transfer patterns 302b arranged in an array.

[0142] The first transfer pattern 302a and the second transfer pattern 302b are arranged alternately along the diagonal direction. The first transfer pattern 302a located in the same row and the second transfer pattern 302b located in the adjacent row are staggered. The first transfer pattern 302a and the second transfer pattern 302b together form the transfer pattern 302.

[0143] It should be noted that, referring to Figure 23 As shown, the first second initial mask layer 701 has a second mask pattern 701b, and the second second initial mask layer 701 has a second mask pattern 701c. Both the second mask pattern 701b and the second mask pattern 701c are dot-shaped, located in different rows, and are staggered. The first transfer pattern 302a and the second transfer pattern 302b are arranged alternately along a diagonal direction or alternately along a direction parallel to the diagonal direction. Figure 23In the diagram, x indicates the column direction, y indicates the row direction, and z indicates the diagonal direction. x, y, and z are all in the same plane.

[0144] Reference Figure 24 As shown, the transfer pattern 302 formed by etching the second spacer 301 along the two second initial mask layers 701 includes a first transfer pattern 302a and a second transfer pattern 302b. The first transfer pattern 302a and the second transfer pattern 302b located in different rows are staggered, and the first transfer pattern 302a and the second transfer pattern 302b can form a hexagon. By adjusting the distance between two adjacent rows of the first transfer pattern 302a and the second transfer pattern 302b, the formed hexagon can be a regular hexagon.

[0145] Combination Figure 25 and Figure 26 As shown, the columnar structures 200a formed by etching the magnetic composite layer 200 along the transfer pattern 302 can also be arranged in a hexagon. The spacing between adjacent columnar structures 200a can be 'a'. Four adjacent columnar structures 200a1, 200a2, 200a3, and 200a4 in a plurality of columnar structures 200a form a unit, and the area occupied by the unit is _____.

[0146] Compared to the first mask pattern embodiment described above, this configuration reduces the area occupied by the cells by 13%, thus decreasing the area occupied by the cells and increasing the density of the magnetic tunnel junctions. Furthermore, among magnetic tunnel junctions with the same density, hexagonal magnetic tunnel junctions exhibit a higher etching rate during etching compared to square magnetic tunnel junctions, which is more beneficial to the etching process and reduces the fabrication difficulty of the magnetic tunnel junctions.

[0147] In the two mask pattern embodiments described above, the shapes of the second mask patterns 701a, 701b, and 701c include dots, and the diameters of the dots in the plurality of second mask patterns 701a, 701b, and 701c are all equal. This effectively reduces the fabrication difficulty of the second initial mask layer 701, and also reduces the difficulty of etching the second spacer 301 along the second initial mask layer 701, thus lowering the fabrication difficulty of the semiconductor. Furthermore, this arrangement can also improve the structural regularity of the fabricated magnetic tunnel junction.

[0148] It should be noted that, referring to Figure 20 , Figure 22 , Figure 24 and Figure 26 As shown, the second spacer 301 is etched along the second initial mask layer 701, and the edge of the resulting transfer pattern 302 has a sharp corner portion. This can make the edge of the columnar structure 200a gradually become smooth during the subsequent etching process of the columnar structure 200a, thereby forming a cylindrical magnetic tunnel junction.

[0149] Secondly, embodiments of this application provide a semiconductor structure, which is fabricated using the above-described fabrication method. This semiconductor structure can be a magnetic tunnel junction.

[0150] Thirdly, embodiments of this application provide a memory including the aforementioned semiconductor structure. This memory can be an MRAM memory, which may include multiple memory cells arranged in an array. Each memory cell may include a transistor and the aforementioned magnetic tunnel junction. The magnetic tunnel junction is connected to an external circuit via the transistor. When the transistor is turned on, a voltage signal from the external circuit is applied across the junction of the magnetic tunnel junction. This reverses the magnetic moment direction of the free layer in the magnetic tunnel junction. When the magnetic moment directions of the free layer and the reference layer are the same, electrons can tunnel through the thin insulating layer 202, the magnetic tunnel junction becomes active, and the voltage signal from the external circuit is stored in the memory cell.

[0151] In the aforementioned memory, optionally, there are multiple semiconductor structures arranged in an array, with an isolation structure between the magnetic tunnel junctions of adjacent semiconductor structures. Since the memory cells are arranged in an array, the magnetic tunnel junctions in each memory cell are also arranged in an array. The isolation structure between adjacent magnetic tunnel junctions can be made of an insulating material, effectively blocking the transmission of electrical signals between adjacent magnetic tunnel junctions, thereby ensuring the stable performance of each memory cell. Unlike the gap isolation 900 mentioned above, this isolation structure can be a shallow trench isolation (STI) formed in the substrate 100, which can be formed before the magnetic tunnel junction fabrication and is mainly used to block signal interference between adjacent memory cells.

[0152] Other technical features in the semiconductor structure and memory of this application are the same as those in the embodiments of the above-described semiconductor structure preparation method, and can achieve the same technical effects, and will not be described in detail here.

[0153] In the above description, it should be understood that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection or an indirect connection through an intermediate medium, or the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances. The terms "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In the description of this application, "multiple" means two or more, unless otherwise precisely specified.

[0154] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0155] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A magnetic composite layer and a transfer mask layer, consisting of a second magnetic layer, an insulating layer and a first magnetic layer, are sequentially formed on the substrate. A first mask etching process and a second mask etching process are performed on the transfer mask layer to form multiple transfer patterns arranged in an array in the transfer mask layer; The mask pattern of the first mask etching process is a strip extending along a first direction, used to form a plurality of strip-shaped second spacers that extend continuously along the first direction and are spaced apart in the transfer mask layer; the mask pattern of the second mask etching process is a dot-shaped circle with equal diameter. During the second mask etching process, cutting points are formed and etched on the strip-shaped second spacer along the dot mask pattern, separating the continuous strip-shaped second spacer into multiple transfer patterns in the form of transfer pillars; the dot mask is arranged in two forms: a single layer of dot pattern forms multiple rows with adjacent rows corresponding one-to-one, or two layers of dot pattern are arranged diagonally alternately. The second magnetic layer, the insulating layer, and the first magnetic layer are sequentially etched along the transfer pattern to form multiple columnar structures arranged in an array, wherein the columnar structures form a magnetic tunnel junction; The adjacent columnar structures are separated by gaps; The first mask etching process on the transfer mask layer includes: A second composite mask layer, a first composite mask layer, and a first initial mask layer are sequentially formed on the transfer mask layer; The first composite mask layer is etched along the first initial mask layer to form a plurality of initial patterns spaced apart in the first composite mask layer; A first sacrificial mask layer is formed on the initial pattern; The second composite mask layer is etched along the first sacrificial mask layer located on the sidewall of the initial pattern to form a plurality of spaced first spacers in the second composite mask layer; A second sacrificial mask layer is formed on the first spacer; The transfer mask layer is etched along the second sacrificial mask layer located on the sidewall of the first spacer to form a plurality of spaced second spacers in the transfer mask layer; Both the first spacer and the second spacer have a strip-like shape; The etching process for forming a second mask on the transfer mask layer includes: At least one second initial mask layer is formed on the second spacer; The second spacer is etched along the second initial mask layer to form multiple transfer patterns arranged in an array; The transfer pattern is a transfer column.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, Two initial mask layers are formed on the second spacer; Forming the second initial mask layer on the second spacer includes: forming a first layer of the second initial mask layer on the second spacer; and forming a second layer of the second initial mask layer on the first layer of the second initial mask layer. Etching the second spacer along the second initial mask layer includes: etching the second spacer along the second initial mask layer to form a plurality of first transfer patterns arranged in an array; etching the second spacer along the first initial mask layer to form a plurality of second transfer patterns arranged in an array. The first transfer pattern and the second transfer pattern are arranged alternately along a diagonal direction. The first transfer pattern in the same row and the second transfer pattern in the adjacent row are staggered. The first transfer pattern and the second transfer pattern together form the transfer pattern.

3. The method for preparing a semiconductor structure according to any one of claims 1-2, characterized in that, Before etching the second composite mask layer along the first sacrificial mask layer located on the sidewall of the initial pattern, the method further includes: Remove the first sacrificial mask layer located on the top surface of the initial pattern and the second composite mask layer, and retain the first sacrificial mask layer located on the sidewall of the initial pattern; Remove the initial pattern; And / or, before etching the transfer mask layer along the second sacrificial mask layer located on the sidewall of the first spacer, the method further includes: Remove the second sacrificial mask layer located on the top surface of the first spacer and the transfer mask layer, and retain the second sacrificial mask layer located on the sidewall of the first spacer; Remove the first spacer.

4. The method for preparing a semiconductor structure according to any one of claims 1-2, characterized in that, Before forming at least one layer of the second initial mask layer on the second spacer, the method further includes: A third composite mask layer is formed on the second spacer; at least one second initial mask layer is formed on the third composite mask layer; Etching the second spacer along the second initial mask layer includes: The third composite mask layer is etched along the second initial mask layer; the second spacer is etched along the second initial mask layer.

5. The method for preparing a semiconductor structure according to any one of claims 1-2, characterized in that, Etching the second spacer along the second initial mask layer includes: The second spacer is etched along the mask pattern of the second initial mask layer until a cut point is formed on the second spacer, the cut point being located at the orthogonal projection position of the mask pattern on the second spacer; The cutting points are etched to cut the second spacer, forming a plurality of discrete transfer patterns.

6. The method for preparing a semiconductor structure according to claim 4, characterized in that, The first composite mask layer, the second composite mask layer, and the third composite mask layer each include a hard mask layer and a filler mask layer, wherein the filler mask layer is located on the side of the hard mask layer away from the substrate.

7. The method for preparing a semiconductor structure according to any one of claims 1-2, characterized in that, After forming the magnetic composite layer on the substrate and before forming the transfer mask layer, the process further includes: An intermediate mask layer is formed, which is located between the magnetic composite layer and the transfer mask layer; Before etching the magnetic composite layer along the transfer pattern, the process further includes: The intermediate mask layer is etched along the transfer pattern.

8. The method for preparing a semiconductor structure according to any one of claims 1-2, characterized in that, The first magnetic layer is located on the side of the second magnetic layer away from the substrate; Forming the magnetic composite layer on the substrate includes: forming a second magnetic layer on the substrate; forming the insulating layer on the second magnetic layer; and forming the first magnetic layer on the insulating layer. Etching the magnetic composite layer along the transfer pattern includes: sequentially etching the first magnetic layer, the insulating layer, and the second magnetic layer along the transfer pattern.

9. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the preparation method according to any one of claims 1-8.

10. A memory, characterized in that, Includes the semiconductor structure described in claim 9.

11. The memory according to claim 10, characterized in that, The semiconductor structure is multiple, and the multiple semiconductor structures are arranged in an array. An isolation structure is provided between the magnetic tunnel junctions of two adjacent semiconductor structures.

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