Carbon nanotube backside dual gate field effect transistor and method of making the same

Abstract

The present disclosure provides a carbon nanotube back double-gate field effect transistor, comprising: a carbon nanotube active layer, the carbon nanotube active layer serving as a channel layer of the field effect transistor; a source electrode, the source electrode being arranged on a first side of the carbon nanotube active layer; a drain electrode, the drain electrode being arranged on the first side of the carbon nanotube active layer, and the source electrode and the drain electrode being arranged at intervals along a first direction; a back double-gate structure, the back double-gate structure being arranged on a second side of the carbon nanotube active layer, and the back double-gate structure comprising a first back gate electrode and a second back gate electrode, the first back gate electrode and the second back gate electrode being arranged at intervals along the first direction. The present disclosure also provides a field effect transistor preparation method.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a carbon nanotube back-side dual-gate field-effect transistor and its fabrication method. Background Technology

[0002] Semiconductor-type carbon nanotubes have a series of advantages such as high carrier mobility, extremely low intrinsic capacitance, ultra-high thermal conductivity, and easy three-dimensional heterogeneous integration, making them an ideal channel material for building next-generation high-speed, low-power CMOS technology.

[0003] However, carbon nanotube materials have low effective carrier mass and narrow band gap (the band gap of a 1.3 nm diameter semiconductor carbon nanotube is only 0.5–0.6 eV). Under the strong electric field applied to the gate, the carriers in the carbon nanotube channel are prone to quantum tunneling, resulting in severe reverse leakage current at the drain of the carbon nanotube device.

[0004] Therefore, novel device structures are needed to suppress gate-induced drain leakage (GIDL effect) in order to reduce the static power consumption of carbon-based CMOS technology. Summary of the Invention

[0005] To address at least one of the aforementioned technical problems, this disclosure provides a carbon nanotube back-side dual-gate field-effect transistor and its fabrication method.

[0006] According to one aspect of this disclosure, a carbon nanotube back-side dual-gate field-effect transistor is provided, comprising:

[0007] A carbon nanotube active layer, which serves as the channel layer of the field-effect transistor;

[0008] A source electrode is disposed on the first side of the active layer of the carbon nanotube.

[0009] A drain electrode is disposed on a first side of the active layer of the carbon nanotube, and the source electrode and the drain electrode are disposed at a distance along a first direction;

[0010] A back-side dual-gate structure is disposed on the second side of the carbon nanotube active layer. The back-side dual-gate structure includes a first back-gate electrode and a second back-gate electrode, which are spaced apart along the first direction.

[0011] According to at least one embodiment of the carbon nanotube back-side dual-gate field-effect transistor of the present disclosure, a first back gate electrode is disposed adjacent to the source electrode and is used to control the turn-on and turn-off of the field-effect transistor, and a second back gate electrode is disposed adjacent to the drain electrode and is used to suppress gate-induced leakage (GIDL) of the drain electrode.

[0012] A carbon nanotube back-side dual-gate field-effect transistor according to at least one embodiment of the present disclosure further includes a first dielectric layer and a gate dielectric layer, wherein the first back gate electrode and the second back gate electrode are embedded in the first dielectric layer, and the gate dielectric layer is formed between the carbon nanotube active layer and the first dielectric layer.

[0013] According to at least one embodiment of the carbon nanotube back-side dual-gate field-effect transistor of the present disclosure, the first end face of the first back gate electrode and the first end face of the second back gate electrode are both in contact with the gate dielectric layer, the second end face of the first back gate electrode and the circumferential surface between the first end face and the second end face are wrapped by the first dielectric layer, and the second end face of the second back gate electrode and the circumferential surface between the first end face and the second end face are wrapped by the first dielectric layer.

[0014] According to at least one embodiment of the carbon nanotube back-side dual-gate field-effect transistor of the present disclosure, a first diffusion barrier layer is disposed at the interface between the first dielectric layer and the first back gate electrode, and a second diffusion barrier layer is disposed at the interface between the first dielectric layer and the second back gate electrode.

[0015] A carbon nanotube back-side dual-gate field-effect transistor according to at least one embodiment of the present disclosure, wherein the equivalent oxide layer thickness of the gate dielectric layer is less than or equal to 10 nanometers.

[0016] A carbon nanotube back-side dual-gate field-effect transistor according to at least one embodiment of the present disclosure further includes a threshold control layer and a second dielectric layer. The threshold control layer is disposed on the carbon nanotube active layer, and the second dielectric layer is disposed on the threshold control layer. The source electrode and the drain electrode are both at least partially embedded within the second dielectric layer. The source electrode and the drain electrode are both in contact with the carbon nanotube active layer through the threshold control layer via the second dielectric layer.

[0017] According to at least one embodiment of the carbon nanotube back-side dual-gate field-effect transistor of the present disclosure, both the source electrode and the drain electrode include a metal conductive layer and an ohmic contact layer. The ohmic contact layer is disposed outside the metal conductive layer to separate the metal conductive layer from the second dielectric layer, the threshold control layer and the carbon nanotube active layer.

[0018] According to at least one embodiment of the present disclosure, a carbon nanotube back-side dual-gate field-effect transistor is provided, wherein the field-effect transistor is an N-type field-effect transistor, and the ohmic contact layer is preferably a metal or alloy with a work function of less than 4.5 electron volts as the N-type ohmic contact layer.

[0019] According to at least one embodiment of the present disclosure, a carbon nanotube back-side dual-gate field-effect transistor is a P-type field-effect transistor, wherein the ohmic contact layer is preferably a metal or alloy with a work function greater than 4.5 electron volts as a P-type ohmic contact layer.

[0020] According to at least one embodiment of the carbon nanotube back-side dual-gate field-effect transistor of the present disclosure, the threshold control layer can be controllably doped to obtain a target doping concentration or a target fixed charge density to obtain a target threshold voltage of the field-effect transistor.

[0021] According to at least one embodiment of the carbon nanotube back-side dual-gate field-effect transistor of the present disclosure, the threshold control layer serves as an etch barrier layer of the second dielectric layer, preferably, the etch selectivity of the etch barrier layer is greater than 5.

[0022] According to another aspect of this disclosure, a method for fabricating a field-effect transistor is provided, for fabricating a carbon nanotube back-side dual-gate field-effect transistor according to any of the above embodiments, the method comprising:

[0023] A grid trench structure is formed on the first dielectric layer;

[0024] A diffusion barrier material layer is deposited on the gate trench structure, and a gate metal material layer is deposited on the diffusion barrier material layer;

[0025] The gate metal material layer is chemically and mechanically polished to form a first back gate electrode, a second back gate electrode, a first diffusion barrier layer and a second diffusion barrier layer within the gate trench structure;

[0026] A gate dielectric layer is grown such that the gate dielectric layer covers the common end face of the first back gate electrode, the second back gate electrode, the first diffusion barrier layer, the second diffusion barrier layer, and the first dielectric layer;

[0027] The carbon nanotube active layer is deposited on the gate dielectric layer;

[0028] A threshold modulation layer is deposited on the active layer of the carbon nanotubes, and a second dielectric layer is deposited on the threshold modulation layer.

[0029] Source contact holes and drain contact holes are formed on the second dielectric layer and the threshold control layer;

[0030] An ohmic contact layer and a metal conductive layer are deposited in both the source contact hole and the drain contact hole.

[0031] The common end face of the ohmic contact layer, the metal conductive layer and the second dielectric layer is chemically mechanically polished to form the source electrode and the drain electrode.

[0032] According to a field-effect transistor fabrication method of at least one embodiment of the present disclosure, the gate trench structure is formed by dry etching on a first dielectric layer. Attached Figure Description

[0033] The accompanying drawings illustrate exemplary embodiments of the present disclosure and, together with the description thereof, serve to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification.

[0034] Figure 1 This is a schematic cross-sectional view of a carbon nanotube back-side dual-gate field-effect transistor according to one embodiment of the present disclosure.

[0035] Figure 2 This is a schematic diagram of a back-side dual-gate structure fabricated in a field-effect transistor fabrication method according to one embodiment of the present disclosure.

[0036] Figure 3 This is a schematic diagram illustrating the fabrication of the gate dielectric layer, carbon nanotube active layer, threshold modulation layer, and second dielectric layer of a carbon nanotube backside dual-gate field-effect transistor according to one embodiment of the present disclosure.

[0037] Figure 4 Is Figure 3 Based on this, a schematic diagram of the further fabrication of the source electrode and drain electrode is shown.

[0038] Figure 5 This is a schematic flowchart of a field-effect transistor fabrication method according to one embodiment of the present disclosure.

[0039] Explanation of reference numerals in the attached figures

[0040] 100 Carbon nanotube back-side dual-gate field-effect transistor

[0041] 101 First Dielectric Layer

[0042] 102 Gate dielectric layer

[0043] 103 Carbon nanotube active layer

[0044] 104 Threshold Control Layer

[0045] 105 Second dielectric layer

[0046] 106 Metal conductive layer

[0047] 107 Ohm Contact Layer

[0048] 110 Diffusion Barrier Material Layer

[0049] 111 First diffusion barrier layer

[0050] 112 Second diffusion barrier layer

[0051] 120 gate metal material layer

[0052] 1011 Grid structure

[0053] 1012 end face

[0054] 1051 end face

[0055] S source electrode

[0056] D drain electrode

[0057] G1 First Back Gate Electrode

[0058] G2 Second back gate electrode. Detailed Implementation

[0059] The present disclosure will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the present disclosure are shown in the accompanying drawings.

[0060] It should be noted that, where there is no conflict, the embodiments and features described in this disclosure can be combined with each other. The technical solutions of this disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0061] Unless otherwise stated, the exemplary implementations / embodiments shown are to be understood as providing exemplary features of various details that provide ways in which the technical concepts of this disclosure can be implemented in practice. Therefore, unless otherwise stated, the features of various implementations / embodiments may be additionally combined, separated, interchanged and / or rearranged without departing from the technical concepts of this disclosure.

[0062] The use of crosshairs and / or shading in the accompanying drawings is generally used to clarify the boundaries between adjacent components. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, dimensions, proportions, commonalities between the illustrated components, or any other characteristics, properties, etc., of the components. Furthermore, in the accompanying drawings, the dimensions and relative dimensions of components may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, a specific process sequence may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Moreover, the same reference numerals denote the same components.

[0063] When a component is referred to as being "on" or "above" another component, "connected to," or "joined to" another component, the component may be directly on, directly connected to, or directly joined to the other component, or there may be intermediate components. However, when a component is referred to as being "directly on" another component, "directly connected to," or "directly joined to" another component, there are no intermediate components. Therefore, the term "connection" can refer to a physical connection, an electrical connection, etc., and may or may not have intermediate components.

[0064] For descriptive purposes, this disclosure may use spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side (e.g., in a “sidewall”)” to describe the relationship between one component and another component as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are also intended to encompass different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, a component described as “below” or “under” another component or feature would subsequently be positioned “above” said other component or feature. Thus, the exemplary term “below” can encompass both “above” and “below” orientations. Furthermore, the device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), thus interpreting the spatial relative descriptive terms used herein accordingly.

[0065] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “the” are intended to include the plural forms as well. Furthermore, when the terms “comprising” and / or “including” and variations thereof are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, parts, components, and / or groups thereof, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, parts, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than as terms of degree, thus explaining the inherent biases in measurements, calculated values, and / or provided values ​​that would be recognized by one of ordinary skill in the art.

[0066] The following text is for reference only. Figures 1 to 5 The present invention provides a detailed description of the carbon nanotube back-side dual-gate field-effect transistor and its fabrication method.

[0067] First refer to Figure 1 According to one embodiment of this disclosure, the carbon nanotube back-side dual-gate field-effect transistor 100 of this disclosure includes:

[0068] Carbon nanotube active layer 103 serves as the channel layer of field-effect transistor 100.

[0069] Source electrode S is disposed on the first side of the carbon nanotube active layer 103.

[0070] Drain electrode D is disposed on the first side of carbon nanotube active layer 103, and source electrode S and drain electrode D are disposed at intervals along the first direction.

[0071] The back-side dual-gate structure is disposed on the second side of the carbon nanotube active layer 103. The back-side dual-gate structure includes a first back-gate electrode G1 and a second back-gate electrode G2, which are disposed at intervals along a first direction.

[0072] The carbon nanotube active layer 103 disclosed herein can use the carbon nanotube active layer described in Chinese Patent CN110137356B. Those skilled in the art can also use carbon nanotube active layers prepared by other processes, all of which fall within the protection scope of this disclosure.

[0073] According to a preferred embodiment of this disclosure, the active carbon nanotube layer 103 is a semiconductor carbon nanotube, and its arrangement includes, but is not limited to, a randomly arranged carbon nanotube network and a directionally arranged carbon nanotube array.

[0074] The first and second sides of the carbon nanotube active layer 103 are opposite sides of the carbon nanotube active layer 103.

[0075] refer to Figure 1 The first side of the carbon nanotube active layer 103 described above is the upper side of the carbon nanotube active layer 103, and the second side of the carbon nanotube active layer 103 is the lower side of the carbon nanotube active layer 103.

[0076] In this disclosure, the source electrode S and drain electrode D can be as follows: Figure 1 The frustum shape / prismatic shape shown, which is wider at the top and narrower at the bottom, can also be a cylindrical shape or a regular prism shape. Those skilled in the art, under the guidance of the technical solutions disclosed herein, may select / adjust the shapes of the source electrode and the drain electrode, and all such selections / adjustments fall within the protection scope of this disclosure.

[0077] The shapes of the first back gate electrode and the second back gate electrode disclosed herein can also be frustum shape / prismatic shape with a wider top and narrower bottom, or cylindrical shape or regular prism shape. The shape of the back gate electrode can be the same as or different from the shape of the source electrode and the drain electrode.

[0078] The gate metal materials of the first back gate electrode G1 and the second back gate electrode G2 of the field-effect transistor 100 disclosed herein include, but are not limited to, one or any combination of tungsten, molybdenum, copper, heavily doped polysilicon.

[0079] Preferably, the gate metal material of this disclosure is tungsten.

[0080] refer to Figure 1 The carbon nanotube back-side dual-gate field-effect transistor 100 disclosed herein, by setting a back-side dual-gate structure and setting the source electrode S and drain electrode D to be spaced apart along a first direction, and setting the first back gate electrode G1 and the second back gate electrode G2 to be spaced apart along the first direction, enables the carbon nanotube back-side dual-gate field-effect transistor 100 disclosed herein to effectively suppress the leakage current of the drain electrode, especially the gate-induced drain current.

[0081] According to a preferred embodiment of the present disclosure, the first back gate electrode G1 of the carbon nanotube back-side dual-gate field-effect transistor 100 is disposed near the source electrode S, and the first back gate electrode G1 is used to control the turn-on and turn-off of the field-effect transistor 100. The second back gate electrode G2 is disposed near the drain electrode D, and the second back gate electrode G2 is used to suppress gate-induced leakage current of the drain electrode D.

[0082] refer to Figure 1 The field-effect transistor 100 of this disclosure sets the first back gate electrode G1 as a proximity to the source electrode S and the second back gate electrode G2 as a proximity to the drain electrode D, so that the first back gate electrode G1 of this disclosure serves as a switch to control the opening and closing of the field-effect transistor 100, and the second back gate electrode G2 serves as a leakage current suppression control electrode for the drain electrode D of the field-effect transistor 100.

[0083] refer to Figure 1 According to a preferred embodiment of this disclosure, the area where the back-side dual-gate structure is disposed on the second side of the carbon nanotube active layer 103 is the area directly opposite the area between the source electrode and the drain electrode.

[0084] According to some embodiments of this disclosure, the first back gate electrode G1 is at least partially opposite to the source electrode S, and the second back gate electrode G2 is at least partially opposite to the drain electrode D.

[0085] For the carbon nanotube back-side dual-gate field-effect transistor 100 of the above embodiments, preferably, refer to Figure 1 The carbon nanotube back-side dual-gate field-effect transistor 100 disclosed herein also includes a first dielectric layer 101 and a gate dielectric layer 102, a first back gate electrode G1 and a second back gate electrode G2 embedded in the first dielectric layer 101, and the gate dielectric layer 102 formed between the carbon nanotube active layer 103 and the first dielectric layer 101.

[0086] The material composition of the gate dielectric layer 102 disclosed herein includes, but is not limited to, one or any combination thereof, of hafnium oxide, aluminum oxide, yttrium oxide, scandium oxide, lanthanum oxide, zirconium oxide, silicon oxide, titanium oxide, tantalum oxide, beryllium oxide, aluminum nitride, silicon nitride, boron nitride, and carbon nitride. Any selection / adjustment of the material composition of the gate dielectric layer 102 by those skilled in the art based on the technical solutions of this disclosure falls within the protection scope of this disclosure.

[0087] According to a preferred embodiment of the present disclosure, the first dielectric layer 101 is compatible with silicon-based copper interconnect technology, and the material composition of the first dielectric layer 101 is preferably silicon oxide or low-k dielectric.

[0088] According to a preferred embodiment of this disclosure, the first back gate electrode G1 and the second back gate electrode G2 are fabricated using a tungsten through-hole process, and the gate metal material is selected as tungsten metal grown by CVD process.

[0089] Still referencing Figure 1 According to the preferred embodiment of the carbon nanotube back-side dual-gate field-effect transistor 100 of this disclosure, the first end face (upper end face in the figure) of the first back gate electrode G1 and the first end face (upper end face in the figure) of the second back gate electrode G2 are both in contact with the gate dielectric layer 102. The second end face (lower end face in the figure) of the first back gate electrode G1 and the circumferential surface (i.e., circumferential side surface) between the first end face and the second end face are wrapped by the first dielectric layer 101. The second end face of the second back gate electrode G2 and the circumferential surface (i.e., circumferential side surface) between the first end face and the second end face are also wrapped by the first dielectric layer 101.

[0090] For the carbon nanotube back-side dual-gate field-effect transistor 100 of the above embodiments, preferably, refer to Figure 1 A first diffusion barrier layer 111 is provided at the interface between the first dielectric layer 101 and the first back gate electrode G1, and a second diffusion barrier layer 112 is provided at the interface between the first dielectric layer 101 and the second back gate electrode G2.

[0091] According to a preferred embodiment of the present disclosure, the diffusion barrier layer (including the first diffusion barrier layer 111 and the second diffusion barrier layer 112) is a high melting point material, and the material composition of the diffusion barrier layer includes, but is not limited to, one or any combination of titanium, tantalum, cobalt, ruthenium, titanium nitride, tantalum nitride, molybdenum nitride, and tungsten nitride.

[0092] According to a preferred embodiment of the present disclosure, the equivalent oxide layer thickness of the gate dielectric layer 102 of the carbon nanotube back-side dual-gate field-effect transistor 100 of the present disclosure is less than or equal to 10 nanometers.

[0093] refer to Figure 1According to a preferred embodiment of the present disclosure, the carbon nanotube backside dual-gate field-effect transistor 100 further includes a threshold control layer 104 and a second dielectric layer 105. The threshold control layer 104 is disposed on the carbon nanotube active layer 103, and the second dielectric layer 105 is disposed on the threshold control layer 104. The source electrode S and the drain electrode D are both at least partially embedded in the second dielectric layer 105. The source electrode S and the drain electrode D are both in contact with the carbon nanotube active layer 103 through the threshold control layer 104 via the second dielectric layer 105.

[0094] For the field-effect transistor 100 of this disclosure, the material composition of the threshold control layer 104 includes, but is not limited to, one or any combination of aluminum oxide, yttrium oxide, scandium oxide, aluminum nitride, silicon nitride, silicon carbide, amorphous silicon, and amorphous carbon.

[0095] For the field-effect transistor 100 of this disclosure, the first dielectric layer 101 and the second dielectric layer 105 can be any insulating dielectric, and the material composition of both includes, but is not limited to, one or any combination of silicon oxide, carbon-doped silicon oxide, silicon nitride, boron nitride, polyimide, and BCB resin.

[0096] refer to Figure 1 According to the preferred embodiment of the carbon nanotube backside dual-gate field-effect transistor 100 of the present disclosure, both the source electrode S and the drain electrode D include a metal conductive layer 106 and an ohmic contact layer 107. The ohmic contact layer 107 is disposed on the outside of the metal conductive layer 106 to isolate the metal conductive layer 106 from the second dielectric layer 105, the threshold control layer 104 and the carbon nanotube active layer 103.

[0097] For the carbon nanotube backside dual-gate field-effect transistor 100 of this disclosure, the material composition of the metal conductive layer 106 of the source electrode S and the drain electrode D includes, but is not limited to, one or any combination of tungsten, molybdenum, copper, cobalt, nickel, aluminum, and gold.

[0098] Those skilled in the art, inspired by the technical solutions disclosed herein, may select or adjust the material composition of the metal conductive layer 106, and all such selections or adjustments fall within the protection scope of this disclosure.

[0099] The carbon nanotube back-side dual-gate field-effect transistor 100 of the above-described embodiments can be fabricated as an N-type field-effect transistor or a P-type field-effect transistor.

[0100] When the carbon nanotube back-side dual-gate field-effect transistor 100 disclosed herein is an N-type field-effect transistor, the ohmic contact layer 107 is preferably a metal or alloy with a work function of less than 4.5 electron volts to serve as the N-type ohmic contact layer.

[0101] For the N-type field-effect transistor of this disclosure, the material composition of the N-type ohmic contact layer includes, but is not limited to, one or any combination of scandium, yttrium, aluminum, titanium, hafnium, and zirconium.

[0102] When the carbon nanotube back-side dual-gate field-effect transistor 100 disclosed herein is a P-type field-effect transistor, the ohmic contact layer 107 is preferably a metal or alloy with a work function greater than 4.5 electron volts to serve as the P-type ohmic contact layer.

[0103] For the P-type field-effect transistor of this disclosure, the material composition of the P-type ohmic contact layer includes, but is not limited to, one or any combination of palladium, rhodium, platinum, gold, and nickel.

[0104] According to one embodiment of this disclosure, the N-type field-effect transistor selects aluminum oxide as the threshold control layer 104, the P-type field-effect transistor selects yttrium oxide as the threshold control layer 104, and the second dielectric layer 105 selects a silicon oxide and silicon nitride stacked structure. When the silicon oxide and silicon nitride are etched by fluorine-based gas dry etching, the etching finally stops on the aluminum oxide or yttrium oxide threshold control layer 104, and the etching selectivity is greater than 10.

[0105] According to one embodiment of the present disclosure, in a carbon nanotube back-side dual-gate field-effect transistor 100, the threshold control layer 104 can be controllably doped to obtain a target doping concentration or a target fixed charge density, thereby obtaining a target threshold voltage of the field-effect transistor 100.

[0106] According to another embodiment of the present disclosure, in the carbon nanotube backside dual-gate field-effect transistor 100, the threshold control layer 104 serves as the etch barrier layer of the second dielectric layer 105, and preferably, the etch selectivity of the etch barrier layer is greater than 5.

[0107] refer to Figures 2 to 5 According to one embodiment of this disclosure, the field-effect transistor fabrication method S100 of this disclosure includes the following steps:

[0108] S101, A gate trench structure 1011 is formed on the first dielectric layer 101 (reference) Figure 2 );

[0109] S102. Deposit a diffusion barrier material layer 110 on the gate trench structure 1011, and deposit a gate metal material layer 120 on the diffusion barrier material layer 110 (reference). Figure 2 );

[0110] S103. Perform chemical mechanical polishing on the gate metal material layer 120 to form a first back gate electrode G1, a second back gate electrode G2, a first diffusion barrier layer 111 and a second diffusion barrier layer 112 within the gate trench structure 1011.

[0111] S104. Grow a gate dielectric layer 102 such that the gate dielectric layer 102 covers the common end face 1012 of the first back gate electrode G1, the second back gate electrode G2, the first diffusion barrier layer 111, the second diffusion barrier layer 112, and the first dielectric layer 101 (reference). Figure 3 );

[0112] S105, Deposit a carbon nanotube active layer 103 on the gate dielectric layer 102 (reference) Figure 3 );

[0113] S106. Deposit a threshold modulation layer 104 on the carbon nanotube active layer 103, and deposit a second dielectric layer 105 on the threshold modulation layer 104 (reference). Figure 3 );

[0114] S107. Source contact holes and drain contact holes are formed on the second dielectric layer 105 and the threshold control layer 104.

[0115] S108. An ohmic contact layer 107 and a metallic conductive layer 106 are deposited in both the source and drain contact holes (see reference). Figure 4 );

[0116] S109. The common end face 1051 of the ohmic contact layer 107, the metal conductive layer 106 and the second dielectric layer 105 is chemically mechanically polished to form the source electrode S and the drain electrode D.

[0117] refer to Figure 2 The gate trench structure 1011 described in this disclosure includes two gate trenches, the shapes of which are respectively matched with the shapes of the first back gate electrode G1 and the second back gate electrode G2 described above.

[0118] In step S101, preferably, the pattern of the back gate electrode is formed by photolithography on the first dielectric layer 101 (silicon oxide), and the gate trench structure (including two gate trenches) described above is formed by dry etching.

[0119] In step S102, preferably, a diffusion barrier material layer 110 (titanium nitride) is deposited by PVD process, and a gate metal material layer 120 (tungsten metal) is deposited by CVD process.

[0120] In step S103, preferably, the first back gate electrode G1, the second back gate electrode G2, the first diffusion barrier layer 111 and the second diffusion barrier layer 112 are formed using a chemical mechanical polishing (CMP) method.

[0121] In step S104, preferably, the gate dielectric layer 102 (hafnium oxide) is grown using atomic layer deposition (ALD) method, and the thickness of the gate dielectric layer is preferably 5 nanometers.

[0122] In step S105, preferably, a carbon nanotube active layer 103 (an array of oriented carbon nanotubes) is deposited on the gate dielectric layer 102, and the surface of the array of oriented carbon nanotubes is cleaned.

[0123] In step S106, preferably, 10 nm aluminum oxide or yttrium oxide is grown using an ALD process as a threshold control layer 104, and the threshold voltage of the field-effect transistor device is adjusted by controlling the process conditions; a second dielectric layer 105 is grown using an ICP-CVD process, preferably using a SiO2 / Si3N4 stack as the second dielectric layer 105, to form a passivation layer and an electrical isolation layer.

[0124] In step S107, preferably, the second dielectric layer 105 (SiO2 / Si3N4) is etched using a fluorine-based gas dry etching method, and the etching stops at the threshold control layer 104 (alumina or yttrium oxide). Subsequently, the underlying alumina or yttrium oxide is removed by wet etching to form source contact holes and drain contact holes.

[0125] In step S108, preferably, an ohmic contact layer 107 is deposited using a PVD process, with Sc (scandium) selected as the ohmic contact layer for the N-type field-effect transistor and Pd (palladium) selected as the ohmic contact layer for the P-type field-effect transistor; and tungsten metal is deposited using a CVD process as a metal conductive layer 106 to form the metal conductive layer of the source and drain electrodes.

[0126] In step S109, preferably, the source electrode S and drain electrode D are formed by chemical mechanical polishing (CMP) to complete the fabrication of the carbon nanotube back-side dual-gate field-effect transistor 100.

[0127] It should be noted that any adjustments made by those skilled in the art to the processes, materials, etc., in each step based on the preparation method described above in this disclosure fall within the protection scope of this disclosure.

[0128] As can be seen from the above description of the carbon nanotube back-side dual-gate field-effect transistor and its fabrication method, the present disclosure uses a back-side dual-gate structure to suppress the gate-induced drain leakage effect of the carbon nanotube field-effect transistor. The first back gate electrode is used to control the switching of the transistor, and the second back gate electrode is used to suppress drain leakage.

[0129] Compared to conventional carbon nanotube top-gate self-aligned field-effect transistors in the prior art, the novel back-side dual-gate carbon nanotube field-effect transistor disclosed in this invention significantly reduces off-state leakage current. Furthermore, the back-side dual-gate structure employed in this invention reduces the difficulty of device fabrication, as the back-side gate electrode deposition and etching are completed before carbon nanotube deposition, avoiding physical damage to the carbon nanotube channel caused by plasma etching of the gate electrode. Simultaneously, the threshold control layer and the second dielectric layer effectively passivate the carbon nanotube channel during the process, significantly reducing contamination caused by water, oxygen, photoresist residue, and metal ions in the process environment, improving process repeatability and device reliability, representing a significant technological advancement.

[0130] The field-effect transistor fabrication method disclosed herein simplifies the device manufacturing process, making it easy for carbon-based CMOS technology to be integrated with silicon-based copper interconnect technology in three dimensions, thus expanding the application potential of carbon-based integrated circuits in high-speed and low-power fields.

[0131] In the description of this specification, the references to terms such as "one embodiment / mode," "some embodiments / modes," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment / mode or example is included in at least one embodiment / mode or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment / mode or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments / modes or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments / modes or examples described in this specification, as well as the features of different embodiments / modes or examples.

[0132] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0133] Those skilled in the art should understand that the above embodiments are merely for illustrating the present disclosure and are not intended to limit the scope of the disclosure. Those skilled in the art can make other changes or modifications based on the above disclosure, and these changes or modifications still fall within the scope of the present disclosure.

Claims

1. A carbon nanotube back-side dual-gate field-effect transistor, characterized in that, include: A carbon nanotube active layer, which serves as the channel layer of the field-effect transistor; A source electrode is disposed on the first side of the active layer of the carbon nanotube. A drain electrode is disposed on a first side of the active layer of the carbon nanotube, and the source electrode and the drain electrode are disposed at a distance along a first direction; as well as A back-side dual-gate structure is disposed on the second side of the carbon nanotube active layer. The back-side dual-gate structure includes a first back-gate electrode and a second back-gate electrode, which are spaced apart along the first direction. The first back gate electrode is disposed near the source electrode and is used to control the turn-on and turn-off of the field-effect transistor. The second back gate electrode is disposed near the drain electrode and is used to suppress gate-induced leakage current of the drain electrode. The carbon nanotube back-side dual-gate field-effect transistor further includes a first dielectric layer and a gate dielectric layer, with the first back gate electrode and the second back gate electrode embedded in the first dielectric layer, and the gate dielectric layer formed between the carbon nanotube active layer and the first dielectric layer. The first end face of the first back gate electrode and the first end face of the second back gate electrode are both in contact with the gate dielectric layer. The second end face of the first back gate electrode and the circumferential surface between the first end face and the second end face are wrapped by the first dielectric layer. The second end face of the second back gate electrode and the circumferential surface between the first end face and the second end face are also wrapped by the first dielectric layer.

2. The carbon nanotube back-side dual-gate field-effect transistor according to claim 1, characterized in that, A first diffusion barrier layer is provided at the interface between the first dielectric layer and the first back gate electrode, and a second diffusion barrier layer is provided at the interface between the first dielectric layer and the second back gate electrode.

3. The carbon nanotube back-side dual-gate field-effect transistor according to claim 1, characterized in that, The equivalent oxide layer thickness of the gate dielectric layer is less than or equal to 10 nanometers.

4. The carbon nanotube back-side dual-gate field-effect transistor according to claim 1, characterized in that, It also includes a threshold control layer and a second dielectric layer. The threshold control layer is disposed on the active carbon nanotube layer, and the second dielectric layer is disposed on the threshold control layer. The source electrode and the drain electrode are both at least partially embedded in the second dielectric layer. The source electrode and the drain electrode are both in contact with the active carbon nanotube layer through the threshold control layer via the second dielectric layer.

5. The carbon nanotube back-side dual-gate field-effect transistor according to claim 4, characterized in that, Both the source electrode and the drain electrode include a metal conductive layer and an ohmic contact layer. The ohmic contact layer is disposed on the outside of the metal conductive layer to separate the metal conductive layer from the second dielectric layer, the threshold control layer and the carbon nanotube active layer.

6. The carbon nanotube back-side dual-gate field-effect transistor according to claim 5, characterized in that, The field-effect transistor is an N-type field-effect transistor, and the ohmic contact layer is a metal or alloy with a work function of less than 4.5 electron volts to serve as the N-type ohmic contact layer.

7. The carbon nanotube back-side dual-gate field-effect transistor according to claim 5, characterized in that, The field-effect transistor is a P-type field-effect transistor, and the ohmic contact layer is a metal or alloy with a work function greater than 4.5 electron volts as the P-type ohmic contact layer.

8. The carbon nanotube back-side dual-gate field-effect transistor according to claim 5, characterized in that, The threshold control layer can be controllably doped to obtain a target doping concentration or a target fixed charge density, thereby obtaining the target threshold voltage of the field-effect transistor.

9. The carbon nanotube back-side dual-gate field-effect transistor according to claim 5, characterized in that, The threshold control layer serves as an etch barrier layer for the second dielectric layer, and the etch selectivity of the etch barrier layer is greater than 5.

10. A method for fabricating a field-effect transistor, used to fabricate a carbon nanotube back-side dual-gate field-effect transistor according to any one of claims 1 to 9, characterized in that, The preparation method includes: A grid trench structure is formed on the first dielectric layer; A diffusion barrier material layer is deposited on the gate trench structure, and a gate metal material layer is deposited on the diffusion barrier material layer; The gate metal material layer is chemically and mechanically polished to form a first back gate electrode, a second back gate electrode, a first diffusion barrier layer and a second diffusion barrier layer within the gate trench structure; A gate dielectric layer is grown such that the gate dielectric layer covers the common end face of the first back gate electrode, the second back gate electrode, the first diffusion barrier layer, the second diffusion barrier layer, and the first dielectric layer; The carbon nanotube active layer is deposited on the gate dielectric layer; A threshold modulation layer is deposited on the active layer of the carbon nanotubes, and a second dielectric layer is deposited on the threshold modulation layer. Source contact holes and drain contact holes are formed on the second dielectric layer and the threshold control layer; An ohmic contact layer and a metal conductive layer are deposited in both the source contact hole and the drain contact hole; and The common end face of the ohmic contact layer, the metal conductive layer and the second dielectric layer is chemically mechanically polished to form the source electrode and the drain electrode.

11. The method for fabricating a field-effect transistor according to claim 10, characterized in that, The gate trench structure is formed by dry etching on the first dielectric layer.

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