A high speed JFET amplifier circuit

Abstract

The application discloses a high-speed JFET amplifier circuit, which comprises an input stage, a gain amplification stage and an output driving stage which are connected in sequence; the input follower comprises JFET tubes J1 and J2, resistors R1 and R2, and transistors Q1, Q2, Q5 and Q6; the gain amplification stage comprises transistors Q3, Q4, Q7, Q8, Q9, Q10, Q11, Q12 and Q13, resistors R3, R4, R5, R6, R7 and R8, and a capacitor C1; and the output driving stage adopts a buffer Buffer to provide a driving current and has a gain of 1. The high-speed JFET amplifier circuit has the input stage being a JFET follower with NPN feedback, so that the input impedance is improved and the input current is reduced; and the gain amplification stage is only one stage, so that the gain-bandwidth product is improved. The transconductance of the gain stage can be adjusted according to the requirements of the bandwidth and frequency stability of the amplifier.

Description

Technical Field

[0001] This invention relates to JFET amplifiers, and more particularly to a high-speed JFET amplifier circuit. Background Technology

[0002] In the field of photoelectric detection, PIN or APD photodiodes have extremely high impedance, thus requiring high input impedance amplifiers for matching. Simultaneously, for accurate ranging, the laser pulse width of the laser emitter is extremely narrow, and the current pulse width of the photodiode output is typically on the order of nanoseconds, demanding that the amplifier have a large gain-bandwidth product and low equivalent input noise voltage. Compared to CMOS or BIPOLAR input amplifiers, JFET input amplifiers offer a balance of low noise and high input impedance, making them the preferred preamplifier circuit for high-impedance sensors. The challenge of high-speed JFET amplifiers lies in achieving a fast response speed.

[0003] An amplifier typically has 2 to 3 gain stages. To ensure frequency stability, compensation capacitors are usually required between the gain stages, which limits the amplifier's gain-bandwidth product and slew rate.

[0004] To reduce noise voltage, the gain of the first gain stage of the amplifier should be maximized to minimize the contribution of other stages to the equivalent input noise voltage. However, gain is inversely proportional to bias current, and reducing bias current means reducing amplifier speed, requiring a trade-off. Summary of the Invention

[0005] The purpose of this invention is to provide a high-speed JFET amplifier circuit that improves input impedance, reduces input current, increases the gain-bandwidth product, and allows the transconductance of the gain stage to be adjusted according to the requirements of the amplifier's bandwidth and frequency stability.

[0006] The technical solution of this invention is: A high-speed JFET amplifier circuit includes an input stage, a gain amplification stage, and an output driver stage cascaded in sequence; wherein the input stage adopts a JFET follower with NPN feedback, the gain amplification stage is only one stage, and the output driver stage provides drive current.

[0007] Preferably, the input follower includes JFETs J1 and J2, resistors R1 and R2, and transistors Q1, Q2, Q5, and Q6; wherein: The resistor R1, JFET J1, and transistor Q5 are connected in series between the power supply voltage VCC and ground to form the first voltage follower. The resistor R2, JFET J2, and transistor Q6 are connected in series between the power supply voltage VCC and ground to form a second voltage follower. Transistors Q1 and Q2 clamp the gate-drain reverse bias voltage of JFETs J1 and J2 respectively, reducing the input current; Transistors Q5 and Q6 form a constant current source with a bias voltage of VB1, providing bias current to JFETs J1 and J2, while isolating the parasitic capacitance from the drain terminals of J1 and J2 to ground.

[0008] Preferably, the gain amplification stage includes transistors Q3, Q4, Q7, Q8, and Q9, resistors R3, R4, R5, and R6, capacitor C1, and a self-biased current source; wherein: Transistors Q3, Q4, R5, R6, Q8, and Q9 form a common-emitter, common-base amplifier. The bases of transistors Q3 and Q4 are connected to the sources of JFETs J2 and J1, respectively. The emitters of transistors Q3 and Q4 are connected to the collectors of transistor Q7 through resistors R3 and R4, respectively. The base of transistor Q7 is connected to a bias voltage of VB1, and the emitter of transistor Q7 is grounded. The collectors of transistors Q3 and Q4 are connected to the emitters of transistors Q8 and Q9, respectively. The emitters of transistors Q8 and Q9 are also connected to the supply voltage VCC through resistors R5 and R6, respectively. The bases of transistors Q8 and Q9 are connected to a bias voltage of VB2, and the collectors of transistors Q8 and Q9 are connected to a self-biased current source. The connection point between transistor Q8 and the self-biased current source is designated as the dominant pole V1, and the dominant pole V1 is grounded through capacitor C1.

[0009] Preferably, the self-biased current source serves as the load of the common-emitter common-base amplifier, comprising transistors Q10, Q11, Q12, Q13 and resistors R7 and R8; Transistors Q10 and Q11 share a common base, as do transistors Q12 and Q13. The emitters of transistors Q10 and Q11 are connected to the collectors of transistors Q12 and Q13, respectively. The emitters of transistors Q12 and Q13 are grounded through resistors R7 and R8, respectively, which are used to adjust the impedance of the self-biased current source. The collectors of transistors Q11 and Q12 are both shorted to their own bases. The collectors of transistors Q10 and Q11 are connected to the collectors of transistors Q8 and Q9, respectively.

[0010] Preferably, the output driver stage uses a buffer to provide drive current with a gain of 1.

[0011] The advantages of this invention are: This invention discloses a high-speed JFET amplifier circuit. The input stage is a JFET follower with NPN feedback to improve input impedance and reduce input current. The gain amplification stage is a single stage to improve the gain-bandwidth product. The transconductance of the gain stage can be adjusted according to the bandwidth and frequency stability requirements of the amplifier. Attached Figure Description

[0012] The present invention will be further described below with reference to the accompanying drawings and embodiments: Figure 1 This is a schematic diagram of the high-speed JFET amplifier circuit of the present invention; Figure 2 This is a simulation diagram of the amplifier of the present invention with a unity-gain bandwidth of 253MHz; Figure 3 The simulation diagram shows that the slew rate of the amplifier at the rising edge of this invention is 637V / us. Detailed Implementation

[0013] like Figure 1 As shown, the high-speed JFET amplifier circuit of the present invention includes an input stage, a gain amplification stage, and an output drive stage cascaded in sequence; wherein the input stage adopts a JFET follower with NPN feedback, the gain amplification stage is only one stage, and the output drive stage provides drive current.

[0014] The input follower includes JFETs J1 and J2, resistors R1 and R2, and transistors Q1, Q2, Q5, and Q6. Specifically: resistor R1, JFET J1, and transistor Q5 are connected in series between the supply voltage VCC and ground, forming a first voltage follower; resistor R2, JFET J2, and transistor Q6 are connected in series between the supply voltage VCC and ground, forming a second voltage follower; NPN transistors Q1 and Q2 clamp the gate-drain reverse bias voltage of JFETs J1 and J2, respectively, reducing the input current; transistors Q5 and Q6 form a constant current source with a bias voltage of VB1, providing bias current to JFETs J1 and J2 while isolating the parasitic capacitance from the drain of J1 and J2 to ground.

[0015] The gain amplification stage includes transistors Q3, Q4, Q7, Q8, Q9, Q10, Q11, Q12, and Q13; resistors R3, R4, R5, R6, R7, and R8; and capacitor C1; wherein: Transistors Q3, Q4, R5, R6, Q8, and Q9 form a common-emitter, common-base amplifier. The bases of transistors Q3 and Q4 are connected to the sources of JFETs J2 and J1, respectively. The emitters of transistors Q3 and Q4 are connected to the collector of transistor Q7 through resistors R3 and R4, respectively. The base of transistor Q7 is biased by voltage VB1, and the emitter of transistor Q7 is grounded. The transconductance of the gain amplification stage is determined by transistor Q7 and resistors R3 and R4. The collectors of transistors Q3 and Q4 are connected to the emitters of transistors Q8 and Q9, respectively. The emitters of transistors Q8 and Q9 are also connected to the supply voltage VCC through resistors R5 and R6, respectively. The bases of transistors Q8 and Q9 are biased by voltage VB2, and the collectors of transistors Q8 and Q9 are connected to a self-biased current source. The connection point between transistor Q8 and the self-biased current source is the dominant pole V1. The dominant pole V1 is grounded through capacitor C1, which can be adjusted.

[0016] The self-biased current source serves as the load of the common-emitter common-base amplifier, completing the dual-channel to single-channel conversion. The self-biased current source includes transistors Q10, Q11, Q12, and Q13, and resistors R7 and R8. Transistors Q10 and Q11 share a common base, as do transistors Q12 and Q13. The emitters of transistors Q10 and Q11 are connected to the collectors of transistors Q12 and Q13, respectively. The emitters of transistors Q12 and Q13 are grounded through resistors R7 and R8, respectively. R7 and R8 are used to adjust the impedance of the self-biased current source. The collectors of transistors Q11 and Q12 are both shorted to their own bases. The collectors of transistors Q10 and Q11 are connected to the collectors of transistors Q8 and Q9, respectively.

[0017] The output driver stage uses a buffer to provide drive current with a gain of 1. Figure 2 and Figure 3 These are simulation diagrams of the key electrical parameters of the amplifier in this invention. Figure 2 In this amplifier, the unity-gain bandwidth is 253MHz; Figure 3 In this amplifier, the slew rate at the rising edge is 637V / µs.

[0018] The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All modifications made according to the spirit and essence of the main technical solution of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A high-speed JFET amplifier circuit, characterized in that, It includes an input stage, a gain amplifier stage, and an output driver stage cascaded in sequence; the input stage uses a JFET follower with NPN feedback, the gain amplifier stage is a single stage, and the output driver stage provides the drive current; The JFET follower includes JFET transistors J1 and J2, resistors R1 and R2, and transistors Q1, Q2, Q5, and Q6; wherein: The resistor R1, JFET J1, and transistor Q5 are connected in series between the power supply voltage VCC and ground to form the first voltage follower. The resistor R2, JFET J2, and transistor Q6 are connected in series between the power supply voltage VCC and ground to form a second voltage follower. Transistors Q1 and Q2 clamp the gate-drain reverse bias voltage of JFETs J1 and J2 respectively, reducing the input current; Transistors Q5 and Q6 form a constant current source with a bias voltage of VB1, which provides bias current to JFET transistors J1 and J2, while isolating the parasitic capacitance from the drain terminals of J1 and J2 to ground. The gain amplification stage includes transistors Q3, Q4, Q7, Q8, and Q9, resistors R3, R4, R5, and R6, capacitor C1, and a self-biased current source; wherein: Transistors Q3, Q4, R5, R6, Q8, and Q9 form a common-emitter, common-base amplifier. The bases of transistors Q3 and Q4 are connected to the sources of JFETs J2 and J1, respectively. The emitters of transistors Q3 and Q4 are connected to the collectors of transistor Q7 through resistors R3 and R4, respectively. The base of transistor Q7 is connected to a bias voltage of VB1, and the emitter of transistor Q7 is grounded. The collectors of transistors Q3 and Q4 are connected to the emitters of transistors Q8 and Q9, respectively. The emitters of transistors Q8 and Q9 are also connected to the supply voltage VCC through resistors R5 and R6, respectively. The bases of transistors Q8 and Q9 are connected to a bias voltage of VB2, and the collectors of transistors Q8 and Q9 are connected to a self-biased current source. The connection point between transistor Q8 and the self-biased current source is designated as the dominant pole V1, and the dominant pole V1 is grounded through capacitor C1.

2. The high-speed JFET amplifier circuit according to claim 1, characterized in that, The self-biased current source serves as the load of the common-emitter common-base amplifier, including transistors Q10, Q11, Q12, Q13 and resistors R7 and R8. Transistors Q10 and Q11 share a common base, as do transistors Q12 and Q13. The emitters of transistors Q10 and Q11 are connected to the collectors of transistors Q12 and Q13, respectively. The emitters of transistors Q12 and Q13 are grounded through resistors R7 and R8, respectively, which are used to adjust the impedance of the self-biased current source. The collectors of transistors Q11 and Q12 are both shorted to their own bases. The collectors of transistors Q10 and Q11 are connected to the collectors of transistors Q8 and Q9, respectively.

3. The high-speed JFET amplifier circuit according to claim 2, characterized in that, The output driver stage uses a buffer to provide drive current with a gain of 1.

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