Structural and materials engineering methods for enhancing the signal-to-noise ratio of optoelectronic devices

Abstract

A method of manufacturing a semiconductor device includes: forming an interconnect structure on the front side of a sensor substrate, thinning the sensor substrate from the back side of the sensor substrate, etching trenches into the sensor substrate, pre-cleaning the exposed surface of the sensor substrate, epitaxially growing a charge layer directly on the pre-cleaned exposed surface of the sensor substrate, and forming an isolation structure within the etched trenches.

Description

Technical Field

[0001] The embodiments described herein generally relate to optoelectronic devices, and more particularly to image sensors having an epitaxially grown charge layer on the surface of a pixel to enhance the signal-to-noise ratio in the image sensor. Background Technology

[0002] Complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) are widely used in various applications such as digital cameras and mobile phones. CIS uses a pixel array (e.g., photodiodes, photogate detectors, or phototransistors) to collect light incident on a semiconductor substrate and convert the collected light energy into electrical signals that can be used in suitable applications. One type of CIS, back-illuminated (BSI) CIS, typically has a silicon substrate comprising: an internally formed pixel array for sensing and recording the intensity of light entering the substrate from the back side; and some circuitry and input / output systems adjacent to the pixel array for providing an operating environment for the pixels and for supporting external communication with these pixels. During device processing such as etching, polishing, or any other material removal process, the surface of the back side of the substrate (and therefore the surface of the pixels) is damaged and leaves dangling bonds and / or defect centers. The charge carriers generated by such dangling bonds and / or defect centers contribute to the formation of noise in the electrical signals within the pixel array.

[0003] Conventional methods for suppressing noise generation include passivating the surface of the back side of the substrate by adding a charge layer (i.e., a layer comprising charge carriers) near the surface of the back side of the substrate. The charge carriers in the charge layer recombine with charge carriers generated by dangling bonds and / or defect centers. The charge layer can be formed by injecting a desired type of charge (i.e., a positive or negative charge opposite to the charge carriers generated by dangling bonds and / or defect centers) into the substrate. Alternatively, the charge layer can be formed by adding a dielectric material to the surface of the back side of the substrate with the opposite type of charge, thereby inducing the desired type of charge in the substrate near the back side. A buffer oxide layer can be inserted between the surface of the back side of the substrate and the dielectric material to separate the charge carriers in the dielectric layer from the induced charge carriers in the substrate near that surface.

[0004] However, recent demands for deeper pixels with high aspect ratio trench isolation (i.e., pixels separated from each other by high aspect ratio trenches) and higher signal-to-noise ratios have presented challenges to these conventional methods. The charge layers formed by these conventional methods may not provide sufficient charge carriers to passivate the substrate surface at a reasonable manufacturing cost and design requirements. Furthermore, charge layers formed by implantation may not provide good coverage on the sidewalls of high aspect ratio trenches. Charge layers formed by thick dielectric layers for better passivation of induced charge carriers may also have high absorption coefficients, resulting in signal reduction from the pixel array.

[0005] Therefore, there is a need in the art for an improved method for passivating damaged surfaces on the back side of BSI CIS devices, as well as any damaged surfaces caused by etching and / or polishing, and more generally, for an improved structure of BSI CIS devices. The method can also be implemented on frontside-illuminated (FSI) CIS to provide similar benefits to BSI CIS. Summary of the Invention

[0006] In one embodiment, a method of manufacturing a semiconductor device includes: forming an interconnect structure on the front side of a sensor substrate; thinning the sensor substrate from the back side of the sensor substrate; etching trenches into the sensor substrate; pre-cleaning the exposed surface of the sensor substrate; epitaxially growing a charge layer directly on the exposed surface of the pre-cleaned sensor substrate; and forming an isolation structure within the etched trenches.

[0007] In another embodiment, a method of manufacturing a semiconductor device includes: epitaxially growing an epitaxial layer directly on the surface of a handle substrate; epitaxially growing a semiconductor layer directly on a charge layer; implanting a dopant into the semiconductor layer; etching trenches into the semiconductor layer; forming an isolation structure within the etched trenches; forming an interconnect structure on the semiconductor layer; and removing the handle substrate from the epitaxial layer.

[0008] In another embodiment, the image sensor includes: a sensor substrate having a front side and a back side; a plurality of pixels formed on the back side within the sensor substrate; a plurality of isolation structures formed within the sensor substrate, wherein the plurality of pixels are isolated from each other by one of the plurality of isolation structures; an interconnection structure on the front side of the sensor substrate; and a charge layer epitaxially grown directly on the surface of the plurality of pixels on the back side of the sensor substrate. Attached Figure Description

[0009] The embodiments of this disclosure, which have been briefly summarized above and discussed in more detail below, can be understood by referring to the illustrative embodiments depicted in the accompanying drawings. However, it should be noted that the drawings only show typical embodiments of this disclosure and should not be considered as limiting the scope of this disclosure, as other equivalent embodiments are permissible.

[0010] Figure 1 This is a cross-sectional view of a back-illuminated (BSI) image sensor device manufactured according to a first embodiment of the present disclosure.

[0011] Figure 2 This is a cross-sectional view of a back-illuminated (BSI) image sensor device manufactured according to a second embodiment of the present disclosure.

[0012] Figure 3 This is a flowchart of a method for manufacturing an image sensor, such as a back-illuminated (BSI) image sensor, according to a first embodiment of the present disclosure.

[0013] Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E Intermediate steps performed in a method of manufacturing an image sensor device, such as a back-illuminated (BSI) image sensor, according to a first embodiment of the present disclosure are illustrated schematically.

[0014] Figure 5 This is a flowchart of a method for manufacturing an image sensor device, such as a back-illuminated (BSI) image sensor device, according to a second embodiment of the present disclosure.

[0015] Figure 6A , 6B Images 6C, 6D, 6E, and 6F schematically illustrate intermediate steps performed in a method of manufacturing an image sensor device, such as a back-illuminated (BSI) image sensor, according to a second embodiment of this disclosure.

[0016] For ease of understanding, the same reference numerals are used where possible to refer to common elements in the figures. These figures are not drawn to scale and have been simplified for clarity. It is anticipated that elements and features of one embodiment can be beneficially incorporated into other embodiments without further description. Detailed Implementation

[0017] The embodiments described herein generally relate to optoelectronic devices, and more particularly to image sensors having an epitaxially grown charge layer on the surface of a pixel to enhance the signal-to-noise ratio in the image sensor.

[0018] The image sensor described herein includes an epitaxially grown charge layer on a sensor substrate in which pixels are formed. The epitaxially grown charge layer conformally covers the damaged surface of the pixel, in which dangling bonds and / or defect centers caused by device manufacturing processes generate unwanted charge carriers (noise). The epitaxially grown charge layer passivates the charge carriers at the pixel surface, thereby preventing noise from being introduced into the electrical signal converted from light energy within the pixel.

[0019] Figure 1 This is a cross-sectional view of a back-illuminated (BSI) image sensor device 100 manufactured according to a first embodiment of the present disclosure. The image sensor device 100 may be a charge-coupled device (CCD), a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS), an active pixel sensor (APS), or a passive pixel sensor.

[0020] Image sensor device 100 includes a sensor substrate 102 having a front side 104 and a back side 106. The sensor substrate 102 may be a photodiode. In some embodiments, the sensor substrate 102 includes a pinned layer photodiode, a gate, a reset transistor, a source follower transistor, or a transfer transistor. The sensor substrate 102 is operable to sense incident light 110 projected onto the back side 106 of the sensor substrate 102. The sensor substrate 102 absorbs the light energy of the projected incident light 110 and generates electron-hole pairs near the back side 106 of the sensor substrate 102, thereby inducing mobile charge carriers. These charge carriers diffuse near the front side 104 of the sensor substrate 102 and are detected as electrical signals.

[0021] Sensor substrate 102 may be a substrate having a p-type dopant (e.g., boron) or an n-type dopant (e.g., phosphorus or arsenic) doped by a suitable implantation process (e.g., diffusion process). The substrate may be bulk silicon, any other suitable semiconductor material (e.g., crystalline germanium), compound semiconductors (e.g., silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, gallium phosphide, indium phosphide, indium antimonide, III-V, III-nitride), or combinations thereof. Alternatively, the substrate may be a silicon-on-insulator (SOI) substrate comprising a semiconductor layer, such as silicon or germanium, formed on an insulating layer using wafer bonding and / or other suitable methods. The insulating layer may be a buried oxide (BOX) layer formed in the semiconductor substrate. The substrate may have any suitable crystallographic orientation (e.g., (100), (110), (111), or (001) crystal orientation). The thickness of the substrate can range from approximately 100 micrometers (μm) to 1000 μm.

[0022] An array or grid of pixels 108 is formed in the sensor substrate 102. The pixels 108 can be different from each other, having different depths, thicknesses, widths, etc. Although in Figure 1 Only two pixels 108 are shown, but any number of pixels 108 can be implemented in the sensor substrate 102. The sensor substrate 102 may further include an isolation structure 112 that provides electrical and optical isolation between the pixels 108. The isolation structure 112 may be a shallow trench isolation (STI) structure formed by a dielectric material such as silicon oxide or silicon nitride filled in the trench 114, or a deep trench isolation (DTI) structure formed by a dielectric or multi-metallic material in the trench 114, or a capacitor with an air gap in the trench 114. The trench 114 is formed by etching the sensor substrate 102. In some embodiments, the isolation structure 112 includes doped isolation features, such as heavily doped n-type or p-type regions. Although in Figure 1Only three isolation structures 112 are shown; however, any number of isolation structures can be implemented in the sensor substrate 102 to properly isolate the pixels 108. The pixels 108 and trenches 114 have a depth between approximately 3 μm and approximately 10 μm or more. The pixels 108 have a width between approximately 1.2 μm and approximately 1.4 μm, and can be reduced to approximately 0.7 μm or more. The isolation structures 112 have a width between approximately 50 nm and approximately 300 nm, and an aspect ratio between 5 and 100, and possibly exceeding that.

[0023] The image sensor device 100 also includes a charge layer 116 conformally epitaxially grown directly on the surface of the pixels 108 on the back side 106 of the sensor substrate 102, including the inner walls of trenches 114. Due to device processing such as etching to form trenches 114 and thinning of the sensor substrate 102 from the back side 106, the pixels 108 may include defect centers and a high concentration of dangling bonds near the surface of the pixels 108 on the back side 106 of the sensor substrate 102. The charge carriers generated by the defect centers and dangling bonds are passivated (i.e., recombined) by the charge carriers formed in the charge layer 116, which would otherwise cause noise in the electrical signals converted from light energy in the array of pixels 108. Therefore, noise in the electrical signals is reduced. The charge layer 116 may include boron-doped silicon (Si:B), boron-doped silicon-germanium (SiGe:B), boron-doped germanium (Ge:B), or combinations of these materials. In some embodiments, the charge layer 116 is formed of carbon-doped silicon (Si:C), which, in addition to providing charge carriers, also prevents metal diffusion from the front side 104 of the sensor substrate 102. The charge layer 116, formed of silicon-germanium (SiGe), germanium (Ge), or carbon-doped silicon (Si:C) on the silicon-doped sensor substrate 102, induces tension at the interface with the sensor substrate 102 due to lattice mismatch, thereby modifying the indirect bandgap of silicon towards the direct bandgap. This increases the generation of electron-hole pairs and thus enhances the electrical signal. The thickness of the charge layer 116 can be between approximately 5 nm and 50 nm. Since this epitaxial charge layer can also be used as an extension of the pixel region, the thickness of this epitaxial charge layer may be increased to exceed 50 nm depending on the level of integration. The charge carrier density formed in the charge layer 116 can be 1 × 10⁻⁶. 18 / cm 3 With 5×10 21 / cm 3 between.

[0024] The image sensor device 100 may also have an interconnect structure 118 formed on the front side 104 of the sensor substrate 102. The interconnect structure 118 may include a plurality of patterned dielectric and conductive layers that provide interconnections (e.g., wiring) between various doped feature structures, circuits, and inputs / outputs of the image sensor device 100. The interconnect structure 118 may further include an interlayer dielectric (ILD) or a multilayer interconnect (MLI) structure, including, for example, contacts, vias, and metal lines. The MLI structure may include aluminum interconnects formed of aluminum / silicon / copper alloys, titanium, titanium nitride, tungsten, polysilicon, metal silicides, or combinations thereof. Alternatively, the MLI structure may include copper multilayer interconnects formed of copper alloys, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicides, or combinations thereof.

[0025] Figure 2 This is a cross-sectional view of a back-illuminated (BSI) image sensor device 200 manufactured according to a second embodiment of this disclosure. In the following description, the same reference numerals are used for components that are substantially the same as those in the first embodiment, and descriptions of repeated components may be omitted.

[0026] The image sensor device 200 includes a sensor substrate 102 having a front side 104 and a back side 106.

[0027] An array or grid of pixels 108 is formed in the sensor substrate 102. The sensor substrate 102 may further include an isolation structure 212 that provides electrical and optical isolation between the pixels 108. The isolation structure 212 may be a shallow trench isolation (STI) structure formed of a dielectric material such as silicon oxide or silicon nitride filled in trenches 214, a deep trench isolation (DTI) structure formed of a dielectric or multi-metallic material filled in trenches 214, or a capacitor with an air gap in trenches 214. Trenches 214 are formed by etching the sensor substrate 102. In some embodiments, the isolation structure 212 includes doped isolation features, such as heavily doped n-type or p-type regions. Although in Figure 2 Only three isolation structures 212 are shown in the figure, but any number of isolation structures can be implemented in the sensor substrate 102 so that the pixels 108 can be properly isolated.

[0028] Image sensor device 200 includes an epitaxial growth layer 216 (hereinafter referred to as the "Epi layer") directly grown on the top surface of pixels 108 on the back side 106 of sensor substrate 102. The Epi layer 216 may be formed of boron-doped silicon (Si:B), boron-doped silicon-germanium (SiGe:B), or boron-doped germanium (Ge:B) or carbon-doped silicon (Si:C). Image sensor device 200 also includes a charge layer 218 above the Epi layer 216 and the inner walls of trench 214. In some embodiments, the charge layer 218 comprises boron-doped silicon (Si:B), boron-doped silicon-germanium (SiGe:B), boron-doped germanium (Ge:B), or carbon-doped silicon (Si:C), which is epitaxially grown on the exposed surface of sensor substrate 102 on the back side 106. In some embodiments, a charge layer 218 is formed by adding a dielectric material having the opposite type of charge to the exposed surface of the sensor substrate 102 on the back side 106, thereby inducing the desired type of charge in the substrate near the back side 106.

[0029] Figure 3 This is a flowchart of a method 300 for manufacturing an image sensor device 100, such as a back-illuminated (BSI) image sensor, according to a first embodiment of the present disclosure. Figures 4A-4E The intermediate steps performed in method 300 are illustrated schematically.

[0030] In block 302 of method 300, as follows Figure 4A As shown, a sensor substrate 102 is provided or manufactured. The sensor substrate 102 may be a photodiode formed from a substrate having a p-type dopant such as boron or an n-type dopant such as phosphorus or arsenic, the dopant being doped by a suitable implantation process such as diffusion. The substrate may be bulk silicon, any other suitable semiconductor material such as crystalline germanium, compound semiconductors (e.g., silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, gallium phosphide, indium phosphide, indium antimonide, III-V, III-nitride), or a combination of these materials. Alternatively, the substrate may be a silicon-on-insulator (SOI) substrate comprising a semiconductor layer such as silicon or germanium formed on an insulating layer, the semiconductor layer being formed using wafer bonding and / or other suitable methods. The insulating layer may be a buried oxide (BOX) layer formed in a semiconductor substrate. The substrate may have any suitable crystal orientation (e.g., (100), (110), (111), or (001) crystal orientation). The thickness of the substrate can range from approximately 100 micrometers (μm) to 1000 μm.

[0031] In block 304 of method 300, as follows Figure 4BAs shown, an interconnect structure 118 is formed on the front side 104 of the sensor substrate 102. The interconnect structure 118 may include multiple patterned dielectric and conductive layers that provide interconnects (e.g., wiring) between various doped feature structures, circuits, and inputs / outputs of the image sensor device 100. The interconnect structure 118 may further include interlayer dielectric (ILD), multilayer interconnect (MLI) structures, including, for example, contacts, vias, and metal lines. The MLI structure may include aluminum interconnects formed from aluminum / silicon / copper alloys, titanium, titanium nitride, tungsten, polysilicon, metal silicides, or combinations thereof. Aluminum interconnects may be formed by processes such as physical vapor deposition (PVD) (or sputtering), chemical vapor deposition (CVD), atomic layer deposition (ALD), photolithography, etching processes for patterning conductive materials for vertical connections (e.g., vias / contacts) and horizontal connections (e.g., wires), or combinations thereof. Alternatively, the MLI structure may comprise a copper multilayer interconnect formed from copper alloys, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicides, or combinations thereof. This copper interconnect structure can be formed by, for example, CVD, sputtering, electroplating, or other suitable processes.

[0032] In block 306 of method 300, the sensor substrate 102 is flipped over and thinned from the back side 106, as shown. Figure 4C As shown. The sensor substrate 102 is thinned to allow charge carriers induced near the back surface 106 of the sensor substrate 102 to diffuse to the front surface 104. The thinning process can include mechanical grinding and chemical thinning. Mechanical grinding can first remove a substantial amount of substrate material from the sensor substrate 102, while chemical thinning can apply etching chemicals to the back surface 106 of the sensor substrate 102 to further thin it to the desired thickness. When the sensor substrate 102 is SOI type, an embedded buried oxide layer (BOX) can be used as an etch stop layer. The desired thickness of the sensor substrate 102 can vary between approximately 3 μm and approximately 10 μm, depending on the application type and design requirements of the image sensor device.

[0033] In block 308 of method 300, trenches 114 are etched from the back side 106 into the sensor substrate 102. Each pixel 108 is defined between two adjacent trenches 114, forming an array or grid of pixels 108. Pixels 108 can differ from each other to have different depths, thicknesses, widths, etc. Although in Figure 4DOnly two pixels 108 and three trenches 114 are shown in the diagram; however, any number of pixels 108 or trenches 114 can be implemented in the sensor substrate 102. The depths of the pixels 108 and trenches 114 are between approximately 3 μm and approximately 10 μm. The pixels 108 have a width between approximately 0.7 μm and approximately 2.5 μm, and can be reduced to approximately 0.5 μm. The widths of the trenches 114 are between approximately 50 nm and approximately 300 nm, with aspect ratios between 50 and 100.

[0034] In block 310 of method 300, the exposed surfaces of the sensor substrate 102 on the back side 106 are pre-cleaned to remove organic materials, such as native oxides of carbon oxides, and other impurities to enhance the performance of the image sensor device 100. The cleaning solution may include H₂O₂-H₂SO₄ and / or a mixture of wet oxidation, dry oxidation, and aqueous HF (hydrofluoric acid). The cleaned surfaces of the sensor substrate 102 may be dried by a dryer to remove any residual liquid or particles. In some embodiments, the pre-cleaning process is performed at a low temperature of approximately 450°C or lower.

[0035] In block 312 of method 300, a charge layer 116 is epitaxially grown on the exposed surface of the sensor substrate 102 on the back side 106, including the inner walls of the trench 114 (i.e., the exposed surface of the pixel 108), such as Figure 4E As shown. The charge layer 116 may comprise boron-doped silicon (Si:B), boron-doped silicon-germanium (SiGe:B), boron-doped germanium (Ge:B), or carbon-doped silicon (Si:C). The epitaxial growth of the charge layer 116 is performed by providing a source gas containing a silicon source (e.g., SiH4 or SiHCl3) and a dopant (e.g., a boron compound (e.g., diborane; B2H6)) at a low temperature of approximately 450°C or lower to ensure that the metal interconnects in the protective wafer front side and the dopants implanted in the sensor substrate 102 do not migrate or deactivate in the sensor substrate 102 (which could damage the sensor substrate 102). Due to the epitaxial growth nature, the charge layer 116 passivates the dangling bonds on the exposed surfaces and conformally covers the surfaces of the pixels 108 on the back side 106, including the inner walls of the trench 114. When the charge layer 116 is epitaxially grown, charge carriers are activated from the dopant (e.g., boron) without the need for activation annealing as is required in cases where charges are activated from the injected dopant. The density of charge carriers activated from the dopant (e.g., boron) in the charge layer 116 can reach 1 × 10⁻⁶. 18 / cm 3 and 5×10 21 / cm 3The charge carriers activated in the charge layer 116 passivate the surface of the pixel 108 (including the inner wall of the trench 114) and induced at defect centers and dangling bonds (i.e., recombined with said charge carriers). These defect centers and dangling bonds are caused by device processes such as thinning in block 306 and etching in block 308. The thickness of the charge layer 116 can be between about 5 nm and 50 nm. In addition to other functions such as passivation, stress engineering, bandpass filtering, or similar functions, the charge layer 116 also provides the same etch stop layer function as the BOX in the SOI type. Therefore, in both the SOI type and the charge layer 116 on the operating substrate 602, the total thickness variation (TTV) is thus determined by the deposition process rather than the removal process.

[0036] In block 314 of method 300, as follows Figure 1 The isolation structure 112 shown is formed by filling trench 114 with a dielectric material such as silicon oxide, silicon nitride, or a multi-metallic material, or by forming a capacitor with an air gap. In some embodiments, the isolation structure 112 may include heavily doped n-type or p-type regions. The isolation structure 112 provides electrical and optical isolation between pixels 108.

[0037] It should be noted that the specific example embodiments described above are merely some possible example methods for manufacturing semiconductor devices with integrated circuits according to this disclosure, and do not limit the possible construction, specifications, or similar matters of the liquid dejecting device according to this disclosure. For example, these methods can be applied to the manufacture of other semiconductor devices, such as solar cells. Furthermore, the order of the blocks in method 300 can be changed, and some blocks of method 300 can be repeated or omitted. The trench 114 can be etched from the front side 104 of the sensor substrate 102.

[0038] Figure 5 This is a flowchart of a method 500 for manufacturing an image sensor device 200, such as a back-illuminated (BSI) image sensor device, according to a second embodiment of the present disclosure. Figures 6A-6F The intermediate steps performed in method 500 are illustrated schematically. In the following description, the same reference numerals are used for components substantially the same as those in the first embodiment, and descriptions of repeated components may be omitted. Furthermore, method 500 according to the second embodiment can be combined with method 300 according to the first embodiment.

[0039] In block 502 of method 500, as follows Figure 6AAs shown, an epitaxial growth layer 216 is epitaxially grown on an operating substrate 602. The epitaxial growth layer 216 (hereinafter referred to as the "Epi layer") may or may not contain charge. The operating substrate 602 may be a silicon wafer, a Ge wafer, an SOI wafer, a III-V wafer with a p-type dopant such as boron or an n-type dopant such as phosphorus or arsenic, or an intrinsic wafer. The Epi layer 216 may include boron-doped silicon (Si:B), boron-doped silicon-germanium (SiGe:B), boron-doped germanium (Ge:B), or carbon-doped silicon (Si:C). The epitaxial growth of the Epi layer 216 is performed by supplying a source gas containing a silicon source (e.g., SiH4 or SiHCl3) and a dopant (e.g., a boron compound (e.g., diborane; B2H6)) at a temperature between approximately 500°C and approximately 900°C. The density of carriers activated from the dopant (e.g., boron) in the Epi layer 216 can be 1 × 10⁻⁶. 17 / cm 3 and 5×10 21 / cm 3 The thickness of Epi layer 216 can be between approximately 5 nm and 100 nm.

[0040] In block 504 of method 500, as follows Figure 6B As shown, a semiconductor layer 604 is epitaxially grown on Epi layer 216. Semiconductor layer 604 can be a single semiconductor material (e.g., silicon or germanium), or a compound semiconductor (e.g., silicon-germanium, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide, III-V, III-nitride); or a combination thereof. Semiconductor layer 604 can be a silicon-on-insulator (SOI) substrate comprising a semiconductor layer such as silicon or germanium formed on an insulating layer using wafer bonding and / or other suitable methods. The insulating layer can be formed of any suitable material, including silicon oxide, sapphire, other suitable insulating materials, and / or combinations thereof. Exemplary insulating layers can be buried oxide layers (BOX) or epitaxial oxide / silicon stacks. The insulating layer is formed by any suitable process, such as separation by oxygen implantation (SIMOX), oxidation, deposition, and / or other suitable processes. The substrate can have any suitable crystal orientation (e.g., (100), (110), (111), or (001) crystal orientation). The thickness of the semiconductor layer 604 can range from approximately 100 micrometers (μm) to 1000 μm.

[0041] In block 506 of method 500, a sensor substrate 102 is formed by doping a p-type dopant (e.g., boron) and an n-type dopant (e.g., phosphorus or arsenic) into a semiconductor layer 604 through a suitable implantation process 606 (e.g., diffusion or epitaxy). Figure 6CAs shown, the front side 104 of the sensor substrate 102 is exposed, and the back side 106 of the sensor substrate 102 is in direct contact with the Epi layer 216.

[0042] In block 508 of method 500, as in block 304, an interconnect structure 118 is formed on the front side 104 of the sensor substrate 102.

[0043] In block 510 of method 500, the sensor substrate 102 is flipped and the operating substrate 602 is removed from the Epi layer 216, as follows. Figure 6D As shown. The operating substrate 602 can be removed by grinding, chemical polishing, and wet or dry etching / cleaning. In some embodiments, the Epi layer 216 is formed of a material having a different composition than the operating substrate 602, such as SiGeB, SiGeBC, Si:C, Si:B, Si:P, Si:PC, or SiAs. Due to the different etching rates of the materials between the operating substrate 602 and the Epi layer 216, the etching process stops at the Epi layer 216.

[0044] In block 512 of method 500, trenches 214 are etched from the back side 106 into the sensor substrate 102. Each pixel 108 is defined between two adjacent trenches 214, forming an array or grid of pixels 108. Pixels 108 can differ from each other to have different depths, thicknesses, widths, etc. Although in Figure 6E Only two pixels 108 and three trenches 214 are shown in the diagram; however, any number of pixels 108 or trenches 214 can be implemented in the sensor substrate 102. The width of the trenches 214 is between approximately 50 nm and approximately 300 nm, and the aspect ratio is between 10 and 100.

[0045] In block 514 of method 500, as follows Figure 6F As shown, a charge layer 218, including the inner walls of trenches 214, is formed on the exposed surface of the sensor substrate 102 on the back side 106. In some embodiments, the charge layer 218 comprises boron-doped silicon (Si:B), boron-doped silicon-germanium (SiGe:B), boron-doped germanium (Ge:B), or carbon-doped silicon (Si:C), which is epitaxially grown after the exposed surface of the sensor substrate 102 on the back side 106 has been pre-cleaned as in block 310 of method 300. In some embodiments, the charge layer 218 is formed by adding a dielectric material having a type opposite to the desired charge type to the exposed surface of the sensor substrate 102 on the back side 106, thereby inducing a desired type of charge in the substrate near the back side 106.

[0046] In block 516 of method 500, as follows Figure 2The isolation structure 212 shown is formed by filling trench 214 with a dielectric material such as silicon oxide, silicon nitride, or a multi-metallic material, or by forming a capacitor with an air gap. In some embodiments, the isolation structure 212 may include heavily doped n-type or p-type regions. The isolation structure 212 provides electrical and optical isolation between pixels 108.

[0047] It should be noted that the specific example embodiments described above are merely some possible example methods for manufacturing semiconductor devices with integrated circuits according to this disclosure, and do not limit the possible construction, specifications, or similar matters of the liquid jetting device according to this disclosure. For example, these methods can be applied to the manufacture of other semiconductor devices, such as solar cells. Furthermore, the order of the blocks in method 500 can be changed, and some blocks of method 500 can be repeated or omitted. Trench 214 can be etched from the front side 104 of the sensor substrate 102.

[0048] In the above example embodiments, an image sensor and a method of manufacturing the same are provided to reduce noise in the electrical signals derived from light energy conversion in a pixel array. An epitaxially grown charge layer in the image sensor provides a high concentration of charge carriers to passivate excess charge carriers generated on the surface of the pixels in the image sensor. The epitaxially grown charge layer can provide additional functionality, such as an etch stop layer or getter during fabrication processes and / or stress-engineered features to address the material bandgap / work function and / or the separation between signal and noise near the sensor surface; the getter prevents metal diffusion within the image sensor.

[0049] Although certain embodiments have been described, these embodiments are given by way of example only and are not intended to limit the scope of the invention. In fact, the novel embodiments described herein can be embodied in various other forms. Furthermore, various omissions, substitutions, and changes can be made to the form of the embodiments described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of the invention.

Claims

1. A method for manufacturing a semiconductor device, comprising the following steps: An interconnect structure is formed on the front side of the sensor substrate; The sensor substrate is thinned from its back side; The trenches are etched into the sensor substrate; Pre-clean the exposed surfaces of the sensor substrate; A charge layer is epitaxially grown directly on the back side of the pre-cleaned exposed surface of the sensor substrate and inside and outside the trench; and An isolation structure is formed within the etched trenches.

2. The method according to claim 1, wherein, The sensor substrate is a silicon photodiode.

3. The method according to claim 1, wherein, The charge layer comprises a material selected from boron-doped silicon, boron-doped silicon-germanium, and boron-doped germanium.

4. The method according to claim 3, wherein, The charge carrier density in the charge layer is 1×10⁻⁶ 18 / cm 3 With 5×10 21 / cm 3 between.

5. The method according to claim 1, wherein, The thickness of the charge layer is between 5 nm and 50 nm.

6. The method according to claim 1, wherein, The epitaxial growth of the charge layer is carried out at a temperature of 450°C or lower.

7. The method according to claim 1, wherein, The isolation structure includes a dielectric material selected from silicon oxide and silicon nitride.

8. A method for manufacturing a semiconductor device, comprising the following steps: An epitaxial growth layer is directly grown on the surface of the operating substrate; A semiconductor layer is epitaxially grown directly on the epitaxial growth layer, the semiconductor layer having a first surface that is in direct contact with the epitaxial growth layer and a second surface that is opposite to the first surface; Dopant is implanted into the semiconductor layer; An interconnect structure is formed on the second surface of the semiconductor layer; Remove the operating substrate from the epitaxial growth layer; The trench is etched from the first surface into the semiconductor layer; A charge layer is epitaxially grown on the exposed surface of the semiconductor layer and inside and outside the trench; and An isolation structure is formed within the etched trenches.

9. The method according to claim 8, wherein: The semiconductor layer includes silicon. Dopants include boron, phosphorus, or arsenic compounds, and The isolation structure includes a dielectric material selected from silicon oxide and silicon nitride.

10. The method according to claim 8, wherein, The charge layer comprises a material selected from boron-doped silicon, boron-doped silicon-germanium, and boron-doped germanium.

11. The method according to claim 10, wherein, The charge carrier density in the charge layer is 1×10⁻⁶ 17 / cm 3 With 5×10 21 / cm 3 between.

12. The method according to claim 8, wherein, The thickness of the charge layer is between 5 nm and 100 nm.

13. The method according to claim 8, wherein, The epitaxial growth of the charge layer was carried out at a temperature between 500°C and approximately 900°C.

14. An image sensor, comprising: A sensor substrate having a front side and a back side; Multiple pixels, the multiple pixels being formed on the back side within the sensor substrate; Multiple isolation structures are formed within the sensor substrate, wherein the multiple pixels are isolated from each other through one of the multiple isolation structures; An interconnect structure, the interconnect structure being located on the front side of the sensor substrate; and A charge layer is epitaxially grown directly on the back side of the sensor substrate onto the surface of the plurality of pixels.

15. The image sensor according to claim 14, wherein, The sensor substrate is a silicon photodiode.

16. The image sensor according to claim 14, wherein, The charge layer comprises a material selected from boron-doped silicon, boron-doped silicon-germanium, and boron-doped germanium.

17. The image sensor according to claim 16, wherein, The charge carrier density in the charge layer is 1×10⁻⁶ 18 / cm 3 With 5×10 21 / cm 3 between.

18. The image sensor according to claim 14, wherein, The thickness of the charge layer is between 5 nm and 50 nm.

19. The image sensor according to claim 14, wherein, The plurality of isolation structures include silicon-containing dielectric materials.

20. The image sensor according to claim 14, wherein, Each of the plurality of isolation structures has a width-to-depth ratio between 50 and 100.

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