Voltage monitoring device

Abstract

To provide a voltage monitoring device capable of determining occurrence of abnormality in the voltage monitoring device itself. A voltage monitoring device (2) includes a comparison circuit (31), a state determination circuit (32), a pulse pattern setting circuit (33), an output circuit (36), a VDD terminal (21), a VSS terminal (22), an input terminal (24), and an output terminal (23), the comparison circuit (31) being connected to the state determination circuit (32), the state determination circuit (32) being connected to the pulse pattern setting circuit (33), and the pulse pattern setting circuit being connected to the output terminal (23) via the output circuit (36).

Description

Technical Field

[0001] This invention relates to a voltage monitoring device. Background Technology

[0002] In recent years, a voltage monitoring device using a window comparator circuit has been known for monitoring voltage. The window comparator circuit uses multiple comparator circuits to output whether the voltage of the monitored object is within a set voltage range (see, for example, Patent Document 1).

[0003] [Existing Technical Documents]

[0004] [Patent Literature]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2008-102094 Summary of the Invention

[0006] [The problem the invention aims to solve]

[0007] The window comparator circuit only changes its output when the input voltage crosses a threshold. If the output terminal is internally short-circuited to the power supply when the output is high, the output will always be high, thus making it impossible to determine if the voltage monitoring device is malfunctioning. The purpose of this invention is to provide a voltage monitoring device that can determine the occurrence of malfunctions within the voltage monitoring device itself.

[0008] [Technical means to solve the problem]

[0009] To address the aforementioned issues, the voltage monitoring device of the present invention includes: a comparison circuit, a state determination circuit, a pulse mode setting circuit, an output circuit, a VDD terminal, a VSS terminal, an input terminal, and an output terminal. The comparison circuit is connected to the state determination circuit, the state determination circuit is connected to the pulse mode setting circuit, and the pulse mode setting circuit is connected to the output terminal via the output circuit.

[0010] [The effects of the invention]

[0011] According to the voltage monitoring device of the present invention, a predetermined pulse group, comprising a predetermined pulse width and a predetermined number of pulses pre-set according to the voltage state of the input terminal, is repeatedly output in each predetermined pulse cycle, thereby periodically confirming the status of the voltage monitoring device. Thus, in the event of an abnormality such as an internal short circuit between the output terminal of the voltage monitoring device and the power supply, the abnormality of the voltage monitoring device can be determined. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating the voltage monitoring device and its utilization method according to the first embodiment of the present invention.

[0013] Figure 2This is a circuit diagram illustrating the comparison circuit of the first embodiment of the present invention.

[0014] Figure 3 This is a circuit diagram illustrating the output circuit of the first embodiment of the present invention.

[0015] Figure 4 This is a diagram illustrating an example of the correspondence between the state, input voltage, and output signal of the voltage monitoring device according to the first embodiment of the present invention.

[0016] Figure 5 This is a diagram illustrating an example of the output signal of the voltage monitoring device according to the first embodiment of the present invention.

[0017] Figure 6 This is a block diagram illustrating a voltage monitoring device according to a second embodiment of the present invention.

[0018] Figure 7 This is a block diagram illustrating a voltage monitoring device according to a third embodiment of the present invention.

[0019] Figure 8 This is a block diagram illustrating a voltage monitoring device according to a fourth embodiment of the present invention.

[0020] Figure 9 This is a block diagram illustrating a voltage monitoring device according to a fifth embodiment of the present invention.

[0021] Figure 10 This is a block diagram illustrating a voltage monitoring device according to a sixth embodiment of the present invention.

[0022] Figure 11 This is a block diagram illustrating a voltage monitoring device according to the seventh embodiment of the present invention.

[0023] Figure 12 This is a block diagram illustrating the voltage monitoring device according to the eighth embodiment of the present invention.

[0024] Figure 13 This is a block diagram illustrating a voltage monitoring device according to a ninth embodiment of the present invention.

[0025] Figure 14 This figure shows an example of connecting the voltage monitoring device according to the ninth embodiment of the present invention.

[0026] Figure 15 This is a block diagram illustrating a voltage monitoring device according to the tenth embodiment of the present invention.

[0027] Figure 16 This figure shows an example of connecting the voltage monitoring device according to the tenth embodiment of the present invention.

[0028] [Explanation of Symbols]

[0029] 1, 1a, 1b: Batteries

[0030] 2, 2a, 2b, 2c, 2d, 2e, 2f, 2g, 2h, 16, 16a: Voltage monitoring devices

[0031] 3: Light-emitting device

[0032] 5: Sensors

[0033] 6: Abnormal current limiting device

[0034] 23: Output terminal

[0035] 24: Input Terminal

[0036] 29: Abnormal current limiting device connection terminal

[0037] 30: Communication terminal

[0038] 31, 38: Comparator circuits

[0039] 32, 32a, 32b: State determination circuit

[0040] 33: Pulse Mode Setting Circuit

[0041] 36: Output Circuit Detailed Implementation

[0042] Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings.

[0043] [First Implementation Method]

[0044] Reference Figure 1 The structure of the first embodiment of the present invention will be described. Figure 1 This is a block diagram illustrating the voltage monitoring device 2 and its utilization method according to the first embodiment of the present invention. Figure 1 In this embodiment, the voltage monitoring device 2 includes: a comparison circuit 31, a state determination circuit 32, a pulse mode setting circuit 33, a reset circuit 34, a clock generation circuit 35, and an output circuit 36. Additionally, the voltage monitoring device 2 includes: a VDD terminal 21, a VSS terminal 22, an input terminal 24, and an output terminal 23.

[0045] VDD terminal 21 is connected to the power supply VDD within the voltage monitoring device 2. VSS terminal 22 is connected to the power supply VSS within the voltage monitoring device 2. Input terminal 24 is connected to the comparator circuit 31. Comparator circuit 31 is connected to the state determination circuit 32. State determination circuit 32 is connected to the comparator circuit 31 and the pulse mode setting circuit 33. Pulse mode setting circuit 33 is connected to the state determination circuit 32, reset circuit 34, clock generation circuit 35, and output circuit 36. Reset circuit 34 is connected to the pulse mode setting circuit 33 and the clock generation circuit 35. Clock generation circuit 35 is connected to the reset circuit 34 and the pulse mode setting circuit 33. Output circuit 36 ​​is connected to the pulse mode setting circuit 33 and output terminal 23. Some details regarding the power supply VDD and its connection to the power supply VSS within the voltage monitoring device 2 are omitted. Battery 1 is connected to the battery connection terminals of the voltage monitoring device 2, namely VDD terminal 21 and VSS terminal 22. Sensor 5 has three terminals: two power supply terminals and one output terminal. Sensor 5 operates powered by battery 1. Sensor 5 applies an input voltage VIN, based on the voltage at VSS terminal 22, from its output terminal to its input terminal 24. Voltage monitoring device 2 outputs an output signal OUT from its output terminal 23, corresponding to the voltage range applied to input terminal 24.

[0046] Next, refer to Figure 2 The structure of the comparison circuit 31 in the first embodiment of the present invention will be described. Figure 2This is a circuit diagram illustrating the comparator circuit 31 according to a first embodiment of the present invention. The comparator circuit 31 includes a resistor circuit 101, a resistor circuit 102, a comparator 103, a comparator 104, and a voltage source 105, all generating a voltage input to the non-inverting input terminal of a comparator. The resistor circuit 101 includes a switch 106, a switch 107, and resistors 110, 111, and 112. Switch 106, resistor 110, and resistor 112 are connected in series between the input terminal 24 and the power supply VSS. Similarly, switch 107, resistor 111, and resistor 112 are connected in series between the input terminal 24 and the power supply VSS. The resistor circuit 102 includes a switch 108, a switch 109, and resistors 113, 114, and 115. Switch 108, resistor 113, and resistor 115 are connected in series between the input terminal 24 and the power supply VSS. Similarly, switch 109, resistors 114 and 115 are connected in series between input terminal 24 and power supply VSS. The inverting input terminal of comparator 103 is connected to power supply VSS via voltage source 105, and the non-inverting input terminal is connected to the junction of resistors 110, 111, and 112. Similarly, the inverting input terminal of comparator 104 is connected to power supply VSS via voltage source 105, and the non-inverting input terminal is connected to the junction of resistors 113, 114, and 115. The output terminals of comparators 103 and 104 are connected to state determination circuit 32.

[0047] The state determination circuit 32 determines, based on the output result of the input comparator, which voltage range the input voltage VIN to the input terminal 24 falls within, relative to the power supply VSS voltage. It then outputs control signals to set the on / off states of switches 106, 107, 108, and 109 of the comparator circuit 31, thereby setting a new monitoring voltage range. Additionally, the state determination circuit 32 outputs the monitoring voltage range of the input voltage VIN to the pulse mode setting circuit 33. The state determination circuit 32 may include logic circuits, processor circuits, etc.

[0048] The pulse mode setting circuit 33 receives the output signal from the state determination circuit 32 and outputs a pulse-shaped output signal OUT from the output terminal 23 via the output circuit 36. The pulse mode of the output signal OUT is generated using signals from the reset circuit 34 and the clock generation circuit 35. The operation of the pulse mode setting circuit 33, the reset circuit 34, and the clock generation circuit 35 will be explained later.

[0049] Reference Figure 3The structure of the output circuit 36 ​​is described below. The output circuit 36 ​​includes an input terminal, an output terminal, a P-channel metal-oxide-semiconductor (PMOS) transistor 361, and an N-channel metal-oxide-semiconductor (NMOS) transistor 362. The gate terminal of the PMOS transistor 361 is connected to the input terminal of the output circuit 36, the source terminal is connected to the power supply VDD, and the drain terminal is connected to the output terminal of the output circuit 36. The gate terminal of the NMOS transistor 362 is connected to the input terminal of the output circuit 36, the source terminal is connected to the power supply VSS, and the drain terminal is connected to the output terminal of the output circuit 36.

[0050] Reference Figure 2 The operation of the input voltage VIN of the input terminal 24 connected to sensor 5, the comparator circuit 31, and the state determination circuit 32 will be explained. The input voltage VIN is set as the voltage applied from sensor 5 to input terminal 24 based on the voltage of VSS terminal 22. Voltage source 105 supplies the reference voltage VREF to the inverting input terminals of comparators 103 and 104.

[0051] The non-inverting input terminal of comparator 103 is supplied with a voltage obtained by dividing the input voltage VIN using resistor circuit 101 by turning on either switch 106 or switch 107. When switch 106 is on, the input voltage VIN that is equal to the reference voltage VREF when applied to the non-inverting input terminal of comparator 103 is set as voltage VDET1. When switch 107 is on, the input voltage VIN that is equal to the reference voltage VREF when applied to the non-inverting input terminal of comparator 103 is set as voltage VDET3.

[0052] The non-inverting input terminal of comparator 104 is supplied with a voltage obtained by dividing the input voltage VIN using resistor circuit 102 by turning on either switch 108 or switch 109. When switch 108 is on, the input voltage VIN that is equal to the reference voltage VREF when applied to the non-inverting input terminal of comparator 104 is set as voltage VDET2. When switch 109 is on, the input voltage VIN that is equal to the reference voltage VREF when applied to the non-inverting input terminal of comparator 104 is set as voltage VDET4. The resistance values ​​of resistors 110 to 115 are set in the order of voltage VDET1 > voltage VDET2 > voltage VDET3 > voltage VDET4.

[0053] Reference Figure 4 The relationship between input voltage VIN and voltages VDET1 to VDET4 and state (STATE) is explained. Figure 4 This diagram shows the status of the voltage monitoring device and the correspondence between the input voltage VIN and the output signal OUT. STATE1 represents an input voltage VIN that is above VDET1. STATE2 represents an input voltage VIN that is above VDET2 but below VDET1. STATE3 represents an input voltage VIN that is above VDET3 but below VDET2. STATE4 represents an input voltage VIN that is above VDET4 but below VDET3. STATE5 represents an input voltage VIN that is below VDET4. Furthermore, the boundary voltages are included in the upper STATE, but whether the boundary voltages are included in the upper or lower STATE can be arbitrarily set.

[0054] exist Figure 2 In the comparator circuit 31, for example, switches 106 and 108 are set to the ON state. The voltage obtained by dividing the input voltage VIN using resistors 110 and 112 is input to the non-inverting input terminal of comparator 103, and the voltage obtained by dividing the input voltage VIN using resistors 113 and 115 is input to the non-inverting input terminal of comparator 104. Based on this voltage relationship, the comparator circuit 31 monitors the upper reference voltage of the input voltage VIN as voltage VDET1 and the lower reference voltage as voltage VDET2, thereby setting the monitoring voltage range. The state determination circuit 32, based on the output signal of the comparator circuit 31, determines which voltage range (STATE1 to STATE5) the input voltage VIN falls within, and outputs the determination result to the pulse mode setting circuit 33. Additionally, a control signal is output to set the ON / OFF state of the switches in the comparator circuit 31, so as to set a new monitoring voltage range according to the determination result.

[0055] Here, we assume that the input voltage VIN changes from a voltage state (STATE2) that is above VDET2 and below VDET1, where the input voltage VIN is below VDET2. The state determination circuit 32 outputs a control signal that opens switch 106 and opens switch 107. Based on the fact that the monitoring voltage range of the comparator circuit 31 is a voltage range that is above VDET3 and below VDET2, the voltage state when the input voltage VIN is within this range is STATE3. Furthermore, if the input voltage VIN changes and becomes below VDET3, the state determination circuit 32 outputs a control signal that opens switch 108 and opens switch 109. The monitoring voltage range of the comparator circuit 31 is a voltage range that is above VDET4 and below VDET3, and the voltage state when the input voltage VIN is within this range is STATE4. Thus, based on the determination result of the comparator circuit 31, the state determination circuit 32 can sequentially switch the monitoring voltage range by outputting switch control signals, and the comparator circuit 31 can monitor multiple voltage ranges using two comparators. When the input voltage VIN changes upwards, the voltage monitoring device performs the opposite switching action.

[0056] Then, referring to Figure 1 The overall operation of the voltage monitoring device 2 will be explained. Based on the monitored voltage range obtained by the comparison circuit 31 and the state determination circuit 32, the voltage monitoring device 2 can obtain, for example... Figure 4 The five voltage states are shown as described. The state determination circuit 32 outputs a signal to the pulse mode setting circuit 33, which determines the voltage range of the input voltage VIN based on the output signal of the comparison circuit 31. The pulse mode setting circuit 33, based on the clock signal supplied from the clock generation circuit 35, repeatedly includes a predetermined pulse group with a predetermined pulse width and number of pulses pre-set according to each state within each predetermined pulse cycle, and outputs it via the output circuit 36 ​​in the form of a predetermined voltage pulse or current pulse. The state determination circuit 32 and the pulse mode setting circuit 33 include a processor circuit or logic circuit that runs using a program.

[0057] The reset circuit 34 operates after receiving the signal of each specified cycle from the pulse mode setting circuit 33 in each specified pulse cycle, and initializes the pulse mode setting circuit 33 and the clock generation circuit 35. The pulse mode setting circuit 33 repeatedly outputs a specified pulse group including a specified pulse width and a specified number of pulses in each specified pulse cycle.

[0058] The pulse mode allocation in this embodiment is illustrated in... Figure 4 . Figure 4This shows the correspondence between each voltage state (STATE) and the input voltage VIN, pulse width (Output Pulse Width), number of pulses constituting a pulse group (Output Pulse Number), and pulse cycle (Output Pulse Cycle). An example of the output signal OUT is shown below. Figure 5 For example, when the input voltage VIN is a voltage value (STATE1) higher than VDET1, the specified pulse group consists of voltage pulses with a pulse width of 128ms, emitted twice at 128ms intervals, with a specified pulse period of 1024ms. The combination of pulse width, pulse interval, and pulse number within the specified pulse period is called the pulse mode. Figure 5 The diagram shows the case where the output signal OUT is a voltage pulse, but the output signal OUT can also be set to a current pulse.

[0059] The microcomputer, which determines the voltage of sensor 5 based on the output signal OUT of voltage monitoring device 2, obtains the voltage information of the output terminal of sensor 5 by judging the pulse width and number of pulses of the pulse group output by voltage monitoring device 2. The microcomputer uses the master clock as a reference to determine the pulse group output by voltage monitoring device 2. In determining the pulse group, the microcomputer measures the initial pulse width and the time until the subsequent pulse in each pulse cycle. If, based on the initially measured time, the subsequent pulses of the same waveform are counted to the same number as the measured time, the state (STATE) can be determined.

[0060] In the voltage monitoring device 2 of this embodiment, the pulse pattern of the output signal OUT is generated based on a clock generated by the clock generation circuit 35, which includes a general oscillation circuit such as a CR oscillation circuit. The clock period output from the CR oscillation circuit has deviations due to power supply voltage dependence, temperature dependence, etc., but as described above, the state determination performed by the microcomputer is determined by measuring the time related to the initial pulse pattern and counting the number of subsequent pulses of the same pattern. The clock generation circuit 35 of the voltage monitoring device 2 can output pulses that are sufficient for state determination even if they are not highly accurate. Therefore, the voltage monitoring device 2 does not require a high-precision reference source such as a crystal oscillator, and a voltage monitoring system can be easily and inexpensively constructed.

[0061] As explained above, the voltage monitoring device 2 of this embodiment repeatedly outputs a predetermined pulse group, including a predetermined pulse width and a predetermined number of pulses corresponding to the voltage range of the input voltage VIN, in each predetermined pulse cycle. The voltage monitoring device 2 of this embodiment can periodically confirm that the input voltage VIN is within a predetermined voltage range in each predetermined pulse cycle. By monitoring the predetermined pulse pattern in a microcomputer or the like, it can be confirmed that the output voltage of the sensor 5 is within a predetermined voltage range in each predetermined cycle, thus periodically determining whether there are faults in the monitoring circuit, such as wiring path failures or power supply short circuits to the output port. Furthermore, the comparison circuit 31 of this embodiment is configured with four reference voltages and five monitoring voltage ranges, but it is configured to increase the voltage obtained by dividing the input voltage VIN by adding switches and voltage divider resistors, and then sequentially switching the switches, thereby enabling more detailed monitoring voltage ranges. Additionally, the state of STATE1 or STATE5 can be set to indicate an abnormality at the monitoring side.

[0062] Furthermore, here, the structure of the reset circuit 34 operating after receiving a signal from the pulse mode setting circuit 33 for each specified pulse period has been described. However, the reset circuit 34 can also be configured as follows: it operates after receiving signals from both the state determination circuit 32 and the pulse mode setting circuit 33, and initializes the clock generation circuit 35 and the pulse mode setting circuit 33 in each specified period of change of the state determination circuit 32 or from the pulse mode setting circuit 33.

[0063] In this structure, a predetermined pulse pattern can be output from the point in time when the output voltage of sensor 5 changes, deviates from the specified voltage range, or its state changes. Sensor 5 can be any sensor that outputs voltage based on the sensed physical quantity; examples include temperature sensors and magnetic sensors, but it is not limited to these.

[0064] [Second Implementation]

[0065] Reference Figure 6 The structure of the voltage monitoring device 2a according to the second embodiment of the present invention will be described. Furthermore, components identical to those in the first embodiment are labeled with the same numbers as in the first embodiment, and their descriptions are omitted. Figure 6 This is a block diagram showing the voltage monitoring device 2a in the second embodiment.

[0066] The voltage monitoring device 2a of this embodiment is configured to include a sensor circuit 37 instead of the input terminal 24 of the voltage monitoring device 2 of the first embodiment. A comparator circuit 31 is connected to the sensor circuit 37 instead of the input terminal 24. The voltage monitoring device 2a of this embodiment applies the sensor voltage output by the sensor circuit 37 to the comparator circuit 31. The sensor voltage is compared by the comparator of the comparator circuit 31, and the result is output to the state determination circuit 32.

[0067] The state determination circuit 32 determines the voltage range of the sensor voltage output by the sensor circuit 37 based on the output result of the input comparator, and outputs control signals to set the on / off state of switches 106, 107, 108, and 109 of the comparator circuit 31, thereby setting a new monitoring voltage range based on the determination. Additionally, the state determination circuit 32 outputs a signal indicating the monitoring voltage range of the sensor voltage to the pulse mode setting circuit 33. The pulse mode setting circuit 33 receives the output signal from the state determination circuit 32 and outputs a pulse-shaped output signal OUT corresponding to the sensor voltage output by the sensor circuit 37 via the output circuit 36.

[0068] As explained above, the voltage monitoring device 2a of this embodiment repeatedly outputs a predetermined pulse group, including a predetermined pulse width and a predetermined number of pulses corresponding to the voltage range of the sensor voltage output by the sensor circuit 37, in each predetermined pulse cycle. The voltage monitoring device 2a of this embodiment can periodically confirm that the sensor voltage output by the sensor circuit 37 is within a predetermined voltage range in each predetermined pulse cycle. The sensor circuit 37 can be any sensor circuit that outputs voltage based on a sensed physical quantity; examples include temperature sensor circuits and magnetic sensor circuits, but it is not limited to these.

[0069] [Third Implementation Method]

[0070] Reference Figure 7 The structure of the voltage monitoring device 2b according to the third embodiment of the present invention will be described. Furthermore, components identical to those in the first embodiment are labeled with the same numbers as in the first embodiment, and their descriptions are omitted. Figure 7 This is a block diagram showing the voltage monitoring device 2b in the third embodiment.

[0071] In this embodiment, the voltage monitoring device 2b is configured to connect the VDD terminal 21 to the comparator circuit 31 instead of the input terminal 24 of the voltage monitoring device 2 in the first embodiment. The VDD terminal 21 is internally connected to the power supply VDD and the comparator circuit 31 within the voltage monitoring device 2b. In this embodiment, the voltage monitoring device 2b applies the battery voltage VBAT of the battery 1, which is applied to the VDD terminal 21, to the comparator circuit 31. The battery voltage VBAT is compared by the comparator of the comparator circuit 31 with the voltage of the power supply VSS as a reference, and the result is output to the status determination circuit 32.

[0072] The state determination circuit 32 determines the voltage range of battery voltage VBAT of battery 1 based on the output result of the input comparator, and outputs control signals to set the on / off state of switches 106, 107, 108, and 109 of the comparator circuit 31, thereby setting a new monitoring voltage range according to the determination. Additionally, the state determination circuit 32 outputs a signal indicating the monitoring voltage range of battery voltage VBAT to the pulse mode setting circuit 33. The pulse mode setting circuit 33 receives the output signal from the state determination circuit 32 and outputs a pulse-shaped output signal OUT corresponding to the voltage range of battery voltage VBAT via the output circuit 36. Regarding the pulse mode allocation, pulses with larger pulse widths and higher current consumption can be allocated when battery voltage VBAT is high, while pulses with smaller pulse widths and lower current consumption can be allocated when battery 1 is depleted and battery voltage VBAT is low. By allocating the pulse mode in this way, battery life can be extended when battery voltage VBAT is low.

[0073] As explained above, the voltage monitoring device 2b of this embodiment repeatedly outputs a predetermined pulse group, including a predetermined pulse width and a predetermined number of pulses corresponding to the voltage range of the battery voltage VBAT of the battery 1, in each predetermined pulse cycle. The voltage monitoring device 2b of this embodiment can periodically confirm that the battery voltage VBAT of the battery 1 is within a predetermined voltage range in each predetermined pulse cycle.

[0074] [Fourth Implementation Method]

[0075] Reference Figure 8 The structure of the voltage monitoring device 2c according to the fourth embodiment of the present invention will be described. Furthermore, components identical to those in the first embodiment are labeled with the same numbers as in the first embodiment, and their descriptions are omitted. Figure 8This is a block diagram illustrating the voltage monitoring device 2c in the fourth embodiment. The voltage monitoring device 2c in this embodiment is configured such that the voltage monitoring device 2 in the first embodiment includes a second comparison circuit 38 with the same structure as the comparison circuit 31. Furthermore, a state determination circuit 32a is included instead of the state determination circuit 32. The state determination circuit 32a receives output signals from the comparison circuit 31 and the second comparison circuit 38, and outputs control signals for setting the switches of the comparison circuit 31 and the second comparison circuit 38.

[0076] Input terminal 24 is connected to state determination circuit 32a via second comparison circuit 38. In the voltage monitoring device 2c of this embodiment, VDD terminal 21 is internally connected to power supply VDD and comparison circuit 31. Furthermore, sensor 5, powered by battery 1, applies a sensor voltage, referenced to the voltage of VSS terminal 22, to input terminal 24. Input terminal 24 is connected to second comparison circuit 38.

[0077] Comparison circuit 31 is connected to state determination circuit 32a, and similarly, second comparison circuit 38 is connected to state determination circuit 32a. State determination circuit 32a outputs a signal indicating the voltage range within which the monitored voltage ranges of comparison circuit 31 and second comparison circuit 38 fall to pulse mode setting circuit 33. Pulse mode setting circuit 33 receives the output signal from state determination circuit 32a and outputs a pulse-shaped output signal OUT via output circuit 36, corresponding to the voltage input to VDD terminal 21 and input terminal 24.

[0078] The pulse mode output by the pulse mode setting circuit 33 can be set to represent any one of the 25 states formed by combining the monitoring voltage ranges of the comparison circuit 31 and the second comparison circuit 38, i.e., five voltage ranges (STATE) each. Alternatively, it can be set to alternate between the pulse mode representing the voltage range of the comparison circuit 31 and the pulse mode representing the voltage range of the second comparison circuit 38. The pulse mode of one of the comparison circuits can also be set to be output only in a predefined abnormal state.

[0079] As explained above, the voltage monitoring device 2c of this embodiment repeatedly outputs a predetermined pulse group in each predetermined pulse cycle, including a predetermined pulse width and a predetermined number of pulses corresponding to the voltage range of the input voltage VIN input to the input terminal 24 and the battery voltage VBAT of the battery 1. The voltage monitoring device 2c of this embodiment can periodically confirm that the input voltage VIN and the battery voltage VBAT are within the predetermined voltage range in each predetermined pulse cycle.

[0080] [Fifth Implementation Method]

[0081] Reference Figure 9The structure of the voltage monitoring device 2d according to the fifth embodiment of the present invention will be described. Furthermore, components identical to those in the fourth embodiment are labeled with the same numbers as in the fourth embodiment, and their descriptions are omitted. Figure 9 This is a block diagram showing the voltage monitoring device 2d in the fifth embodiment.

[0082] In this embodiment, the voltage monitoring device 2d is configured to connect the VDD terminal 21 to the comparator circuit 31. The VDD terminal 21 is internally connected to the power supply VDD and the comparator circuit 31 within the voltage monitoring device 2d. Furthermore, a sensor circuit 37 is included instead of the input terminal 24 of the voltage monitoring device 2c in the fourth embodiment. The sensor circuit 37 is connected to the second comparator circuit 38.

[0083] Comparison circuit 31 is connected to state determination circuit 32a, and similarly, second comparison circuit 38 is connected to state determination circuit 32a. State determination circuit 32a outputs a signal indicating the voltage range monitored by comparison circuit 31 and second comparison circuit 38 to pulse mode setting circuit 33. Pulse mode setting circuit 33 receives the output signal from state determination circuit 32a and outputs a pulse-shaped output signal OUT via output circuit 36, corresponding to the voltage output from VDD terminal 21 and sensor circuit 37.

[0084] The pulse mode output by the pulse mode setting circuit 33 can be set to represent any one of the 25 states formed by combining the monitoring voltage ranges of the comparison circuit 31 and the second comparison circuit 38, i.e., five voltage ranges (STATE) each. Alternatively, it can be set to alternate between the pulse mode representing the voltage range of the comparison circuit 31 and the pulse mode representing the voltage range of the second comparison circuit 38. The pulse mode of one of the comparison circuits can also be set to be output only in a predefined abnormal state.

[0085] As explained above, the voltage monitoring device 2d of this embodiment repeatedly outputs a predetermined pulse group in each predetermined pulse cycle, including a predetermined pulse width and a predetermined number of pulses corresponding to the voltage range of the battery voltage VBAT of battery 1 and the sensor voltage output from sensor circuit 37. The voltage monitoring device 2d of this embodiment can periodically confirm that the battery voltage VBAT and the sensor voltage are within a predetermined voltage range in each predetermined pulse cycle.

[0086] [Sixth Implementation Method]

[0087] Reference Figure 10 The structure of the voltage monitoring device 2e according to the sixth embodiment of the present invention will be described. Furthermore, the components that are the same as those in the first embodiment are labeled with the same numbers as those in the first embodiment, and their descriptions are omitted. Figure 10This is a block diagram illustrating the voltage monitoring device 2e in the sixth embodiment. The voltage monitoring device 2e in this embodiment is configured such that the voltage monitoring device 2 in the first embodiment includes an abnormal signal input terminal 25. Furthermore, a state determination circuit 32b is included instead of the state determination circuit 32. The abnormal signal input terminal 25 is connected to the state determination circuit 32b. When the abnormal signal input terminal 25 receives an activation signal, the state determination circuit 32b determines an abnormal state and outputs the abnormal state to the pulse mode setting circuit 33. The pulse mode setting circuit 33 receives the output signal from the state determination circuit 32b and outputs a pulse-shaped output signal OUT corresponding to the abnormal state.

[0088] [Seventh Implementation Method]

[0089] Reference Figure 11 The structure of the seventh embodiment of the present invention will be described. Furthermore, components that are the same as those in the first embodiment are labeled with the same numbers as those in the first embodiment, and their descriptions are omitted. Figure 11 This is a block diagram showing the voltage monitoring device 16 in the seventh embodiment. The voltage monitoring device 16 of this embodiment includes the voltage monitoring device 2 of the first embodiment and a light-emitting device 3. The light-emitting device 3 of this embodiment is connected between the VDD terminal 21 and the output terminal 23 of the voltage monitoring device 2 of the first embodiment. The VDD terminal 21 of the voltage monitoring device 2 is connected to the positive terminal of the battery 1 via the second VDD terminal 26, and the VSS terminal 22 of the voltage monitoring device 2 is connected to the negative terminal of the battery 1 via the second VSS terminal 27. The input terminal 24 is connected to the output terminal of the sensor 5 via the second input terminal 28.

[0090] In this embodiment, the voltage monitoring device 16 causes the light-emitting device 3 to pulse and emit light in a pulse pattern that repeats in each predetermined pulse cycle, consisting of a predetermined pulse group with a predetermined pulse width and a predetermined number of pulses corresponding to the voltage range of the input voltage VIN from the sensor 5. The voltage monitoring device 16 of this embodiment can periodically confirm that the input voltage VIN output by the sensor 5 is within a predetermined voltage range in each predetermined pulse cycle. By receiving the light emitted by the light-emitting device 3 through a light-emitting receiving device, the voltage monitoring device 16 of this embodiment is capable of electrically isolated communication with the battery 1 and the voltage monitoring device 16.

[0091] The output circuit 36 ​​and pulse mode setting circuit 33 of the voltage monitoring device 16 are appropriately set so that the light-emitting receiver can accurately receive the pulse mode output by the light-emitting device 3. The output circuit 36 ​​is set to output an appropriate output current so that the light-emitting device 3 emits light at a communicable intensity. In addition, considering the required lighting and extinguishing time of the light-emitting device 3, the pulse mode setting circuit 33 is set to an appropriate pulse width.

[0092] Furthermore, this embodiment is designed as a structure in which a light-emitting device 3 is added to the voltage monitoring device 2 of the first embodiment, but it may also be a structure in which a light-emitting device 3 is added to the voltage monitoring device 2a of the second embodiment, the voltage monitoring device 2b of the third embodiment, the voltage monitoring device 2c of the fourth embodiment, and the voltage monitoring device 2d of the fifth embodiment. In addition, examples of the light-emitting device 3 include infrared light-emitting diodes or visible light-emitting diodes, but it is not limited to these.

[0093] [Eighth Implementation Method]

[0094] Reference Figure 12 The structure of the eighth embodiment of the present invention will be described. Furthermore, components that are the same as those in the seventh embodiment are labeled with the same numbers as those in the seventh embodiment, and their descriptions are omitted. Figure 12 This is a block diagram showing the voltage monitoring device 16a in the eighth embodiment. The voltage monitoring device 16a in this embodiment replaces the voltage monitoring device 2 of the seventh embodiment with a voltage monitoring device 2f that includes an abnormal current limiting device connection terminal 29. In the voltage monitoring device 2f, Figure 3 The source terminal of the NMOS transistor 362 in the output circuit 36 ​​shown is connected to the abnormal current limiting device connection terminal 29 instead of the power supply VSS. The voltage monitoring device 16a is configured such that an abnormal current limiting device 6 is connected between the abnormal current limiting device connection terminal 29 and the VSS terminal 22. When a current exceeding a preset current value flows between the terminals, the abnormal current limiting device 6 limits the current value.

[0095] In this structure, consider Figure 3 The output circuit 36 ​​shown is in the case of a short-circuit fault in the transistor. In the case of a short-circuit fault in the PMOS transistor 361, whenever pulse mode is activated, the through current flows through the output circuit 36 ​​to the abnormal current limiting device 6. However, when a current exceeding a preset current value flows between the terminals of the abnormal current limiting device 6, the current value is limited, thus limiting the abnormal current. The same applies to a short-circuit fault in the NMOS transistor 362, where the abnormal current is limited. Furthermore, this embodiment is a structure added to the seventh embodiment, but it could also be a structure added to the first to sixth embodiments. Additionally, even if the structure is configured such that an abnormal current limiting device connection terminal 29a is provided at the source terminal of the PMOS transistor 361 in the output circuit 36, connected to the VDD terminal 21 via the abnormal current limiting device connection terminal 29a, and the light-emitting device 3 is connected to the output terminal 23, the same effect can be obtained.

[0096] [Ninth Implementation Method]

[0097] Reference Figure 13The structure of the ninth embodiment of the present invention will be described. Furthermore, components that are the same as those in the third embodiment are labeled with the same numbers as those in the third embodiment, and their descriptions are omitted. Figure 13 This is a block diagram illustrating the voltage monitoring device 2g in the ninth embodiment. In this embodiment, the voltage monitoring device 2b of the third embodiment includes a communication terminal 30 and a pulse synthesis circuit 39. The communication terminal 30 is configured to be connected to the output circuit 36 ​​via the pulse synthesis circuit 39. The communication terminal 30 is externally daisy-chained to other voltage monitoring devices and outputs an output signal OUT from the output terminal 23 in conjunction with the monitoring status of other voltage monitoring devices.

[0098] The pulse synthesis circuit 39 is located between the pulse mode setting circuit 33 and the output circuit 36, and outputs the sum of the signal from the pulse mode setting circuit 33 and the signal from the communication terminal 30 to the output circuit 36.

[0099] Figure 14 This is an example of a daisy-chain structure connecting the voltage monitoring devices 2g of this embodiment. The communication terminal 30 of the first voltage monitoring device 2g-1 in this embodiment is connected to the output terminal 23 of the second voltage monitoring device 2g-2. The communication terminal 30 of the second voltage monitoring device 2g-2 is connected to a third voltage monitoring device 2g-3 (not shown). The voltage monitoring device of this embodiment can aggregate and output multiple battery monitoring results from the first voltage monitoring device 2g-1, which is the final stage. As described above, if the microcomputer determines the number of subsequent pulses based on the initial pulse width, it can determine the state (STATE), thus eliminating the need for clock synchronization between the voltage monitoring devices. Therefore, a multi-voltage monitoring system can be easily and inexpensively constructed while reducing the communication load on the processing circuit.

[0100] Furthermore, the pulse period has been explained up to this point using 1024ms as an example. However, in cases where signals from multiple voltage monitoring devices are aggregated via a daisy chain, a longer pulse period, such as 60s (60 seconds), can be set to avoid interference between the output signals.

[0101] [Tenth Implementation Method]

[0102] Reference Figure 15 The structure of the tenth embodiment of the present invention will be described. Furthermore, components that are the same as those in the third embodiment are labeled with the same numbers as those in the third embodiment, and their descriptions are omitted. Figure 15This is a block diagram illustrating the voltage monitoring device 2h in the tenth embodiment. In this embodiment, the voltage monitoring device 2b of the third embodiment includes a communication terminal 30, a pulse determination circuit 40, and a status comparison circuit 41. The communication terminal 30 is configured to be connected to the status comparison circuit 41 via the pulse determination circuit 40. The status comparison circuit 41 is configured to be connected to the status determination circuit 32, the pulse determination circuit 40, and the pulse mode setting circuit 33. The communication terminal 30 is externally daisy-chained to other voltage monitoring devices and outputs an output signal OUT from the output terminal 23 in conjunction with the monitoring status of other voltage monitoring devices.

[0103] The pulse determination circuit 40 receives a pulse signal from the communication terminal 30 and outputs the state signal (STATE) indicated by the pulse signal to the state comparison circuit 41. The state comparison circuit 41 compares the state signal (STATE) from the state determination circuit 32 with the state signal (STATE) from the pulse determination circuit 40 using a predefined reference, and outputs the state signal (STATE) determined to be more important to the pulse mode setting circuit 33.

[0104] Figure 16 This is an example of a daisy-chain connection structure for the voltage monitoring devices 2h of this embodiment. The communication terminal 30 of the first voltage monitoring device 2h-1 in this embodiment is connected to the output terminal 23 of the second voltage monitoring device 2h-2. The communication terminal 30 of the second voltage monitoring device 2h-2 is connected to a third voltage monitoring device 2h-3 (not shown). The voltage monitoring device of this embodiment can output the monitoring result with the highest importance among multiple battery monitoring results from the voltage monitoring device 2h-1. As described above, if the microcomputer determines the number of subsequent pulses based on the initial pulse width, it can determine the state (STATE), thus eliminating the need for clock synchronization between the voltage monitoring devices. Therefore, a multi-voltage monitoring system can be easily and inexpensively constructed while reducing the communication load on the processing circuit.

[0105] According to the voltage monitoring device of the present invention, a predetermined pulse group, including a predetermined pulse width and a predetermined number of pulses preset according to the monitored voltage state, is repeatedly output in each predetermined pulse cycle, thereby periodically confirming the state of the monitored voltage. Therefore, in the event of an abnormality where the output terminal of the voltage monitoring device is internally short-circuited to the power supply, the abnormality of the voltage monitoring device can be determined.

Claims

1. A voltage monitoring device, comprising: The circuit includes a comparator circuit, a state determination circuit, a pulse mode setting circuit, an output circuit, a VDD terminal, a VSS terminal, input terminals, and output terminals. The comparison circuit is connected to the state determination circuit. The state determination circuit is connected to the pulse mode setting circuit. The pulse mode setting circuit is connected to the output terminal via the output circuit. The VDD terminal is connected to the power supply VDD within the voltage monitoring device, and the VSS terminal is connected to the power supply VSS within the voltage monitoring device. The comparator circuit has two resistor circuits, two comparators, and a voltage source. The two resistor circuits each have multiple switches controlled by the state determination circuit, and multiple voltage divider resistors connected to the multiple switches. Each resistor circuit uses the voltage-dividing resistor selected by the plurality of switches to divide the voltage input to the resistor circuit, and then inputs the divided voltage to one of the two comparators. The comparison circuit receives the voltages from each resistor circuit and the voltage from the voltage source as inputs, and outputs the comparison result to the state determination circuit. The state determination circuit determines, based on the output of the comparator in the comparison circuit, which of a plurality of voltage ranges the input voltage at the input terminal belongs to, and outputs a signal to control the plurality of switches in the resistor circuit to set a new monitoring voltage range for the comparison circuit, based on the determined voltage range. The state determination circuit outputs a signal to control the pulse mode setting circuit based on the output of the comparator in the comparison circuit.

2. The voltage monitoring device according to claim 1, wherein, The voltage input to the comparator circuit is the voltage input from the input terminal.

3. The voltage monitoring device according to claim 1 further includes a sensor circuit. The voltage input to the comparison circuit is the voltage input from the sensor circuit.

4. The voltage monitoring device according to claim 1, wherein, The voltage input to the comparator circuit is the voltage input from the VDD terminal.

5. The voltage monitoring device according to claim 1 further includes a second comparison circuit. The voltage input to the second comparator circuit is the voltage input from the input terminal. The signal input to the state determination circuit is the signal input from the comparison circuit and the second comparison circuit.

6. The voltage monitoring device according to claim 1 further includes a sensor circuit and a second comparison circuit. The voltage input to the second comparator circuit is the voltage input from the sensor circuit. The signal input to the state determination circuit is the signal input from the comparison circuit and the second comparison circuit.

7. The voltage monitoring device according to claim 1 further includes an abnormal signal input terminal. The signal input from the abnormal signal input terminal is input to the state determination circuit.

8. The voltage monitoring device according to claim 1 further includes a light-emitting device. The light-emitting device is connected to the output terminal and the VDD terminal.

9. The voltage monitoring device according to claim 1 further includes an abnormal current limiting device connection terminal and an abnormal current limiting device. The output circuit has a P-channel metal-oxide-semiconductor transistor and an N-channel metal-oxide-semiconductor transistor. The source terminal of the N-channel metal-oxide-semiconductor transistor is connected to the connection terminal of the abnormal current limiting device. The abnormal current limiting device is connected to the abnormal current limiting device connection terminal.

10. The voltage monitoring device according to claim 1 further includes a communication terminal and a pulse synthesis circuit. The pulse mode setting circuit and the communication terminal are connected to the pulse synthesis circuit. The pulse synthesis circuit is connected to the output terminal via the output circuit.

11. The voltage monitoring device according to claim 1 further includes a communication terminal, a pulse determination circuit, and a state comparison circuit. The communication terminal is connected to the state comparison circuit via the pulse determination circuit. The state comparison circuit is connected to the state determination circuit, the pulse determination circuit, and the pulse mode setting circuit.

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