Semiconductor memory device and method for manufacturing the same

Abstract

A semiconductor memory device and a method for manufacturing the same are provided herein. The semiconductor memory device comprises: a stacked body, the stacked body comprising alternately stacked conductive patterns and interlayer insulating layers; a lower channel portion passing through the stacked body; a memory layer disposed between the stacked body and the lower channel portion; an upper channel portion disposed on the lower channel portion; a gate insulating layer surrounding a sidewall of the upper channel portion; a first gate pattern surrounding a sidewall of the gate insulating layer; a separation insulating pattern contacting a first portion of the first gate pattern; and a second gate pattern contacting a second portion of the first gate pattern.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to semiconductor memory devices and methods of manufacturing the same, and more particularly, to three-dimensional (3D) semiconductor memory devices and methods of manufacturing the 3D semiconductor memory devices. Background Art

[0002] In order to improve the integration of semiconductor memory devices, three-dimensional (3D) semiconductor memory devices have been proposed. The 3D semiconductor memory device may include memory cells arranged in three dimensions. The memory cells of the 3D semiconductor memory device may be stacked in the longitudinal direction of the channel structure. The channel structure may be connected to a bit line and a source line under the control of a selection transistor. Summary of the invention

[0003] Embodiments of the present disclosure may provide a method for manufacturing a semiconductor memory device. The method for manufacturing a semiconductor memory device may include the following steps: forming a stacked body; forming a channel hole passing through the stacked body; forming a memory layer on a sidewall of the channel hole; forming a lower channel portion in the channel hole; forming an upper channel portion on the lower channel portion; forming a gate insulating layer surrounding the sidewall of the upper channel portion; forming a first gate pattern surrounding the sidewall of the gate insulating layer; forming a separation insulating pattern contacting a first sidewall of the first gate pattern; and forming a second gate pattern contacting a second sidewall of the first gate pattern.

[0004] Embodiments of the present disclosure may provide a method for manufacturing a semiconductor memory device. The method for manufacturing a semiconductor memory device may include the following steps: forming a stack penetrated by a lower channel portion; forming an upper channel portion overlapping the lower channel portion; forming a gate insulating layer surrounding the sidewall of the upper channel portion; forming first gate patterns surrounding the sidewall of the gate insulating layer and arranged in a plurality of rows; forming a separation insulating pattern between a first row of the first gate patterns and a second row of the first gate patterns; forming a conductive layer filling a space between the first gate patterns; and forming second gate patterns separated from each other by etching the conductive layer so that the separation insulating pattern is exposed.

[0005] Embodiments of the present disclosure may provide a semiconductor memory device. The semiconductor memory device may include: a stacked body including alternately stacked conductive patterns and interlayer insulating layers; a lower channel portion passing through the stacked body; a memory layer disposed between the stacked body and the lower channel portion; an upper channel portion disposed on the lower channel portion; a gate insulating layer surrounding a sidewall of the upper channel portion; a first gate pattern surrounding a sidewall of the gate insulating layer; a separation insulating pattern contacting a first portion of the first gate pattern; and a second gate pattern contacting a second portion of the first gate pattern.

[0006] Embodiments of the present disclosure may provide a semiconductor memory device. The semiconductor memory device may include: a separation insulating pattern including a first surface and a second surface facing opposite directions; a first groove formed in the first surface of the separation insulating pattern; a second groove formed in the second surface of the separation insulating pattern; a first linear gate pattern contacting the first surface of the separation insulating pattern and including a third groove facing the first groove; a second linear gate pattern contacting the second surface of the separation insulating pattern and including a fourth groove facing the second groove; a first tubular gate pattern extending along a surface of the first groove and a surface of the third groove; a second tubular gate pattern extending along a surface of the second groove and a surface of the fourth groove; a channel portion inserted into a central area of ​​the first tubular gate pattern and the second tubular gate pattern; and a gate insulating layer disposed between each of the first tubular gate pattern and the second tubular gate pattern and each of the channel portions. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a circuit diagram showing a memory cell array of a semiconductor memory device according to an embodiment of the present disclosure.

[0008] Figure 2A is a perspective view schematically showing a partial region of a semiconductor memory device according to an embodiment of the present disclosure.

[0009] Figure 2B yes Figure 2A An enlarged cross-sectional view of region A.

[0010] Figure 3A and Figure 3B An embodiment of a layout of a semiconductor memory device at a height where drain select lines are arranged is shown.

[0011] Figure 4 is along Figure 3A A cross-sectional view of a semiconductor memory device taken along line II'.

[0012] Figure 5A is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure.

[0013] Figure 5B yes Figure 5A An exploded perspective view of a partial area of ​​a semiconductor memory device.

[0014] Figure 6 is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure.

[0015] Figure 7 is a plan view showing the stack, memory layer, and lower channel portion.

[0016] Fig. 8A , Figure 8B and Figure 8C is a cross-sectional view illustrating an embodiment of a method of manufacturing a stack, a memory layer, and a lower channel portion.

[0017] Fig. 9 and Fig.10 2 are a plan view and a cross-sectional view respectively illustrating an embodiment of a method of manufacturing an upper stack and a first mask pattern.

[0018] Fig.11A , Fig. 11B , Fig. 11C and Fig.11D is a cross-sectional view illustrating an embodiment of a subsequent process to be performed after forming a first mask pattern.

[0019] Fig.12 is a cross-sectional view illustrating an embodiment of a subsequent process to be performed after forming an insulating layer.

[0020] Fig.13 is along Fig.12 A plan view taken along line III-III'.

[0021] Fig.14 and Fig.15 1 and 2 are respectively a plan view and a cross-sectional view showing an embodiment of a method of manufacturing a separate insulation pattern.

[0022] Fig.16 is a cross-sectional view showing an embodiment of a method of manufacturing a conductive layer.

[0023] Fig.17A , Fig. 17B and Fig. 17C It shows that Fig.16 An enlarged cross-sectional view of an embodiment of a subsequent process of region C is shown.

[0024] Fig.18 is along Fig. 17C Plan view taken along line IV-IV'.

[0025] Fig.19 is a plan view showing a first mask pattern, an upper insulating layer, a sidewall insulating layer, and a vertical source contact.

[0026] Fig. 20A , Fig. 20B , Fig. 20C , Fig.20D and Fig.20E It shows the manufacturing Fig.19 A cross-sectional view of an embodiment of a method of constructing.

[0027] Fig.21A , Fig. 21B , Fig. 21C , Fig.21D and Fig.21E It is shown in the formation Fig.20E sectional view of an embodiment of a subsequent process to be performed after the structure of FIG.

[0028] Fig.22A and Fig. 22B It shows that Fig.16 An enlarged cross-sectional view of an embodiment of a subsequent process of region C is shown.

[0029] Fig.23A , Fig. 23B , Fig.23C , Fig.23D , Fig.23E , Fig.23F , Figure 23G and Fig.23H It is shown in Fig.11D A cross-sectional view of an embodiment of a subsequent process to be performed after the process of FIG.

[0030] Fig.24 is a block diagram showing a configuration of a memory system according to an embodiment of the present disclosure.

[0031] Fig.25 is a block diagram illustrating a configuration of a computing system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] The description of the specific structures and functions disclosed herein is only for the purpose of describing embodiments according to the concepts of the present disclosure. Embodiments according to the concepts of the present disclosure can be implemented in various forms, and they should not be interpreted as limited to the specific embodiments set forth herein.

[0033] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element, and do not imply the number or order of the elements.

[0034] Various embodiments of the present disclosure relate to a semiconductor memory device having improved operational reliability and a method of manufacturing the semiconductor memory device.

[0035] Figure 1 is a circuit diagram showing a memory cell array of a semiconductor memory device according to an embodiment of the present disclosure.

[0036] Reference Figure 1, the memory cell array may include a plurality of memory cell strings CS1 and CS2 coupled to a bit line BL. The plurality of memory cell strings CS1 and CS2 may be commonly coupled to a source line SL. In one embodiment, the plurality of memory cell strings CS1 and the plurality of memory cell strings CS2 may be commonly coupled to a source line SL.

[0037] A pair of first and second memory cell strings CS1 and CS2 may be coupled to each of the bit lines BL.

[0038] Each of the first and second memory cell strings CS1 and CS2 may include a source select transistor SST, a plurality of memory cells MC, and a drain select transistor DST arranged between a source line SL and a corresponding bit line BL.

[0039] The source select transistor SST may control the electrical connection between the plurality of memory cells MC and the source line SL. A single source select transistor SST may be arranged between the source line SL and the plurality of memory cells MC. Although not shown in the figure, two or more source select transistors connected in series may be arranged between the source line SL and the plurality of memory cells MC. The source select transistor SST may be connected to a source select line SSL. The operation of the source select transistor SST may be controlled in response to a source gate signal applied to the source select line SSL.

[0040] The plurality of memory cells MC may be arranged in series between a source selection transistor SST and a drain selection transistor DST. The memory cells MC between the source selection transistor SST and the drain selection transistor DST may be connected in series to each other. The memory cells MC may be connected to word lines WL, respectively. The operation of the memory cells MC may be controlled in response to a cell gate signal applied to the word line WL.

[0041] The drain select transistor DST may control electrical coupling between a plurality of memory cells MC and corresponding bit lines BL. The drain select transistor DST may be coupled to a drain select line DSL1 or DSL2. The operation of the drain select transistor DST may be controlled in response to a drain gate signal applied to the drain select line DSL1 or DSL2.

[0042] The first memory cell string CS1 may be coupled to the first drain selection line DSL1. The second memory cell string CS2 may be coupled to the second drain selection line DSL2. Thus, the first memory cell string CS1 or the second memory cell string CS2 may be selected by selecting one of the bit lines BL and selecting one of the first drain selection line DSL1 and the second drain selection line DSL2.

[0043] The first and second memory cell strings CS1 and CS2 may be commonly coupled to respective word lines WL.

[0044] The first memory cell string CS1 and the second memory cell string CS2 may be commonly connected to a source selection line SSL. The embodiments of the present disclosure are not limited thereto. Although not shown in the figures, in one embodiment, the memory cell array may include a first source selection line and a second source selection line separated from each other. The first source selection line may be connected to the first memory cell string, and the second source selection line may be connected to the second memory cell string.

[0045] Figure 2A is a perspective view schematically showing a partial region of a semiconductor memory device according to an embodiment of the present disclosure.

[0046] Reference Figure 2A , the semiconductor memory device may include a stack body 10, a channel structure, a memory layer 21, a gate insulating layer 35, a first gate pattern 41, a second gate pattern 45, and a separation insulating pattern 43. The channel structure may include a lower channel portion CH1 and an upper channel portion CH2.

[0047] The stacked body 10 may include a conductive pattern 13 and an interlayer insulating layer 11 . Figure 2A A portion of the stack 10 is shown. Figure 2A The conductive pattern 13 shown in FIG. 1 can be used as the reference numeral 13 in the above reference numeral 13. Figure 1 The word line WL described. Each of the interlayer insulating layer 11 and the conductive pattern 13 may have a planar shape extending in the XY plane. The interlayer insulating layer 11 and the conductive pattern 13 may be alternately stacked in the Z-axis direction. The Z-axis direction may be defined as a longitudinal direction of each of the lower channel portion CH1 and the upper channel portion CH2.

[0048] The lower channel portion CH1 may penetrate the stack body 10 . A memory layer 21 may be disposed between each of the lower channel portions CH1 and the stack body 10 . Figure 2A A portion of each of the lower channel portions CH1 and a portion of the memory layer 21 are shown.

[0049] Each of the lower channel portions CH1 may include a channel layer 23, a core insulating layer 25, and a semiconductor pattern 31. The channel layer 23 may extend along the inner wall 21SW of the memory layer 21. The channel layer 23 may include a semiconductor material such as silicon. The core insulating layer 25 and the semiconductor pattern 31 may fill a central region CH1[CO] of each lower channel portion CH1. The core insulating layer 25 may be surrounded by the channel layer 23. The semiconductor pattern 31 may be disposed between the core insulating layer 25 and the corresponding upper channel portion CH2. The semiconductor pattern 31 may include a semiconductor material such as silicon.

[0050] The upper channel portions CH2 may be disposed on the lower channel portions CH1, respectively. The channel structure of each memory cell string may include the lower channel portion CH1 and the upper channel portion CH2 coupled to each other.

[0051] The upper channel portion CH2 may be stably coupled to the lower channel portion CH1 through the semiconductor pattern 31. Each upper channel portion CH2 may include a semiconductor material such as silicon. Each upper channel portion CH2 may include a first region 33A and a second region 33B. The first region 33A may be formed of a substantially intrinsic semiconductor material. The second region 33B may be a doped region including conductive impurities. In one embodiment, the second region 33B may include n-type impurities.

[0052] The gate insulating layer 35 may surround the corresponding sidewall 33SW of the upper channel portion CH2. Each gate insulating layer 35 may include a semiconductor oxide. In one embodiment, each gate insulating layer 35 may include silicon oxide.

[0053] The first gate pattern 41 may surround corresponding sidewalls 35SW of the gate insulating layer 35 .

[0054] The second gate pattern 45 may include a first linear gate pattern 45L1 and a second linear gate pattern 45L2 isolated from each other by a separation insulating pattern 43. The first linear gate pattern 45L1 and the second linear gate pattern 45L2 may extend in parallel. In one embodiment, each of the first linear gate pattern 45L1 and the second linear gate pattern 45L2 may extend in the Y-axis direction.

[0055] The first gate patterns 41 spaced apart from each other may be coupled to each other through the first linear gate pattern 45L1 or the second linear gate pattern 45L2. The first linear gate pattern 45L1 and some of the first gate patterns 41 coupled to the first linear gate pattern 45L1 may be used as the reference numerals above. Figure 1 The first drain selection line DSL1 described above. The second linear gate pattern 45L2 and other first gate patterns 41 connected to the second linear gate pattern 45L2 among the first gate patterns 41 may be used as the reference numerals in the above Figure 1 The second drain selection line DSL2.

[0056] The first gate pattern 41 may include a conductive material different from that of the second gate pattern 45. In one embodiment, the first gate pattern 41 may include a conductive barrier layer formed of titanium or titanium nitride, etc. The second gate pattern 45 may include a metal layer formed of tungsten, etc.

[0057] The first gate pattern 41 may include the same kind of conductive material as the second gate pattern 45. In one embodiment, the first gate pattern 41 and the second gate pattern 45 may include a refractory metal. The refractory metal may include titanium nitride, tantalum nitride, tungsten nitride, or the like.

[0058] The separation insulating pattern 43 may include a vertical portion 43P1 and a horizontal portion 43P2. The vertical portion 43P1 of the separation insulating pattern 43 may be disposed between the first linear gate pattern 45L1 and the second linear gate pattern 45L2. The first linear gate pattern 45L1 and the second linear gate pattern 45L2 may be isolated from each other by the vertical portion 43P1 of the separation insulating pattern 43. The horizontal portion 43P2 of the separation insulating pattern 43 may extend from the vertical portion 43P1. The horizontal portion 43P2 of the separation insulating pattern 43 may extend into a space between each of the first linear gate pattern 45L1 and the second linear gate pattern 45L2 and the stacked body 10. The horizontal portion 43P2 of the separation insulating pattern 43 may surround the first gate pattern 41.

[0059] Each of the interlayer insulating layer 11 and the conductive pattern 13 may continuously extend in the XY plane such that it overlaps the first linear gate pattern 45L1 , the vertical portion 43P1 of the separation insulating pattern 43 , and the second linear gate pattern 45L2 .

[0060] The semiconductor memory device may further include an upper insulating layer 47 and a conductive contact 49 .

[0061] The upper insulating layer 47 may cover the separation insulating pattern 43 and the second gate pattern 45 . Conductive contacts 49 may be disposed on the upper channel portions CH2 , respectively. The conductive contacts 49 may be isolated from each other by the upper insulating layer 47 .

[0062] Figure 2B yes Figure 2A An enlarged cross-sectional view of region A.

[0063] Reference Figure 2B , the memory layer 21 may include a tunnel insulating layer TL, a data storage layer DL, and a first blocking insulating layer BI1. The first blocking insulating layer BI1 may surround the channel layer 23. The first blocking insulating layer BI1 may extend to Figure 2AThe stack 10 shown in the figure has an uppermost interlayer insulating layer 11T and a separation insulating pattern 43 in the space between them. The data storage layer DL may be disposed between the first blocking insulating layer BI1 and the channel layer 23. The data storage layer DL may include a material capable of capturing charges. In one example, the data storage layer DL may include silicon nitride. The tunnel insulating layer TL may be disposed between the data storage layer DL and the channel layer 23. The tunnel insulating layer TL may include an insulating material capable of achieving charge tunneling. In one embodiment, the tunnel insulating layer TL may include silicon oxide.

[0064] The semiconductor memory device may further include a second blocking insulating layer BI2. The second blocking insulating layer BI2 may be disposed between the first blocking insulating layer BI1 and the conductive pattern 13. The second blocking insulating layer BI2 may extend into a space between each interlayer insulating layer 11 and the corresponding conductive pattern 13. The first blocking insulating layer BI1 and the second blocking insulating layer BI2 may each include an insulating material that blocks charges. The second blocking insulating layer BI2 may include an insulating material having a dielectric constant higher than that of the first blocking insulating layer BI1. In one embodiment, the first blocking insulating layer BI1 may include silicon oxide, and the second blocking insulating layer BI2 may include a metal oxide.

[0065] The first gate pattern 41 may be spaced apart from the channel layer 23 and the semiconductor pattern 31 of each of the lower channel portions CH1. In one embodiment, the gate insulating layer 35 may extend into a space between the first gate pattern 41 and the channel layer 23 of the lower channel portion CH1 and a space between the first gate pattern 41 and the semiconductor pattern 31 of the lower channel portion CH1. In this way, the first gate pattern 41 may be spaced apart from the channel layer 23 and the semiconductor pattern 31 of each of the lower channel portions CH1 by the gate insulating layer 35.

[0066] Each of the gate insulating layer 35 and the upper channel portion CH2 may protrude higher than each of the first and second gate patterns 41 and 45 in a direction toward the conductive contact 49. The upper channel portion CH2 may protrude higher than the gate insulating layer 35 in a direction toward the conductive contact 49.

[0067] A width W2 of each conductive contact 49 may be formed to be greater than a width W1 of the upper channel portion CH2 . In one embodiment, the conductive contact 49 may overlap the upper channel portion CH2 , and may extend onto the gate insulating layer 35 .

[0068] The conductive contact 49 may include a groove 49G. The upper portion of the upper channel portion CH2 may be inserted into the groove 49G. Through the conductive contact 49, the upper channel portion CH2 may be connected to the above-mentioned Figure 1 The bit line BL.

[0069] Figure 3A and Figure 3B An embodiment of a layout of a semiconductor memory device at a level where drain select lines are arranged is shown. Figure 3A Shown in the ratio Figure 2A The layout of the semiconductor memory device in a wider area of ​​the XY plane. Figure 3B It is shown Figure 3A An enlarged plan view of region B is shown. Hereinafter, repeated description of overlapping components will be omitted.

[0070] Reference Figure 3A , the semiconductor memory device may include drain selection lines DSL1, DSL2, and DSL3, which are divided into a first group DSL[A] and a second group DSL[B]. The first group DSL[A] and the second group DSL[B] may be disposed on both sides of the vertical source contact 53. In one embodiment, the first group DSL[A] may include a first drain selection line DSL1 and a second drain selection line DSL2, and the second group DSL[B] may include a third drain selection line DSL3.

[0071] The vertical source contact 53 may include at least one of a doped semiconductor, a metal, a metal silicide, and a metal nitride.

[0072] The first group DSL[A] and the second group DSL[B] may be spaced apart from the vertical source contact 53. Sidewalls of the vertical source contact 53 may be covered with a sidewall insulating layer 51.

[0073] Each of the first drain selection line DSL1, the second drain selection line DSL2, and the third drain selection line DSL3 may include first gate patterns 41 spaced apart from each other and second gate patterns 45 coupling the first gate patterns 41 to each other. The second gate pattern 45 of the first drain selection line DSL1 may be defined as a first linear gate pattern 45L1, and the second gate pattern 45 of the second drain selection line DSL2 may be defined as a second linear gate pattern 45L2.

[0074] The drain selection lines of each group may be isolated from each other by a separation insulating pattern 43. In one embodiment, the separation insulating pattern 43 may be disposed between the first drain selection line DSL1 and the second drain selection line DSL2. The first linear gate pattern 45L1 may be spaced apart from the second linear gate pattern 45L2 by the separation insulating pattern 43.

[0075] Each of the first gate patterns 41 may be a tubular gate pattern. The gate insulating layer 35 and the upper channel portion CH2 may be inserted into a central region defined by the tubular gate pattern.

[0076] The first gate patterns 41 may be arranged in a plurality of rows. The row direction may be defined as the extension direction of the second gate patterns 45. In one embodiment, the row direction may be the Y-axis direction. Each of the second gate patterns 45 may couple the first gate patterns 41 arranged in two or more rows to each other. In one embodiment, each of the first linear gate pattern 45L1 and the second linear gate pattern 45L2 may couple the first gate patterns 41 arranged in four rows to each other.

[0077] The separation insulating pattern 43 may be disposed between two adjacent rows. The first row and the second row of the first gate patterns 41 may be defined as adjacent rows. The separation insulating pattern 43 may be disposed between the first row and the second row. The first row of the first gate patterns 41 may be defined as a row included in the first drain selection line DSL1, and the second row of the first gate patterns 41 may be defined as a row included in the second drain selection line DSL2.

[0078] The first gate patterns 41 may include first tubular gate patterns 41T1 arranged in a first row, second tubular gate patterns 41T2 arranged in a second row, third tubular gate patterns 41T3 arranged in a third row, and fourth tubular gate patterns 41T4 arranged in a fourth row. The third row of the first gate patterns 41 may be defined as a row included in the first drain selection line DSL1, and the fourth row of the first gate patterns 41 may be defined as a row included in the second drain selection line DSL2. The first row and the second row may be defined as rows disposed between the third row and the fourth row.

[0079] Reference Figure 3B , the separation insulating pattern 43 may include a first surface SU1 and a second surface SU2 facing opposite directions. The separation insulating pattern 43 may include a first groove G1 formed in the first surface SU1 and a second groove G2 formed in the second surface SU2.

[0080] The first linear gate pattern 45L1 may contact the first surface SU1 of the separation insulating pattern 43. The first linear gate pattern 45L1 may include a third groove G3 facing the first groove G1 of the separation insulating pattern 43. The second linear gate pattern 45L2 may contact the second surface SU2 of the separation insulating pattern 43. The second linear gate pattern 45L2 may include a fourth groove G4 facing the second groove G2 of the separation insulating pattern 43.

[0081] The first tubular gate pattern 41T1 may extend along a surface of the first groove G1 and a surface of the third groove G3. The first tubular gate pattern 41T1 may be divided into a first portion T1A and a second portion T1B. The first portion T1A of the first tubular gate pattern 41T1 may be inserted into the first groove G1 of the separation insulating pattern 43 and may contact the separation insulating pattern 43. The second portion T1B of the first tubular gate pattern 41T1 may extend from the first portion T1A and may extend in a direction away from the separation insulating pattern 43. The second portion T1B of the first tubular gate pattern 41T1 may be inserted into the third groove G3 of the first linear gate pattern 45L1 and may contact the first linear gate pattern 45L1.

[0082] The second tubular gate pattern 41T2 may extend along the surface of the second groove G2 and the surface of the fourth groove G4. The second tubular gate pattern 41T2 may be divided into a first portion T2A and a second portion T2B. The first portion T2A of the second tubular gate pattern 41T2 may be inserted into the second groove G2 of the separation insulating pattern 43 and may contact the separation insulating pattern 43. The second portion T2B of the second tubular gate pattern 41T2 may be inserted into the fourth groove G4 of the second linear gate pattern 45L2 and may contact the second linear gate pattern 45L2.

[0083] The first linear gate pattern 45L1 may couple the first tubular gate pattern 41T1 to the third tubular gate pattern 41T3. The second linear gate pattern 45L2 may couple the second tubular gate pattern 41T2 to the fourth tubular gate pattern 41T4.

[0084] Figure 4 is along Figure 3A 1-1' is a cross-sectional view of a semiconductor memory device taken along line II' of FIG. 1-1. Hereinafter, repeated description of overlapping components will be omitted.

[0085] Reference Figure 4 The vertical source contact portion 53 may extend into a space between the stacked bodies 10A and 10B adjacent to each other. The sidewall insulating layer 51 may extend into a space between each of the stacked bodies 10A and 10B and the vertical source contact portion 53 .

[0086] The semiconductor memory device may further include a source line SL. The stacked bodies 10A and 10B may be disposed on the source line SL.

[0087] Each of the stacked bodies 10A and 10B may further include a lower interlayer insulating layer 11L and a lower conductive pattern 13L as described above with reference to Figure 2AThe interlayer insulating layers 11 and the conductive patterns 13 may be alternately stacked in a direction in which the interlayer insulating layers 11 and the conductive patterns 13 are alternately stacked.

[0088] The lower interlayer insulating layer 11L may be formed of the same insulating material as the interlayer insulating layer 11. The lower conductive pattern 13L may be formed of the same conductive material as the conductive pattern 13. In the lower conductive pattern 13L, at least one layer adjacent to the source line SL may be used as the above reference Figure 1 The source selection line SSL is described.

[0089] The channel layer 23 and the memory layer 21 may extend to the source line SL to pass through the lower interlayer insulating layer 11L and the lower conductive pattern 13L. A lower blocking insulating layer BI2L may be disposed between each lower conductive pattern 13L and the memory layer 21. The lower blocking insulating layer BI2L may extend into a space between each lower conductive pattern 13L and the corresponding lower interlayer insulating layer 11L. The lower blocking insulating layer BI2L may be formed of the same insulating material as the second blocking insulating layer BI2.

[0090] The source line SL may include a channel contact layer 3 in contact with the channel layer 23. The structure for contact between the channel contact layer 3 and the channel layer 23 may be implemented in various ways. In one embodiment, the channel contact layer 3 may surround a portion of a sidewall of the channel layer 23 and may be in contact with the sidewall of the channel layer 23. The channel contact layer 3 may be formed of a semiconductor material including conductive impurities. In one embodiment, the channel contact layer 3 may include n-type doped silicon.

[0091] The source line SL may further include a first doped semiconductor layer 1 disposed under the channel contact layer 3. The first doped semiconductor layer 1 may be doped with at least one of n-type and p-type impurities.

[0092] The channel layer 23 may extend to the inside of the first doped semiconductor layer 1. A dummy memory layer 21D may be further disposed between the channel layer 23 and the first doped semiconductor layer 1. The dummy memory layer 21D may be formed of the same material as the memory layer 21. The dummy memory layer 21D and the memory layer 21 may be separated from each other by the channel contact layer 3. The channel layer 23 may extend into the space between the dummy memory layer 21D and the core insulating layer 25.

[0093] The source line SL may further include a second doped semiconductor layer 5 disposed between each of the stacked bodies 10A and 10B and the channel contact layer 3. The second doped semiconductor layer 5 may include the same conductive impurities as the channel contact layer 3. Each of the memory layer 21, the channel layer 23, the core insulating layer 25, the sidewall insulating layer 51, and the vertical source contact 53 may pass through the second doped semiconductor layer 5.

[0094] The vertical source contact 53 may be coupled to the channel contact layer 3 .

[0095] The sidewall insulating layer 51 and the vertical source contact 53 may protrude upward higher than the semiconductor pattern 31. In one embodiment, the sidewall insulating layer 51 and the vertical source contact 53 may pass through the horizontal portion 43P2 of the separation insulating pattern 43.

[0096] The sidewall insulating layer 51 and the vertical source contact 53 may protrude upward higher than each of the first gate pattern 41, the vertical portion 43P1 of the separation insulating pattern 43, and the second gate pattern 45. The upper insulating layer 47 and the sidewall insulating layer 51 may be interposed between the second gate pattern 45 and the vertical source contact 53.

[0097] The semiconductor memory device may further include an upper source contact 55 disposed on the vertical source contact 53. The upper source contact 55 may include the same conductive material as the conductive contact 49. The upper insulating layer 47 and the sidewall insulating layer 51 may be interposed between the upper source contact 55 and the conductive contact 49 adjacent to the upper source contact 55.

[0098] Although not shown in the figure, the above reference Figure 1 The depicted bit line BL may be disposed on the conductive contact 49 and may extend in a direction intersecting the second gate pattern 45 .

[0099] Figure 5A is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure. Figure 5A Modifications of the first gate pattern 41' and the second gate pattern 45' are shown. Hereinafter, repeated descriptions of overlapping components will be omitted.

[0100] Reference Figure 5A The semiconductor memory device may include a stack body 10 , a lower channel portion CH1 , a memory layer 21 , an upper channel portion CH2 , a first gate pattern 41 ′, a second gate pattern 45 ′, a gate insulating layer 35 , a separation insulating pattern 43 , an upper insulating layer 47 , and a conductive contact 49 .

[0101] The stacked body 10 may include a conductive pattern 13 and an interlayer insulating layer 11. Each of the lower channel portions CH1 may include a channel layer 23, a core insulating layer 25, and a semiconductor pattern 31. The separation insulating pattern 43 may include a vertical portion 43P1 and a horizontal portion 43P2.

[0102] The vertical portion 43P1 of the separation insulating pattern 43 may protrude higher than the second gate pattern 45' in the Z-axis direction. In other words, the top surface of each of the first linear gate pattern 45L1' and the second linear gate pattern 45L2' of the second gate pattern 45' may be disposed at a height lower than the top surface of the vertical portion 43P1 of the separation insulating pattern 43.

[0103] Similar to reference Figure 3A and Figure 3B As described above, the first gate pattern 41' may include tubular gate patterns arranged in a plurality of rows. Some tubular gate patterns may be formed asymmetrically. Figure 5B Describe the tubular grid pattern.

[0104] Figure 5B yes Figure 5A An exploded perspective view of a partial area of ​​a semiconductor memory device.

[0105] Reference Figure 5B , the first gate pattern 41 ′ may include a first tubular gate pattern 41T1 ′, a second tubular gate pattern 41T2 ′, a third tubular gate pattern 41T3 ′, and a fourth tubular gate pattern 41T4 ′.

[0106] The first tubular gate pattern 41T1' and the second tubular gate pattern 41T2' may be arranged in the first and second rows adjacent to each other of the first gate pattern 41', respectively. The third tubular gate pattern 41T3' and the fourth tubular gate pattern 41T4' may be arranged in the third and fourth rows of the first gate pattern 41', respectively. The first and second rows may be disposed between the third and fourth rows.

[0107] The vertical portion 43P1 of the separation insulating pattern 43 may be disposed between the first row and the second row.

[0108] The first tubular gate pattern 41T1' may include a first portion T1A' and a second portion T1B', and the second tubular gate pattern 41T2' may also include a first portion T2A' and a second portion T2B'. The first portion T1A' of the first tubular gate pattern 41T1' and the first portion T2A' of the second tubular gate pattern 41T2' may contact the separation insulating pattern 43. The second portion T1B' of the first tubular gate pattern 41T1' and the second portion T2B' of the second tubular gate pattern 41T2' may contact the first linear gate pattern 45L1' and the second linear gate pattern 45L2', respectively. The first portions T1A' and T2A' may protrude higher than the second portions T1B' and T2B' in the Z-axis direction. In this way, each of the first tubular gate pattern 41T1' and the second tubular gate pattern 41T2' may be defined as an asymmetric gate pattern. The first portions T1A′ and T2A′ may protrude higher than the third and fourth tubular gate patterns 41T3 ′ and 41T4 ′ in the Z-axis direction.

[0109] The first linear gate pattern 45L1' and the second linear gate pattern 45L2' may be disposed on the horizontal portion 43P2 of the separation insulating pattern 43. The first groove G1 and the second groove G2 may be formed in both sidewalls of the vertical portion 43P1 of the separation insulating pattern 43, respectively. The third groove G3 and the fourth groove G4 may be formed in the sidewalls of the first linear gate pattern 45L1' and the second linear gate pattern 45L2', respectively. The first groove G1 of the separation insulating pattern 43 may be disposed to face the third groove G3 of the first linear gate pattern 45L1'. The second groove G2 of the separation insulating pattern 43 may be disposed to face the fourth groove G4 of the second linear gate pattern 45L2'.

[0110] The first portion T1A' of the first tubular gate pattern 41T1' and the first portion T2A' of the second tubular gate pattern 41T2' may be inserted into the first and second grooves G1 and G2, respectively. The second portion T1B' of the first and second tubular gate patterns 41T1' and the second portion T2B' of the second tubular gate pattern 41T2' may be inserted into the third and fourth grooves G3 and G4, respectively.

[0111] The first linear gate pattern 45L1' and the second linear gate pattern 45L2' may include a first hole 45H. Some of the third tubular gate pattern 41T3' and the fourth tubular gate pattern 41T4' may be inserted into the first hole 45H.

[0112] The horizontal portion 43P2 of the separation insulating pattern 43 may be penetrated by the second hole 43H. Lower portions of the first to fourth tubular gate patterns 41T1', 41T2', 41T3', and 41T4' may be inserted into the second hole 43H.

[0113] The upper channel portion CH2 and a portion of the gate insulating layer 35 may be inserted into a central region of each of the first to fourth tubular gate patterns 41T1 ′, 41T2 ′, 41T3 ′, and 41T4 ′.

[0114] Figure 6 is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure. Figure 6 Modifications of the sidewall insulating layer 51' and the vertical source contact 53' are shown. Hereinafter, repeated descriptions of the overlapping components will be omitted.

[0115] Reference Figure 6 The semiconductor memory device may include a source line SL, stack bodies 10A and 10B adjacent to each other, a sidewall insulating layer 51', a vertical source contact 53', a memory layer 21, a dummy memory layer 21D, a lower channel portion CH1, a separation insulating pattern 43, an upper channel portion CH2, a gate insulating layer 35, a first gate pattern 41, a second gate pattern 45, an upper insulating layer 47 and a conductive contact 49.

[0116] The source line SL may include a first doped semiconductor layer 1 , a channel contact layer 3 , and a second doped semiconductor layer 5 .

[0117] The stacked bodies 10A and 10B may be disposed on the source line SL.

[0118] A sidewall insulating layer 51 ′ may be formed on a sidewall of each of the stacked bodies 10A and 10B. A vertical source contact portion 53 ′ may extend from the channel contact layer 3 in the Z-axis direction.

[0119] The lower channel portion CH1 may include a channel layer 23, a core insulation layer 25, and a semiconductor pattern 31. The sidewall insulation layer 51' and the vertical source contact 53' may protrude higher than the lower channel portion CH1 in the Z-axis direction. In one embodiment, the sidewall insulation layer 51' and the vertical source contact 53' may pass through the horizontal portion 43P2 of the separation insulation pattern 43.

[0120] A top surface of each of the sidewall insulating layer 51' and the vertical source contact 53' may be disposed at a height lower than a height of a top surface of each of the upper channel portion CH2, the gate insulating layer 35, the first gate pattern 41, and the second gate pattern 45. An upper insulating layer 47 may cover a top surface of each of the sidewall insulating layer 51' and the vertical source contact 53'.

[0121] Hereinafter, a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure will be described.

[0122] Figure 7is a plan view showing the stack, memory layer, and lower channel portion.

[0123] Reference Figure 7 , the stack 110 may extend along the XY plane. The stack 110 may include isolation regions IR1 and IR2 and array regions AR1 and AR2. The isolation regions IR1 and IR2 and the array regions AR1 and AR2 may extend in parallel. In the XY plane, the isolation regions IR1 and IR2 may be arranged to alternate with the array regions AR1 and AR2. In one embodiment, the isolation regions IR1 and IR2 and the array regions AR1 and AR2 may be arranged alternately in the X-axis direction.

[0124] In each of the array areas AR1 and AR2, the stack 110 may be penetrated by the channel hole 117. The channel hole 117 may form a plurality of rows and a plurality of columns. The Y-axis direction may be defined as a row direction, and the X-axis direction may be defined as a column direction.

[0125] The memory layer 121 may be disposed on a sidewall of each channel hole 117 .

[0126] The lower channel portions 130 may be disposed within the corresponding channel holes 117. Each of the lower channel portions 130 may include a channel layer 123 and a semiconductor pattern 131.

[0127] The array regions AR1 and AR2 may include a first array region AR1 and a second array region AR2. The lower channel portions 130 may include a first group passing through the stack 110 in the first array region AR1 and a second group passing through the stack 110 in the second array region AR2. A distance L1 between the lower channel portions 130 in each group may be shorter than a distance L2 between the first group of the lower channel portions 130 and the second group of the lower channel portions 130.

[0128] Fig. 8A , Figure 8B and Figure 8C is a cross-sectional view illustrating an embodiment of a method of manufacturing a stack, a memory layer, and a lower channel portion. Fig. 8A , Figure 8B and Figure 8C is along Figure 7 A cross-sectional view taken along line II-II'.

[0129] Reference Fig. 8A , a stack 110 may be formed on the preliminary source structure 100 .

[0130] In one embodiment, the preliminary source structure 100 may include a first doped semiconductor layer 101, a first source protection layer 103, a sacrificial source layer 105, a second source protection layer 107, and a preliminary source layer 109 stacked sequentially. The first doped semiconductor layer 101 may include at least one of n-type and p-type impurities. In one embodiment, the first doped semiconductor layer 101 may include n-type doped silicon. The first source protection layer 103 and the second source protection layer 107 may be formed of a material capable of protecting the first doped semiconductor layer 101 and the preliminary source layer 109 during a subsequent etching process for selectively removing the sacrificial source layer 105. In one embodiment, the first source protection layer 103 and the second source protection layer 107 may include an oxide. The sacrificial source layer 105 may include silicon. The preliminary source layer 109 may include undoped silicon or doped silicon.

[0131] The stack 110 may include first material layers 111 and second material layers 113 alternately stacked on the preliminary source structure 100. The second material layer 113 may be formed of a material different from that of the first material layer 111. In one embodiment, the first material layer 111 may include oxide, and the second material layer 113 may include nitride.

[0132] After the stacked body 110 is formed, a channel hole 117 may be formed through the stacked body 110. The channel hole 117 may extend to the inside of the first doped semiconductor layer 101 of the preliminary source structure 100.

[0133] Then, a memory layer 121 may be formed on the surface of each channel hole 117. The memory layer 121 may include Figure 2B The tunnel insulating layer TL, the data storage layer DL, and the first blocking insulating layer BI1 are shown. The memory layer 121 may extend to overlap with the top surface of the stack body 110.

[0134] Thereafter, a channel layer 123 may be formed on the memory layer 121 . The channel layer 123 may include a semiconductor material such as silicon. The channel layer 123 may extend to overlap with a top surface of the stack body 110 .

[0135] Next, a central region of each channel hole 117 defined by the channel layer 123 may be filled with the core insulating layer 125 .

[0136] Reference Figure 8B , a portion of the core insulating layer 125 may be etched. In this way, a recessed region 129 may be defined at the top of each channel hole 117.

[0137] Reference Figure 8C , the semiconductor pattern 131 can be used to fill Figure 8BThe process for forming the semiconductor pattern 131 may include applying a semiconductor material onto the channel layer 123 to fill the channel layer 123. Figure 8B and performing a planarization process so that the semiconductor material remains only in the channel hole 117 .

[0138] A process for planarizing the semiconductor material may be performed so that the memory layer 121 is exposed. In this way, lower channel parts 130 may be formed in corresponding channel holes 117. Each lower channel part 130 may include a channel layer 123, a core insulating layer 125, and a semiconductor pattern 131.

[0139] Fig. 9 and Fig.10 2 are a plan view and a cross-sectional view respectively illustrating an embodiment of a method of manufacturing an upper stack and a first mask pattern. Fig.10 is along Fig. 9 A cross-sectional view taken along line II-II'.

[0140] Reference Fig. 9 and Fig.10 , an upper stack 140 overlapping the lower channel portion 130 and the stack 110 may be formed. Thereafter, a first mask pattern 147 overlapping each of the lower channel portions 130 may be formed on the upper stack 140 .

[0141] The upper stack 140 may include a semiconductor layer 141, a protective layer 143, and a sacrificial layer 145. The semiconductor layer 141 may overlap the stack 110 and the lower channel portion 130. The semiconductor layer 141 may be formed of a substantially intrinsic semiconductor material. The protective layer 143 may be formed on the semiconductor layer 141. The sacrificial layer 145 may be formed on the protective layer 143. The protective layer 143 may include an insulating material having an etching selectivity with respect to the semiconductor layer 141 and the sacrificial layer 145. In one embodiment, the protective layer 143 may include an oxide, and the semiconductor layer 141 and the sacrificial layer 145 may include silicon.

[0142] A first mask pattern 147 may be formed on the sacrificial layer 145. The first mask pattern 147 may include a material having an etch selectivity with respect to the semiconductor layer 141, the protective layer 143, and the sacrificial layer 145. In an embodiment, the first mask pattern 147 may include nitride.

[0143] Fig.11A , Fig. 11B , Fig. 11C and Fig.11D is a cross-sectional view illustrating an embodiment of a subsequent process to be performed after forming a first mask pattern.

[0144] Reference Fig.11A, by an etching process using the first mask pattern 147 as an etching barrier, it is possible to etch Fig.10 The semiconductor layer 141, the protective layer 143 and the sacrificial layer 145 are shown. In this way, Fig.10 The semiconductor layer 141 shown may be patterned into an upper channel portion 141C. Fig.10 The sacrificial layer 145 is shown patterned into sacrificial patterns 145S.

[0145] The upper channel portions 141C may be spaced apart from each other. The upper channel portions 141C may be disposed on the lower channel portions 130, respectively. According to an embodiment of the present disclosure, the upper channel portions 141C may be defined as having a shape similar to that of the lower channel portions 130. Fig.10 The thickness of the semiconductor layer 141 is shown to be uniform over the length.

[0146] The sacrificial patterns 145S may be disposed on the upper channel portions 141C, respectively. The protective layer 143 may remain between the upper channel portions 141C and the sacrificial patterns 145S.

[0147] In one embodiment, the width of each of the upper channel portions 141C may be controlled to be smaller than the width of each of the lower channel portions 130. In this case, an edge of a top surface of each of the lower channel portions 130 may be exposed.

[0148] Reference Fig. 11B , a gate insulating layer 149 may be formed through an oxidation process. The gate insulating layers 149 may be formed on sidewalls of the upper channel portions 141C, respectively, and may extend onto sidewalls of the sacrificial patterns 145S, respectively.

[0149] During the oxidation process, a portion of the channel layer 123 and a portion of the semiconductor pattern 131 of each lower channel portion 130 may be oxidized. In this manner, each gate insulating layer 149 may include a protrusion 149P extending along an edge of a top surface of each lower channel portion 130 .

[0150] Reference Fig. 11C , a first gate pattern 151 surrounding a corresponding sidewall of the gate insulating layer 149 may be formed.

[0151] The process for forming the first gate pattern 151 may include a step of conformally depositing a conductive barrier layer and a step of etching the conductive barrier layer by an etch-back process. The conductive barrier layer may include titanium, titanium nitride, or the like.

[0152] The protrusion 149P of the gate insulating layer 149 allows the first gate pattern 151 to be spaced apart from the channel layer 123 and the semiconductor pattern 131 of the lower channel portion 130 .

[0153] Reference Fig.11D , an insulating layer 153 may be formed on the stacked body 110. The insulating layer 153 may cover the first gate pattern 151 and the first mask pattern 147. The insulating layer 153 may be formed to fill a space between the first gate patterns 151.

[0154] Fig.12 is a cross-sectional view illustrating an embodiment of a subsequent process to be performed after forming an insulating layer.

[0155] Reference Fig.12 , can be etched Fig.11D The insulating layer 153A shown in the figure may be etched to reduce the thickness of the insulating layer 153. The insulating layer 153A remaining after the etching process may have a top surface 153TS disposed at a height lower than that of the top surface 141TS of each upper channel portion 141C. The remaining insulating layer 153A may fill the space between the lower portions of the first gate patterns 151 and may overlap the stacked body 110.

[0156] The first gate patterns 151 may be divided into a plurality of groups. In one embodiment, the first gate patterns 151 may include a first group disposed on the stack 110 in the first array region AR1 and a second group disposed on the stack 110 in the second array region AR2.

[0157] Fig.13 is along Fig.12 A plan view taken along line III-III'.

[0158] Reference Fig.13 , a first space WS1 may be defined between the first gate patterns 151 in each group. A second space WS2 may be defined between the first and second groups of the first gate patterns 151. The first space WS1 may be defined to have a width smaller than that of the second space WS2.

[0159] The first gate patterns 151 may be tubular gate patterns surrounding the corresponding sidewalls of the gate insulating layer 149. The first gate patterns 151 in each group may be arranged in two or more rows. In one embodiment, the first gate patterns 151 may include a first tubular gate pattern 151T1 arranged in a first row, a second tubular gate pattern 151T2 arranged in a second row, a third tubular gate pattern 151T3 arranged in a third row, and a fourth tubular gate pattern 151T4 arranged in a fourth row.

[0160] Fig.14 and Fig.15 1 and 2 are respectively a plan view and a cross-sectional view showing an embodiment of a method of manufacturing a separate insulation pattern.

[0161] Reference Fig.14and Fig.15 , you can Fig.12 and Fig.13 A second mask pattern 155 is formed on the insulating layer 153A as shown. The second mask pattern 155 may be a photoresist pattern.

[0162] The second mask pattern 155 may be Fig.12 and Fig.13 A portion of the insulating layer 153A is shown overlapping. For example, the second mask pattern 155 may overlap a portion of the insulating layer 153A between the first tubular gate pattern 151T1 and the second tubular gate pattern 151T2.

[0163] The width WA of the second mask pattern 155 may be defined as a value greater than the separation distance between the first tubular gate pattern 151T1 and the second tubular gate pattern 151T2. The second mask pattern 155 may overlap the first sidewall T1S1 of the first tubular gate pattern 151T1 and the first sidewall T2S1 of the second tubular gate pattern 151T2. The second sidewall T1S2 of the first tubular gate pattern 151T1 and the second sidewall T2S2 of the second tubular gate pattern 151T2 may be defined as a sidewall that does not overlap with the second mask pattern 155.

[0164] Next, the insulating layer may be etched by an etching process using the second mask pattern 155 as an etching barrier, so that a separation insulating pattern 153B may be defined. The separation insulating pattern 153B may include a vertical portion 153P1 and a horizontal portion 153P2 extending to both sides of the vertical portion 153P1. The vertical portion 153P1 may be defined as a portion between the first tubular gate pattern 151T1 and the second tubular gate pattern 151T2. The thickness of the horizontal portion 153P2 may be defined to be smaller than the thickness of the vertical portion 153P1.

[0165] The vertical portion 153P1 of the separation insulating pattern 153B may contact the first sidewall T1S1 of the first tubular gate pattern 151T1 and the first sidewall T2S1 of the second tubular gate pattern 151T2. A portion of each of the second sidewall T1S2 of the first tubular gate pattern 151T1 and the second sidewall T2S2 of the second tubular gate pattern 151T2 may be exposed to the outside of the separation insulating pattern 153B. The third tubular gate pattern 151T3 and the fourth tubular gate pattern 151T4 may also be exposed to the outside of the separation insulating pattern 153B.

[0166] The second mask pattern 155 may be removed after forming the separation insulating pattern 153B.

[0167] Fig.16 is a cross-sectional view showing an embodiment of a method of manufacturing a conductive layer.

[0168] Reference Fig.16 , a conductive layer 161L may be formed on the separation insulating pattern 153B. The conductive layer 161L may include a metal layer formed of tungsten or the like. The conductive layer 161L may be formed to fill the first space WS1 between the first gate patterns 151. The conductive layer 161L may cover the vertical portion 153P1 of the separation insulating pattern 153B and the first mask pattern 147. The conductive layer 161L may be conformally formed in the second space WS2 having a width greater than that of the first space WS1. The central area of ​​the second space WS2 may be opened without being filled with the conductive layer 161L.

[0169] Fig.17A , Fig. 17B and Fig. 17C It shows that Fig.16 An enlarged cross-sectional view of an embodiment of a subsequent process of region C is shown.

[0170] Reference Fig.17A , Fig.16 A portion of the conductive layer 161L shown may be etched by an etch-back process or the like. The conductive layer 161L may be etched so that the separation insulating pattern 153B is exposed. Second gate patterns 161G1, 161G2, and 161G3 separated from each other may be formed by a process of etching the conductive layer 161L. The second gate patterns 161G1, 161G2, and 161G3 may be patterned into a linear shape.

[0171] According to the embodiments of the present disclosure, even in Fig.16 Although no etching barrier pattern is separately formed on the conductive layer 161L as shown, the second gate patterns 161G1 , 161G2 , and 161G3 separated from each other may be formed using an etch-back process.

[0172] The vertical portion 153P1 of the separation insulating pattern 153B may be disposed between the second gate patterns 161G1, 161G2, and 161G3, or a trench 163 may be defined between the second gate patterns 161G1, 161G2, and 161G3. In one embodiment, the second gate patterns 161G1, 161G2, and 161G3 may include a first linear gate pattern 161G1, a second linear gate pattern 161G2, and a third linear gate pattern 161G3. The first linear gate pattern 161G1 and the second linear gate pattern 161G2 may be arranged on the stacked body 110 in the first array region AR1, and the third linear gate pattern 161G3 may be arranged on the stacked body 110 in the second array region AR2. The first linear gate pattern 161G1 may be spaced apart from the second linear gate pattern 161G2 by the vertical portion 153P1 of the separation insulating pattern 153B. The second linear gate pattern 161G2 may be spaced apart from the third linear gate pattern 161G3 by the trench 163 .

[0173] In one embodiment, the first gate pattern 151 may have a Fig.16 The etching selectivity of the conductive layer 161L is shown. Therefore, even if Fig.16 The conductive layer 161L shown is etched, and the first gate pattern 151 is not lost, and can be retained while protruding higher than the second gate patterns 161G1, 161G2, and 161G3 in the longitudinal direction of the upper channel portion 141C. Hereinafter, the portion of the first gate pattern 151 that protrudes higher than the second gate patterns 161G1, 161G2, and 161G3 in the longitudinal direction of the upper channel portion 141C is defined as a protrusion 151P. The protrusion 151P can protrude higher than the vertical portion 153P1 of the separation insulation pattern 153B in the longitudinal direction of the upper channel portion 141C.

[0174] Reference Fig. 17B , Fig.17A The protrusion 151P shown can be selectively removed by wet etching or the like. The gate length can be determined by Fig.17A The height 151H of the first gate pattern remaining after the protrusion 151P has been removed is defined.

[0175] The first gate pattern 151R may be protected by the second gate patterns 161G1, 161G2, and 161G3 or by the vertical portion 153P1 of the separation insulating pattern 153B. In this manner, the first gate pattern 151R may provide a gate-all-around structure surrounding each of the upper channel portions 141C.

[0176] exist Fig.17AAfter the protrusion 151P shown has been removed, the gate insulating layer 149 may remain while protruding higher than the first gate pattern 151R in the longitudinal direction of the upper channel portion 141C.

[0177] Reference Fig. 17C , an upper insulating layer 171 may be formed to cover the first gate pattern 151R, the second gate patterns 161G1, 161G2, and 161G3, and the separation insulating pattern 153B. The upper insulating layer 171 may fill the trench 163. The upper insulating layer 171 may surround the gate insulating layer 149. The upper insulating layer 171 may extend onto the first mask pattern 147. The upper insulating layer 171 may include an oxide.

[0178] Fig.18 is along Fig. 17C Plan view taken along line IV-IV'.

[0179] Reference Fig.18 , the tubular gate patterns arranged in two or more adjacent rows among the first gate patterns 151R may be coupled to each other through each of the second gate patterns 161G1 , 161G2 , and 161G3 .

[0180] In one embodiment, the first linear gate pattern 161G1 may couple the first tubular gate pattern 151T1 arranged in the first row to the third tubular gate pattern 151T3 arranged in the third row. In one embodiment, the second linear gate pattern 161G2 may couple the second tubular gate pattern 151T2 arranged in the second row to the fourth tubular gate pattern 151T4 arranged in the fourth row.

[0181] The first linear gate pattern 161G1 and the second linear gate pattern 161G2 arranged on both sides of the vertical portion 153P1 of the separation insulating pattern 153B may contact not only the separation insulating pattern 153B but also some of the first gate patterns 151R. In one embodiment, the first linear gate pattern 161G1 may contact the second sidewall T1S2 of the first tubular gate pattern 151T1. In addition, the second linear gate pattern 161G2 may contact the second sidewall T2S2 of the second tubular gate pattern 151T2.

[0182] The vertical portion 153P1 of the separation insulating pattern 153B may remain while contacting the first sidewall T1S1 of the first tubular gate pattern 151T1 and the first sidewall T2S1 of the second tubular gate pattern 151T2 .

[0183] An upper insulating layer 171 may be disposed between the second linear gate pattern 161G2 and the third linear gate pattern 161G3 .

[0184] Fig.19 is a plan view showing a first mask pattern, an upper insulating layer, a sidewall insulating layer, and a vertical source contact.

[0185] Reference Fig.19 , in the formation Fig. 17C After forming the structure shown, a sidewall insulating layer 181 and a vertical source contact 187 may be formed. Thereafter, a portion of the upper insulating layer 171 may be removed so that the first mask pattern 147 is exposed. Before forming the sidewall insulating layer 181, an alternative process for forming a conductive pattern may be performed.

[0186] Fig. 20A , Fig. 20B , Fig. 20C , Fig.20D and Fig.20E It shows the manufacturing Fig.19 A cross-sectional view of an embodiment of a method of constructing.

[0187] Reference Fig. 20A The slits 173 may be formed to pass through the upper insulating layer 171 and the stacked body 110 . The memory layer 121 and the horizontal portion 153P2 of the separation insulating pattern 153B disposed between the upper insulating layer 171 and the stacked body 110 , and the stacked body 110 may be penetrated by the slits 173 .

[0188] The slit 173 may pass through the preliminary source layer 109 and the second source protection layer 107 of the preliminary source structure 100 . A bottom surface of the slit 173 may be defined along a surface of the sacrificial source layer 105 .

[0189] Reference Fig. 20B , can be removed by slit 173 Fig. 20A The second material layer 113 is shown. In this way, an opening 175 may be defined between the first material layers 111. The memory layer 121 may be exposed through the opening 175.

[0190] Reference Fig. 20C , you can follow Fig. 20B The surface of each opening 175 is shown to form a blocking insulating layer 177. The blocking insulating layer 177 may include a metal oxide. In one embodiment, the blocking insulating layer 177 may include aluminum oxide (Al 2 O 3 After the blocking insulating layer 177 has been deposited, an annealing process may be performed on the blocking insulating layer 177. The blocking insulating layer 177 may be formed along Fig. 20B The corresponding surface of the opening 175 shown is formed conformally so that the blocking insulating layer 177 does not fill Fig. 20B The corresponding central area of ​​the opening 175 is shown.

[0191] Thereafter, a conductive pattern 179 may be formed. The conductive pattern 179 may be filled with Fig. 20B The corresponding central area of ​​the opening 175 is shown. The conductive patterns 179 may be separated from each other by the slits 173 and the first material layer 111 .

[0192] Thereafter, a sidewall insulating layer 181 may be formed on the sidewalls of the slit 173 .

[0193] Reference Fig.20D , can be removed by slit 173 Fig. 20C The sacrificial source layer 105 is shown. Next, the Fig. 20C A portion of the memory layer 121 is shown. When removing Fig. 20C The portion of the memory layer 121 shown may be removed Fig. 20C The first source protection layer 103 and the second source protection layer 107 are shown.

[0194] As described above, when the sacrificial source layer 105, the portion of the memory layer 121, the first source protection layer 103 and the second source protection layer 107 (such as Fig. 20C 121A and 121B. When the first memory layer 121A and the second memory layer 121B are removed, the horizontal space 183 may be opened. The sidewalls of the channel layer 123, the first doped semiconductor layer 101, and the preliminary source layer 109 may be exposed through the horizontal space 183. The memory layer may be divided into a first memory layer 121A and a second memory layer 121B through the horizontal space 183. The second memory layer 121B may be defined as a dummy memory layer.

[0195] Reference Fig.20E , the channel contact layer 185 can be used to fill Fig.20D Horizontal space 183 is shown. Channel contact layer 185 may include a semiconductor material containing conductive impurities. Channel contact layer 185 may include conductive impurities of at least one of n-type and p-type. In one embodiment, channel contact layer 185 may include n-type doped silicon.

[0196] The conductive impurities of the channel contact layer 185 may diffuse into Fig.20D The preliminary source layer 109 is shown. In this way, the second doped semiconductor layer 109S of the source line 100S can be defined. The source line 100S can include the first doped semiconductor layer 101, the channel contact layer 185 and the second doped semiconductor layer 109S.

[0197] Thereafter, a channel contact layer 185 may be formed and filled with Fig.20D A vertical source contact 187 of the slit 173 is shown. The vertical source contact 187 may include at least one of a doped semiconductor, a metal, a metal silicide, and a metal nitride.

[0198] The vertical source contact 187 may be isolated from the conductive pattern 179 by the sidewall insulating layer 181. The vertical source contact 187 and the upper insulating layer 171 may be planarized. The first mask pattern 147 may be exposed by planarizing the upper insulating layer 171. The upper insulating layer 171 may remain as a sidewall surrounding the first mask pattern 147.

[0199] Fig.21A , Fig. 21B , Fig. 21C , Fig.21D and Fig.21E It is shown in the formation Fig.20E sectional view of an embodiment of a subsequent process to be performed after the structure of FIG.

[0200] Reference Fig.21A , which can be selectively removed Fig.20E The first mask pattern 147 is shown. In this way, a fifth groove 189A may be defined. Each sacrificial pattern 145S may be exposed through the fifth groove 189A.

[0201] Reference Fig. 21B , which can be selectively removed Fig.21A Each sacrificial pattern 145S shown. In this way, a primarily expanded fifth groove 189B can be defined. Through the primarily expanded fifth groove 189B, the top of the protection layer 143 and the top of each gate insulating layer 149 can be exposed. When the sacrificial pattern 145S is removed, a portion of the vertical source contact 187 can be removed. In this way, a recessed area 190 can be defined in the top of the remaining vertical source contact 187. The sidewall of the recessed area 190 can be defined along the sidewall insulating layer 181.

[0202] Reference Fig. 21C , by performing an ion implantation process through the preliminarily enlarged fifth groove 189B, conductive impurities may be implanted into the top of the upper channel portion 141C. In one embodiment, n-type impurities may be implanted into the top of the upper channel portion 141C. Therefore, the upper channel portion 141C may be divided into a first region CA and a second region CB. The second region CB may be defined as a doped region including conductive impurities. The first region CA may be defined as a region formed of a substantially intrinsic semiconductor material. According to an embodiment of the present disclosure, the depth of the second region CB may be uniformly controlled by an ion implantation process.

[0203] Reference Fig.21D , can be Fig. 21C The fifth groove 189B shown in the preliminary expansion is removed Fig. 21CThe protective layer 143 is shown. Here, the top of the gate insulating layer 149 and a portion of the upper insulating layer 171 may be etched. In this way, a secondarily enlarged fifth groove 189C may be defined.

[0204] The second region CB of each upper channel portion 141C may be exposed through the second-enlarged fifth groove 189C.

[0205] When the protective layer 143 is removed, a portion of the sidewall insulating layer 181 may be etched, and thus the recessed region 190 may be expanded.

[0206] Reference Fig.21E , the conductive contact portion 191 can be used to fill Fig.21D The second expanded fifth groove 189C is shown. Here, the upper source contact 195 can be used to fill Fig.21D The recessed region 190 shown. The conductive contact 191 may contact the second region CB of each of the upper channel portions 141C. The upper source contact 195 may contact the vertical source contact 187. According to an embodiment of the present disclosure, the conductive contact 191 may be automatically aligned in the secondly enlarged fifth groove 189C opened to the upper channel portion 141C. In addition, the upper source contact 195 may be automatically aligned in the recessed region 190.

[0207] You can use the above reference Figure 7 , FIG. 8A to FIG. 8C , Fig. 9 , Fig.10 , FIG. 11A to FIG. 11D , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , FIG. 17A to FIG. 17C , Fig.18 , Fig.19 , FIG. 20A to FIG. 20E and FIG. 21A to FIG. 21E The process described above is provided by reference Figure 3A , Figure 3B and Figure 4 A semiconductor memory device is described.

[0208] In addition to the above embodiments, Fig. 20CThe first gate pattern 151R and the second gate pattern 161G1, 161G2, and 161G3 shown may include a refractory metal. The refractory metal may include titanium nitride, tantalum nitride, tungsten nitride, etc. The refractory metal has thermal stability. Therefore, although the annealing process is performed on the blocking insulating layer 177 after the first gate pattern 151R and the second gate pattern 161G1, 161G2, and 161G3 have been formed, the degradation of the electrical characteristics of the first gate pattern 151R and the second gate pattern 161G1, 161G2, and 161G3 caused by the heat generated in the annealing process can be alleviated.

[0209] Fig.22A and Fig. 22B It shows that Fig.16 An enlarged cross-sectional view of an embodiment of a subsequent process of region C is shown.

[0210] Fig.16 A portion of the conductive layer 161L shown may be etched through an etch-back process, etc. The conductive layer 161L may be etched so that the separation insulating pattern 153B is exposed. Fig.16 The conductive layer 161L shown may be separated into second gate patterns 161G1', 161G2', and 161G3' by an etching process. Respective top surfaces 161TS of the second gate patterns 161G1', 161G2', and 161G3' may be disposed at a height lower than that of the top surface 153TS of the vertical portion 153P1 of the separation insulating pattern 153B.

[0211] The first gate pattern 151 may include protrusions 151P1 and 151P2 that protrude higher than the second gate patterns 161G1', 161G2', and 161G3' and the vertical portion 153P1 of the separation insulating pattern 153B in the longitudinal direction of the upper channel portion 141C. The protrusions 151P1 and 151P2 may include a first protrusion 151P1 and a second protrusion 151P2 that is longer than the first protrusion 151P1.

[0212] As mentioned above Fig.17A As described, the second gate patterns 161G1', 161G2', and 161G3' may include a first linear gate pattern 161G1', a second linear gate pattern 161G2', and a third linear gate pattern 161G3'. Moreover, the first linear gate pattern 161G1' may be spaced apart from the second linear gate pattern 161G2' by a vertical portion 153P1 of the separation insulating pattern 153B. Moreover, a trench 163 may be defined between the second linear gate pattern 161G2' and the third linear gate pattern 161G3'. The horizontal portion 153P2 of the separation insulating pattern 153B may be exposed through the trench 163.

[0213] Reference Fig. 22B , Fig.22A The protrusions 151P1 and 151P2 shown may be selectively removed by wet etching or the like. Here, some of the first gate patterns 151' may remain as asymmetric gate patterns. In more detail, the first row and the second row of the first gate patterns 151' contacting the vertical portion 153P1 of the separation insulating pattern 153B may remain as asymmetric gate patterns. In other words, the first tubular gate patterns 151T1' arranged in the first row and the second tubular gate patterns 151T2' arranged in the second row may be asymmetric gate patterns.

[0214] The first sidewall T1S1' of the first tubular gate pattern 151T1' may remain while contacting the vertical portion 153P1 of the separation insulating pattern 153B, and the second sidewall T1S2' of the first tubular gate pattern 151T1' may remain while contacting the first linear gate pattern 161G1'. The first sidewall T2S1' of the second tubular gate pattern 151T2' may remain while contacting the vertical portion 153P1 of the separation insulating pattern 153B, and the second sidewall T2S2' of the second tubular gate pattern 151T2' may remain while contacting the second linear gate pattern 161G2'. The retained first sidewalls T1S1' and T2S1' protrude higher than the retained second sidewalls T1S2' and T2S2' in the longitudinal direction of the upper channel portion 141C, and thus the first tubular gate pattern 151T1' and the second tubular gate pattern 151T2' may be defined as asymmetric gate patterns.

[0215] You can use the reference above Fig.22A and Fig. 22B The process described above is provided for reference Figure 5A and 5B A semiconductor memory device is described.

[0216] Fig.23A , Fig. 23B , Fig.23C , Fig.23D , Fig.23E , Fig.23F , Figure 23G and Fig.23H It is shown in Fig.11D A cross-sectional view of an embodiment of a subsequent process to be performed after the process of FIG.

[0217] Reference Fig.23A The slits 273 may be formed in a state where the first mask pattern 147 and the first gate pattern 151 are covered by the insulating layer 153. The slits 273 may pass through the insulating layer 153 and the stacked body 110. The memory layer 121 between the insulating layer 153 and the stacked body 110 may be penetrated by the slits 273.

[0218] The slit 273 may pass through the preliminary source layer 109 and the second source protection layer 107 of the preliminary source structure 100 . A bottom surface of the slit 273 may be defined along a surface of the sacrificial source layer 105 .

[0219] Reference Fig. 23B , can be obtained through Fig.23A The replacement process may include replacing the insulating layer 177" and the conductive pattern 179" with the insulating layer 177". Fig.23A The steps of each of the second material layers 113 shown, and replacing the channel contact layer 185 " Fig.23A The steps of forming the first source protection layer 103 , the sacrificial source layer 105 and the second source protection layer 107 are shown.

[0220] You can use the reference above Fig. 20B and Fig. 20C The described process forms a blocking insulating layer 177 ″ and a conductive pattern 179 ″.

[0221] Before forming the channel contact layer 185 ″, a sidewall insulating layer 281 covering the sidewalls of the first material layer 111 and the conductive pattern 179 ″ may be formed.

[0222] You can use the reference above Fig.20D and Fig.20E The channel contact layer 185" may be formed by the process described above. Fig.23A The first doped semiconductor layer 101 is in contact with the preliminary source layer 109. The conductive dopant can be diffused from the channel contact layer 185 to the Fig.23A In this way, a second doped semiconductor layer 109S" can be defined.

[0223] The channel contact layer 185" may be disposed between the first doped semiconductor layer 101 and the second doped semiconductor layer 109S", and may contact the sidewall of the channel layer 123. Fig.23A The illustrated memory layer 121 is separated into a first memory layer 121A" and a second memory layer 121B".

[0224] After the channel contact layer 185" has been formed, a filling Fig.23A A vertical source contact 287 is shown at the slit 273. The vertical source contact 287 may extend to a height at which a top surface of the insulating layer 153 is disposed. The vertical source contact 287 may include doped silicon.

[0225] Reference Fig.23C , can be etched Fig. 23BA portion of the insulating layer 153 is shown, thereby reducing the thickness of the insulating layer 153. The insulating layer 153A" remaining after the etching process may have a top surface 153TS" disposed at a height lower than that of the top surface 141TS of each upper channel portion 141C.

[0226] When etching the portion of the insulating layer, a portion of the sidewall insulating layer 281 may be etched. Therefore, a first protrusion 287P1 of the vertical source contact 287 may be defined, which protrudes upward higher than the sidewall insulating layer 281 and the insulating layer 153A″.

[0227] Reference Fig.23D , can be selectively removed by etch-back process Fig.23C The first protrusion 287P1 is shown. When removing Fig.23C As shown in the first protrusion 287P1 , the sacrificial pattern 145S may be protected by the first mask pattern 147 .

[0228] Reference Fig.23E , as mentioned above Fig.14 and Fig.15 The second mask pattern 155" may be formed on Fig.23D Thereafter, the second mask pattern 155" may be etched by an etching process using the second mask pattern 155" as an etching barrier. Fig.23D In this way, a separate insulating pattern 153B" can be defined. As described above with reference to Fig.14 and Fig.15 As described above, the separation insulating pattern 153B" may include a vertical portion 153P1" and a horizontal portion 153P2".

[0229] During the process of etching the insulating layer, a portion of the sidewall insulating layer 281 may be etched. Therefore, a second protrusion 287P2 of the vertical source contact 287 may be defined, which protrudes upward higher than the sidewall insulating layer 281 and the horizontal portion 153P2" of the separation insulating layer 153B".

[0230] Reference Fig.23F , can be selectively removed by etch-back process Fig.23E The second protrusion 287P2 is shown. When removing Fig.23E When the second protrusion 287P2 is shown, the sacrificial pattern 145S may be protected by the first mask pattern 147 .

[0231] Reference Figure 23G , Fig.23F The illustrated second mask pattern 155 ″ may be removed so that the vertical portion 153P1 ″ of the separation insulating pattern 153B″ is exposed.

[0232] Afterwards, you can use the above reference Fig.16 and Fig.17A The described process forms the second gate patterns 161G1", 161G2", and 161G3". The second gate patterns 161G1", 161G2", and 161G3" may be disposed on the horizontal portions 153P2" of the separation insulating patterns 153B".

[0233] Reference Fig.23H , can be etched Figure 23G The upper portion of the first gate pattern 151 is shown. The gate length may be defined by a height 151H" of the first gate pattern 151" remaining after etching.

[0234] Next, an upper insulating layer 271 may be formed. The upper insulating layer 271 may cover Figure 23G The sidewall insulating layer 281 , the vertical source contact 287 , the gate insulating layer 149 , the first gate pattern 151 ″, the separation insulating pattern 153B″, the second gate patterns 161G1 ″, 161G2 ″ and 161G3 ″, and the first mask pattern 147 .

[0235] Thereafter, the surface of the upper insulating layer 271 may be planarized so that Figure 23G The first mask pattern 147 is exposed. Thereafter, the above reference FIG. 21A to FIG. 21C The process described above forms the concentrations of conductive impurities in the first region CA" and the second region CB" included in the upper channel portion 141C to be different from each other. In one embodiment, the second region CB" can be defined as a doped region including conductive impurities. The first region CA" can be defined as a region formed of a substantially intrinsic semiconductor material.

[0236] Afterwards, you can use the above reference Fig.21D and Fig.21E The described process forms a conductive contact 191" in contact with the second region CB" of the upper channel portion 141C.

[0237] You can use the above reference Fig.23A , Fig. 23B , Fig.23C , Fig.23D , Fig.23E , Fig.23F , Figure 23G and Fig.23H The process described above is provided by reference Figure 6 A semiconductor memory device is described.

[0238] According to an embodiment of the present disclosure, a separation insulating pattern may be stably disposed between a first gate pattern in a first row and a first gate pattern in a second row. According to an embodiment of the present disclosure, first gate patterns spaced apart from each other may be coupled to each other through a second gate pattern, and thus a drain selection line may be defined. According to an embodiment of the present disclosure, a process variation of a length of an upper channel portion of a channel structure surrounded by a first gate pattern and a process variation of a range of a dopant region in the channel structure may be reduced.

[0239] Fig.24 is a block diagram showing a configuration of a memory system according to an embodiment of the present disclosure.

[0240] Reference Fig.24 , the memory system 1100 includes a memory device 1120 and a memory controller 1110 .

[0241] The memory device 1120 may be a multi-chip package consisting of a plurality of flash memory chips. The memory device 1120 may include a lower channel portion surrounded by a memory layer, an upper channel portion on the lower channel portion, a gate insulating layer surrounding the upper channel portion, a first gate pattern surrounding the gate insulating layer, a separation insulating pattern disposed on one side of the first gate pattern, and a second gate pattern disposed on the other side of the first gate pattern. The first gate pattern may include a first sidewall contacting the separation insulating pattern and a second sidewall contacting the second gate pattern.

[0242] The memory controller 1110 may control the memory device 1120, and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 may be used as a working memory of the CPU 1112, the CPU 1112 may perform an overall control operation for data exchange of the memory controller 1110, and the host interface 1113 may be equipped with a data exchange protocol of a host connected to the memory system 1100. The error correction block 1114 may detect an error included in data read from the memory device 1120, and may correct the detected error. The memory interface 1115 may interface with the memory device 1120. The memory controller 1110 may also include a read-only memory (ROM), etc., which stores code data for interfacing with the host.

[0243] The above-mentioned memory system 1100 may be a memory card or a solid state drive (SSD) in which the memory device 1120 and the memory controller 1110 are combined with each other. For example, when the memory system 1100 is an SSD, the memory controller 1110 may communicate with an external device (e.g., a host) via one of various interface protocols such as Universal Serial Bus (USB), Multimedia Card (MMC), Peripheral Component Interconnect Express (PCI-E), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), or Integrated Drive Electronics (IDE).

[0244] Fig.25 is a block diagram illustrating a configuration of a computing system according to an embodiment of the present disclosure.

[0245] Reference Fig.25 , the computing system 1200 may include a CPU 1220 electrically coupled to a system bus 1260, a random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210. When the computing system 1200 is a mobile device, it may further include a battery for providing an operating voltage to the computing system 1200, and may further include an application chipset, an image processor, a mobile DRAM, and the like.

[0246] The memory system 1210 may include a memory device 1212 and a memory controller 1211 .

[0247] The memory device 1212 may include a lower channel portion surrounded by a memory layer, an upper channel portion on the lower channel portion, a gate insulating layer surrounding the upper channel portion, a first gate pattern surrounding the gate insulating layer, a separation insulating pattern disposed on one side of the first gate pattern, and a second gate pattern disposed on the other side of the first gate pattern. The first gate pattern may include a first sidewall contacting the separation insulating pattern and a second sidewall contacting the second gate pattern.

[0248] The memory controller 1211 can be used with reference Fig.24 The memory controller 1110 is implemented in the same manner as described above.

[0249] The present disclosure may improve the operational reliability of a semiconductor memory device by reducing process variations.

[0250] CROSS-REFERENCE TO RELATED APPLICATIONS

[0251] This application claims the priority of Korean Patent Application No. 10-2021-0028909 filed in the Korean Intellectual Property Office on March 4, 2021, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A method for manufacturing a semiconductor memory device, the method comprising the steps of: forming a stack; forming a channel hole through the stack; forming a memory layer on the sidewalls of the channel hole; forming a lower channel portion in the channel hole; forming an upper channel portion on the lower channel portion; forming a gate insulating layer surrounding the sidewalls of the upper channel portion; forming a first gate pattern surrounding a sidewall of the gate insulating layer; forming a separation insulating pattern in contact with a first sidewall of the first gate pattern; as well as A second gate pattern is formed in contact with a second sidewall of the first gate pattern.

2. The method according to claim 1, wherein: The first gate pattern includes a protrusion protruding higher than each of the separation insulating pattern and the second gate pattern in a longitudinal direction of the upper channel portion.

3. The method according to claim 2, further comprising the steps of: After forming the second gate pattern, the protrusion of the first gate pattern is selectively removed.

4. The method according to claim 3, wherein: A top surface of the second gate pattern is disposed at a height lower than a height of a top surface of the separation insulating pattern.

5. The method according to claim 4, wherein: The step of selectively removing the protrusion is performed such that the first sidewall of the first gate pattern remains while protruding higher than the second sidewall of the first gate pattern in the longitudinal direction of the upper channel portion.

6. The method according to claim 1, wherein: The step of forming the lower channel portion comprises the following steps: forming a channel layer on the memory layer; filling a central region of the channel hole defined by the channel layer with a core insulating layer; defining a recessed area by etching a portion of the core insulating layer; and The recessed area is filled with a semiconductor pattern.

7. The method according to claim 1, wherein: The step of forming the upper channel portion comprises the following steps: forming a semiconductor layer overlapping the stack and the lower channel portion; forming a protective layer on the semiconductor layer; forming a sacrificial layer on the protective layer; forming a first mask pattern on the sacrificial layer to overlap the lower channel portion; and etching the semiconductor layer, the protective layer, and the sacrificial layer by an etching process using the first mask pattern as an etching barrier, The semiconductor layer is patterned into the upper channel portion through the etching process.

8. The method according to claim 7, wherein: The step of forming the separated insulating pattern comprises the following steps: forming an insulating layer on the stack; reducing a thickness of the insulating layer so that a top surface of the insulating layer is disposed at a height lower than a height of a top surface of the upper channel portion; forming a second mask pattern overlapping the first sidewall of the first gate pattern and a portion of the insulating layer; etching the insulating layer by an etching process using the second mask pattern as an etching barrier to expose the second sidewall of the first gate pattern; and The second mask pattern is removed.

9. The method according to claim 8, further comprising the steps of: forming an upper insulating layer covering the separation insulating pattern and the second gate pattern; forming a slit passing through the upper insulating layer and the stack; as well as performing a replacement process through the slit, The stacked body includes first material layers and second material layers that are alternately stacked, and During the replacement process, the second material layer is replaced by a conductive pattern.

10. The method according to claim 8, further comprising the steps of: Before reducing the thickness of the insulating layer, forming a slit passing through the insulating layer and the stacked body; and performing a replacement process through the slit, The stacked body includes first material layers and second material layers that are alternately stacked, and During the replacement process, the second material layer is replaced by a conductive pattern.

11. The method according to claim 7, wherein: The sacrificial layer is patterned into a sacrificial pattern through the etching process.

12. The method according to claim 11, wherein: The gate insulating layer extends onto sidewalls of the sacrificial pattern.

13. The method according to claim 11, further comprising the steps of: forming an upper insulating layer covering the separation insulating pattern and the second gate pattern, The upper insulating layer surrounds the sidewall of the first mask pattern.

14. The method according to claim 13, further comprising the steps of: removing the first mask pattern and the sacrificial pattern so that a groove is defined in the upper insulating layer; forming a doped region by implanting conductive impurities into a portion of the upper channel portion adjacent to the protective layer; removing a portion of the protection layer and the gate insulating layer to enlarge the groove and expose the doped region; as well as The enlarged recess is filled with an electrically conductive contact.

15. The method according to claim 1, wherein: The first gate pattern includes a conductive barrier layer, and The second gate pattern includes a metal layer.

16. The method according to claim 1, wherein: Each of the first gate pattern and the second gate pattern includes a refractory metal.

17. A method for manufacturing a semiconductor memory device, the method comprising the steps of: forming a stack partially penetrated by the lower channel; forming an upper channel portion overlapping the lower channel portion; forming a gate insulating layer surrounding the sidewalls of the upper channel portion; forming a first gate pattern, the first gate pattern surrounding a sidewall of the gate insulating layer and arranged in a plurality of rows; forming a separation insulating pattern between a first row of the first gate patterns and a second row of the first gate patterns; forming a conductive layer filling spaces between the first gate patterns; as well as Second gate patterns separated from each other are formed by etching the conductive layer so that the separation insulating patterns are exposed.

18. The method according to claim 17, wherein: The second gate pattern includes: a first linear gate pattern configured to couple the first row of the first gate patterns to a third row of the first gate patterns; and A second linear gate pattern is configured to couple the second row of the first gate patterns to a fourth row of the first gate patterns.

19. The method according to claim 17, wherein: Each of the first row and the second row of the first gate patterns includes an asymmetric gate pattern.

20. The method according to claim 19, wherein: The asymmetric gate pattern includes a first sidewall contacting the separation insulating pattern and a second sidewall contacting any one of the second gate patterns, and The first side wall protrudes higher than the second side wall in a longitudinal direction of the upper channel portion.

21. A semiconductor memory device, comprising: A stacked body comprising alternately stacked conductive patterns and interlayer insulating layers; a lower channel portion passing through the stack; a memory layer disposed between the stack and the lower channel portion; an upper channel portion disposed on the lower channel portion; a gate insulating layer surrounding the sidewalls of the upper channel portion; a first gate pattern surrounding a sidewall of the gate insulating layer; a separation insulating pattern contacting a first portion of the first gate pattern; as well as A second gate pattern contacts the second portion of the first gate pattern.

22. The semiconductor memory device according to claim 21, wherein: The lower channel portion comprises: a channel layer extending along an inner wall of the memory layer; a core insulating layer surrounded by the channel layer; and A semiconductor pattern is disposed between the core insulating layer and the upper channel portion.

23. The semiconductor memory device according to claim 21, wherein The gate insulating layer extends to a space between the first gate pattern and the lower channel portion.

24. The semiconductor memory device according to claim 21, wherein The first portion of the first gate pattern protrudes higher than the second portion of the first gate pattern in a longitudinal direction of the upper channel portion.

25. The semiconductor memory device according to claim 21, further comprising: A conductive contact is disposed on the upper channel portion.

26. The semiconductor memory device according to claim 25, wherein: The conductive contact has a width greater than a width of the upper channel portion.

27. The semiconductor memory device according to claim 26, wherein: Each of the gate insulating layer and the upper channel portion protrudes higher than each of the first gate pattern and the second gate pattern in a direction toward the conductive contact.

28. The semiconductor memory device according to claim 27, wherein: The upper channel portion protrudes higher than the gate insulating layer in a direction toward the conductive contact.

29. The semiconductor memory device according to claim 28, wherein: The conductive contact includes a groove into which the upper channel portion is inserted.

30. The semiconductor memory device according to claim 21, wherein The first gate pattern includes a conductive barrier layer, and The second gate pattern includes a metal layer.

31. The semiconductor memory device according to claim 21, wherein: Each of the first gate pattern and the second gate pattern includes a refractory metal.

32. A semiconductor memory device, comprising: a separation insulating pattern, the separation insulating pattern comprising a first surface and a second surface facing in opposite directions; forming a first groove in the first surface of the separation insulation pattern; forming a second groove in the second surface of the separation insulating pattern; a first linear gate pattern contacting the first surface of the separation insulating pattern and including a third groove facing the first groove; a second linear gate pattern contacting the second surface of the separation insulating pattern and including a fourth groove facing the second groove; a first tubular gate pattern extending along a surface of the first groove and a surface of the third groove; a second tubular grid pattern extending along a surface of the second groove and a surface of the fourth groove; a channel portion inserted into a central region of the first tubular gate pattern and the second tubular gate pattern; as well as A gate insulating layer is disposed between each of the first tubular gate pattern and the second tubular gate pattern and a corresponding channel portion.

33. The semiconductor memory device according to claim 32, wherein: Each of the first tubular grid pattern and the second tubular grid pattern comprises: a first portion contacting the separation insulating pattern and a second portion extending from the first portion in a direction away from the separation insulating pattern, wherein the first portion protrudes higher than the second portion in a longitudinal direction of the channel portion.

34. The semiconductor memory device according to claim 32, wherein: Each of the first tubular gate pattern and the second tubular gate pattern includes a conductive barrier layer, and Each of the first linear gate pattern and the second linear gate pattern includes a metal layer.

35. The semiconductor memory device according to claim 32, wherein: Each of the first tubular gate pattern, the second tubular gate pattern, the first linear gate pattern, and the second linear gate pattern includes a refractory metal.

36. The semiconductor memory device according to claim 32, wherein: The first tubular gate pattern and the first linear gate pattern contact each other to form a first selection line, and The second tubular gate pattern and the second linear gate pattern contact each other to form a second selection line.

37. The semiconductor memory device according to claim 32, further comprising: a lower channel portion, the lower channel portion being disposed below the channel portion; a stacked body including an interlayer insulating layer and a word line, the interlayer insulating layer and the word line surrounding the lower channel portion and alternately arranged along a longitudinal direction of each of the lower channel portions; as well as A memory layer is disposed between each of the lower channel portions and the stack.

38. The semiconductor memory device according to claim 37, wherein: Each of the word lines includes a conductive pattern having a planar shape overlapping the first linear gate pattern, the separation insulating pattern, and the second linear gate pattern.

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