Semiconductor structure and wafer cutting method

Abstract

The present disclosure relates to a semiconductor structure and a wafer cutting method. The wafer cutting method comprises the following steps: providing a wafer prepared with a semiconductor initial structure; the semiconductor initial structure has a chip area and a cutting lane surrounding the chip area; the cutting lane has a test structure and an interconnection structure. A pre-cut opening is formed in the cutting lane, and a part of the test structure and a part of the interconnection structure located directly below the pre-cut opening are etched and removed along the pre-cut opening to form a pre-cut groove, the pre-cut groove extends along the extension direction of the cutting lane. The wafer is cut along the pre-cut groove. The wafer cutting method can avoid the problem of splitting of the interlayer dielectric layer in the interconnection structure caused by cutting stress, thereby improving the yield of dynamic random access memory.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a semiconductor structure and wafer dicing method. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory in computers and other electronic devices. It consists of multiple memory cells. Each memory cell includes a storage capacitor and a transistor electrically connected to the storage capacitor.

[0003] In DRAM fabrication, transistors can be pre-fabricated on a wafer, and then back-end of line (BEOL) processes are performed to connect multiple transistors on the wafer according to design requirements through a multilayer interconnect structure, thereby achieving specific functions. The interconnect structure includes interlayer dielectric layers of metal line structures and isolation metal line structures.

[0004] However, during the dicing process, the dicing stress may cause the interlayer dielectric layer to split. Furthermore, this dicing stress can also be transmitted to other layers connected to the interlayer dielectric layer, causing those layers to split and affecting the DRAM fabrication yield. Summary of the Invention

[0005] Therefore, it is necessary to provide a semiconductor structure and wafer cutting method to address the problem that cutting stress in the existing technology can easily cause the interlayer dielectric layer to split and affect the DRAM fabrication yield.

[0006] A wafer dicing method includes the following steps: A wafer having a semiconductor initial structure is provided; the semiconductor initial structure has a chip region and a dicing channel surrounding the chip region; the dicing channel has a test structure and an interconnect structure. A pre-dicing opening is formed in the dicing channel; a portion of the test structure and a portion of the interconnect structure located directly below the pre-dicing opening are etched away along the pre-dicing opening to form a pre-dicing trench, the pre-dicing trench extending along the dicing channel extension direction. The wafer is diced along the pre-dicing trench.

[0007] In some embodiments, the interconnect structure includes a metal wire structure and an interlayer dielectric layer for isolating the metal wire structure; etching away a portion of the test structure and a portion of the interconnect structure located directly below the pre-cut opening includes: etching away the metal wire structure and the interlayer dielectric layer respectively.

[0008] In some embodiments, wet etching is used to remove the metal line structure, and dry etching is used to remove the interlayer dielectric layer.

[0009] In some embodiments, wet etching is used to remove the metal wire structure, including cleaning the metal wire structure with a diluted sulfuric acid-hydrogen peroxide mixture to remove the metal wire structure.

[0010] In some embodiments, the cleaning time of the metal wire structure using a diluted sulfuric acid-hydrogen peroxide mixture is 20s to 180s.

[0011] In some embodiments, the material of the interlayer dielectric layer includes silicon oxide, silicon nitride, silicon carbide, hydrogenated silicon oxide, or silicon carbon nitride.

[0012] In some embodiments, the use of dry etching to remove the interlayer dielectric layer includes: etching the interlayer dielectric layer using an etching gas; wherein the etching gas includes: carbon tetrafluoride, octafluoropropane, or trifluoromethane.

[0013] In some embodiments, the test structure includes test pads and a top dielectric layer that isolates the test pads; etching away a portion of the test structure and a portion of the interconnect structure located directly below the pre-cut opening includes: using dry etching to remove the test pads and the top dielectric layer.

[0014] In some embodiments, the cutting channel has a centerline extending along its length; the distance from the boundary line of the pre-cut groove along its length to the centerline of the cutting channel ranges from 10 μm to 30 μm.

[0015] In some embodiments, forming a pre-cut opening in the dicing tract includes the following steps: forming a hard mask material layer covering the initial structure of the semiconductor; patterning the hard mask material layer to form a hard mask and a pre-cut opening located in the hard mask; the hard mask at least covers the chip region; the pre-cut opening extends along the dicing tract extension direction.

[0016] In some embodiments, the chip region has a packaging protection layer. A step is provided between the packaging protection layer and the test structure; the step includes an upper step surface and a lower step surface at different heights. A hard mask covers the step, and a pre-cut opening is formed in the portion of the hard mask covering the lower step surface.

[0017] In some embodiments, the chip region also has a bonding structure. The bonding structure is exposed on the lower step surface, and a hard mask further covers the bonding structure. After forming the pre-cut trench and before dicing the wafer along the pre-cut trench, the fabrication method further includes: removing residual hard mask to expose the encapsulation protective layer and the bonding structure.

[0018] In some embodiments, the hard mask includes: a first hard mask covering the step, and a second hard mask located on the first hard mask away from the surface of the step; wherein the first hard mask includes a spin-coated hard mask.

[0019] In some embodiments, forming a hard mask material layer covering the initial semiconductor structure includes: sequentially stacking a first hard mask material layer and a second hard mask material layer on the initial semiconductor structure;

[0020] Patterning a hard mask material layer to form a hard mask and a pre-cut opening within the hard mask includes the following steps: A patterned photoresist layer is formed on the side of the second hard mask material layer opposite to the first hard mask material layer. The photoresist layer has a first opening that exposes a portion of the second hard mask material layer. Based on the first opening, the second hard mask material layer is patterned to form the second hard mask and a second opening within the second hard mask, the second opening exposing a portion of the first hard mask material layer. Based on the second opening, the first hard mask material layer is patterned to form the first hard mask and a third opening within the first hard mask. The second and third openings together constitute the pre-cut opening; the pre-cut opening exposes a portion of the test structure.

[0021] Based on the same inventive concept, this disclosure also provides a semiconductor structure formed using the wafer dicing methods described in some of the foregoing embodiments. The semiconductor structure can also achieve the technical effects achievable by the wafer dicing methods described in the foregoing embodiments, and will not be detailed here.

[0022] The wafer dicing method in this embodiment can form a pre-dicing opening within the dicing channel of the initial semiconductor structure before the actual wafer dicing. A portion of the test structure and a portion of the interconnect structure located within the dicing channel are then removed along the pre-dicing opening to form a pre-dicing trench. In other words, the wafer dicing method described above can perform pre-dicing by removing a portion of the test structure and a portion of the interconnect structure within the dicing channel to form a pre-dicing trench. This eliminates the interlayer dielectric layer, which is prone to splitting, within the pre-dicing trench. Therefore, when dicing the wafer along the pre-dicing trench, the problem of splitting of the interlayer dielectric layer in the interconnect structure due to dicing stress can be avoided, thereby improving the DRAM fabrication yield.

[0023] Furthermore, the pre-cut trenches are formed by removing part of the test structure and part of the interconnect structure, meaning that the wafer in this disclosure can effectively utilize the dicing channels to improve the wafer's space utilization, thereby helping to reduce R&D and manufacturing costs. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic cross-sectional view of an initial semiconductor structure provided in one embodiment;

[0026] Figure 2 This is a schematic flowchart of a wafer dicing method provided in one embodiment;

[0027] Figure 3 This is a schematic cross-sectional view of the structure obtained in step S10 of a wafer dicing method provided in one embodiment;

[0028] Figure 4 This is a flowchart illustrating each step in step S20 of a wafer dicing method provided in one embodiment;

[0029] Figure 5 This is a cross-sectional schematic diagram of the structure obtained in step S21 of a wafer dicing method provided in one embodiment;

[0030] Figure 6 This is a flowchart illustrating each step in step S22 of a wafer dicing method provided in one embodiment;

[0031] Figure 7 This is a schematic cross-sectional view of the structure obtained in step S221 of a wafer dicing method provided in one embodiment;

[0032] Figure 8 This is a schematic cross-sectional view of the structure obtained in step S222 of a wafer dicing method provided in one embodiment;

[0033] Figure 9 This is a schematic cross-sectional view of the structure obtained in step S223 of a wafer dicing method provided in one embodiment;

[0034] Figure 10 This is a schematic cross-sectional view of the structure obtained after removing part of the test structure in a wafer dicing method provided in one embodiment;

[0035] Figure 11 This is a schematic cross-sectional view of the structure obtained after removing part of the third interconnect structure in a wafer dicing method provided in one embodiment;

[0036] Figure 12 This is a schematic cross-sectional view of the structure obtained after removing part of the second interconnect structure in a wafer dicing method provided in one embodiment;

[0037] Figure 13 This is a schematic cross-sectional view of the structure obtained after removing part of the first interconnect structure in a wafer dicing method provided in one embodiment;

[0038] Figure 14This is a schematic cross-sectional view of the structure obtained after removing the hard mask in a wafer dicing method provided in one embodiment;

[0039] Figure 15 This is a cross-sectional schematic diagram of the structure obtained after removing part of the test structure in another wafer dicing method provided in one embodiment;

[0040] Figure 16 This is a schematic cross-sectional view of the structure obtained after removing part of the third interconnect structure in another wafer dicing method provided in one embodiment;

[0041] Figure 17 This is a schematic cross-sectional view of the structure obtained after removing part of the second interconnect structure in another wafer dicing method provided in one embodiment;

[0042] Figure 18 This is a schematic cross-sectional view of the structure obtained after removing part of the first interconnect structure in another wafer dicing method provided in one embodiment;

[0043] Figure 19 This is a cross-sectional schematic diagram of the structure obtained in step S30 of a wafer dicing method provided in one embodiment;

[0044] Figure 20 This is a top view schematic diagram illustrating the positional relationship between a pre-cut trench, a cutting track, and a chip area in one embodiment;

[0045] Figure 21 This is a schematic cross-sectional view of a semiconductor structure provided in one embodiment.

[0046] Explanation of reference numerals in the attached figures:

[0047] 1-Wafer; 11-Unit transistor region; 12-Capacitor region; 13-Peripheral transistor region; 14-Contact structure;

[0048] 15 - Bottom dielectric layer; 201 - First interconnect structure; 202 - Second interconnect structure; 203 - Third interconnect structure;

[0049] 21-Metal wire structure; 22-Interlayer dielectric layer; 221-First interlayer dielectric layer;

[0050] 222 - Second interlayer dielectric layer; 3 - Test structure; 31 - Test pad; 311 - Conductive via;

[0051] 312 - Conductive layer; 32 - Top dielectric layer; 321 - First top dielectric layer; 322 - Second top dielectric layer;

[0052] 4-Top pad; 41-Bonding structure; 500-Hard mask material layer; 510-First hard mask material layer;

[0053] 520 - Second hard mask material layer; 50 - Hard mask; 51 - First hard mask; 52 - Second hard mask;

[0054] 6-Encapsulation protection layer; 61-First encapsulation protection layer; 62-Second encapsulation protection layer; 7-Photoresist layer;

[0055] B - Barrier layer; K - Pre-cut opening; K1 - First opening; K2 - Second opening; K3 - Third opening;

[0056] H - Pre-cut trench; Die - Chip area; Cell - Cell array area; Peri - Peripheral circuit area;

[0057] SL - Cutting track; Test - Test area; S1 - Upper step surface; S2 - Lower step surface. Detailed Implementation

[0058] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0060] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0061] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0062] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0063] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for the anticipation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. Consequently, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of the present disclosure.

[0064] In DRAM fabrication, transistors can be fabricated on the wafer in advance, and then subsequent processes are performed to connect multiple transistors on the wafer according to design requirements through a multilayer interconnect structure, thereby achieving specific functions.

[0065] like Figure 1 As shown, a semiconductor initial structure is fabricated on wafer 1. The semiconductor initial structure has a die region (Die) and a test region (Test) surrounding the die region. The die region includes a cell array region (Cell) and a peripheral circuit region (Peri) located around the cell array region. The test region (Test) is located next to the peripheral circuit region (Peri). The cell array region includes a cell transistor region (11) and a capacitor region (12). The cell transistor region (11) contains an array of cell transistors, and the capacitor region (12) contains multiple capacitors connected to the cell transistors. The peripheral circuit region (Peri) includes a peripheral transistor region (13), which may contain peripheral transistors. Furthermore, the die region and the test region (Test) also include a contact structure (14) and a bottom dielectric layer (15) for isolating the contact structure (14). The contact structure (14) within the die region is used to lead out the cell transistors or peripheral transistors. A barrier layer (B) is also provided between the contact structure (14) and the bottom dielectric layer (15) to prevent atoms in the contact structure (14) from diffusing into the bottom dielectric layer (15).

[0066] For example, such as Figure 1 As shown, both the Die and Test areas include multi-layer interconnect structures (first interconnect structure 201, second interconnect structure 202, and third interconnect structure 203). Each interconnect structure includes a metal line structure 21 and an interlayer dielectric layer 22 that isolates the metal line structure 21. The metal line structure 21 in the first interconnect structure 201 is connected to the contact structure 14.

[0067] The Test area also includes Test Structure 3, and the Die area includes Top Pad 4. The interconnect structures within the Test area can be connected to Test Structure 3, and the interconnect structures within the Die area can be connected to Top Pad 4.

[0068] It should be noted that in this embodiment, the contact structure 14, interconnect structure, and test structure 3 within the test area Test can all be formed simultaneously with their corresponding structures within the die area. For example, the contact structure 14 within the test area Test and the contact structure 14 within the die area can be formed simultaneously using the same materials and processes. Similarly, the interconnect structure within the test area Test and the interconnect structure within the die area can be formed simultaneously using the same materials and processes. The test structure 3 and the top pad 4 can also be formed simultaneously using the same materials and processes. This allows for electrical testing of the corresponding structures within the die area by performing electrical tests on the test structure 3, contact structure 14, and interconnect structure within the test area Test.

[0069] It is understood that dicing channels are also provided in the initial semiconductor structure. After testing, the wafer with the prepared initial semiconductor structure can be diced. For example, the test area can be set within the dicing channel.

[0070] In DRAM, low-k dielectric materials are typically used as interlayer dielectric layers to reduce parasitic capacitance in the structures formed during subsequent processes. However, low-k materials have low density, low elastic modulus, and low hardness. During the dicing process, the cutting stress may cause the interlayer dielectric layer to split. Furthermore, this cutting stress can also be transmitted to other layers connected to the interlayer dielectric layer, causing them to split and affecting the DRAM fabrication yield.

[0071] Based on this, please refer to Figure 2 This disclosure provides a wafer dicing method, including steps S10 to S30.

[0072] S10 provides a wafer with a semiconductor initial structure; the semiconductor initial structure has a chip region and dicing channels surrounding the chip region; the dicing channels have test structures and interconnect structures.

[0073] It should be noted that the initial semiconductor structure in this embodiment is the same as the initial semiconductor structure in the foregoing embodiments. For example, in the foregoing embodiments, the test area of ​​the initial semiconductor structure is located within the dicing channel, or a portion of the test area is located within the dicing channel.

[0074] S20, a pre-cutting opening is formed in the cutting channel, and a portion of the test structure and a portion of the interconnect structure located directly below the pre-cutting opening are etched away along the pre-cutting opening to form a pre-cutting groove, which extends along the cutting channel extension direction.

[0075] S30, dicing wafers along pre-cut grooves.

[0076] The wafer dicing method in this embodiment can form a pre-dicing opening within the dicing channel of the initial semiconductor structure before the actual wafer dicing. A portion of the test structure and a portion of the interconnect structure located within the dicing channel are then removed along the pre-dicing opening to form a pre-dicing trench. In other words, the above-mentioned wafer dicing method can perform pre-dicing by removing a portion of the test structure and a portion of the interconnect structure within the dicing channel to form a pre-dicing trench. This removes the interlayer dielectric layer, which is prone to splitting, within the pre-dicing trench. Therefore, when dicing the wafer along the pre-dicing trench, the problem of splitting of the interlayer dielectric layer in the interconnect structure due to dicing stress can be avoided, thereby improving the DRAM fabrication yield.

[0077] Furthermore, the pre-cut trenches are formed by removing part of the test structure and part of the interconnect structure, meaning that the wafer in this disclosure can effectively utilize the dicing channels to improve the wafer's space utilization, thereby helping to reduce R&D and manufacturing costs.

[0078] The following combination Figures 3 to 19 The above wafer dicing method is described in detail.

[0079] In step S10, please refer to Figure 3 The wafer 1 is provided with a semiconductor initial structure; the semiconductor initial structure has a chip region Die and a dicing track SL around the chip region Die; the dicing track SL has a test structure 3 and an interconnect structure.

[0080] For example, test structure 3 includes test pads 31 and a top dielectric layer 32 that isolates the test pads 31. Optionally, test pads 31 include conductive vias 311 and conductive layers 312. Conductive vias 311 include, but are not limited to, tungsten vias, and conductive layers 312 include, but are not limited to, aluminum (Al) layers. Optionally, the top dielectric layer 32 can be a single-layer structure or a multilayer structure. For example, the top dielectric layer 32 includes a first top dielectric layer 321 and a second top dielectric layer 322. The first top dielectric layer 321 includes, but is not limited to, a silicon nitride (SiN) layer, and the second top dielectric layer 322 includes a silicon oxide (SiO2) layer.

[0081] For example, the interconnect structure includes a metal line structure 21 and an interlayer dielectric layer 22 that isolates the metal line structure 21. In this embodiment of the disclosure, a multilayer interconnect structure is disposed within the initial semiconductor structure, such as a first interconnect structure 201, a second interconnect structure 202, and a third interconnect structure 203. Each interconnect structure includes a metal line structure 21 and an interlayer dielectric layer 22.

[0082] Optionally, the material of the metal wire structure 21 includes, but is not limited to, copper (Cu). Optionally, the material of the interlayer dielectric layer 22 includes silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon carbide oxycarbonate (SiCOH), or silicon carbon nitride (SiCN).

[0083] It is understood that the interlayer dielectric layer 22 can be a single-layer structure or a multilayer structure. For example, in the first interconnect structure 201, the interlayer dielectric layer 22 is a single-layer structure, while in the second interconnect structure 202 and the third interconnect structure 203, the interlayer dielectric layer 22 is a multilayer structure, which includes a first interlayer dielectric layer 221 and a second interlayer dielectric layer 222. Optionally, when the interlayer dielectric layer 22 is a single-layer structure, it can be a low-k dielectric layer. When the interlayer dielectric layer 22 is a multilayer structure, at least one of the first interlayer dielectric layer 221 and the second interlayer dielectric layer 222 is a low-k dielectric layer.

[0084] In step S20, please refer to Figures 4 to 18 A pre-cut opening K is formed in the cutting channel SL. A portion of the test structure 2 and a portion of the interconnect structure located directly below the pre-cut opening K are etched away to form a pre-cut groove H. The pre-cut groove H extends along the cutting channel extension direction.

[0085] In some embodiments, please refer to Figure 4 The process involves forming a pre-cut opening in the cutting channel, including steps S21 and S22.

[0086] S21, forming a hard mask material layer covering the initial structure of the semiconductor.

[0087] S22, patterning the hard mask material layer to form a hard mask and a pre-cut opening in the hard mask; the hard mask at least covers the chip area; the pre-cut opening extends along the cutting path extension direction.

[0088] In step S21, please refer to Figure 5 A hard mask material layer 500 is formed covering the initial structure of the semiconductor.

[0089] It should be understood that the hard mask material layer 500 in the embodiments of this disclosure can be a single-layer structure or a stacked structure. Correspondingly, the hard mask can also be a single-layer structure or a stacked structure.

[0090] For example, please continue reading Figure 5 The formation of a hard mask material layer 500 covering the initial structure of a semiconductor includes: sequentially stacking a first hard mask material layer 510 and a second hard mask material layer 520 on the initial semiconductor structure.

[0091] For example, the thickness of the first hard mask material layer 510 is greater than the thickness of the second hard mask material layer 520. Optionally, the thickness of the first hard mask material layer 510 ranges from 500nm to 1000nm, for example, 500nm, 600nm, 700nm, 800nm, 900nm, or 1000nm. Optionally, the thickness of the second hard mask material layer 510 ranges from 40nm to 100nm, for example, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, or 100nm.

[0092] In step S22, please refer to Figures 6-9 The hard mask material layer 500 is patterned to form a hard mask 50 and a pre-cut opening K located in the hard mask 50; the hard mask 50 at least covers the chip region Die; the pre-cut opening K extends along the dicing SL extension direction. Figure 9 As shown, the hard mask layer 50 covers not only the chip area Die, but also part of the test structure 3 within the dicing channel SL.

[0093] For example, please refer to Figure 6 The hard mask material layer 500 is patterned to form a hard mask 50 and a pre-cut opening K located in the hard mask 50, including steps S221 to S223.

[0094] S221, please refer to Figure 7 A patterned photoresist layer 7 is formed on the side of the second hard mask material layer 520 opposite to the first hard mask material layer 510. The photoresist layer 7 has a first opening K1, which exposes a portion of the second hard mask material layer 520.

[0095] For example, the orthographic projection of the first opening K1 on wafer 1 is located within the orthographic projection range of the dicing track SL on wafer 1.

[0096] In this embodiment, the thickness of the photoresist layer 7 can be selected and set according to actual needs, and is not limited here.

[0097] S222, please refer to Figure 8 Based on the first opening K1, the second hard mask material layer 520 is patterned to form the second hard mask 52 and the second opening K2 located in the second hard mask 52, the second opening K2 exposing a portion of the first hard mask material layer 510.

[0098] S223, please refer to Figure 9 Based on the second opening K2, the first hard mask material layer 510 is patterned to form the first hard mask 51 and the third opening K3 located in the first hard mask 51. The second opening K2 and the third opening K3 together constitute the pre-cut opening K; the pre-cut opening K exposes part of the test structure 3.

[0099] For example, the orthographic projections of the second opening K2 and the third opening K3 on wafer 1 coincide with the orthographic projection of the first opening K1 on wafer 1.

[0100] For example, the photoresist layer 7 can be removed after the formation of the first hard mask 51 and the pre-cut opening K.

[0101] In some embodiments, please continue reading Figure 9 The chip area die has a packaging protection layer 6. A step is provided between the packaging protection layer 6 and the test structure 2; the step includes an upper step surface S1 and a lower step surface S2 located at different heights. A hard mask 50 covers the step, and a pre-cut opening K is formed in the portion of the hard mask 50 covering the lower step surface S2.

[0102] For example, the encapsulation protection layer 6 includes a first encapsulation protection layer 61 and a second encapsulation protection layer 62. The first encapsulation protection layer 61 can be formed together with the second top dielectric layer 322 in the test structure 3 through a single patterning process. Optionally, the material of the first encapsulation protection layer 61 includes, but is not limited to, silicon oxide, and the material of the second encapsulation protection layer 62 includes, but is not limited to, silicon nitride.

[0103] For example, the hard mask 50 includes: a first hard mask 51 covering the step, and a second hard mask 52 located on the first hard mask 51 away from the surface of the step; wherein the first hard mask 51 includes a spin-on hard mask (SOH).

[0104] Optionally, the second hard mask 52 includes a silicon oxynitride (SiON) hard mask.

[0105] It can be understood that the first hard mask 51 and the second hard mask 52 are formed by the first hard mask material layer 510 and the second hard mask material layer 520, respectively. The first hard mask material layer 510 can eliminate the height difference between the packaging protection layer 6 and the test structure 3, and the second hard mask material layer 520 can serve as a bottom anti-reflection layer to absorb reflected light during the photolithography process.

[0106] In this embodiment, the chip region Die has a packaging protection layer 6, which protects the underlying structure. A step exists between the packaging protection layer 6 and the test structure 3, and the step includes an upper step surface S1 and a lower step surface S2 at different heights. A hard mask 50 covers the step, and a pre-cut opening K is formed in the portion of the hard mask 50 covering the lower step surface S2. This allows the hard mask 50 to protect the chip region Die and the test structure 3 and interconnect structures within the etch path SL that do not need to be etched away.

[0107] The hard mask 50 and the pre-cut opening K can be formed using the wafer dicing methods described in the foregoing embodiments. After forming the pre-cut opening K, the step of etching along the pre-cut opening K to remove part of the test structure 3 and part of the interconnect structure located directly below the pre-cut opening K can be performed.

[0108] In some embodiments, please combine Figure 9 and Figure 10 Understand that the test structure 3 includes test pads 31 and a top dielectric layer 32 for isolating the test pads 31; the portion of the test structure 3 and the portion of the interconnect structure located directly below the pre-cut opening K are etched away, including: the test pads 31 and the top dielectric layer 32 are removed by dry etching.

[0109] For example, the test pad 31 includes a conductive via 311 and a conductive layer 312. When removing the test pad 31, the conductive layer 312 and the conductive via 311 can be removed sequentially.

[0110] In some embodiments, please combine Figures 10-13 Understand that the interconnect structure includes a metal line structure 21 and an interlayer dielectric layer 22 that isolates the metal line structure 21; etching along the pre-cut opening K removes a portion of the test structure 3 and a portion of the interconnect structure located directly below the pre-cut opening K, including etching away the metal line structure 21 and the interlayer dielectric layer 22 respectively.

[0111] It should be understood that when the initial semiconductor structure includes multiple interconnect structures, the interconnect structures can be removed sequentially from top to bottom. For example, the third interconnect structure 203 can be removed first. Figure 11 As shown), then remove the second interconnect structure 202 (as shown). Figure 12 As shown), finally remove the first interconnect structure 201 (as shown). Figure 13 (As shown).

[0112] For example, wet etching is used to remove the metal line structure 21, and dry etching is used to remove the interlayer dielectric layer 22.

[0113] Optionally, the metal wire structure 21 can be removed using wet etching, including cleaning the metal wire structure 21 with a diluted sulfuric acid-hydrogen peroxide mixture to remove the metal wire structure 21. The ratio of the components in the diluted sulfuric acid-hydrogen peroxide mixture can be sulfuric acid (H2SO4): hydrogen peroxide (H2O2): dilute hydrofluoric acid (DHF): water (H2O) = 84575:38266:300:877159.

[0114] Optionally, the cleaning time for the metal wire structure 21 using a diluted sulfuric acid-hydrogen peroxide mixed solution is 20s to 180s, for example, 20s, 50s, 80s, 110s, 140s, or 180s. It should be understood that the cleaning time can be determined based on the thickness of the metal wire structure 21. For example, if the metal wire structure 21 in the first interconnect structure 201 is relatively thin, the cleaning time is shorter, typically 20s to 90s is sufficient to completely remove the metal wire structure 21. Conversely, if the metal wire structure 21 in the second interconnect structure 201 and the third interconnect structure 203 is relatively thick, the cleaning time is longer, typically 30s to 180s is sufficient to completely remove the metal wire structure 21.

[0115] Optionally, the interlayer dielectric layer 22 is removed by dry etching, including: etching the interlayer dielectric layer 22 with an etching gas; wherein the etching gas includes: carbon tetrafluoride (CF4), octafluoropropane (C3F8) or trifluoromethane (CHF3).

[0116] In some embodiments, a barrier layer B is provided between the metal wire structure 21 and the interlayer dielectric layer 22, between the conductive via 311 and the top dielectric layer 32, on the side of the conductive layer 312 near the conductive via 311, and on the side of the conductive layer 312 away from the conductive via 311. Based on this, etching away a portion of the test structure 3 and a portion of the interconnect structure located directly below the pre-cut opening K further includes removing the barrier layer B.

[0117] The barrier layer B here can be formed of the same material as the barrier layer B between the contact structure 14 and the bottom dielectric layer 15 in some of the aforementioned embodiments. Optionally, the material of the barrier layer B includes tantalum (Ta) or tantalum nitride (TaN).

[0118] It should be noted that in the above wafer dicing method, after forming the pre-dicing trench H, a portion of the test structure and interconnect structure is still left within the dicing track SL. This allows the remaining test structure and interconnect structure within the dicing track SL to protect the chip area, preventing damage to the chip area during subsequent dicing or other processes.

[0119] In some embodiments, please combine Figure 13 and Figure 14 It is understood that the chip region Die also has a bonding structure 41. The bonding structure 41 is exposed on the lower step surface S2, and the hard mask 50 also covers the bonding structure 41. After forming the pre-cut trench H and before cutting the wafer 1 along the pre-cut trench H, the fabrication method further includes: removing the residual hard mask 50 to expose the packaging protective layer 6 and the bonding structure 41.

[0120] For example, the bonding structure 41 can be the portion of the top pad 4 not covered by the encapsulation protective layer 6 in some of the aforementioned embodiments. The bonding structure 41 is a reserved connection structure in the DRAM, which allows the DRAM to be connected to external circuit boards or other electronic components after wafer dicing. The structure and materials of the bonding structure 41 (i.e., the top pad 4) can be referred to in test structure 3, and will not be described in detail here.

[0121] In this embodiment, the chip region Die also has a bonding structure 41 exposed to the lower step surface S2, and the hard mask 50 further covers the bonding structure 41. Furthermore, the hard mask 50 is removed after the pre-cut trench H is formed and before the wafer 1 is cut along the pre-cut trench H. Thus, during the formation of the pre-cut trench H, the hard mask layer 50 can be used to protect the underlying bonding structure 41, preventing damage to the bonding structure 41.

[0122] In other embodiments, the hard mask 50 can be etched simultaneously during the removal of a portion of the test structure 3 and a portion of the interconnect structure.

[0123] For example, the hard mask 50 includes a first hard mask 51 and a second hard mask 52.

[0124] Please see Figures 15-18 The wafer dicing method further includes: simultaneously etching the second hard mask 52 and the first hard mask 51 during the removal of a portion of the test structure 3; and simultaneously etching the remaining first hard mask 51 during the removal of a portion of the interconnect structure.

[0125] In this embodiment, the first hard mask 51 is not removed all at once, but gradually during the removal of a portion of the test structure 3 and the interconnect structure. That is to say, throughout the entire process of removing a portion of the test structure 3 and the interconnect structure, a portion of the first hard mask 51 still covers the encapsulation protection layer 6 and the bonding structure 41 to protect them.

[0126] It should be understood that only a certain thickness of the first hard mask 51 can be removed during each etching process. Since the first hard mask 51 is relatively thick, a portion of the first hard mask 51 may still remain after the first interconnect structure 201 is etched. This portion of the first hard mask 51 can be removed separately after the pre-cut trench H is formed.

[0127] In step S30, please refer to Figure 19 , cut wafer 1 along the pre-cut groove H.

[0128] In some embodiments, please refer to Figure 20The cutting track SL has a centerline L1 extending along its length; the distance D from the boundary line L2 of the pre-cut groove H along its length to the centerline L1 of the cutting track SL ranges from 10 μm to 30 μm. This distance is, for example, 10 μm, 15 μm, 20 μm, 25 μm, or 30 μm.

[0129] In this embodiment of the disclosure, there is a relatively wide distance between the boundary line of the pre-cut groove H along the length direction and the center line of the cutting path SL, so that enough space can be reserved to facilitate cutting.

[0130] Based on the same inventive concept, this disclosure also provides a semiconductor structure that can be formed using the wafer dicing methods described in some of the foregoing embodiments. The semiconductor structure can also achieve the technical effects achievable by the wafer dicing methods described in the foregoing embodiments, and will not be detailed here.

[0131] Please see Figure 21 In some embodiments, the semiconductor structure includes a wafer 1 and a chip region Die disposed on the wafer 1. The chip region Die includes a cell array region and a peripheral circuit region Peri located around the cell array region. The cell array region includes a cell transistor region 11 and a capacitor region 12, and the peripheral circuit region Peri includes a peripheral transistor region 13.

[0132] For example, the chip region die also includes a contact structure 14 and a bottom dielectric layer 15 for isolating the contact structure 14.

[0133] For example, the chip area die also includes a multilayer interconnect structure (a first interconnect structure 201, a second interconnect structure 202, and a third interconnect structure 203) connected to the contact structure 12.

[0134] For example, the chip area die also includes a top pad 4 and a packaging protection layer 6.

[0135] like Figure 21 As shown, other structures are also provided on the side of the chip area Die. These structures are the structures that were not removed in the cutting channel in some of the aforementioned embodiments, and will not be described in detail here.

[0136] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0137] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A wafer dicing method, characterized in that, include: Provide wafers with initial semiconductor structures prepared; The initial semiconductor structure has a chip region and dicing tracks surrounding the chip region; The dicing channel has a test structure and an interconnect structure; the interconnect structure includes a metal wire structure and an interlayer dielectric layer that isolates the metal wire structure. A pre-cut opening is formed in the dicing channel, and a portion of the test structure and a portion of the interconnect structure located directly below the pre-cut opening are etched away along the pre-cut opening, including: removing the metal line structure using wet etching and removing the interlayer dielectric layer using dry etching, respectively, to form a pre-cut trench, the pre-cut trench extending along the extension direction of the dicing channel; The wafer is cut along the pre-cut groove; The process of removing the metal wire structure using wet etching includes: cleaning the metal wire structure with a diluted sulfuric acid-hydrogen peroxide mixed solution for 20s to 180s to remove the metal wire structure.

2. The wafer dicing method according to claim 1, characterized in that, The material of the interlayer dielectric layer includes silicon oxide, silicon nitride, silicon carbide, hydrogenated carbon silicon oxide, or silicon carbon nitride.

3. The wafer dicing method according to claim 2, characterized in that, Removing the interlayer dielectric layer using dry etching includes: etching the interlayer dielectric layer using an etching gas; wherein the etching gas includes: carbon tetrafluoride, octafluoropropane, or trifluoromethane.

4. The wafer dicing method according to claim 1, characterized in that, The test structure includes test pads and a top dielectric layer that isolates the test pads; Etching away a portion of the test structure and a portion of the interconnect structure located directly below the pre-cut opening includes: using dry etching to remove the test pads and the top dielectric layer.

5. The wafer dicing method according to claim 1, characterized in that, The cutting channel has a centerline extending along its length; The distance from the boundary line of the pre-cut groove along the length direction to the center line of the cutting path ranges from 10μm to 30μm.

6. The wafer dicing method according to any one of claims 1 to 5, characterized in that, Forming a pre-cut opening in the cutting channel includes: Form a hard mask material layer covering the initial structure of the semiconductor; The hard mask material layer is patterned to form a hard mask and the pre-cut opening located in the hard mask; the hard mask at least covers the chip area; the pre-cut opening extends along the cutting path extension direction.

7. The wafer dicing method according to claim 6, characterized in that, The chip area has a packaging protection layer; there is a step between the packaging protection layer and the test structure; the step includes an upper step surface and a lower step surface located at different heights; The hard mask covers the step, and the pre-cut opening is formed in the portion of the hard mask that covers the lower step surface.

8. The wafer dicing method according to claim 7, characterized in that, The chip region also has a bonding structure; the bonding structure is exposed on the lower step surface, and the hard mask also covers the bonding structure. After forming the pre-cut trench, before cutting the wafer along the pre-cut trench, the wafer cutting method further includes: removing the remaining hard mask to expose the packaging protective layer and the bonding structure.

9. The wafer dicing method according to claim 7, characterized in that, The hard mask includes: a first hard mask covering the step, and a second hard mask located on the first hard mask away from the surface of the step; The first hard mask includes a spin-coated hard mask.

10. The wafer dicing method according to claim 6, characterized in that, Forming a hard mask material layer covering the initial semiconductor structure includes: sequentially stacking a first hard mask material layer and a second hard mask material layer on the initial semiconductor structure; Patterning the hard mask material layer to form a hard mask and the pre-cut opening located in the hard mask includes: A patterned photoresist layer is formed on the side of the second hard mask material layer opposite to the first hard mask material layer. The photoresist layer has a first opening that exposes a portion of the second hard mask material layer. Based on the first opening, the second hard mask material layer is patterned to form a second hard mask and a second opening located in the second hard mask, the second opening exposing a portion of the first hard mask material layer; Based on the second opening, the first hard mask material layer is patterned to form a first hard mask and a third opening located in the first hard mask; The second opening and the third opening together constitute the pre-cut opening; the pre-cut opening exposes part of the test structure.

11. A semiconductor structure, characterized in that, It is formed using the wafer dicing method as described in any one of claims 1 to 10.

Images