Memory devices, methods of manufacturing the same, and systems

Abstract

The present application relates to a memory device and a manufacturing method and system thereof, the memory device comprising: providing a semiconductor structure, the semiconductor structure comprising a stack layer, the stack layer comprising alternately stacked sacrificial layers and dielectric layers, the stack layer comprising a first region and a second region adjacently distributed along a first direction, the second region comprising a plurality of channel structures penetrating through the stack layer; forming a top cap layer on top of the stack layer; forming a plurality of openings penetrating through the top cap layer in the first region, and simultaneously forming a plurality of second contact holes penetrating through the top cap layer and reaching top ends of the plurality of channel structures in the second region, wherein the plurality of openings correspond to a plurality of first contact holes, each first contact hole penetrating through a number of layers in the stack layer to reach a respective predetermined depth of a sacrificial layer; forming a first contact structure in each first contact hole, and forming a second contact structure in each second contact hole.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a semiconductor device, and more particularly to a memory device and a method for manufacturing the same, and a system including the memory device. Background Technology

[0002] With the continuous development of 3D NAND technology, memory devices can be stacked with an increasing number of layers, from 24, 32, and 64 layers to high-order stacking structures exceeding 400 layers. This significantly increases storage density and reduces the price per unit of memory cell. In the three-dimensional memory of 3D NAND flash memory, there are core and stair step (SS) regions. The core region forms multiple memory strings, each containing multiple memory cells. The stair step region is used to bring out contact structures from the word lines of each layer. The core region also includes contact structures extending from the top of the memory strings. These contact structures connect to a controller, allowing the memory cells to perform operations such as programming, reading, and erasing / writing.

[0003] The formation process of the step region requires etching a large-area stacked structure, followed by filling and planarization. This method is costly, has a long production cycle, and suffers from the challenge of planarization. These issues limit the development of 3D memory towards more layers and larger capacities. Furthermore, current processes for handling the step and core regions are complex and costly. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a memory device and a method and system for manufacturing the same that saves process steps and reduces costs.

[0005] The present invention provides a method for manufacturing a memory device to solve the aforementioned technical problems. The method includes: providing a semiconductor structure comprising a stacked layer, the stacked layer comprising alternately stacked sacrificial layers and dielectric layers, the stacked layer comprising a first region and a second region adjacent to each other along a first direction, the second region comprising a plurality of channel structures penetrating the stacked layer; forming a top cap layer on top of the stacked layer; forming a plurality of openings penetrating the top cap layer in the first region, and simultaneously forming a plurality of second contact holes penetrating the top cap layer and reaching the top ends of the plurality of channel structures in the second region, wherein the plurality of openings correspond to a plurality of first contact holes, each first contact hole penetrating several layers in the stacked layer and reaching a sacrificial layer of a predetermined depth; forming a first contact structure in each first contact hole, and forming a second contact structure in each second contact hole.

[0006] In one embodiment of the present invention, the step of forming a plurality of openings penetrating the top cap layer in the first region and simultaneously forming a plurality of second contact holes penetrating the top cap layer and reaching the top of the plurality of channel structures in the second region includes: covering the top cap layer with a first hard mask layer; covering the first hard mask layer with a first photoresist layer; and patterning the first hard mask layer through the first photoresist layer to form the plurality of second contact holes and a plurality of openings penetrating the top cap layer and reaching the top of the stacked layer.

[0007] In one embodiment of the invention, after forming the plurality of second contact holes and the plurality of openings of the sacrificial layer that penetrate the top cap layer to reach the top of the stacked layer, the method further includes: covering the first hard mask layer with a second photoresist layer; and cyclically performing the steps of trimming the second photoresist layer in the first direction, exposing a predetermined number of the openings, and etching a predetermined number of stacked layers through the exposed openings, thereby forming the plurality of first contact holes using the plurality of openings.

[0008] In one embodiment of the present invention, after forming the plurality of first contact holes, the method further includes: removing the first hard mask layer; simultaneously forming an insulating layer on the sidewalls and bottom of the plurality of first contact holes and the plurality of second contact holes; simultaneously filling the insulating layer inside the plurality of first contact holes and the plurality of second contact holes with a sacrificial material; forming a capping layer on top of the semiconductor structure; forming a gate line slot through the stacked layer along the first direction; removing the sacrificial layer in the stacked layer through the gate line slot; and filling the gap formed after removing the sacrificial layer with a conductive material to form a gate layer.

[0009] In one embodiment of the present invention, the steps of forming a first contact structure in each first contact hole and forming a second contact structure in each second contact hole include: covering the cap layer with a third photoresist layer; patterning the cap layer through the third photoresist layer to form a plurality of first openings penetrating the cap layer to the top of the plurality of first contact holes and a plurality of second openings penetrating the cap layer to the top of the plurality of second contact holes; removing sacrificial material from the plurality of first contact holes through the plurality of first openings and simultaneously removing sacrificial material from the plurality of second contact holes through the plurality of second openings; removing an insulating layer at the bottom of the first contact holes through the plurality of first openings and simultaneously removing an insulating layer at the bottom of the plurality of second contact holes through the plurality of second openings; and filling the plurality of first contact holes with conductive material to form the first contact structure and simultaneously filling the plurality of second contact holes with conductive material to form the second contact structure.

[0010] In one embodiment of the present invention, the critical dimension of the first opening is greater than the critical dimension of the first contact hole, and the critical dimension of the second opening is greater than the critical dimension of the second contact hole.

[0011] In one embodiment of the invention, prior to the step of forming a top cover layer on top of the stacked layers, the method further includes: forming a plurality of virtual channel structures through the stacked layers in a first region of the stacked layers.

[0012] In one embodiment of the present invention, prior to the step of forming a top cap layer on top of the stacked layers, the method further includes: covering the top of the stacked layers with a second hard mask layer; covering the second hard mask layer with a fourth photoresist layer; patterning the second hard mask layer through the fourth photoresist layer to form a plurality of third openings in the first region, the plurality of third openings penetrating the dielectric layer on top of the stacked layers to reach the sacrificial layer on top of the stacked layers; covering the second hard mask layer with a fifth photoresist layer; and cyclically performing the steps of trimming the fifth photoresist layer in the first direction, exposing a predetermined number of the third openings, and etching a predetermined number of stacked layers through the exposed third openings, thereby forming the plurality of first contact holes using the plurality of third openings.

[0013] In one embodiment of the invention, the step of forming the plurality of first contact holes includes: removing the second hard mask layer; forming an insulating layer on the sidewalls and bottom of the plurality of first contact holes; and filling the inner walls of the insulating layer in the plurality of first contact holes with a sacrificial material.

[0014] In one embodiment of the present invention, after the step of forming the top cap layer on top of the semiconductor structure, the method includes: forming a gate line slot through the stacked layer along the first direction, removing the sacrificial layer in the stacked layer through the gate line slot, and filling the void formed after removing the sacrificial layer with a conductive material to form a gate layer.

[0015] In one embodiment of the present invention, the step of forming a plurality of openings penetrating the top cover layer in the first region and simultaneously forming a plurality of second contact holes penetrating the top cover layer and reaching the top of the plurality of channel structures in the second region includes: forming a sixth photoresist layer on the top cover layer; and patterning the top cover layer through the sixth photoresist layer to simultaneously form the plurality of openings and the plurality of second contact holes.

[0016] In one embodiment of the present invention, the steps of forming a first contact structure in each first contact hole and forming a second contact structure in each second contact hole include: removing sacrificial material from the plurality of first contact holes through the plurality of openings; removing an insulating layer from the bottom of the first contact holes through the plurality of openings; and filling the plurality of first contact holes with conductive material to form the first contact structure, while simultaneously filling the plurality of second contact holes with conductive material to form the second contact structure.

[0017] In one embodiment of the present invention, the critical dimension of the opening is larger than the critical dimension of the first contact hole.

[0018] In one embodiment of the present invention, prior to the step of forming the plurality of first contact holes, the method further includes: forming a plurality of virtual channel structures penetrating the stacked layer in a first region of the stacked layer.

[0019] In one embodiment of the present invention, the first region includes a word line connection area, and the second region includes a core storage area.

[0020] To address the aforementioned technical problems, this invention also proposes a memory device, comprising: a stacked structure including alternately stacked gate layers and dielectric layers, the stacked structure including a first region and a second region adjacently distributed along a first direction, the second region including a plurality of channel structures penetrating the stacked structure; a plurality of first contact structures located in the first region, each first contact structure penetrating several layers in the stacked structure and respectively contacting a gate layer at a predetermined depth; and a plurality of second contact structures located in the second region, each second contact structure contacting the top end of the channel structure.

[0021] In one embodiment of the present invention, the first region includes a word line connection area, and the second region includes a core storage area.

[0022] In one embodiment of the present invention, the first region includes a plurality of virtual channel structures that run through the stacked structure.

[0023] In one embodiment of the invention, at least one grid line slot extends along the first direction and penetrates the stacked structure.

[0024] In one embodiment of the invention, a top cover layer is further formed above the stacked structure, the top cover layer including a first contact plug that contacts the first contact structure, the critical dimension of the first contact plug being larger than the critical dimension of the first contact structure.

[0025] In one embodiment of the invention, a top cover layer is further formed above the stacked structure, the top cover layer including a second contact plug that contacts the second contact structure, the critical dimension of the second contact plug being larger than the critical dimension of the second contact structure.

[0026] In one embodiment of the invention, a semiconductor layer is further included, and the stacked structure covers the semiconductor layer.

[0027] To address the aforementioned technical problems, the present invention also proposes a system comprising a memory device as described above, configured to store data, and a memory controller coupled to the memory device and configured to control the memory device.

[0028] In one embodiment of the invention, a host coupled to the memory controller is also included.

[0029] The memory device and its manufacturing method of the present invention do not require a step forming method, resulting in low manufacturing cost, saving wafer area, and improving product density and product performance. Furthermore, by forming multiple openings and multiple second contact holes corresponding to multiple first contact holes in the same step, process steps are saved, further reducing costs. The first contact structure and / or the second contact structure have a large-sized plug at the top, which is beneficial for the memory device to establish an electrical connection with the outside. Attached Figure Description

[0030] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0031] Figure 1A-1C This is a schematic diagram of a semiconductor structure with a stepped region;

[0032] Figure 1D This is a schematic diagram of another semiconductor structure with a stepped region;

[0033] Figure 2 This is an exemplary flowchart of a method for manufacturing a memory device according to an embodiment of the present invention;

[0034] Figures 3A-3D This is an exemplary process flowchart of the manufacturing method of the memory device according to Embodiment 1 of the present invention;

[0035] Figures 4A to 4W This is a schematic diagram of the manufacturing process of the memory device according to Embodiment 1 of the present invention;

[0036] Figures 5A-5E This is an exemplary process flowchart of the manufacturing method of the memory device according to Embodiment 2 of the present invention;

[0037] Figure 6A-6U This is a schematic diagram of the manufacturing process of the memory device according to Embodiment 2 of the present invention;

[0038] Figure 7 This is a cross-sectional structural schematic diagram of the memory device according to Embodiment 1 of the present invention;

[0039] Figure 8 This is a cross-sectional structural schematic diagram of the memory device according to Embodiment 2 of the present invention;

[0040] Figure 9 This is a block diagram of a system having a memory device according to an embodiment of the present invention;

[0041] Figure 10A This is a block diagram of a memory card including a memory device according to an embodiment of the present invention;

[0042] Figure 10B This is a block diagram of an SSD including a memory device according to an embodiment of the present invention. Detailed Implementation

[0043] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0044] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the invention is not limited to the specific embodiments disclosed below.

[0045] As indicated in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not specifically singular and may include plural forms. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0046] In detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure will be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0047] For ease of description, spatial relation terms such as “below,” “below,” “lower than,” “below,” “above,” “upper,” etc., may be used herein to describe the relationship of an element or feature shown in the accompanying drawings to other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, the orientation of an element described as “below,” “below,” or “below” to other elements or features will change to “above” said other elements or features. Thus, the exemplary terms “below” and “below” can encompass both upward and downward directions. The device may also have other orientations (rotated 90 degrees or in other orientations), and therefore the spatial relation descriptors used herein should be interpreted accordingly. Furthermore, it will be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more layers in between.

[0048] In the context of this application, the structure described above the second feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0049] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore cannot be construed as limiting the scope of protection of this application.

[0050] As used herein, the term "three-dimensional (3D) memory device" refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings," such as NAND strings) on a laterally oriented substrate, such that the memory strings extend in a vertical direction relative to the substrate. As used herein, the term "vertical / vertically" means nominally perpendicular to the lateral surface of the substrate.

[0051] As used herein, "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0052] As used in this application, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes thereon. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0053] Flowcharts are used in this application to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously. Furthermore, other operations may be added to these processes, or one or more steps may be removed from these processes.

[0054] In the fabrication of semiconductor devices (such as 3D NAND), a stepped region with a stepped structure is needed to connect the contact structure to each word line. The process steps for forming the stepped structure include etching, deposition, and planarization. As the number of layers in 3D NAND increases, the time required for these process steps increases significantly, which also increases the complexity of the process.

[0055] Figure 1A-1C This is a schematic diagram of a semiconductor structure with a stepped region. Figure 1D This is a schematic diagram of another semiconductor structure with a stepped region.

[0056] refer to Figure 1A As shown, a substrate 101 and a stacked structure 110 formed on the substrate 101 are illustrated. The stacked structure 110 is formed by alternating layers of two different materials. A step structure 111 is formed on one side of the stacked structure 110, which constitutes a step region 120 of the semiconductor structure. To form the step region 120, a trimming-etching operation is typically performed on the stacked structure 110 to gradually remove the stacked material above the step structure 111. This process is time-consuming and costly.

[0057] refer to Figure 1BAs shown, in order to form a contact structure connecting each word line in the step region 120, the space above the step structure 111 needs to be filled first. For example, an oxide layer 130 is formed using high-density plasma (HDP) + tetraethyl orthosilicate (TEOS) deposition. The top of the oxide layer 130 is then planarized, for example using a CMP (chemical mechanical planarization) process. Figure 1C As shown, the upper surface of the oxide layer 130 is smoothed after the CMP process.

[0058] However, in actual production processes, on the one hand, as the number of layers in 3D NAND increases, the depressions formed by the step region 120 become deeper, making it difficult to fully fill them; on the other hand, the planarization process for the filling material is quite difficult, making it hard to grind it to an ideal level, resulting in issues such as... Figure 1C The uneven upper surface is shown. Furthermore, in some special stepped structures, for example... Figure 1D The semiconductor structure shown has multiple step regions of different depths. This step-forming method, which removes large areas of stacked layers, also brings severe stress effects, makes the process steps more complex, and increases costs.

[0059] Figure 2 This is an exemplary flowchart of a method for manufacturing a memory device according to an embodiment of the present invention. (See reference) Figure 2 As shown, the manufacturing method of this embodiment includes the following steps:

[0060] Step S210: Provide a semiconductor structure, the semiconductor structure including a stacked layer, the stacked layer including alternately stacked sacrificial layers and dielectric layers, the stacked layer including a first region and a second region distributed adjacent to each other along a first direction, the second region including a plurality of channel structures through the stacked layer;

[0061] Step S220: Form a top cover layer on top of the stacked layers;

[0062] Step S230: A plurality of openings penetrating the top cover layer are formed in the first region, and a plurality of second contact holes penetrating the top cover layer and reaching the top of the plurality of channel structures are formed in the second region, wherein the plurality of openings correspond to a plurality of first contact holes, and each first contact hole penetrates several layers in the stacked layers and reaches a sacrificial layer at a predetermined depth.

[0063] Step S240: A first contact structure is formed in each of the first contact holes, and a second contact structure is formed in each of the second contact holes.

[0064] The method for manufacturing the memory device of the present invention simultaneously forms multiple openings corresponding to multiple first contact holes in a first region and multiple second contact holes in a second region in the same process step, saving process steps and reducing production costs. The multiple first contact holes are used to contact sacrificial layers at various predetermined depths, avoiding issues such as… Figure 1A-1C The step of re-grinding a large amount of filler material, as shown, reduces the complexity and cost of the process.

[0065] The present invention does not restrict the order between the formation of the multiple first contact holes corresponding to the multiple openings in step S230 and the formation of the top cover layer in step S220.

[0066] In Embodiment 1, a top cover layer is formed first, followed by the formation of multiple first contact holes.

[0067] In Embodiment 2, multiple first contact holes are formed first, and then a top cover layer is formed.

[0068] The following description, in conjunction with the accompanying drawings, will illustrate Embodiment 1 and Embodiment 2 respectively.

[0069] Example 1

[0070] Figures 3A-3D This is an exemplary process flowchart of the manufacturing method of the memory device according to Embodiment 1 of the present invention. (See reference) Figure 3A As shown, in the manufacturing method of this embodiment, the step S230 of forming a plurality of openings penetrating the top cover layer in the first region and simultaneously forming a plurality of second contact holes penetrating the top cover layer and reaching the top of a plurality of channel structures in the second region includes:

[0071] Step S310: Cover the top cap layer with a first hard mask layer;

[0072] Step S312: Cover the first photoresist layer on the first hard mask layer;

[0073] Step S314: Pattern the first hard mask layer through the first photoresist layer to form multiple openings and multiple second contact holes through the top cap layer to the top of the stacked layer in the sacrificial layer.

[0074] According to Embodiment 1, a top cover layer is first formed in step S220, and then multiple openings corresponding to multiple first contact holes and multiple second contact holes are simultaneously formed in step S314.

[0075] refer to Figure 3B As shown, in some embodiments, after step S314, the following steps are further included:

[0076] Step S316: Cover the first hard mask layer with a second photoresist layer;

[0077] Step S318: Repeatedly perform the steps of trimming the second photoresist layer in the first direction, exposing a predetermined number of openings, and etching a predetermined number of stacked layers through the exposed openings, thereby forming a plurality of first contact holes using the plurality of openings.

[0078] refer to Figure 3C As shown, in some embodiments, after step S318, the following steps are further included:

[0079] Step S320: Remove the first hard mask layer;

[0080] Step S322: Simultaneously form an insulating layer on the sidewalls and bottom of the plurality of first contact holes and the plurality of second contact holes;

[0081] Step S324: Simultaneously fill the inner side of the insulating layer in multiple first contact holes and multiple second contact holes with sacrificial material;

[0082] Step S326: Form a capping layer on top of the semiconductor structure;

[0083] Step S328: Form a gate line slot through the stacked layer along the first direction, remove the sacrificial layer in the stacked layer through the gate line slot, and fill the gap formed after removing the sacrificial layer with conductive material to form a gate layer.

[0084] refer to Figure 3D As shown, in some embodiments, step S240 is performed after step S328, which includes the following steps:

[0085] Step S330: Cover the cap layer with a third photoresist layer;

[0086] Step S332: Pattern the cap layer through the third photoresist layer to form a plurality of first openings that penetrate the cap layer to reach the top of a plurality of first contact holes, and a plurality of second openings that penetrate the cap layer to reach the top of a plurality of second contact holes;

[0087] Step S334: Remove sacrificial material from multiple first contact holes through multiple first openings, and simultaneously remove sacrificial material from multiple second contact holes through multiple second openings;

[0088] Step S336: Remove the insulating layer at the bottom of the first contact hole through multiple first openings, and simultaneously remove the insulating layer at the bottom of multiple second contact holes through multiple second openings; and

[0089] Step S338: Fill the plurality of first contact holes with conductive material to form a first contact structure, and at the same time fill the plurality of second contact holes with conductive material to form a second contact structure.

[0090] The following is combined Figures 4A to 4W Example 1 will be described.

[0091] Figures 4A to 4W This is a schematic diagram illustrating the manufacturing process of the memory device according to Embodiment 1 of the present invention. Most of the figures are as follows. Figure 4A The front view shown also includes parts such as Figure 4E The top view shown is a sectional view along line AA' in the top view.

[0092] refer to Figure 4A As shown, a semiconductor structure is provided in step S210, which includes a stacked layer 410 composed of alternately stacked sacrificial layers 411 and dielectric layers 412. The sacrificial layers 411 and dielectric layers 412 can be materials selected from and including at least one insulating medium, such as silicon nitride, silicon oxide, amorphous carbon, diamond-like amorphous carbon, germanium oxide, aluminum oxide, and combinations thereof. The sacrificial layers 411 and dielectric layers 412 have different etching selectivities. For example, they can be a combination of silicon nitride and silicon oxide, a combination of silicon oxide and undoped polycrystalline or amorphous silicon, or a combination of silicon oxide or silicon nitride and amorphous carbon. The deposition methods for the sacrificial layers 411 and dielectric layers 412 can include chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), atomic layer deposition (ALD), or physical vapor deposition methods such as molecular beam epitaxy (MBE), thermal oxidation, evaporation, sputtering, and various other methods. The sacrificial layer 411 can be a pseudo-gate layer, i.e., a gate sacrificial layer, and its material can be, for example, a silicon nitride layer. The material used as the dielectric layer can be, for example, silicon oxide, aluminum oxide, hafnium oxide, tantalum oxide, etc.

[0093] In some embodiments, the semiconductor structure further includes a semiconductor layer 401, and a stacked layer 410 is formed on the semiconductor layer 401, wherein the bottom of the stacked layer 410 is in contact with the semiconductor layer 401, and the top of the stacked layer 410 is also exposed as a dielectric layer.

[0094] In some embodiments, semiconductor layer 401 is a substrate. The substrate may be a silicon substrate (Si), a germanium substrate (Ge), a silicon germanide substrate (SiGe), silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. The aforementioned materials may be doped or undoped, such as being doped with p-type or n-type dopants. In some embodiments, the substrate may also be a substrate comprising other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC. It may also be a stacked structure, such as Si / SiGe. Other epitaxial structures may also be included, such as silicon-germanium-on-insulator (SGOI). In some embodiments, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers. Figure 4AThe substrate shown may have undergone some necessary processing, such as forming a common active region and undergoing necessary cleaning.

[0095] In embodiments of the present invention, the substrate material is, for example, silicon. The sacrificial layer 411 and the dielectric layer 412 are, for example, a combination of silicon nitride and silicon oxide. Taking the combination of silicon nitride and silicon oxide as an example, silicon nitride and silicon oxide can be alternately deposited on the substrate sequentially using chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable deposition methods to form a stacked layer 410.

[0096] refer to Figure 4A As shown, the first direction D1 is as follows Figure 4A The diagram shows the extension direction of the upper surface of semiconductor layer 401. A first region 420 and a second region 430 are adjacently distributed along the first direction D1. The present invention does not limit the size and position of the first region 420 and the second region 430. Figure 4A In the illustrated embodiment, the first region 420 is located to the left of the second region 430 and has a larger area than the second region 430.

[0097] refer to Figure 4A As shown, the second region 430 includes a channel structure 431 that penetrates the stacked layer 410, indicating that the channel structure 431 has been formed in the second region 430 in step S210.

[0098] The channel structure 431 may include a channel layer and a memory layer. Overall, the channel structure 431 may include a channel via, with the memory layer and channel layer sequentially arranged radially from the outside to the inside along the channel via. The memory layer may include a barrier layer, a charge trapping layer, and a tunneling layer sequentially arranged radially from the outside to the inside along the channel via. A filler layer may also be provided within the channel layer. The filler layer can act as a support. The material of the filler layer may be silicon oxide. The filler layer can be solid or hollow, provided it does not affect device reliability. The vertical channel structure can be formed using one or more thin-film deposition processes, such as ALD, CVD, PVD, or any combination thereof.

[0099] In an embodiment where the memory device is 3D NAND, the first region 420 includes a word line connection region, and the second region 430 includes a core memory region.

[0100] refer to Figure 4B As shown, in step S220, a top cover layer 440 is formed on top of the stacked layer 410.

[0101] Combination Figure 4AThe top of the stacked layer 410 is a dielectric layer 413, and a top cap layer 440 covers the top dielectric layer 413. In some embodiments, the material of the top cap layer 440 includes one or more of silicon oxide (SiO2), silicon oxynitride, aluminum oxide (Al2O3), and titanium nitride. For example, the material of the top cap layer 440 is silicon oxide (SiO2). The deposition method for forming the top cap layer 440 includes various methods such as chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). Reference Figure 4B As shown, in this embodiment, the top cover layer 440 uses the same material as the dielectric layer 413 to avoid internal stress caused by the difference in thermal expansion coefficients. Figure 4B The same pattern is used for identification.

[0102] refer to Figure 4A As shown, in some embodiments, prior to the step of forming the top cap layer 440 in step S220, the method further includes: forming a plurality of virtual channel structures 421 penetrating the stacked layer 410 in a first region 420 of the stacked layer 410. These plurality of virtual channel structures 421 may be formed in the same process step as the channel structures 431 in the second region 430. It should be noted that in Figure 4A The same fill pattern is used to represent the channel structure 431 and the virtual channel structure 421, but this is not intended to limit the internal structure and materials of the two to be the same. In some embodiments, after the channel structure 431 and the virtual channel structure 421 are formed, the top of the stacked layer 410 is further planarized before step S220.

[0103] Figure 4A It is not used to limit the number, location, etc. of virtual channel structures 421 and channel structures 431.

[0104] In some embodiments, the distribution density of the virtual channel structure 421 in the first region 420 is less than the distribution density of the channel structure 431 in the second region 430.

[0105] In other embodiments, no virtual channel structure is formed in the first region 420.

[0106] refer to Figure 4A As shown, the bottom of the channel structure 431 and the virtual channel structure 421 are located in the substrate.

[0107] refer to Figure 4B As shown, the top cover 440 covers the first region 420 and the second region 430.

[0108] refer to Figure 4CAs shown, in step S310, a first hard mask layer 450 is applied over the top cap layer 440. The material of the first hard mask layer 450 includes alumina (Al2O3) and silicon oxynitride (SiO2). x N y The deposition method for forming the first hard mask layer 450 includes various methods such as chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). The first hard mask layer 450 covers the first region 420 and the second region 430.

[0109] refer to Figure 4D As shown, in step S312, a first photoresist layer 460 is applied to the first hard mask layer 450. The first photoresist layer 460 covers the first region 420 and the second region 430.

[0110] In order to perform step S314, a pattern is formed on the first photoresist layer 460, wherein a first pattern 461 is formed in a first region and a second pattern 462 is formed in a second region.

[0111] Figure 4E yes Figure 4D Top view, Figure 4D It is along Figure 4E A cross-sectional view of line AA'. The first direction D1 is parallel to line AA'. (Reference) Figure 4E As shown, in the first region 420, the first pattern 461 includes three rows of open patterns distributed along the first direction D1, such as... Figure 4E Rows 461a, 461b, and 461c shown each contain multiple open patterns. The direction of the rows here is as follows: Figure 4E The first direction D1 is shown. In some embodiments, the spacing between the plurality of opening patterns in each row is equal.

[0112] The process steps for forming multiple openings can include applying photoresist, exposure, development, etching, etc., and this invention does not limit these steps.

[0113] In 3D NAND, the first direction D1 is parallel to the word line extension direction.

[0114] In the second region 430, the second pattern 462 includes three sub-patterns: sub-patterns 462a, 462b, and 462c. Each sub-pattern includes multiple columns of open patterns. The direction of each column refers to a second direction D2 perpendicular to the first direction D1. Each column of open patterns includes multiple openings. In some embodiments, the multiple open patterns in each column are equally spaced, and adjacent columns are equally spaced.

[0115] In some embodiments, sub-patterns 462a, 462b, and 462c correspond to various memory regions distributed in memory blocks of a memory device, for example, within memory regions. Figure 4E It includes three pointer storage areas distributed in parallel along the first direction D1.

[0116] refer to Figure 4E As shown, the virtual channel structure 421 and the communication structure 431 are covered by a first photoresist layer 460, a first hard mask layer 450, and a top cap layer 440. Figure 4E As can be seen from the angle shown, in the first region 420, the opening pattern in the first pattern 461 is offset from the virtual channel structure 421, and the opening pattern in the first pattern 461 and the virtual channel structure 421 do not intersect. The multiple openings in the second pattern 462 correspond one-to-one with the channel structure 431.

[0117] refer to Figure 4F As shown, in step S314, after the first hard mask layer 450 is patterned by the first photoresist layer 460, the first photoresist layer 460 is removed, and a pattern is formed in the first hard mask layer 450, forming a plurality of openings 451 and a plurality of second contact holes 452 that penetrate through the top cap layer 440 to the top of the sacrificial layer 414. The plurality of second contact holes 452 reach the top of the channel structure 431.

[0118] refer to Figure 4G As shown, in step S316, a second photoresist layer 463 is covered on the first hard mask layer 450.

[0119] In the cyclically executed trimming-etching step of step S318, Figure 4G The image shows the initial step of this cycle, where the second photoresist layer 463 is trimmed in the first direction D1. (Combined with...) Figure 4G A bird's-eye view Figure 4H As shown, the leftmost column of openings 451a is exposed.

[0120] refer to Figure 4I As shown, a predetermined number of stacked layers, specifically two layers (one sacrificial layer 414 and one dielectric layer 415), are etched through the exposed opening 451a. After etching, the depth of the opening 451a increases downwards, reaching the sacrificial layer 416. It should be noted that "opening 451a reaching the sacrificial layer 416" means that the etching process of the stacked layers is controlled so that the sacrificial layer 414 and the dielectric layer 415 are etched, but the sacrificial layer 416 is not etched. Due to the etching process, a portion of the thickness of the upper surface of the sacrificial layer 416 may be etched; therefore, the opening 451a may reach the upper surface of the sacrificial layer 416 or even the interior of the sacrificial layer 416, but it does not penetrate the sacrificial layer 416. This paragraph describes other opening structures applicable to the present invention.

[0121] This invention does not limit the setting of the predetermined number of layers.

[0122] refer to Figure 4J As shown, after the second photoresist layer 463 is trimmed, the opening 451b adjacent to the opening 451a is also exposed. Figure 4K yes Figure 4J The top view shows three openings 451a and three openings 451b exposed.

[0123] refer to Figure 4L As shown, the stacked layers below are simultaneously etched through the exposed openings 451a and 451b, which represent a predetermined number of layers. After etching, the depth of opening 451a increases downward to reach the sacrificial layer 418; the depth of opening 451b increases downward to reach the sacrificial layer 416.

[0124] Figure 4G-4L This illustrates an example of the first few steps of a trim-etch cycle. As the trim-etch steps continue, the second photoresist layer 463 is progressively trimmed, gradually increasing the number of exposed openings 451, until multiple openings 451 in the first region 420 are utilized to form a shape similar to... Figure 4M The diagram shows a plurality of first contact holes 470. In this example, the leftmost first contact hole 470a extends to the sacrificial layer 419 at the bottom of the stacked layer 410, and the rightmost first contact hole 470b extends to the sacrificial layer 414 at the top of the stacked layer 410. Furthermore, from left to right, the depths of the plurality of first contact holes 470 decrease sequentially, each reaching its predetermined depth in the sacrificial layer. The predetermined depths of the first contact holes 470 in the same column are the same, while the predetermined depths of the first contact holes 470 in different columns are different. The plurality of first contact holes 470 form a stepped, incremental structure along the first direction D1.

[0125] Figure 4M The illustration is for illustrative purposes only. As needed, the predetermined depths of the first contact holes 470 located in different columns among the multiple first contact holes 470 can be the same.

[0126] refer to Figure 4M As shown, after the formation of multiple first contact holes 470, the second photoresist layer 463 is removed, exposing the second contact holes 452.

[0127] refer to Figure 4N As shown, in step S320, the first hard mask layer 450 is removed.

[0128] refer to Figure 4OAs shown, in step S322, an insulating layer is formed on the sidewalls and bottom of the plurality of first contact holes 470 and the plurality of second contact holes 452 simultaneously, and in step S324, sacrificial material is filled inside the insulating layer in the plurality of first contact holes 470 and the plurality of second contact holes 452 simultaneously.

[0129] refer to Figure 4O As shown, taking the first contact hole 470a and the second contact hole 452a as examples, the partial structures of the first contact hole 470a and the second contact hole 452a (circled by dashed lines) are enlarged respectively. The diagram shows an insulating layer 472a formed on the sidewall of the first contact hole 470a, an insulating layer 472b formed at the bottom, and sacrificial material 471 filling the inner sides of insulating layers 472a and 472b. It can be understood that insulating layers 472a and 472b are formed in the same process step and have the same or similar layer thickness. Sacrificial material 471 fills the space inside the first contact hole 470a. Correspondingly, an insulating layer 454a is formed on the sidewall of the second contact hole 452a, an insulating layer 454b is formed at the bottom, and sacrificial material 453 fills the inner sides of insulating layers 454a and 454b.

[0130] It should be noted that in this embodiment, insulating layers are formed simultaneously in the first contact hole 470 and the second contact hole 452. Therefore, insulating layers 472 and 454 are made of the same insulating material. Furthermore, sacrificial material is filled simultaneously in the first contact hole 470 and the second contact hole 452. Therefore, sacrificial materials 471 and 453 are made of the same material.

[0131] In some embodiments, the insulating layers 472 and 454 are made of oxides, and the sacrificial materials 471 and 453 are made of carbon.

[0132] In some embodiments, after step S324, the top of the stacked layer 410 is further ground flat to remove excess sacrificial material from the top during the filling process, so that the top cap layer 440 of the stacked layer 410 has a flat upper surface, such as... Figure 4O As shown.

[0133] refer to Figure 4P As shown, in step S326, a cap layer 441 is formed on top of the semiconductor structure. In some embodiments, the cap layer 441 may be made of the same material as the top cap layer 440, such as the same material as the dielectric layer 413. Figure 4P The same fill pattern is used to represent them.

[0134] Combination Figure 4Q and Figure 4R As shown, where, Figure 4R yes Figure 4QIn the top view, in step S328, a gate line slot 480 is formed along the first direction D1, penetrating the stacked layer 410. The sacrificial layer in the stacked layer 410 is removed through the gate line slot 480, and the void formed after removing the sacrificial layer is filled with conductive material to form a gate layer 481. Figure 4R In the illustrated embodiment, gate line slots 480 are formed between adjacent memory regions. These gate line slots 480 extend to the substrate 401 in a direction perpendicular to the substrate 401. The gate line slots 480 have an elongated shape and are also referred to as slits. The sacrificial layer 411 in the stacked layer 410 can be completely removed through the gate line slots 480. The sacrificial layer 411, which serves as the gate sacrificial layer, is then filled with conductive material through semiconductor processing to form the gate layer 481. This creates a structure in the stacked layer 410 that includes alternating stacked gate layers 481 and dielectric layers 412. For example, the sacrificial layer 411 can be removed using a wet etching process. The material for the gate layer 481 can be a conductive material such as tungsten, cobalt, copper, nickel, etc., or it can be polysilicon, doped silicon, or any combination thereof. In 3D NAND, the gate layer 481 can be a word line of the three-dimensional memory.

[0135] Figure 4T yes Figure 4S Top view, combined Figure 4S and 4T As shown, in step S330, a third photoresist layer 464 is applied to the cap layer 441, and in step S332, the cap layer 441 is patterned using the third photoresist layer 464 to form a plurality of first openings 465 penetrating the cap layer 441 to the top of a plurality of first contact holes, and a plurality of second openings 466 penetrating the cap layer 441 to the top of a plurality of second contact holes. It should be noted that in this step, the first and second contact holes have already had insulating layers formed and sacrificial materials filled in them after steps S322 and S324.

[0136] refer to Figure 4U As shown, in step S334, sacrificial material is removed from multiple first contact holes through multiple first openings 465, and sacrificial material is removed from multiple second contact holes through multiple second openings 466. Figure 4O Similarly, Figure 4U Taking the first contact hole 470a and the second contact hole 452a as examples, the partial structures of the first contact hole 470a and the second contact hole 452a in the dashed circle in the figure are magnified respectively. It can be seen that after step S334, the sacrificial material 471 in the first contact hole 470a is removed, and the insulating layers 472a and 472b are exposed. At the same time, the sacrificial material 453 in the second contact hole 452a is removed, and the insulating layers 454a and 454b are exposed.

[0137] refer to Figure 4V As shown, in step S336, the insulating layer at the bottom of the first contact hole 470 is removed through multiple first openings 465, and the insulating layer at the bottom of multiple second contact holes 452 is removed through multiple second openings 466. Figure 4V Taking the first contact hole 470a and the second contact hole 452a as examples, the partial structures of the first contact hole 470a and the second contact hole 452a (circled by dashed lines in the figure) are magnified respectively. It can be seen that after step S336, the insulating layer 472b at the bottom of the first contact hole 470a is removed, and at the same time, the insulating layer 454b at the bottom of the second contact hole 452a is removed. The method for removing the bottom insulating layer includes dry etching.

[0138] refer to Figure 4W As shown, in step S338, conductive material is filled into a plurality of first contact holes 470 to form a first contact structure 482, and conductive material is filled into a plurality of second contact holes 452 to form a second contact structure 484. In some embodiments, the conductive material includes tungsten. Figure 4W In the embodiment shown, the first contact structure 482 is connected to the corresponding gate layer 481. Since both the gate layer 481 and the first contact structure 482 are made of conductive materials, the gate layer 481 can be electrically connected to external components through the first contact structure 482.

[0139] Combination Figure 4W and Figure 4S As shown, in some embodiments, the critical dimension of the first opening 465 is larger than the critical dimension of the first contact hole 470, and the critical dimension of the second opening 466 is larger than the critical dimension of the second contact hole 452. Therefore, after step S338, a first contact plug 483 with a larger critical dimension is formed on the top of the first contact structure 482, and a second contact plug 485 with a larger critical dimension is formed on the top of the second contact structure 484. In this embodiment, since the first opening 465, the second opening 466, the first contact hole 470, and the second contact hole 452 are all circular holes, the critical dimension can be their inner diameter. According to these embodiments, the first contact structure 482 and the second contact structure 484 have a structural feature that is larger at the top and smaller at the bottom, which is beneficial for the electrical connection between the semiconductor structure and other components.

[0140] according to Figure 4A-4W The embodiment shown simultaneously forms multiple openings corresponding to multiple first contact holes 470 and multiple second contact holes 452, reducing process steps and saving semiconductor manufacturing costs.

[0141] Example 2

[0142] Figures 5A-5EThis is an exemplary process flowchart of the manufacturing method of the memory device according to Embodiment 2 of the present invention. Some steps in Embodiment 2 are similar to those in Embodiment 1, and the foregoing description of Embodiment 1 can be used to explain similar steps in Embodiment 2.

[0143] refer to Figure 5A As shown, in the manufacturing method of this embodiment, in Figure 2 The steps between steps S210 and S220 shown include the following:

[0144] Step S510: Cover the top of the stacked layers with a second hard mask layer;

[0145] Step S512: Cover the second hard mask layer with the fourth photoresist layer;

[0146] Step S514: Pattern the second hard mask layer through the fourth photoresist layer to form a plurality of third openings in the first region, the plurality of third openings penetrating the dielectric layer on top of the stacked layer and reaching the sacrificial layer on top of the stacked layer;

[0147] Step S516: Cover the second hard mask layer with the fifth photoresist layer;

[0148] Step S518: Repeatedly perform the steps of trimming the fifth photoresist layer in the first direction, exposing a predetermined number of third openings, and etching a predetermined number of stacked layers through the exposed third openings, thereby forming a plurality of first contact holes using the plurality of third openings.

[0149] refer to Figure 5B As shown, in some embodiments, after forming a plurality of first contact holes in step S518, the following steps are further included:

[0150] Step S520: Remove the second hard mask layer;

[0151] Step S522: Form an insulating layer on the sidewalls and bottom of the plurality of first contact holes; and

[0152] Step S524: Fill the inner wall of the insulating layer in the plurality of first contact holes with sacrificial material.

[0153] refer to Figure 5C As shown, in some embodiments, step S220 is performed after step S524 to form a top cap layer on top of the semiconductor structure. Following this step, the following steps are also included:

[0154] Step S530: A gate line partition is formed along the first direction, penetrating the stacked layer, the sacrificial layer in the stacked layer is removed through the gate line partition, and the gap formed after removing the sacrificial layer is filled with conductive material to form a gate layer.

[0155] refer to Figure 5DAs shown, in some embodiments, the following steps are performed after step S530: Figure 2 Step S230 shown in the figure includes the following steps:

[0156] Step S532: Form a sixth photoresist layer on the top cap layer;

[0157] Step S534: Pattern the top cap layer through the sixth photoresist layer to simultaneously form multiple openings and multiple second contact holes.

[0158] refer to Figure 5E As shown, in some embodiments, the following steps are performed after step S534: Figure 2 Step S240 shown in the figure includes the following steps:

[0159] Step S536: Remove sacrificial material from multiple first contact holes through multiple openings;

[0160] Step S538: Remove the insulating layer at the bottom of the first contact hole through multiple openings; and

[0161] Step S540: Fill the plurality of first contact holes with conductive material to form a first contact structure, and at the same time fill the plurality of second contact holes with conductive material to form a second contact structure.

[0162] The following is combined Figures 6A to 6U Example 2 will be described.

[0163] Figures 6A-6U This is a schematic diagram of the manufacturing process of the memory device according to Embodiment 2 of the present invention.

[0164] refer to Figure 6A As shown, a semiconductor structure is provided in step S210. The semiconductor structure includes a stacked layer 610, which is composed of alternately stacked sacrificial layers 611 and dielectric layers 612. The stacked layer 610 includes a first region 620 and a second region 630 that are adjacently distributed along a first direction D1. The second region 630 includes a plurality of channel structures 631 that penetrate the stacked layer.

[0165] Step S210 in Example 2 is the same as step S210 in Example 1, and the same content will not be elaborated further.

[0166] refer to Figure 6A As shown, in some embodiments, the semiconductor structure further includes a semiconductor layer 601, which is a substrate.

[0167] refer to Figure 6AAs shown, in some embodiments, prior to the step of forming a plurality of first contact holes, the method further includes forming a plurality of virtual channel structures 621 that penetrate the stacked layer 610 in a first region 620 of the stacked layer 610.

[0168] In some embodiments, after the channel structure 631 and the virtual channel structure 621 are formed, the top of the stacked layer 610 is further planarized. (See reference...) Figure 6A As shown, the top of the stacked layer 610 is a dielectric layer 613, which is thicker than the dielectric layers 612 at other locations in the stacked layer 610.

[0169] refer to Figure 6B As shown, step S510 is performed after step S210, where a second hard mask layer 650 is placed on top of the stacked layer 610. In this embodiment, the second hard mask layer 650 simultaneously covers the first region 620 and the second region 630.

[0170] refer to Figure 6C As shown, in step S512, a fourth photoresist layer 660 is applied to the second hard mask layer 650. To pattern the second hard mask layer 650 in step S514, in step S512, a third pattern 661 is first formed in the fourth photoresist layer 660 in the first region 620. In this embodiment, the fourth photoresist layer 660 simultaneously covers both the first region 620 and the second region 630, and no pattern including openings is formed in the second region 630.

[0171] Figure 6D yes Figure 6C Top view, Figure 6C It is along Figure 6D The side sectional view of line AA' in Embodiment 2. The first direction D1 in Embodiment 2 is the same as the first direction D1 in Embodiment 1. Figure 6D The diagram also shows a channel structure 631 and a virtual channel structure 621 covered by a fourth photoresist layer 660 and a second hard mask layer 650.

[0172] refer to Figure 6E As shown, in step S514, the second hard mask layer 650 is patterned through the fourth photoresist layer 660 to form a plurality of third openings 651 that penetrate the dielectric layer at the top of the stacked layer 610 and reach the sacrificial layer 613 at the top of the stacked layer. It can be understood that the positional distribution of these plurality of third openings 651 and... Figure 6D The openings in the third pattern 661 shown are distributed in the same position.

[0173] refer to Figure 6FAs shown, in step S516, a fifth photoresist layer 662 is applied to the second hard mask layer 650. The fifth photoresist layer 662 simultaneously covers the first region 620 and the second region 630.

[0174] In the cyclically executed trimming-etching step of step S518, Figure 6F The image shows the initial step of this cycle, where the fifth photoresist layer 662 is trimmed in the first direction D1. (Combined with...) Figure 6F Top view Figure 6G As shown, the third opening 651a in the leftmost column is exposed.

[0175] refer to Figure 6H As shown, a predetermined number of stacked layers, namely two layers (one sacrificial layer 613 and one dielectric layer 614), are etched through the exposed third opening 651a. After etching, the depth of the third opening 651a increases downward to reach the sacrificial layer 615.

[0176] refer to Figure 6I As shown, after the fifth photoresist layer 662 is trimmed, the third opening 651b adjacent to the third opening 651a is also exposed. Figure 6J yes Figure 6I The top view shows three third openings 651a and three third openings 651b exposed.

[0177] refer to Figure 6K As shown, the stacked layers below are simultaneously etched through the exposed third openings 651a and 651b, which represent a predetermined number of layers. After etching, the depth of the third opening 651a increases downward to reach the sacrificial layer 617; the depth of the third opening 651b increases downward to reach the sacrificial layer 615.

[0178] Figure 6F-6K The diagram illustrates the first few steps of a trimming-etching cycle. As the trimming-etching steps continue, the fifth photoresist layer 662 is gradually trimmed, progressively increasing the number of exposed third openings 651, until multiple third openings 651 in the first region 620 are used to form a shape similar to... Figure 6L The diagram shows a plurality of first contact holes 670. Among them, the leftmost first contact hole 670a is shown, the bottom of which reaches the bottommost sacrificial layer 618 in the stack, and the rightmost first contact hole 670b is shown, the bottom of which reaches the topmost sacrificial layer 613 in the stack.

[0179] It should be noted that the trimming-etching cycle step in Embodiment 2 is similar to the trimming-etching cycle step in Embodiment 1. The relevant content mentioned above can be used to explain the process of forming multiple first contact holes 670 in Embodiment 2. The same content will not be elaborated here.

[0180] refer to Figure 6M As shown, step S520 is performed after step S518 to remove the second hard mask layer 650. It can be understood that after the formation of the plurality of first contact holes 670, the fifth photoresist layer 662 is removed, and then the second hard mask layer 650 is removed.

[0181] refer to Figure 6M As shown, in step S522, an insulating layer is formed on the sidewalls and bottom of the plurality of first contact holes 670; and in step S524, a sacrificial material is filled into the inner wall of the insulating layer in the plurality of first contact holes 670.

[0182] Taking the leftmost first contact hole 670a as an example, the structure of the first contact hole 670a in the dashed circle in the figure is enlarged, showing the insulating layer 672a formed on the side wall of the first contact hole 670a, the insulating layer 672b formed at the bottom, and the sacrificial material 671 filled inside the insulating layers 672a and 672b.

[0183] In some embodiments, after step S524, the top of the stacked layer 610 is further ground flat to remove excess sacrificial material from the top during the filling process, so that the top of the stacked layer 610 has a flat upper surface, such as... Figure 6M As shown.

[0184] refer to Figure 6N As shown, step S220 is performed after step S524, that is, a top capping layer 640 is formed on top of the semiconductor structure. This top also refers to the current top of the stacked layer 610. The material of the top capping layer 640 is the same as that of the top capping layer 440 in Embodiment 1, and will not be described again.

[0185] refer to Figure 6O and 6P ,in, Figure 6P yes Figure 6O In the top view, in step S530, a gate line slot 680 is formed along the first direction D1, penetrating the stacked layer 610. The sacrificial layer 611 in the stacked layer 610 is removed through the gate line slot 680, and the gap formed after removing the sacrificial layer 611 is filled with conductive material to form the gate layer 681.

[0186] Step S530 is similar to step S328 in Embodiment 1, and will not be elaborated here.

[0187] In some embodiments, execution is performed after step S530. Figure 2 Step S230 shown includes steps S532-S534.

[0188] refer to Figure 6QAs shown, in step S532, a sixth photoresist layer 641 is formed on the top cap layer 640. In step S534, the top cap layer 640 is patterned through the sixth photoresist layer 641 to simultaneously form the plurality of openings 673 and the plurality of second contact holes 674 described in step S230. Clearly, the plurality of openings 673 penetrate the top cap layer 640 and correspond to the plurality of first contact holes 670, while the plurality of second contact holes 674 penetrate the top cap layer 640 and reach the top of the plurality of channel structures 631. In this step, the first contact holes 670 have been formed with an insulating layer and filled with sacrificial material.

[0189] Figure 6R yes Figure 6Q Top view, combined Figure 6R and 6Q Multiple second contact holes 674 correspond one-to-one with the channel structure 631. In this embodiment, in each finger storage area, the channel structure 631 has multiple rows along the first direction D1 and multiple columns along the second direction D2.

[0190] In some embodiments, execution is performed after step S534. Figure 2 Step S240 shown includes steps S536-S540.

[0191] refer to Figure 6S As shown, in step S536, sacrificial material in multiple first contact holes 670 is removed through multiple openings 673. Taking the leftmost first contact hole 670a as an example, a partial structure of the first contact hole 670a in the dashed circle in the figure is enlarged, showing that after step S536, the sacrificial material 671 in the first contact hole 670a is removed, and the insulating layers 672a and 672b on the sidewalls and bottom are retained.

[0192] refer to Figure 6T As shown, in step S538, the insulating layer at the bottom of the first contact hole 670 is removed through multiple openings 673. Taking the leftmost first contact hole 670a as an example, the partial structure of the first contact hole 670a in the dashed circle in the figure is enlarged, showing that after step S538, the insulating layer 672b at the bottom of the first contact hole 670a is removed, leaving the insulating layer 672a on the sidewall.

[0193] refer to Figure 6UAs shown, in step S540, conductive material is filled into a plurality of first contact holes 670 to form a first contact structure 691, and conductive material is filled into a plurality of second contact holes 674 to form a second contact structure 692. In some embodiments, the critical dimension of the opening 673 is larger than the critical dimension of the first contact hole 670, thus forming a first contact plug 693 with a larger critical dimension on the top of the first contact structure 691. In this embodiment, the first contact structure 691 has a structural feature that is larger at the top and smaller at the bottom, which is beneficial for the electrical connection between the semiconductor structure and other components.

[0194] according to Figure 6A-6U The illustrated embodiment simultaneously forms multiple openings corresponding to multiple first contact holes and multiple second contact holes, reducing process steps and saving semiconductor manufacturing costs.

[0195] According to the method for manufacturing a memory device of the present invention, the process steps of forming multiple openings corresponding to multiple first contact holes in a first region and multiple second contact holes in a second region are combined, and multiple contact structures with a stepped form are directly formed in the stacked layer, eliminating the need for the original step forming method, and having one or more of the following beneficial effects:

[0196] (1) It saves process steps and reduces costs;

[0197] (2) It ensures the uniformity of film distribution between the step area and the core storage area, and solves various stress problems caused by film changes;

[0198] (3) The process is highly flexible, which improves the effective utilization rate of wafer area and enhances product performance.

[0199] Figure 7 This is a cross-sectional structural schematic diagram of the memory device according to Embodiment 1 of the present invention. The memory device 700 can be manufactured by Embodiment 1 of the manufacturing method described above. Therefore, the description of Embodiment 1 of the manufacturing method can be used to describe the memory device 700.

[0200] refer to Figure 7As shown, the memory device 700 includes a stacked structure 710, which includes alternately stacked gate layers 711 and dielectric layers 712. The stacked structure 710 includes a first region 720 and a second region 730 distributed adjacently along a first direction D1. The second region 730 includes a plurality of channel structures 731 penetrating the stacked structure 710; a plurality of first contact structures 722 located in the first region 720, each first contact structure 722 penetrating several layers in the stacked structure 710 and contacting a gate layer at a predetermined depth; and a plurality of second contact structures 732 located in the second region 730, each second contact structure 732 contacting the top end of the channel structure 731.

[0201] In some embodiments, the first region 720 includes a word line connection region, and the second region 730 includes a core storage region.

[0202] In some embodiments, the first region 720 includes a plurality of virtual channel structures 721 that extend through the stacked structure 710.

[0203] In some embodiments, the memory device 700 further includes at least one gate line slot (not shown) extending along a first direction D1 and penetrating the stacked structure 710.

[0204] In some embodiments, the memory device 700 further includes a top cover layer 740 formed over the stacked structure 710, the top cover layer 740 including a first contact plug 723 in contact with the first contact structure 722, the critical dimension of the first contact plug 723 being larger than the critical dimension of the first contact structure 722.

[0205] In some embodiments, the top cover 740 also includes a second contact plug 733 that contacts the second contact structure 732, the critical dimension of the second contact plug 733 being larger than the critical dimension of the second contact structure 722.

[0206] In some embodiments, the memory device 700 further includes a semiconductor layer 701, and a stacked structure 710 covers the semiconductor layer 701.

[0207] Figure 8This is a cross-sectional structural schematic diagram of the memory device according to Embodiment 2 of the present invention. The memory device 800 can be manufactured using Embodiment 2 of the manufacturing method described above; therefore, the description of Embodiment 2 of the manufacturing method can be used to describe the memory device 800. The differences between memory device 800 and memory device 700 include, but are not limited to, the critical dimension of the first contact plug 823 of memory device 800 being larger than the critical dimension of the first contact structure 822; the top of the second contact structure 832 not including the second contact plug 733 with a larger critical dimension in memory device 700; the bottom 723a of the first contact plug 723 of memory device 700 being higher than the top 721a of the virtual channel structure 721, and the height difference between them being equal to the distance between the bottom of the second contact plug 733 and the top of the channel structure 731; and the bottom 823a of the first contact plug 823 of memory device 800 being substantially flush with the top 821a of the virtual channel structure 821.

[0208] In some embodiments, the memory device is a 3D NAND memory.

[0209] The memory devices provided by some embodiments of the present invention have one or more advantages, such as low manufacturing cost, saving wafer area, and improving product density and product performance, because they do not require the use of step forming methods; and further reduce costs by combining the steps of forming multiple openings corresponding to multiple first contact holes and multiple second contact holes; the first contact structure and / or the second contact structure have a larger head size, which is beneficial for the memory device to establish an electrical connection with the outside.

[0210] Figure 9 This is a block diagram of a system having a memory device according to an embodiment of the present invention. (See reference) Figure 9 As shown, the system 900 includes a memory system 902. The memory system 902 has one or more memory devices 904 and a memory controller 906. The memory device 904 is any of the memory devices described above and is configured to store data. The memory controller 906 is coupled to the memory device 904 and is configured to control the memory device 904.

[0211] refer to Figure 9 As shown, in some embodiments, the system 900 also includes a host 908 coupled to the memory controller 906.

[0212] System 900 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (having storage therein). Host 908 may be a processor of the electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). Host 908 may be configured to send or receive data to and from memory device 904.

[0213] The memory device 904 can be any memory device disclosed herein. In some embodiments, each memory device 904 includes an array of memory cells and peripheral circuitry of the array of memory cells, the array of memory cells and the peripheral circuitry being stacked on top of each other in different planes.

[0214] According to some embodiments, a memory controller 906 is coupled to a memory device 904 and a host 908 and is configured to control the memory device 904. The memory controller 906 can manage data stored in the memory device 904 and communicate with the host 908. In some embodiments, the memory controller 906 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the memory controller 906 is designed to operate in a high duty cycle environment, such as an SSD or embedded multi-media card (eMMC) used as a data storage device in a mobile device such as a smartphone, tablet, laptop, etc. The memory controller 906 can be configured to control the operation of the memory device 904, such as read, erase, and program operations. In some embodiments, the memory controller 906 is configured to control an array of memory cells via first and second peripheral circuitry. The memory controller 906 may also be configured to manage various functions relating to data stored in or to be stored in the memory device 904, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 906 is further configured to process error correction codes (ECCs) relating to data read from or written to the memory device 904. The memory controller 906 may also perform any other appropriate functions, such as formatting the memory device 904. The memory controller 906 may communicate with external devices (e.g., host 908) according to a specific communication protocol.For example, the memory controller 906 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, peripheral component interconnect (PCI), high-speed PCI (PCI-express, PCI-E), advanced technology attachment (ATA), serial ATA, parallel ATA, small computer small interface (SCSI), enhanced small disk interface (ESDI), integrated drive electronics (IDE), and Firewire.

[0215] The memory controller 906 and one or more memory devices 904 can be integrated into various types of memory devices, for example, included in the same package (such as a universal flash storage (UFS) package or an eMMC package). That is, the memory system 902 can be implemented and packaged into different types of end electronic products. Figure 10A In one example shown, the memory controller 906 and a single memory device 904 can be integrated into the memory card 1002. The memory card 1002 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1002 may further include a connection between the memory card 1002 and a host computer (e.g., Figure 9 The memory card connector 1004 is coupled to the host 908. In such a... Figure 10B In another example shown, a memory controller 906 and multiple memory devices 904 can be integrated into an SSD 1006. The SSD 1006 may further include interfaces for connecting the SSD 1006 to a host computer (e.g., ...). Figure 9 The SSD connector 1008 is coupled to the host 908 in the memory card 1002. In some embodiments, the storage capacity and / or operating speed of the SSD 1006 is higher than that of the memory card 1002.

[0216] Although the present invention has been described with reference to specific embodiments, those skilled in the art should recognize that the above embodiments are merely illustrative of the invention, and various equivalent changes or substitutions can be made without departing from the spirit of the invention. Therefore, any changes or modifications to the above embodiments within the essential spirit of the invention will fall within the scope of the claims of this application.

Claims

1. A method for manufacturing a memory device, comprising: A semiconductor structure is provided, the semiconductor structure including a stacked layer, the stacked layer including alternately stacked sacrificial layers and dielectric layers, the stacked layer including a first region and a second region distributed adjacent to each other along a first direction, the second region including a plurality of channel structures through the stacked layer; A top cover layer is formed on top of the stacked layers; Forming a plurality of openings penetrating the top cap layer in the first region, and simultaneously forming a plurality of second contact holes penetrating the top cap layer and reaching the top of the plurality of channel structures in the second region, includes: covering the top cap layer with a first hard mask layer; covering the first hard mask layer with a first photoresist layer; and patterning the first hard mask layer through the first photoresist layer to form the plurality of second contact holes and a plurality of openings penetrating the top cap layer and reaching the top of the stacked layer, wherein the plurality of openings correspond to a plurality of first contact holes, and each first contact hole penetrates several layers in the stacked layer and reaches a sacrificial layer at a respective predetermined depth; A first contact structure is formed by filling each of the first contact holes with conductive material, and a second contact structure is formed by filling each of the second contact holes with conductive material.

2. The manufacturing method as described in claim 1, characterized in that, After the steps of forming the plurality of second contact holes and the plurality of openings in the sacrificial layer that penetrate the top cap layer to reach the top of the stacked layers, the method further includes: A second photoresist layer is coated on the first hard mask layer; and The steps of trimming the second photoresist layer in the first direction, exposing a predetermined number of the openings, and etching a predetermined number of stacked layers through the exposed openings are performed cyclically to form the plurality of first contact holes using the plurality of openings.

3. The manufacturing method as described in claim 2, characterized in that, After forming the plurality of first contact holes, the method further includes: Remove the first hard mask layer; Simultaneously, an insulating layer is formed on the sidewalls and bottom of the plurality of first contact holes and the plurality of second contact holes; Simultaneously, sacrificial material is filled inside the insulating layer in the plurality of first contact holes and the plurality of second contact holes; A capping layer is formed on top of the semiconductor structure; A gate line slot is formed along the first direction, penetrating the stacked layer, the sacrificial layer in the stacked layer is removed through the gate line slot, and a conductive material is filled into the gap formed after the sacrificial layer is removed to form a gate layer.

4. The manufacturing method as described in claim 3, characterized in that, The steps of forming a first contact structure in each of the first contact holes and forming a second contact structure in each of the second contact holes include: A third photoresist layer is applied to the cap layer; The cap layer is patterned through the third photoresist layer to form a plurality of first openings that penetrate the cap layer to reach the top of the plurality of first contact holes, and a plurality of second openings that penetrate the cap layer to reach the top of the plurality of second contact holes; The sacrificial material in the plurality of first contact holes is removed through the plurality of first openings, and the sacrificial material in the plurality of second contact holes is removed through the plurality of second openings. The insulating layer at the bottom of the first contact hole is removed through the plurality of first openings, and the insulating layer at the bottom of the plurality of second contact holes is removed through the plurality of second openings; and Conductive material is filled into the plurality of first contact holes to form the first contact structure, and conductive material is filled into the plurality of second contact holes to form the second contact structure.

5. The manufacturing method as described in claim 4, characterized in that, The critical dimension of the first opening is greater than the critical dimension of the first contact hole, and the critical dimension of the second opening is greater than the critical dimension of the second contact hole.

6. The manufacturing method as described in claim 1, characterized in that, Prior to the step of forming a top cap layer on top of the stacked layers, the method further includes: forming a plurality of virtual channel structures through the stacked layers in a first region of the stacked layers.

7. The manufacturing method as described in claim 1, characterized in that, Prior to the step of forming a top cap layer on top of the stacked layers, the method further includes: A second hard mask layer is placed on top of the stacked layers; A fourth photoresist layer is applied over the second hard mask layer; The second hard mask layer is patterned by the fourth photoresist layer to form a plurality of third openings in the first region, the plurality of third openings penetrating the dielectric layer on top of the stacked layer and reaching the sacrificial layer on top of the stacked layer; A fifth photoresist layer is coated on the second hard mask layer; and The steps of trimming the fifth photoresist layer in the first direction, exposing a predetermined number of the third openings, and etching a predetermined number of stacked layers through the exposed third openings are performed cyclically to form the plurality of first contact holes using the plurality of third openings.

8. The manufacturing method as described in claim 7, characterized in that, Following the step of forming the plurality of first contact holes: Remove the second hard mask layer; An insulating layer is formed on the sidewalls and bottom of the plurality of first contact holes; and The inner walls of the insulating layer in the plurality of first contact holes are filled with sacrificial material.

9. The manufacturing method as described in claim 8, characterized in that, The step of forming the top cap layer on top of the semiconductor structure includes: forming a gate line slot through the stacked layer along the first direction, removing the sacrificial layer in the stacked layer through the gate line slot, and filling the void formed after removing the sacrificial layer with a conductive material to form a gate layer.

10. The manufacturing method as described in claim 9, characterized in that, The steps of forming a plurality of openings penetrating the top cover layer in the first region and simultaneously forming a plurality of second contact holes penetrating the top cover layer and reaching the top of the plurality of channel structures in the second region include: A sixth photoresist layer is formed on the top cover layer; The top cap layer is patterned using the sixth photoresist layer to simultaneously form the plurality of openings and the plurality of second contact holes.

11. The manufacturing method as described in claim 10, characterized in that, The steps of forming a first contact structure in each of the first contact holes and forming a second contact structure in each of the second contact holes include: The sacrificial material in the plurality of first contact holes is removed through the plurality of openings; The insulating layer at the bottom of the first contact hole is removed through the plurality of openings; and Conductive material is filled into the plurality of first contact holes to form the first contact structure, and conductive material is filled into the plurality of second contact holes to form the second contact structure.

12. The manufacturing method as described in claim 10, characterized in that, The critical dimension of the opening is greater than the critical dimension of the first contact hole.

13. The manufacturing method as described in claim 7, characterized in that, Prior to the step of forming the plurality of first contact holes, the method further includes: forming a plurality of virtual channel structures through the stacked layer in a first region of the stacked layer.

14. The manufacturing method as described in claim 1, characterized in that, The first region includes a word line connection area, and the second region includes a core storage area.

15. A memory device, characterized in that, include: A stacked structure, the stacked structure comprising alternately stacked gate layers and dielectric layers, the stacked structure comprising a first region and a second region distributed adjacent to each other along a first direction, the second region comprising a plurality of channel structures penetrating the stacked structure; Multiple first contact structures are located in the first region, and each first contact structure penetrates several layers in the stacked structure and contacts a gate layer at a predetermined depth respectively. Multiple second contact structures are located in the second region, and each second contact structure contacts the top end of the channel structure; The plurality of first contact structures and the plurality of second contact structures are coplanar on the top surface of the stacked structure.

16. The memory device as claimed in claim 15, characterized in that, The first region includes a word line connection area, and the second region includes a core storage area.

17. The memory device as claimed in claim 15, characterized in that, The first region includes multiple virtual channel structures that run through the stacked structure.

18. The memory device as claimed in claim 15, characterized in that, It also includes at least one grid line slot that extends along the first direction and penetrates the stacked structure.

19. The memory device as claimed in claim 15, characterized in that, It also includes a top cover layer formed above the stacked structure, wherein the top cover layer includes a first contact plug that contacts the first contact structure, the critical dimension of the first contact plug being larger than the critical dimension of the first contact structure.

20. The memory device as claimed in claim 15, characterized in that, It also includes a top cover layer formed above the stacked structure, wherein the top cover layer includes a second contact plug that contacts the second contact structure, the critical dimension of the second contact plug being larger than the critical dimension of the second contact structure.

21. The memory device as claimed in claim 15, characterized in that, It also includes a semiconductor layer, on which the stacked structure covers the semiconductor layer.

22. A system, characterized in that, Includes a memory device as described in any one of claims 15-21, configured to store data, and a memory controller coupled to the memory device and configured to control the memory device.

23. The system as described in claim 22, characterized in that, It also includes a host coupled to the memory controller.

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