A method for fabricating a semiconductor structure and the semiconductor structure.

Abstract

This disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself. The method for fabricating the semiconductor structure includes: providing a substrate, the substrate including a cell array region and a peripheral circuit region; forming a bit line material layer on the cell array region and etching the bit line material layer to form a bit line structure extending along a first direction; forming a gate material layer on the peripheral circuit region and etching the gate material layer to form a peripheral gate structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a method for preparing a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] Semiconductor memories, such as Dynamic Random Access Memory (DRAM), typically include a cell array region for storing data and a peripheral circuit region surrounding the cell array region. Currently, bit line structures and peripheral gate structures tend to be formed simultaneously in the cell array region and peripheral circuit region of the semiconductor memory, respectively. However, this makes it difficult to individually adjust the performance of the cell array region and the peripheral circuit region. Summary of the Invention

[0003] In view of the above, this disclosure provides a method for preparing a semiconductor structure and a semiconductor structure.

[0004] According to a first aspect of the present disclosure, a method for fabricating a semiconductor structure is provided, the method comprising:

[0005] A substrate is provided, the substrate comprising a cell array region and a peripheral circuit region;

[0006] A bit line material layer is formed on the cell array region, and the bit line material layer is etched to form a bit line structure extending along a first direction;

[0007] A gate material layer is formed on the peripheral circuit region, and the gate material layer is etched to form a peripheral gate structure.

[0008] In some embodiments, forming a bit line material layer on the cell array region and etching the bit line material layer to form a bit line structure extending along a first direction includes:

[0009] A bit line material layer is formed on the cell array region and the peripheral circuit region;

[0010] Etching removes the bit line material layer on the peripheral circuit region;

[0011] The bit line material layer on the cell array region is etched to form a bit line structure extending along a first direction.

[0012] In some embodiments, forming a gate material layer on the peripheral circuit region and etching the gate material layer to form a peripheral gate structure includes:

[0013] A gate material layer is formed on the cell array region and the peripheral circuit region;

[0014] Etching removes the gate material layer on the cell array region;

[0015] The gate material layer on the peripheral circuit region is etched to form a peripheral gate structure.

[0016] In some embodiments, it also includes:

[0017] Before forming the bit line structure, a word line structure extending along a second direction is formed within the substrate of the cell array region, wherein the first direction and the second direction are perpendicular to each other; the word line structure includes an isolation barrier, the top surface of which is higher than the top surface of the substrate;

[0018] A filler layer is formed on the substrate; the top surface of the filler layer is flush with the top surface of the isolation fence.

[0019] In some embodiments, it also includes:

[0020] After the fill layer is formed, a first spacer layer is formed within the fill layer and the substrate in the cell array region; the first spacer layer encloses the sidewall of the portion of the bit line structure located below the top surface of the fill layer.

[0021] In some embodiments, forming the first spacer layer includes:

[0022] The filling layer and the substrate of the cell array region are etched to form a first contact hole;

[0023] A first sub-spacer layer, a second sub-spacer layer, and a third sub-spacer layer are formed sequentially within the first contact hole;

[0024] The materials of the first sub-spacer layer and the third sub-spacer layer comprise nitrides, and the material of the second sub-spacer layer comprises oxides.

[0025] In some embodiments, forming the bit line structure includes:

[0026] A bit line material layer is formed in the first contact hole after the formation of the third sub-spacer layer and on the surface of the filler layer;

[0027] A bit line mask layer, a bit line insulating layer, and a bit line photoresist layer are sequentially formed on the bit line material layer;

[0028] The bit line photoresist layer is patterned to form a patterned bit line photoresist layer;

[0029] Based on the patterned bit line photoresist layer, the bit line insulating layer and the bit line mask layer are etched to form the patterned bit line insulating layer and the patterned bit line mask layer; the patterned bit line insulating layer and the patterned bit line mask layer extend along a first direction and expose a portion of the bit line material layer;

[0030] A bit line dielectric layer prelayer is formed on the sidewalls and top surface of the patterned bit line insulating layer and the patterned bit line mask layer, as well as on the top surface of the exposed portion of the bit line material layer;

[0031] The bit line dielectric layer pre-layer is etched away in part, leaving the bit line dielectric layer pre-layer located on the sidewalls of the patterned bit line insulating layer and the patterned bit line mask layer to form a bit line dielectric layer extending in a first direction.

[0032] Remove the patterned bit line insulating layer and the patterned bit line mask layer, and use the bit line dielectric layer as a mask to etch the bit line material layer on the surface of the filling layer to form a bit line structure extending along the first direction.

[0033] In some embodiments, it also includes:

[0034] After the bit line structure is formed, a second spacer layer is formed on the filler layer; the second spacer layer covers the sidewall of the portion of the bit line structure above the top surface of the filler layer.

[0035] In some embodiments, forming the second spacer layer includes:

[0036] On the sidewall of the portion of the bit line structure above the top surface of the filling layer, a fourth sub-spacer layer, a fifth sub-spacer layer, and a sixth sub-spacer layer are formed sequentially.

[0037] The materials of the fourth and sixth sub-spacer layers comprise nitrides, and the material of the fifth sub-spacer layer comprises oxides.

[0038] In some embodiments, bitline structures extending in a first direction and isolation fences extending in a second direction are arranged in an intersecting pattern to form an array of node contact areas.

[0039] The method further includes:

[0040] After forming the bit line structure, the filling layer and the substrate of the node contact area are etched to form node contact holes;

[0041] A node contact plug is formed inside the node contact hole.

[0042] According to a second aspect of the present disclosure, a semiconductor structure is provided, comprising:

[0043] The substrate includes a unit array region and a peripheral circuit region;

[0044] The bitline structure is located on the cell array region and extends along the first direction;

[0045] A peripheral gate structure is located on the peripheral circuit region;

[0046] A word line structure is located within the substrate of the cell array region, the word line structure including an isolation fence, the top surface of the isolation fence being higher than the top surface of the substrate.

[0047] In some embodiments, it also includes:

[0048] A filler layer is located on the substrate; the top surface of the filler layer is flush with the top surface of the isolation fence.

[0049] In some embodiments, it also includes:

[0050] A first spacer layer is located within the fill layer and the substrate of the cell array region; the first spacer layer encloses the sidewall of the bit line structure below the top surface of the fill layer;

[0051] The first spacer layer includes a first sub-spacer layer, a second sub-spacer layer, and a third sub-spacer layer arranged sequentially;

[0052] The materials of the first sub-spacer layer and the third sub-spacer layer comprise nitrides, and the material of the second sub-spacer layer comprises oxides.

[0053] In some embodiments, it also includes:

[0054] A second spacer layer is located on the filler layer; the second spacer layer encloses the sidewall of the portion of the bit line structure above the top surface of the filler layer;

[0055] The second spacer layer includes a fourth sub-spacer layer, a fifth sub-spacer layer, and a sixth sub-spacer layer arranged sequentially;

[0056] The materials of the fourth and sixth sub-spacer layers comprise nitrides, and the material of the fifth sub-spacer layer comprises oxides.

[0057] In some embodiments, the character line structure extends along a second direction, wherein the first direction and the second direction are perpendicular to each other;

[0058] The bit line structure is located on the isolation fence.

[0059] In some embodiments, bitline structures extending in a first direction and isolation fences extending in a second direction are arranged in an intersecting pattern to form an array of node contact areas.

[0060] The semiconductor structure also includes:

[0061] A node contact plug is located within the fill layer and the substrate of the node contact area.

[0062] In this embodiment of the disclosure, by fabricating the bit line structure of the unit array region and the peripheral gate structure of the peripheral circuit region separately, different materials can be used to fabricate the bit line structure and the peripheral gate structure. Different materials can result in different threshold voltages. For example, ion doping can be performed separately when forming the bit line structure or the peripheral gate structure. This is more conducive to adjusting the threshold voltage of the unit array region and the peripheral circuit region separately, and adjusting the voltage of one region will not affect the performance of the other region. Attached Figure Description

[0063] To more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0064] Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to embodiments of this disclosure;

[0065] Figures 2a to 2w This is a schematic diagram of the semiconductor structure during the fabrication process provided in the embodiments of this disclosure;

[0066] Figures 3a to 3e This is a schematic diagram of the structure of the first spacer layer during the fabrication process, as provided in an embodiment of this disclosure.

[0067] Figure 4 A top view of a semiconductor structure provided in an embodiment of this disclosure;

[0068] Figure 5 The semiconductor structure provided in the embodiments of this disclosure is along Figure 4 A sectional view along the A-A' direction;

[0069] Figure 6 The semiconductor structure provided in the embodiments of this disclosure is along Figure 4 A cross-sectional view along the B-B' direction.

[0070] Explanation of reference numerals in the attached figures:

[0071] 10-Substrate; 11-Unit array region; 12-Peripheral circuit region; 101-Isolation structure; 102-Unit active region; 103-Peripheral active region;

[0072] 200 - Bit line material layer; 20 - Bit line structure; 21 - Bit line mask layer; 22 - Bit line insulating layer; 23 - Bit line photoresist layer; 210 - Patterned bit line mask layer; 220 - Patterned bit line insulating layer; 230 - Patterned bit line photoresist layer; 24' - Bit line dielectric layer pre-layer; 24 - Bit line dielectric layer;

[0073] 300 - Gate material layer; 30 - Peripheral gate structure; 301 - Gate insulating material layer; 302 - First gate conductive material layer; 303 - Second gate conductive material layer; 31 - Gate insulating layer; 32 - First gate conductive layer; 33 - Second gate conductive layer; 34 - Sidewall;

[0074] 40 - Character line structure; 41 - Isolation fence; 401 - Character line groove; 402 - Patterned character line mask layer;

[0075] 50 - Filler layer;

[0076] 61-First spacer layer; 611-First sub-spacer layer; 612-Second sub-spacer layer; 613-Third sub-spacer layer; 601-First contact hole; 611'-First sub-spacer layer pre-layer; 612'-Second sub-spacer layer pre-layer; 613'-Third sub-spacer layer pre-layer; 62-Second spacer layer; 621-Fourth sub-spacer layer; 622-Fifth sub-spacer layer; 623-Sixth sub-spacer layer;

[0077] 701 - Node contact hole; 70 - Node contact plug;

[0078] 81 - First mask layer; 82 - First photoresist layer;

[0079] 91' - Pre-layer of peripheral gate dielectric layer; 91 - Peripheral gate dielectric layer; 92 - Peripheral gate mask layer; 93 - Peripheral gate insulating layer; 940 - Patterned peripheral gate photoresist layer. Detailed Implementation

[0080] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0081] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0082] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0083] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0084] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0085] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0086] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0087] This disclosure provides a method for fabricating a semiconductor structure; please refer to the appendix for details. Figure 1 As shown in the figure, the method includes the following steps:

[0088] Step 101: Provide a substrate, the substrate including a cell array region and a peripheral circuit region;

[0089] Step 102: Form a bit line material layer on the cell array region, and etch the bit line material layer to form a bit line structure extending along the first direction;

[0090] Step 103: Form a gate material layer on the peripheral circuit area, and etch the gate material layer to form a peripheral gate structure.

[0091] In this embodiment of the disclosure, by fabricating the bit line structure of the unit array region and the peripheral gate structure of the peripheral circuit region separately, different materials can be used to fabricate the bit line structure and the peripheral gate structure. Different materials can result in different threshold voltages. For example, ion doping can be performed separately when forming the bit line structure or the peripheral gate structure. This is more conducive to adjusting the threshold voltage of the unit array region and the peripheral circuit region separately, and adjusting the voltage of one region will not affect the performance of the other region.

[0092] The method for preparing the semiconductor structure provided in this disclosure will be further described in detail below with reference to specific embodiments.

[0093] Figures 2a to 2w This is a schematic diagram of the semiconductor structure provided in the embodiments of this disclosure during the fabrication process. Figures 3a to 3e This is a schematic diagram illustrating the structure of the first spacer layer during its fabrication process, as provided in an embodiment of this disclosure. It should be explained that... Figures 2a to 2d Figure (1) shows the route along Figures 2a to 2d (2) is a cross-sectional view along the A-A' direction in the figure. Figures 2e to 2w Figure (1) shows the route along Figures 2e to 2w (2) is a cross-sectional view along the B-B' direction.

[0094] First, see Figure 2a Step 101 is performed, providing a substrate 10, which includes a unit array region 11 and a peripheral circuit region 12.

[0095] In one embodiment, the substrate 10 may be a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, SOI (silicon on insulator) substrate, or GOI (germanium on insulator) substrate, etc. It may also be a substrate including other elemental semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (e.g., gallium nitride substrate or gallium arsenide substrate, etc.), and may also be a stacked structure, such as Si / SiGe, etc., or other epitaxial structures, such as SGOI (germanium on silicon insulator), etc.

[0096] See Figure 2a The substrate 10 includes a unit array region 11 for forming a device structure and a peripheral circuit region 12 located around the unit array region 11.

[0097] An isolation structure 101 can be formed in the substrate 10 of the unit array region 11 and the peripheral circuit region 12. The isolation structure 101 defines a unit active region 102 in the substrate of the unit array region 11 and a peripheral active region 103 in the substrate of the peripheral circuit region 12. The material of the isolation structure 101 may include one or more of oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), and oxynitrides (e.g., silicon oxynitride). The isolation structure 101 may consist of one or more of the following: a single layer comprising one insulating layer, a double layer comprising two insulating layers, or a multilayer comprising at least three insulating layers.

[0098] Next, see Figures 2b to 2d The method further includes: forming a word line structure 40 extending in a second direction within the substrate 10 of the cell array region 11 before forming the bit line structure, wherein the first direction and the second direction are perpendicular to each other; the word line structure 40 includes an isolation barrier 41, the top surface of the isolation barrier 41 being higher than the top surface of the substrate 10; forming a fill layer 50 on the substrate 10; the top surface of the fill layer 50 being flush with the top surface of the isolation barrier 41.

[0099] Specifically, see first. Figure 2b First, a word line mask layer (not shown) can be grown on the upper surface of the substrate 10. Then, this word line mask layer is patterned to form a patterned word line mask layer 402, displaying the pattern of the word line trenches 401 to be etched. The word line mask layer can be patterned using photolithography. The word line mask layer can be a photoresist mask or a hard mask patterned based on a photolithography mask. When the word line mask layer is a photoresist mask, it is patterned through steps such as exposure, development, and resist removal. Then, word line trenches 401 of a certain depth are etched according to the pattern of the word line trenches to be etched.

[0100] Next, see Figure 2c A word line structure 40 is formed within the word line groove 401. The material of the word line structure 40 includes tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, metal alloys, or any combination thereof.

[0101] See also Figure 2c The word line structure 40 further includes an isolation barrier 41, the top surface of which is higher than the top surface of the substrate 10. The material of the isolation barrier 41 includes, but is not limited to, silicon nitride.

[0102] Next, see Figure 2d A filling layer 50 is formed on the substrate 10; the top surface of the filling layer 50 is flush with the top surface of the isolation fence 41.

[0103] Specifically, a filler layer 50 is formed between two adjacent word line structures 40 to fill the gaps between the protruding substrate portions of the isolation barriers 41 of the two adjacent word lines. The material of the filler layer 50 includes, but is not limited to, oxides, such as silicon oxide.

[0104] Next, see Figures 2e to 2f After the filling layer 50 is formed, a first spacer layer 61 is formed in the filling layer 50 and the substrate 10 of the cell array region 11; the first spacer layer 61 encloses the sidewall of the bit line structure 20 located below the top surface of the filling layer 50.

[0105] In one embodiment, forming the first spacer layer 61 includes: etching the filling layer 50 and the substrate 10 of the cell array region 11 to form a first contact hole 601; and sequentially forming a first sub-spacer layer 611, a second sub-spacer layer 612, and a third sub-spacer layer 613 within the first contact hole 601; the materials of the first sub-spacer layer 611 and the third sub-spacer layer 613 include nitrides, such as silicon nitride, and the material of the second sub-spacer layer 612 includes oxides, such as silicon oxide.

[0106] In this embodiment of the disclosure, a first spacer layer is provided between the bit line and the node contact plug, and the first spacer layer is a nitride-oxide-nitride stacked structure, which increases the thickness of the insulating material and can more effectively reduce the leakage current between the bit line and the node contact plug and reduce parasitic capacitance.

[0107] Specifically, see first. Figure 2eFirst, a first contact hole mask layer (not shown) can be grown on the upper surface of the filler layer 50. Then, this first contact hole mask layer is patterned to form a patterned first contact hole mask layer (not shown), displaying the pattern of the first contact hole 601 to be etched. The patterning of the first contact hole mask layer can be achieved through photolithography. The first contact hole mask layer can be a photoresist mask or a hard mask patterned based on a photolithography mask. When the first contact hole mask layer is a photoresist mask, it is patterned through steps such as exposure, development, and resist removal. Then, the first contact hole 601 with a certain depth is etched according to the pattern of the first contact hole to be etched.

[0108] Next, see Figure 2f A first sub-spacer layer 611, a second sub-spacer layer 612, and a third sub-spacer layer 613 are sequentially formed within the first contact hole 601.

[0109] Specifically, see Figure 2f as well as Figures 3a to 3e .

[0110] See Figure 3a First, a first sub-spacer layer pre-layer 611' is deposited and formed on the sidewalls and bottom surface of the first contact hole 601 and on the surface of the filling layer 50; see also Figure 3b Remove the bottom surface of the first contact hole 601 and the first sub-spacer layer pre-layer 611' on the surface of the filling layer 50 to form a first sub-spacer layer 611 on the sidewall of the first contact hole 601; see also Figure 3c A second sub-spacer pre-layer 612' is deposited on the sidewall of the first sub-spacer layer 611, the bottom surface of the first contact hole 601, and the surface of the filler layer 50; see also Figure 3d The second sub-spacer layer pre-layer 612' is removed from the bottom surface of the first contact hole 601 and the surface of the filling layer 50 to form a second sub-spacer layer 612 on the sidewall of the first sub-spacer layer 611; see also Figure 3e A third sub-spacer pre-layer 613' is deposited on the sidewall of the second sub-spacer layer 612, the bottom surface of the first contact hole 601, and the surface of the filler layer 50; see also Figure 2f The third sub-spacer layer pre-layer 613' is removed from the bottom surface of the first contact hole 601 and the surface of the filling layer 50 to form a third sub-spacer layer 613 on the sidewall of the second sub-spacer layer 612.

[0111] Next, see Figures 2g to 2n Step 102 is executed, in which a bit line material layer 200 is formed on the cell array region 11, and the bit line material layer 200 is etched to form a bit line structure 20 extending along the first direction.

[0112] In one embodiment, forming a bit line material layer 200 on the cell array region 11 and etching the bit line material layer 200 to form a bit line structure 20 extending along a first direction includes:

[0113] Bit line material layers 200 are formed on the cell array region 11 and the peripheral circuit region 12, see [reference]. Figure 2g ;

[0114] Etching removes the bit line material layer 200 on the peripheral circuit region 12, see [link / reference] Figure 2h ;

[0115] The bit line material layer 200 on the cell array region 11 is etched to form a bit line structure 20 extending along the first direction. See [reference needed]. Figures 2i to 2n .

[0116] Specifically, in one embodiment, forming the bit line structure 20 includes:

[0117] A bit line material layer 200 is formed in the first contact hole 601 after the formation of the third sub-spacer layer 613 and on the surface of the filling layer 50.

[0118] A bit line mask layer 21, a bit line insulating layer 22, and a bit line photoresist layer 23 are sequentially formed on the bit line material layer 200.

[0119] The bit line photoresist layer 23 is patterned to form a patterned bit line photoresist layer 230;

[0120] The patterned bit line photoresist layer 230 is used to etch the bit line insulating layer 22 and the bit line mask layer 21 to form a patterned bit line insulating layer 220 and a patterned bit line mask layer 210; the patterned bit line insulating layer 220 and the patterned bit line mask layer 210 extend along a first direction and expose a portion of the bit line material layer 200.

[0121] A bit line dielectric layer prelayer 24' is formed on the sidewalls and top surface of the patterned bit line insulating layer 220 and the patterned bit line mask layer 210, as well as on the top surface of the exposed portion of the bit line material layer 200;

[0122] Part of the bit line dielectric layer pre-layer 24' is etched away, while the bit line dielectric layer pre-layer 24' located on the sidewalls of the patterned bit line insulating layer 220 and the patterned bit line mask layer 210 is retained to form a bit line dielectric layer 24 extending in the first direction.

[0123] Remove the patterned bit line insulating layer 220 and the patterned bit line mask layer 210, and use the bit line dielectric layer 24 as a mask to etch the bit line material layer 200 on the surface of the filling layer 50 to form a bit line structure 20 extending along the first direction.

[0124] Specifically, see first. Figure 2g A bit line material layer 200 is formed within the first contact hole 601 after the formation of the third sub-spacer layer 613 and on the surface of the filler layer 50. Specifically, the bit line material layer 200 is located on the surfaces of the filler layer 50 and the isolation fence 41.

[0125] Next, see Figure 2h The bit line material layer 200 on the peripheral circuit region 12 is etched away. It should be explained that the bit line material layer of the peripheral circuit region adjacent to the cell array region may be retained.

[0126] Next, see Figure 2i A bit line mask layer 21, a bit line insulating layer 22, and a bit line photoresist layer 23 are sequentially formed on the bit line material layer 200.

[0127] The material of the bit line mask layer 21 includes, but is not limited to, spin-coated hard mask material, and the material of the bit line insulating layer 22 includes, but is not limited to, silicon oxynitride (SiON).

[0128] Next, see Figure 2j The bit line photoresist layer 23 is patterned to form a patterned bit line photoresist layer 230.

[0129] Next, see Figure 2k Based on the patterned bit line photoresist layer 230, the bit line insulating layer 22 and the bit line mask layer 21 are etched to form a patterned bit line insulating layer 220 and a patterned bit line mask layer 210; the patterned bit line insulating layer 220 and the patterned bit line mask layer 210 extend along a first direction and expose a portion of the bit line material layer 200; and the patterned bit line photoresist layer 230 is removed.

[0130] Next, see Figure 2l A bit line dielectric layer prelayer 24' is formed on the sidewalls and top surface of the patterned bit line insulating layer 220 and the patterned bit line mask layer 210, as well as on the top surface of the exposed portion of the bit line material layer 200.

[0131] The material of the bit line dielectric layer pre-layer 24' includes, but is not limited to, silicon nitride.

[0132] Next, see Figure 2m The bit line dielectric layer pre-layer 24' is etched away, leaving the bit line dielectric layer pre-layer 24' located on the sidewalls of the patterned bit line insulating layer 220 and the patterned bit line mask layer 210 to form a bit line dielectric layer 24 extending in the first direction, and the patterned bit line insulating layer 220 and the patterned bit line mask layer 210 are removed.

[0133] Then, see Figure 2n Using the bit line dielectric layer 24 as a mask, the bit line material layer 200 on the surface of the filling layer 50 is etched to form a bit line structure 20 extending along the first direction.

[0134] In practice, the self-aligned reverse patterning (SARP) process can be used to form bit lines.

[0135] The bit line structure 20 may include a multilayer material layer structure, for example, it may include a first conductive layer and a second conductive layer (not shown) located on the first conductive layer. The material of the first conductive layer includes, but is not limited to, titanium nitride, and the material of the second conductive layer includes, but is not limited to, tungsten.

[0136] In some embodiments, the bit line structure 20 may further include a third conductive layer (not shown) located below the first conductive layer. The material of the third conductive layer includes, but is not limited to, one or more of cobalt silicide, nickel silicide, and titanium silicide. An ohmic contact can be formed between the third conductive layer and the substrate, thereby reducing the contact resistance between the first and second conductive layers and the substrate.

[0137] like Figure 2n As shown in this embodiment, since the portion of the bit line structure above the top surface of the filling layer is formed on the isolation fence, the surface of the formed bit line structure is higher than the surface of the word line structure. This increases the spacing between the word line structure and the bit line structure, which helps to reduce the parasitic capacitance between the word line structure and the bit line structure.

[0138] Next, see Figure 2o The method further includes: after forming the bit line structure 20, forming a second spacer layer 62 on the filling layer 50; the second spacer layer 62 encloses the sidewall of the portion of the bit line structure 20 located above the top surface of the filling layer 50.

[0139] Specifically, in one embodiment, forming the second spacer layer 62 includes:

[0140] On the sidewall of the portion of the bit line structure 20 above the top surface of the filling layer 50, a fourth sub-spacer layer 621, a fifth sub-spacer layer 622, and a sixth sub-spacer layer 623 are formed sequentially.

[0141] The materials of the fourth sub-spacer layer 621 and the sixth sub-spacer layer 623 include nitrides, such as silicon nitride, and the material of the fifth sub-spacer layer 622 includes oxides, such as silicon oxide.

[0142] The second spacer layer 62 not only covers the sidewalls of the portion of the bit line structure 20 above the top surface of the filler layer 50, but also covers the sidewalls and surface of the bit line dielectric layer 24.

[0143] In this embodiment of the present disclosure, a second spacer layer is provided on the sidewall of the portion of the bit line located above the top surface of the filler layer, which can reduce the leakage current between the bit line and the node contact plug and reduce parasitic capacitance.

[0144] Next, see Figure 2p and Figure 2q The bit line structure 20 extending along the first direction and the isolation fence 41 extending along the second direction are arranged in an intersecting pattern to form an array of node contact areas; it should be explained that the location of the node contact area is the location of the node contact hole formed subsequently.

[0145] The method further includes:

[0146] After forming the bit line structure 20, the filling layer 50 and the substrate 10 of the node contact area are etched to form the node contact hole 701. See [link to documentation]. Figure 2p ;

[0147] A node contact plug 70 is formed within the node contact hole 701, see [link / reference]. Figure 2q The material of the node contact plug 70 includes, but is not limited to, polycrystalline silicon.

[0148] In this embodiment of the disclosure, a self-aligned node contact hole for forming a node contact plug can be formed by the isolation fence 41 and the bit line structure 20 located under the second spacer layer 62, reducing the use of the mask layer for forming the node contact hole.

[0149] Next, see Figure 2r and Figure 2s The method further includes etching away the filling layer 50 of the peripheral circuit region 12.

[0150] Specifically, see Figure 2r A first mask layer 81 is formed on the unit array region 11 and the peripheral circuit region 12, and a first photoresist layer 82 is formed on the first mask layer 81 of the unit array region 11. Then, see... Figure 2s Based on the first photoresist layer 82, the filling layer 50 of the peripheral circuit area 12 is etched away, and the first photoresist layer 82 and the first mask layer 81 are removed.

[0151] Next, see Figures 2t to 2w Step 103 is executed, in which a gate material layer 300 is formed on the peripheral circuit region 12, and the gate material layer 300 is etched to form a peripheral gate structure 30.

[0152] In one embodiment, forming a gate material layer 300 on the peripheral circuit region 12 and etching the gate material layer 300 to form a peripheral gate structure 30 includes:

[0153] A gate material layer 300 is formed on the unit array region 11 and the peripheral circuit region 12;

[0154] Etching removes the gate material layer 300 on the unit array region 11;

[0155] The gate material layer 300 on the peripheral circuit region 12 is etched to form a peripheral gate structure 30.

[0156] Specifically, see first. Figure 2t A gate insulating material layer 301 is formed on the peripheral circuit region 12, and a first gate conductive material layer 302 and a second gate conductive material layer 303 are sequentially formed on the gate insulating material layer 301 and the unit array region 11.

[0157] Next, see Figure 2u A peripheral gate dielectric layer pre-layer 91' is formed on the second gate conductive material layer 303 of the peripheral circuit region 12. A peripheral gate mask layer 92, a peripheral gate insulating layer 93, and a peripheral gate photoresist layer (not shown) are sequentially formed on the second gate conductive material layer 303 and the peripheral gate dielectric layer pre-layer 91' of the unit array region 11. The peripheral gate photoresist layer is etched to form a patterned peripheral gate photoresist layer 940.

[0158] Next, see Figure 2v According to the patterned peripheral gate photoresist layer 940, the peripheral gate layer is sequentially transferred on the peripheral gate insulating layer 93, the peripheral gate mask layer 92, and the peripheral gate dielectric layer pre-layer 91' according to the pattern of the peripheral gate layer to be etched, so as to form the peripheral gate dielectric layer 91, and the gate material layer 300 on the unit array region 11 is etched away.

[0159] Next, see Figure 2w Based on the peripheral gate dielectric layer 91, the gate material layer 300 on the peripheral circuit region 12 is etched to form the peripheral gate structure 30.

[0160] The peripheral gate structure 30 includes a gate insulating layer 31, a first gate conductive layer 32, and a second gate conductive layer 33. The gate insulating layer 31 includes, but is not limited to, oxides, nitrides, metal oxides, and oxynitrides. The first gate conductive layer 32 includes, but is not limited to, polysilicon. The second gate conductive layer 33 includes, but is not limited to, tungsten. In some embodiments, a diffusion barrier layer (e.g., titanium nitride) may be formed between the first gate conductive layer 32 and the second gate conductive layer 33 to prevent the diffusion of metal atoms.

[0161] See also Figure 2w The method further includes forming a sidewall 34 at the sidewall of the peripheral gate structure 30. The sidewall can provide insulation protection for the peripheral gate structure.

[0162] This disclosure also provides a semiconductor structure. Figure 4 This is a top view of a semiconductor structure provided in an embodiment of the present disclosure. Figure 5 The semiconductor structure provided in the embodiments of this disclosure is along Figure 4 A sectional view along the A-A' direction. Figure 6 The semiconductor structure provided in the embodiments of this disclosure is along Figure 4 A cross-sectional view along the B-B' direction.

[0163] like Figures 4 to 6 As shown, the semiconductor structure includes: a substrate 10, the substrate 10 including a cell array region 11 and a peripheral circuit region 12; a bit line structure 20 located on the cell array region 11 and extending along a first direction; a peripheral gate structure 30 located on the peripheral circuit region 12; and a word line structure 40 located within the substrate 10 of the cell array region 11, the word line structure 40 including an isolation barrier 41, the top surface of the isolation barrier 41 being higher than the top surface of the substrate 10.

[0164] In one embodiment, the substrate 10 may be a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, SOI (silicon on insulator) substrate, or GOI (germanium on insulator) substrate, etc. It may also be a substrate including other elemental semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (e.g., gallium nitride substrate or gallium arsenide substrate, etc.), and may also be a stacked structure, such as Si / SiGe, etc., or other epitaxial structures, such as SGOI (germanium on silicon insulator), etc.

[0165] An isolation structure 101 can be formed in the substrate 10 of the unit array region 11 and the peripheral circuit region 12. The isolation structure 101 defines a unit active region 102 in the substrate of the unit array region 11 and a peripheral active region 103 in the substrate of the peripheral circuit region 12. The material of the isolation structure 101 may include one or more of oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), and oxynitrides (e.g., silicon oxynitride). The isolation structure 101 may consist of one or more of the following: a single layer comprising one insulating layer, a double layer comprising two insulating layers, or a multilayer comprising at least three insulating layers.

[0166] In one embodiment, such as Figure 5 As shown, the semiconductor structure further includes a filling layer 50 located on the substrate 10; the top surface of the filling layer 50 is flush with the top surface of the isolation barrier 41.

[0167] The material of the word line structure 40 includes tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, metal alloys, or any combination thereof. The material of the isolation fence 41 includes, but is not limited to, silicon nitride. The material of the filler layer 50 includes, but is not limited to, oxides.

[0168] In one embodiment, the word line structure 40 extends along a second direction, the first direction being perpendicular to the second direction; wherein the bit line structure 20 is located on the isolation fence 41.

[0169] In this embodiment of the disclosure, since the portion of the bit line structure located above the top surface of the filling layer is formed on the isolation fence, the surface of the formed bit line structure is higher than the surface of the word line structure. This increases the spacing between the word line structure and the bit line structure, which helps to reduce the parasitic capacitance between the word line structure and the bit line structure.

[0170] In one embodiment, the bit line structure 20 may include a multilayer material layer structure, for example, it may include a first conductive layer and a second conductive layer (not shown) located on the first conductive layer, wherein the material of the first conductive layer includes, but is not limited to, titanium nitride, and the material of the second conductive layer includes, but is not limited to, tungsten.

[0171] In some embodiments, the bit line structure 20 may further include a third conductive layer (not shown) located below the first conductive layer. The material of the third conductive layer includes, but is not limited to, one or more of cobalt silicide, nickel silicide, and titanium silicide. An ohmic contact can be formed between the third conductive layer and the substrate, thereby reducing the contact resistance between the first and second conductive layers and the substrate.

[0172] In one embodiment, the semiconductor structure further includes a bit line dielectric layer 24 located on the bit line structure 20. The material of the bit line dielectric layer 24 includes, but is not limited to, silicon nitride.

[0173] In one embodiment, such as Figure 6 As shown, the semiconductor structure further includes: a first spacer layer 61 located within the fill layer 50 and the substrate 10 of the cell array region 11; the first spacer layer 61 encloses the sidewall of the bit line structure 20 below the top surface of the fill layer 50;

[0174] See Figure 2f The first spacer layer 61 includes a first sub-spacer layer 611, a second sub-spacer layer 612 and a third sub-spacer layer 613 disposed sequentially; the materials of the first sub-spacer layer 611 and the third sub-spacer layer 613 include nitrides, and the material of the second sub-spacer layer 612 includes oxides.

[0175] In this embodiment of the disclosure, a first spacer layer is provided between the bit line and the node contact plug, and the first spacer layer is a nitride-oxide-nitride stacked structure, which increases the thickness of the insulating material and can more effectively reduce the leakage current between the bit line and the node contact plug and reduce parasitic capacitance.

[0176] In one embodiment, the semiconductor structure further includes a second spacer layer 62 located on the fill layer 50; the second spacer layer 62 encloses the sidewall of the bit line structure 20 above the top surface of the fill layer 50.

[0177] See Figure 2o The second spacer layer includes a fourth sub-spacer layer 621, a fifth sub-spacer layer 622, and a sixth sub-spacer layer 623 arranged sequentially; the materials of the fourth sub-spacer layer 621 and the sixth sub-spacer layer 623 include nitrides, and the material of the fifth sub-spacer layer 622 includes oxides.

[0178] The second spacer layer 62 not only covers the sidewalls of the portion of the bit line located above the top surface of the filler layer 50, but also covers the sidewalls and surface of the bit line dielectric layer 24.

[0179] In this embodiment of the present disclosure, a second spacer layer is provided on the sidewall of the portion of the bit line located above the top surface of the filler layer, which can reduce the leakage current between the bit line and the node contact plug and reduce parasitic capacitance.

[0180] In one embodiment, such as Figure 4 and Figure 6 As shown, the bit line structure 20 extending along the first direction and the isolation fence 41 extending along the second direction are arranged in an intersecting pattern to form an array of node contact areas.

[0181] The semiconductor structure further includes a node contact plug 70 located within the fill layer 50 and the substrate 10 in the node contact region. The material of the node contact plug 70 includes, but is not limited to, polycrystalline silicon.

[0182] In this embodiment of the disclosure, a self-aligned node contact hole for forming a node contact plug can be formed by the isolation fence 41 and the bit line structure 20 located under the second spacer layer 62, reducing the use of the mask layer for forming the node contact hole.

[0183] In one embodiment, the peripheral gate structure 30 includes a gate insulating layer 31, a first gate conductive layer 32, and a second gate conductive layer 33. The gate insulating layer 31 includes, but is not limited to, oxides, nitrides, metal oxides, and oxynitrides. The first gate conductive layer 32 includes, but is not limited to, polysilicon. The second gate conductive layer 33 includes, but is not limited to, tungsten metal.

[0184] The semiconductor structure further includes a peripheral gate dielectric layer 91 located on the peripheral gate structure 30.

[0185] A sidewall 34 is formed on the sidewall of the peripheral gate structure 30. The sidewall can provide insulation protection for the peripheral gate structure.

[0186] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The method includes: A substrate is provided, the substrate comprising a cell array region and a peripheral circuit region; A bit line material layer is formed on the cell array region, and the bit line material layer is etched to form a bit line structure extending along a first direction; A gate material layer is formed on the peripheral circuit region, and the gate material layer is etched to form a peripheral gate structure; Before forming the bit line structure, a word line structure extending along a second direction is formed within the substrate of the cell array region, wherein the first direction and the second direction are perpendicular to each other; the word line structure includes an isolation barrier, the top surface of which is higher than the top surface of the substrate; A filler layer is formed on the substrate; the top surface of the filler layer is flush with the top surface of the isolation fence.

2. The method according to claim 1, characterized in that, The step of forming a bit line material layer on the cell array region and etching the bit line material layer to form a bit line structure extending along a first direction includes: A bit line material layer is formed on the cell array region and the peripheral circuit region; Etching removes the bit line material layer on the peripheral circuit region; The bit line material layer on the cell array region is etched to form a bit line structure extending along a first direction.

3. The method according to claim 1, characterized in that, The process of forming a gate material layer on the peripheral circuit region and etching the gate material layer to form a peripheral gate structure includes: A gate material layer is formed on the cell array region and the peripheral circuit region; Etching removes the gate material layer on the cell array region; The gate material layer on the peripheral circuit region is etched to form a peripheral gate structure.

4. The method of claim 1, wherein, Also includes: After the filling layer is formed, a first spacer layer is formed within the filling layer and the substrate in the cell array region; The first spacer layer encloses the sidewall of the portion of the bit line structure located below the top surface of the filler layer.

5. The method according to claim 4, characterized in that, The formation of the first spacer layer includes: The filling layer and the substrate of the cell array region are etched to form a first contact hole; A first sub-spacer layer, a second sub-spacer layer, and a third sub-spacer layer are formed sequentially within the first contact hole; The materials of the first sub-spacer layer and the third sub-spacer layer comprise nitrides, and the material of the second sub-spacer layer comprises oxides.

6. The method according to claim 5, characterized in that, The formation of the bit line structure includes: A bit line material layer is formed in the first contact hole after the formation of the third sub-spacer layer and on the surface of the filler layer; A bit line mask layer, a bit line insulating layer, and a bit line photoresist layer are sequentially formed on the bit line material layer; The bit line photoresist layer is patterned to form a patterned bit line photoresist layer; Based on the patterned bit line photoresist layer, the bit line insulating layer and the bit line mask layer are etched to form the patterned bit line insulating layer and the patterned bit line mask layer; the patterned bit line insulating layer and the patterned bit line mask layer extend along a first direction and expose a portion of the bit line material layer; A bit line dielectric layer prelayer is formed on the sidewalls and top surface of the patterned bit line insulating layer and the patterned bit line mask layer, as well as on the top surface of the exposed portion of the bit line material layer; The bit line dielectric layer pre-layer is etched away in part, leaving the bit line dielectric layer pre-layer located on the sidewalls of the patterned bit line insulating layer and the patterned bit line mask layer to form a bit line dielectric layer extending in a first direction. Remove the patterned bit line insulating layer and the patterned bit line mask layer, and use the bit line dielectric layer as a mask to etch the bit line material layer on the surface of the filling layer to form a bit line structure extending along the first direction.

7. The method according to claim 1, characterized in that, Also includes: After the bit line structure is formed, a second spacer layer is formed on the filler layer; the second spacer layer covers the sidewall of the portion of the bit line structure above the top surface of the filler layer.

8. The method according to claim 7, characterized in that, The formation of the second spacer layer includes: On the sidewall of the portion of the bit line structure above the top surface of the filling layer, a fourth sub-spacer layer, a fifth sub-spacer layer, and a sixth sub-spacer layer are formed sequentially. The materials of the fourth and sixth sub-spacer layers comprise nitrides, and the material of the fifth sub-spacer layer comprises oxides.

9. The method according to claim 1, characterized in that, The bitline structure extending along the first direction and the isolation fence extending along the second direction are arranged in an intersecting pattern to form an array of node contact areas; The method further includes: After forming the bit line structure, the filling layer and the substrate of the node contact area are etched to form node contact holes; A node contact plug is formed inside the node contact hole.

10. A semiconductor structure, formed using the method for fabricating a semiconductor structure as described in any one of claims 1-9, characterized in that, include: The substrate includes a unit array region and a peripheral circuit region; The bitline structure is located on the cell array region and extends along the first direction; A peripheral gate structure is located on the peripheral circuit region; A word line structure is located within the substrate of the cell array region, the word line structure including an isolation fence, the top surface of the isolation fence being higher than the top surface of the substrate.

11. The semiconductor structure according to claim 10, characterized in that, Also includes: A filler layer is located on the substrate; the top surface of the filler layer is flush with the top surface of the isolation fence.

12. The semiconductor structure according to claim 11, characterized in that, Also includes: A first spacer layer is located within the fill layer and the substrate of the cell array region; the first spacer layer encloses the sidewall of the bit line structure below the top surface of the fill layer; The first spacer layer includes a first sub-spacer layer, a second sub-spacer layer, and a third sub-spacer layer arranged sequentially; The materials of the first sub-spacer layer and the third sub-spacer layer comprise nitrides, and the material of the second sub-spacer layer comprises oxides.

13. The semiconductor structure according to claim 11, characterized in that, Also includes: A second spacer layer is located on the filler layer; the second spacer layer encloses the sidewall of the portion of the bit line structure above the top surface of the filler layer; The second spacer layer includes a fourth sub-spacer layer, a fifth sub-spacer layer, and a sixth sub-spacer layer arranged sequentially; The materials of the fourth and sixth sub-spacer layers comprise nitrides, and the material of the fifth sub-spacer layer comprises oxides.

14. The semiconductor structure according to claim 11, characterized in that, The character line structure extends along a second direction, and the first direction and the second direction are perpendicular to each other; The bit line structure is located on the isolation fence.

15. The semiconductor structure according to claim 14, characterized in that, The bitline structure extending along the first direction and the isolation fence extending along the second direction are arranged in an intersecting pattern to form an array of node contact areas; The semiconductor structure also includes: A node contact plug is located within the fill layer and the substrate of the node contact area.

Images