Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The present disclosure provides a semiconductor structure manufacturing method and a semiconductor structure. The semiconductor structure manufacturing method comprises: providing a substrate; forming a plurality of shallow trench isolation structures on the substrate to define an active region and performing first ion doping on the active region to form a first ion doped region; forming a word line trench in the active region; performing second ion doping to form a second ion doped region, the electronegativity of the doping ions of the second ion doped region being higher than that of the substrate material; forming a word line structure in the word line trench after forming the second ion doped region, and part of the second ion doped region being located between the first ion doped region and the word line structure. Before forming the word line structure, the second ion doped region is formed, and the electronegativity of the doping ions of the second ion doped region is higher, thereby increasing the resistance between the first ion doped region and the word line structure, effectively solving the problem of current leakage and improving the quality and performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] With the gradual development of storage device technology, Dynamic Random Access Memory (DRAM) has been increasingly used in various electronic devices due to its high density and fast read / write speeds. DRAM generally consists of a substrate and a dielectric layer disposed on the substrate. The substrate has a core region and a peripheral region surrounding the core region. Both the core region and the peripheral region have embedded word lines, which can reduce the short-channel effect to a certain extent, thereby reducing leakage current in the middle of the device.

[0003] However, in the aforementioned DRAM manufacturing process, as critical dimensions shrink, the manufacturing requirements for word lines become increasingly stringent, leading to GIDL (gate-induced gate leakage) problems in embedded word lines, which affect product quality and performance. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself.

[0006] A first aspect of this disclosure provides a method for fabricating a semiconductor structure, the method comprising:

[0007] Provide substrate;

[0008] Multiple shallow trench isolation structures are formed on the substrate to define the active region, and the active region is subjected to first ion doping to form a first ion-doped region;

[0009] Word line grooves are formed in the active region;

[0010] A second ion doping process is performed to form a second ion doped region, wherein the electronegativity of the dopant ion in the second ion doping process is higher than that of the substrate material;

[0011] A word line structure is formed within the word line trench after the formation of the second ion-doped region, with a portion of the second ion-doped region located between the first ion-doped region and the word line structure.

[0012] According to some embodiments of this disclosure, the substrate material includes silicon, and the dopant ions of the second ion doping include carbon and / or germanium.

[0013] According to some embodiments of this disclosure, a portion of the second ion-doped region is located between the first ion-doped region and the word line structure, including:

[0014] The top of the word line structure is lower than the top of the second ion-doped region, and the bottom of the first ion-doped region is higher than the bottom of the second ion-doped region.

[0015] According to some embodiments of this disclosure, the top of the second ion-doped region is 5 nm to 10 nm higher than the top of the word line structure, the bottom of the second ion-doped region is 5 nm to 10 nm lower than the top of the word line structure, and the depth of the second ion-doped region is not less than 15 nm. According to some embodiments of this disclosure, the second ion-doped region includes at least a portion of the sidewalls of the word line trench, and the step of forming the second ion-doped region by performing second ion doping includes:

[0016] At least a portion of the sidewalls of the word line trench are subjected to a second ion doping, wherein the implantation dose of the dopant ions in the second ion doping is 15E14 per square centimeter to 40E14 per square centimeter, and the implantation energy of the dopant ions in the second ion doping is 5 keV to 10 keV.

[0017] According to some embodiments of this disclosure, after performing a second ion doping on at least a portion of the sidewalls of the word line trench, the method for fabricating the semiconductor structure further includes:

[0018] A gate oxide insulating layer is formed in the word line groove, and the gate oxide insulating layer covers the groove wall surface of the word line groove;

[0019] The process of forming a word line structure within the word line trench after forming the second ion-doped region includes:

[0020] A metal protective layer is formed on the gate oxide insulating layer, the metal protective layer covering a portion of the gate oxide insulating layer, and the top end of the metal protective layer being lower than the top end of the gate oxide insulating layer;

[0021] A gate conductive layer is filled within the space enclosed by the metal protective layer, and the gate conductive layer and the metal protective layer constitute the word line structure.

[0022] According to some embodiments of this disclosure, the second ion-doped region further includes at least a portion of the sidewalls of the gate oxide insulating layer, and the second ion doping to form the second ion-doped region further includes performing the second ion doping before forming a metal protective layer on the gate oxide insulating layer:

[0023] At least a portion of the sidewalls of the gate oxide insulating layer are subjected to a second ion doping, wherein the implantation dose of the dopant ions in the second ion doping is 10E14 per square centimeter to 30E14 per square centimeter, and the implantation energy of the dopant ions in the second ion doping is 5 keV to 10 keV.

[0024] According to some embodiments of this disclosure, before performing second ion doping to form the second ion-doped region, the method for fabricating the semiconductor structure further includes:

[0025] A gate oxide insulating layer is formed in the word line groove, and the gate oxide insulating layer covers the groove wall surface of the word line groove;

[0026] The second ion-doped region includes at least a portion of the sidewalls of the gate oxide insulating layer, and the process of forming the second ion-doped region by performing second ion doping includes:

[0027] At least a portion of the sidewalls of the gate oxide insulating layer are subjected to a second ion doping, wherein the implantation dose of the dopant ions in the second ion doping is 10E14 per square centimeter to 30E14 per square centimeter, and the implantation energy of the dopant ions in the second ion doping is 5 keV to 10 keV.

[0028] According to some embodiments of this disclosure, forming a word line structure within the word line trench after forming the second ion-doped region includes:

[0029] A metal protective layer is formed on the gate oxide insulating layer, the metal protective layer covering a portion of the gate oxide insulating layer, and the top end of the metal protective layer being lower than the top end of the gate oxide insulating layer;

[0030] A gate conductive layer is filled within the space enclosed by the metal protective layer, and the gate conductive layer and the metal protective layer constitute the word line structure.

[0031] According to some embodiments of this disclosure, the top of the word line structure is lower than the top of the word line trench. After forming the word line structure in the word line trench after forming the second ion-doped region, the method for fabricating the semiconductor structure further includes:

[0032] A dielectric layer is formed on the word line structure, and the dielectric layer fills the word line grooves.

[0033] A second aspect of this disclosure provides a semiconductor structure, the semiconductor structure comprising:

[0034] A substrate having a shallow trench isolation structure thereon, the shallow trench isolation structure defining an active region on the substrate, the active region including a first ion-doped region;

[0035] The character line groove is disposed in the active area;

[0036] The character line structure is disposed within the character line groove;

[0037] The second ion-doped region is partially located between the first ion-doped region and the word line structure, and the electronegativity of the doped ions in the second ion-doped region is higher than that of the substrate material.

[0038] According to some embodiments of this disclosure, the substrate material includes silicon, and the dopant ions include carbon and / or germanium.

[0039] According to some embodiments of this disclosure, the top of the second ion-doped region is higher than the top of the word line structure, and the bottom of the first ion-doped region is higher than the bottom of the second ion-doped region.

[0040] According to some embodiments of this disclosure, the semiconductor structure further includes:

[0041] A gate oxide insulating layer that covers the groove wall of the word line trench;

[0042] The second ion-doped region includes at least a portion of the sidewalls of the word line trench and / or at least a portion of the sidewalls of the gate oxide insulating layer.

[0043] According to some embodiments of this disclosure, the word line structure includes:

[0044] A metal protective layer covers a portion of the sidewall of the gate oxide insulating layer, wherein the top of the metal protective layer is lower than the top of the gate oxide insulating layer;

[0045] The gate conductive layer fills the space enclosed by the metal protective layer.

[0046] According to some embodiments of this disclosure, the top of the word line structure is lower than the top of the word line trench, and the semiconductor structure further includes a dielectric layer that fills the word line trench.

[0047] In the semiconductor structure fabrication method and semiconductor structure provided in this disclosure, a second ion-doped region is formed before the word line structure is formed. After the word line structure is formed, part of the second ion-doped region is located between the first ion-doped region of the active region and the word line structure. The doped ions in the second ion-doped region have higher electronegativity, thereby giving the second ion-doped region higher resistance. This increases the resistance between the first ion-doped region and the word line structure, effectively solving the leakage problem and improving the quality and performance of the semiconductor structure.

[0048] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0049] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0050] Figure 1 This is a schematic diagram of the semiconductor structure in related technologies;

[0051] Figure 2 A flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0052] Figure 3 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0053] Figure 4 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0054] Figure 5 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0055] Figure 6 This is a schematic diagram of the structure after forming a shallow trench isolation structure and a first ion-doped region in a semiconductor structure fabrication method according to an exemplary embodiment.

[0056] Figure 7 This is a schematic diagram of the structure after word line trenches are formed in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0057] Figure 8 This is a schematic diagram illustrating ion implantation of the sidewalls of a word line trench in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0058] Figure 9 This is a schematic diagram of the structure after forming a second ion-doped region in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0059] Figure 10 This is a schematic diagram of the structure after the gate oxide insulating layer is formed in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0060] Figure 11 This is a schematic diagram of the structure after a metal protective layer is formed in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0061] Figure 12 This is a schematic diagram of the structure after the gate conductive layer is formed in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0062] Figure 13 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment.

[0063] Figure 14 This is a schematic diagram of the structure after the formation of the first sub-region in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0064] Figure 15 This is a schematic diagram of the structure after the gate oxide insulating layer is formed in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0065] Figure 16 This is a schematic diagram illustrating ion implantation of the sidewalls of a gate oxide insulating layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0066] Figure 17 This is a schematic diagram of the structure after the second sub-region is formed in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0067] Figure 18 This is a schematic diagram of the structure after a metal protective layer is formed in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0068] Figure 19 This is a schematic diagram of the structure after the gate conductive layer is formed in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0069] Figure 20 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment;

[0070] Figure 21 This is a schematic diagram illustrating ion implantation of the sidewalls of a gate oxide insulating layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0071] Figure 22 This is a schematic diagram of the structure after forming a second ion-doped region in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0072] Figure 23 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment.

[0073] Figure label:

[0074] 10. Substrate; 20. Active region; 21. First ion-doped region; 30. Word line trench; 40. Second ion-doped region; 41. First sub-region; 42. Second sub-region; 50. Word line structure; 51. Metal protective layer; 52. Gate conductive layer; 60. Shallow trench isolation structure; 70. Gate oxide insulating layer; 80. Dielectric layer. Detailed Implementation

[0075] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0076] In related technologies, semiconductor structures with embedded word lines, such as... Figure 1 As shown, a gate oxide insulating layer 70, a metal protective layer 51, and a gate conductive layer 52 are sequentially disposed within the word line trench 30 of the substrate 10. The metal protective layer 51 and the gate conductive layer 52 constitute the word line structure 50. A dielectric layer 80 covers the top of the gate conductive layer 52 to fill the word line trench 30. As the feature size of semiconductor structures continues to decrease, the thickness of the gate oxide insulating layer 70 also becomes thinner. As a result, the leakage current in the gate-drain overlap region (region A in the figure) will increase sharply. Typically, the gate oxide insulating layer 70 used in buried word lines is generated by consuming silicon material in the substrate 10 to form silicon oxide in the channel. Therefore, the thickness of the gate oxide insulating layer 70 is limited by the width of the device channel. When a sufficiently thick silicon oxide layer cannot be generated, the GIDL problem will occur. At the same time, the continuous reduction in size means that the distance between the two word line structures 50 will become closer and closer, and parasitic capacitance (COV) will easily be generated between them, thereby reducing conductivity.

[0077] Based on this, the exemplary embodiments of this disclosure provide a method for fabricating a semiconductor structure and a semiconductor structure, wherein a second ion-doped region with higher resistance is formed between the word line structure and the first ion-doped region, thereby increasing the resistance between the first ion-doped region and the word line structure, effectively solving the leakage problem, and improving the quality and performance of the semiconductor structure.

[0078] This disclosure provides a method for fabricating a semiconductor structure in exemplary embodiments, such as... Figure 2 As shown, Figure 2 A flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure is shown. Figures 6-23 The diagram below illustrates the various stages of semiconductor structure fabrication. Figures 6-23 The methods for fabricating semiconductor structures are introduced.

[0079] This embodiment does not limit the semiconductor structure. The following description will take dynamic random access memory (DRAM) as an example, but this embodiment is not limited to this. Other semiconductor structures are also possible in this embodiment.

[0080] like Figure 2 As shown, an exemplary embodiment of this disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:

[0081] Step S100: Provide a substrate.

[0082] Among them, such as Figure 6 As shown, substrate 10 is used to support other structural devices disposed thereon. For example, substrate 10 can be a semiconductor substrate, and the material of the semiconductor substrate can include one or more of silicon (Si), germanium (Ge), silicon-germanium (GeSi), and silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can include other materials, such as gallium arsenide and other III-V compounds. An active region 20 extending along a first direction is provided on substrate 10. The active region 20 is used to form transistor devices in subsequent process steps. Exemplarily, the active region 20 can be defined in substrate 10 by forming a shallow trench isolation structure 60 in substrate 10.

[0083] Step S200: Form multiple shallow trench isolation structures on the substrate to define the active region, and perform first ion doping on the active region to form a first ion-doped region.

[0084] Continue to refer to Figure 6 By forming a shallow trench isolation structure 60 within the substrate 10, the substrate 10 is divided into multiple isolated active regions 20. Exemplarily, isolation trenches are first formed on the substrate 10, and then an insulating layer is deposited within the isolation trenches using chemical vapor deposition or other deposition techniques to form the shallow trench isolation structure 60. The material of the shallow trench isolation structure 60 may include silicon nitride or silicon oxide, etc. The shallow trench isolation structure 60 isolates multiple active regions 20 within the substrate 10, for example, isolating multiple active regions 20 arranged in an array. The shallow trench isolation structure 60 provides excellent isolation between the subsequently formed word line structures 50.

[0085] The active region 20 can be doped with ion implantation to form a first ion-doped region 21. The first ion-doped region 21 constitutes the source and drain regions. Depending on the requirements, the dopant ions can be P-type impurity ions, such as boron (B), gallium (Ga), or indium (In), or N-type impurity ions, such as phosphorus (P), antimony (Sb), or arsenic (As). The region between the source and drain regions in the active region 20 constitutes the channel region.

[0086] Step S300: Form word line grooves in the active region.

[0087] like Figure 7 As shown, the cross-sectional shape of the word line trench 30 can be U-shaped or rectangular, or other shapes suitable for device performance. The word line trench 30 can be formed by photolithography, etching, or other methods. For example, a mask layer (not shown) and a photoresist layer (not shown) are formed on a substrate using atomic layer deposition, physical vapor deposition, or chemical vapor deposition. A mask pattern is formed on the photoresist layer by exposure or development etching. Using the photoresist layer with the mask pattern as a mask, part of the material in the active region 20 is etched away, thereby forming the word line trench 30 in the active region 20. The word line trench 30 passes through the channel region in the active region 20, and the bottom of the word line trench 30 is lower than the bottom of the first ion-doped region 21, so as to form an embedded word line structure 50 in subsequent process steps.

[0088] Step S400: Perform second ion doping to form a second ion-doped region, wherein the electronegativity of the dopant ions in the second ion doping is higher than that of the substrate material.

[0089] Step S500: A word line structure is formed in the word line trench after the formation of the second ion-doped region, and part of the second ion-doped region is located between the first ion-doped region and the word line structure.

[0090] like Figure 13 As shown, the word line structure 50 formed in the substrate 10 can serve as the gate of a corresponding transistor in the memory. Meanwhile, a portion of the structure of the second ion-doped region 40 formed in step S400 is located between the first ion-doped region 21 and the word line structure 50. It is understood that the location between the first ion-doped region 21 and the word line structure 50 can mean that one side of the second ion-doped region 40 is in contact with the first ion-doped region 21 and the other side is in contact with the word line structure 50; alternatively, it can mean that one side of the second ion-doped region 40 is in contact with the first ion-doped region 21 and / or the other side of the second ion-doped region 40 is in contact with the word line structure 50, and this disclosure does not limit this.

[0091] In this embodiment, a second ion-doped region 40 is formed before the word line structure 50 is formed. After the word line structure 50 is formed, a portion of the second ion-doped region 40 is located between the first ion-doped region 21 of the active region 20 and the word line structure 50. The doped ions in the second ion-doped region 40 have higher electronegativity, thereby giving the second ion-doped region 40 higher resistance. This increases the resistance between the first ion-doped region 21 and the word line structure 50, effectively solving the leakage problem and improving the quality and performance of the semiconductor structure.

[0092] It is understood that the doping process for forming the first ion-doped region 21 in step S200 can be performed before forming the word line trench 30 or after forming the word line structure 50, and this disclosure does not limit it in this way.

[0093] As previously mentioned, the second ion doping uses a dopant ion with higher electronegativity. Electronegativity is a scale indicating the ability of an element's atoms to attract electrons in a compound. The higher the electronegativity of an element, the stronger its ability to attract electrons in a compound, resulting in a higher electrical resistance in the portion containing that element. Conversely, the lower the electronegativity value, the weaker the ability of the corresponding atom to attract electrons in a compound. In embodiments where the substrate 10 material includes silicon, the dopant ions used for the second ion doping can be, for example, carbon and / or germanium, which have higher electronegativity than silicon.

[0094] The following example, using carbon doping in a silicon wafer, illustrates how second-ion doping can increase the resistance of the doped region. Silicon wafer samples one, two, and three are provided. First, silicon wafer samples one, two, and three are subjected to ion doping, for example, implantation of pentavalent elements such as phosphorus. After doping, the doped silicon wafers are tempered to activate them and form a P-type substrate. Specifically, silicon wafer sample one corresponds to P-type substrate one, silicon wafer sample two corresponds to P-type substrate two, and silicon wafer sample three corresponds to P-type substrate three.

[0095] P-type substrate 1 was used as a control sample and left untreated. P-type substrate 2 and P-type substrate 3 were doped with carbon using the same ion doping process, for example, by ion implantation. The carbon implantation dose for P-type substrate 2 was 100*10^14 per square centimeter, and the carbon implantation dose for P-type substrate 3 was 300*10^14 per square centimeter. After doping, the resistance of P-type substrate 1, P-type substrate 2 and P-type substrate 3 were measured. The measurement results are shown in the table below.

[0096]

[0097]

[0098] As shown in the table above, doping the substrate 10 with elements such as carbon, which have high electronegativity, can effectively improve the resistance of the doped region.

[0099] In this case, a portion of the second ion-doped region 40 is located between the first ion-doped region 21 and the word line structure 50, for example, as shown in the figure. Figure 13 As shown, the top of the word line structure 50 is lower than the top of the second ion-doped region 40, meaning the top of the second ion-doped region 40 extends beyond the word line structure 50. Conversely, the bottom of the first ion-doped region 21 is higher than the bottom of the second ion-doped region 40, meaning the bottom of the second ion-doped region 40 extends beyond the first ion-doped region 21. This ensures that the second ion-doped region 40 completely covers the junction between the word line structure 50 and the first ion-doped region 21, further preventing leakage current.

[0100] For example, the top of the second ion-doped region 40 is 5 nm to 10 nm higher than the top of the word line structure 50, and the bottom of the second ion-doped region 40 is 5 nm to 10 nm lower than the top of the word line structure 50, that is, as shown... Figure 13 As shown, the distance H1 between the top of the second ion-doped region 40 and the top of the word line structure 50 is 5nm to 10nm, and the distance H2 between the bottom of the second ion-doped region 40 and the top of the word line structure 50 is 5nm to 10nm. The depth of the second ion-doped region 40 is not less than 15nm. In this way, it can be ensured that the second ion-doped region 40 can completely cover the top area of ​​the word line structure 50, while reducing the amount of second ion implantation, saving costs and ensuring structural reliability.

[0101] In some embodiments, the step of performing second ion doping to form the second ion-doped region 40 may be performed before forming the gate oxide insulating layer 70, by forming the second ion-doped region 40 from at least a portion of the sidewalls of the word line trench 30, i.e., by performing second ion doping on at least a portion of the sidewalls of the word line trench 30 to form the second ion-doped region 40. In other embodiments, the step of performing second ion doping to form the second ion-doped region 40 may also be performed after forming the gate oxide insulating layer 70, by forming the second ion-doped region 40 from at least a portion of the sidewalls of the gate oxide insulating layer 70, i.e., by performing second ion doping on at least a portion of the sidewalls of the gate oxide insulating layer 70 to form the second ion-doped region 40. Of course, the second ion doping may also be performed both before and after forming the gate oxide insulating layer 70.

[0102] An exemplary embodiment of this disclosure provides a method for fabricating a semiconductor structure, such as... Figure 3 As shown, the method for fabricating this semiconductor structure includes:

[0103] Step S100A: Provide a substrate.

[0104] Step S200A: Multiple shallow trench isolation structures are formed on the substrate to define the active region, and the active region is subjected to first ion doping to form a first ion-doped region.

[0105] Step S300A: Form word line trenches in the active area.

[0106] Step S400A: Perform a second ion doping on at least a portion of the sidewalls of the word line trench to form a second ion-doped region.

[0107] In this step, such as Figure 8 As shown, the sidewalls of the word line trench 30 are used as the doping target. Secondary ion doping is performed on the sidewalls of the word line trench 30 using dopant ions with higher electronegativity. That is, secondary ion doping is performed on a portion of the surface of the exposed active region 20 of the word line trench 30. (Refer to...) Figure 9 This causes a portion of the sidewalls of the word line trench 30 to form a second ion-doped region 40. This can be achieved by performing second ion doping on the entire sidewalls of the word line trench 30, resulting in the formation of the second ion-doped region 40 on the entire sidewalls, or by performing second ion doping on a portion of the sidewalls of the word line trench 30. For example, the bottom of the second ion-doped region 40 is at a predetermined distance from the bottom wall of the word line trench 30.

[0108] As an example, ion implantation can be used to implant ions into a predetermined region of the word line trench 30. By adjusting the implantation angle and dosage, highly electronegative dopant ions are implanted onto the sidewalls of the word line trench 30 to form a second ion-doped region 40 in the predetermined region. Ion implantation allows for the implantation of ions into a specific region, making the implantation area controllable and ensuring the accurate positioning of the formed second ion-doped region 40. The predetermined region can be, for example, a portion of each of the opposite sidewalls of the word line trench 30.

[0109] The implantation dose of the dopant ions in the second ion doping region is 15E14 per square centimeter to 40E14 per square centimeter, and the implantation energy of the dopant ions in the second ion doping region is 5 keV to 10 keV. This ensures that the formed second ion doped region 40 has a sufficiently high resistance without compromising structural reliability, so as to form an effective isolation between the word line structure 50 and the first ion doped region 21, and further avoid leakage problems.

[0110] Step S500A: A gate oxide insulating layer is formed in the word line trench, and the gate oxide insulating layer covers the trench wall surface.

[0111] In some embodiments, a thin-film deposition process is used to form a gate oxide insulating layer 70 within the ion-doped word line trench 30, such as... Figure 10As shown, the gate oxide insulating layer 70 covers the trench wall of the word line trench 30. Since a second ion-doped region 40 is formed on the trench wall of the word line trench 30, the gate oxide insulating layer 70 covers the second ion-doped region 40. The material of the gate oxide insulating layer 70 can be, for example, silicon dioxide, silicon oxynitride, silicon nitride, etc. The gate oxide insulating layer 70 can be a single layer or a multilayer structure. When the gate oxide insulating layer 70 is a multilayer structure, the materials of each layer of the gate oxide insulating layer 70 can be the same or different. In some embodiments, the gate oxide insulating layer 70 is formed using an in-situ water vapor oxidation process, which can effectively reduce the thickness of the gate oxide insulating layer 70, making the prepared semiconductor structure more compact.

[0112] For example, after the second ion-doped region 40 is formed by ion doping, the substrate 10 can be wet-cleaned to remove surface impurities, providing good interface performance and process basis for subsequent processes, thereby improving the quality of the formed semiconductor structure.

[0113] Step S600A: A metal protective layer is formed on the gate oxide insulating layer, the metal protective layer covering part of the gate oxide insulating layer, and the top of the metal protective layer being lower than the top of the gate oxide insulating layer.

[0114] like Figure 11 As shown, the top of the metal protective layer 51 is lower than the top of the gate oxide insulating layer 70, and covers all surfaces of the gate oxide insulating layer 70 except for the upper sidewall, to form a space for accommodating the gate conductive material. By setting the metal protective layer 51, the subsequently filled gate conductive material can be protected, and the diffusion of the gate conductive material can be prevented. The material of the metal protective layer 51 can be titanium (Ti), titanium nitride (TiN), etc., and it can be formed on the gate oxide insulating layer 70 by deposition processes such as atomic layer deposition (ALD) and chemical vapor deposition (CVD).

[0115] Step S700A: Fill the space enclosed by the metal protective layer with the gate conductive layer. The gate conductive layer and the metal protective layer constitute a word line structure.

[0116] like Figure 12As shown, after forming a metal protective layer 51 covering a portion of the gate oxide insulating layer 70, the metal protective layer 51 encloses a space within the word line trench 30, and the gate conductive layer 52 is filled into this space. Thus, the gate conductive layer 52 and the metal protective layer 51 together constitute the word line structure 50. The material of the gate conductive layer 52 can be at least one of tungsten (W), copper (Cu), gold (Au), and silver (Ag), and it can be filled into the space enclosed by the metal protective layer 51 through deposition processes such as atomic layer deposition (ALD) and chemical vapor deposition (CVD).

[0117] Continue to refer to Figure 12 After the word line structure 50 is formed, the top of the word line structure 50 is lower than the top of the second ion doped region 40. For example, the top of the second ion doped region 40 is flush with the top surface of the substrate 10. In this way, the second ion doped region 40 can completely cover the junction of the word line structure 50 and the first ion doped region 21, thereby further avoiding leakage problems.

[0118] In an exemplary embodiment, such as Figure 3 As shown, after forming the word line structure 50 within the word line trench 30 following the formation of the second ion-doped region 40, the semiconductor structure fabrication method further includes:

[0119] Step S800A: A dielectric layer is formed on the word line structure, which fills the word line grooves.

[0120] like Figure 13 As shown, a dielectric layer 80 is formed on the word line structure 50 to planarize the surface of the semiconductor structure, thereby ensuring the flatness of the upper structure of the semiconductor structure. The material of the dielectric layer 80 can be, for example, silicon oxide, silicon oxynitride, etc., and the dielectric layer 80 can be formed by deposition processes such as atomic layer deposition (ALD) and chemical vapor deposition (CVD).

[0121] Steps S100A, S200A, and S300A are similar to the aforementioned steps S100, S200, and S300, respectively. Please refer to the previous description for details, which will not be repeated here.

[0122] In another exemplary embodiment of this disclosure, such as Figure 4 As shown, the method for fabricating this semiconductor structure includes:

[0123] Step S100B: Provide a substrate.

[0124] Step S200B: Multiple shallow trench isolation structures are formed on the substrate to define the active region, and the active region is subjected to first ion doping to form a first ion-doped region.

[0125] Step S300B: Form word line trenches in the active area.

[0126] Step S400B: Perform second ion doping on at least a portion of the sidewalls of the word line trench to form a first sub-region.

[0127] In this step, such as Figure 14 As shown, the sidewalls of the word line trench 30 are used as the doping target. Highly electronegative doping ions are used to perform a second ion doping on the sidewalls of the word line trench 30, causing a portion of the sidewalls of the word line trench 30 to form a first sub-region 41. Alternatively, the entire sidewalls of the word line trench 30 can be doped with the second ion to form the first sub-region 41, or only a portion of the sidewalls of the word line trench 30 can be doped to form the first sub-region 41. For example, the bottom of the first sub-region 41 is at a predetermined distance from the bottom wall of the word line trench 30.

[0128] The implantation dose of the dopant ions in the second ion doping is 15E14 per square centimeter to 40E14 per square centimeter, and the implantation energy of the dopant ions in the second ion doping is 5 keV to 10 keV, so as to ensure that the formed first sub-region 41 has a sufficiently high resistance without compromising the structural reliability, so as to form an effective isolation between the word line structure 50 and the first ion doping region 21, and further avoid leakage problems.

[0129] Step S500B: A gate oxide insulating layer is formed in the word line trench, and the gate oxide insulating layer covers the trench wall surface.

[0130] The structure after the gate oxide insulating layer 70 is formed is as follows Figure 15 As shown.

[0131] Step S600B: At least a portion of the sidewalls of the gate oxide insulating layer are subjected to second ion doping to form a second sub-region, wherein the first sub-region and the second sub-region together constitute the second ion-doped region.

[0132] In this step, such as Figure 16 As shown, the second ion doping is performed using the sidewalls of the gate oxide insulating layer 70 as the doping target, as follows: Figure 17As shown, a portion of the gate oxide insulating layer 70 constitutes a second sub-region 42. As an example, an ion implantation process can be used to implant ions into a predetermined region of the gate oxide insulating layer 70. By adjusting the implantation angle and implantation dose, highly electronegative doped ions are implanted onto the sidewalls of the gate oxide insulating layer 70 to form a second sub-region 42 within the predetermined region. Ion implantation allows for the implantation of specific regions, making the implantation area controllable and ensuring the accurate positioning of the formed second sub-region 42.

[0133] Specifically, when performing a second ion doping on at least a portion of the sidewalls of the gate oxide insulating layer 70, the implantation dose of the dopant ions for the second ion doping is 10E14 per square centimeter to 30E14 per square centimeter, and the implantation energy of the dopant ions for the second ion doping is 5 keV to 10 keV. It is understood that the amount of dopant ions implanted into the gate oxide insulating layer 70 is less than the amount of dopant ions implanted into the word line trench 30 to avoid damage to the gate oxide insulating layer 70.

[0134] Step S700B: A metal protective layer is formed on the gate oxide insulating layer, the metal protective layer covering part of the gate oxide insulating layer, and the top of the metal protective layer being lower than the top of the gate oxide insulating layer.

[0135] The structure after the formation of the metal protective layer 51 is as follows Figure 18 As shown.

[0136] Step S800B: Fill the space enclosed by the metal protective layer with the gate conductive layer. The gate conductive layer and the metal protective layer constitute a word line structure.

[0137] The structure after forming the gate conductive layer 52 is as follows Figure 19 As shown.

[0138] Step S900B: A dielectric layer is formed on the word line structure, which fills the word line grooves.

[0139] The structure after the formation of the dielectric layer is as follows Figure 20 As shown.

[0140] Steps S100B, S200B, and S300B are similar to the aforementioned steps S100, S200, and S300, respectively. Steps S500B, S700B, S800B, and S900B are similar to the aforementioned steps S500A, S600A, S700A, and S800A, respectively. For details, please refer to the preceding descriptions, which will not be repeated here.

[0141] In another exemplary embodiment of this disclosure, such as Figure 5 As shown, the method for fabricating this semiconductor structure includes:

[0142] Step S100C: Provide a substrate.

[0143] Step S200C: Multiple shallow trench isolation structures are formed on the substrate to define the active region, and the active region is subjected to first ion doping to form a first ion-doped region.

[0144] Step S300C: Form word line trenches in the active region.

[0145] Step S400C: A gate oxide insulating layer is formed in the word line trench, and the gate oxide insulating layer covers the trench wall surface.

[0146] Step S500C: Perform a second ion doping on at least a portion of the sidewalls of the gate oxide insulating layer to form a second ion-doped region.

[0147] In this step, such as Figure 21 As shown, the second ion doping is performed using the sidewalls of the gate oxide insulating layer 70 as the doping target, as follows: Figure 22 As shown, a portion of the gate oxide insulating layer 70 constitutes a second ion-doped region 40. As an example, an ion implantation process can be used to implant ions into a predetermined region of the gate oxide insulating layer 70. By adjusting the implantation angle and implantation dose, highly electronegative dopant ions are implanted onto the sidewalls of the gate oxide insulating layer 70 to form a second ion-doped region 40 in the predetermined region. Ion implantation allows for the implantation of ions into a specific region, making the implantation area controllable and ensuring the accurate positioning of the formed second ion-doped region 40.

[0148] Specifically, when performing second ion doping on at least a portion of the sidewalls of the gate oxide insulating layer 70, the implantation dose of the dopant ions for the second ion doping is 10E14 per square centimeter to 30E14 per square centimeter, and the implantation energy of the dopant ions for the second ion doping is 5 keV to 10 keV. This ensures that the formed second ion doped region 40 has sufficiently high resistance without compromising structural reliability, thereby forming effective isolation between the word line structure 50 and the first ion doped region 21 and further preventing leakage problems.

[0149] Step S600C: A metal protective layer is formed on the gate oxide insulating layer, the metal protective layer covering part of the gate oxide insulating layer, and the top of the metal protective layer being lower than the top of the gate oxide insulating layer.

[0150] Step S700C: Fill the space enclosed by the metal protective layer with the gate conductive layer. The gate conductive layer and the metal protective layer constitute a word line structure.

[0151] Step S800C: A dielectric layer is formed on the word line structure, which fills the word line grooves.

[0152] The semiconductor structure obtained through the above steps is as follows: Figure 23 As shown.

[0153] Steps S100C, S200C, and S300C are similar to the aforementioned steps S100, S200, and S300, respectively. Steps S400C, S600C, S700C, and S800C are similar to the aforementioned steps S500A, S600A, S700A, and S800A, respectively. For details, please refer to the preceding descriptions, which will not be repeated here.

[0154] In this embodiment, the gate oxide insulating layer 70 can be doped, or the gate oxide insulating layer 70 and a portion of the first doped region near the gate oxide insulating layer 70 can be doped.

[0155] An exemplary embodiment of this disclosure also provides a semiconductor structure, such as Figure 13 As shown, the semiconductor structure includes a substrate 10, a word line trench 30, and a word line structure 50 disposed within the word line trench 30. The substrate 10 can be a semiconductor substrate, and its material may include one or more of silicon (Si), germanium (Ge), silicon-germanium (GeSi), and silicon carbide (SiC); it may also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it may include other materials, such as gallium arsenide or other III-V group compounds.

[0156] A shallow trench isolation structure 60 is provided on the substrate 10, which isolates multiple active regions 20 within the substrate 10, for example, multiple active regions 20 arranged in an array. Each active region includes a first ion-doped region 21, formed by first ion doping. The first ion-doped region 21 constitutes the source and drain regions. Depending on the requirements, the dopant ion can be a P-type impurity ion, such as boron (B), gallium (Ga), or indium (In), or an N-type impurity ion, such as phosphorus (P), antimony (Sb), or arsenic (As). The region between the source and drain regions in the active region 20 constitutes a channel region. A word line trench 30 is disposed in the active region, for example, in the channel region.

[0157] The semiconductor structure also includes a second ion-doped region 40, part of which is located between the first ion-doped region 21 and the word line structure 50. The electronegativity of the doped ions in the second ion-doped region 40 is higher than that of the substrate material.

[0158] In this embodiment, a second ion-doped region 40 is provided between the first ion-doped region 21 of the active region 20 and the word line structure 50. The doped ions of the second ion-doped region 40 have high electronegativity, which makes the second ion-doped region 40 have high resistance, thereby increasing the resistance between the first ion-doped region 21 and the word line structure 50, effectively solving the leakage problem and improving the quality and performance of the semiconductor structure.

[0159] In this embodiment, the dopant ions in the second ion doping region 40 can be ions with higher electronegativity. For example, in an embodiment where the substrate 10 is made of silicon, the dopant ions can be carbon and / or germanium, which have higher electronegativity than silicon, thereby effectively improving the resistance of the ion doping region.

[0160] In one embodiment, a portion of the second ion-doped region 40 is located between the first ion-doped region 21 and the word line structure 50, for example as shown in the figure. Figure 13 As shown, the top of the word line structure 50 is lower than the top of the second ion-doped region 40, meaning the top of the second ion-doped region 40 extends beyond the word line structure 50. Conversely, the bottom of the first ion-doped region 21 is higher than the bottom of the second ion-doped region 40, meaning the bottom of the second ion-doped region 40 extends beyond the first ion-doped region 21. This ensures that the second ion-doped region 40 completely covers the junction between the word line structure 50 and the first ion-doped region 21, further preventing leakage current.

[0161] In some embodiments, such as Figure 13 As shown, the second ion-doped region 40 includes at least a portion of the sidewalls of the word line trench 30. The semiconductor structure also includes a gate oxide insulating layer 70, which covers the trench wall surface of the word line trench 30, thereby covering the second ion-doped region 40. The material of the gate oxide insulating layer 70 can be, for example, silicon dioxide, silicon oxynitride, silicon nitride, etc. The gate oxide insulating layer 70 can be a single layer or a multilayer structure. When the gate oxide insulating layer 70 is a multilayer structure, the materials of each gate oxide insulating layer 70 can be the same or different. In other embodiments, such as... Figure 23 As shown, the second ion-doped region 40 includes a portion of the sidewall of the gate oxide insulating layer 70. In yet other embodiments, such as Figure 20 As shown, the second ion-doped region 40 includes at least a portion of the sidewalls of the word line trench 30 and a portion of the sidewalls of the gate oxide insulating layer 70.

[0162] In one embodiment, such as Figure 13 As shown, the word line structure 50 includes a metal protective layer 51 and a gate conductive layer 52. The metal protective layer 51 covers a portion of the sidewalls of the word line trench 30, and the top of the metal protective layer 51 is lower than the top of the word line trench 30. The metal protective layer 51 encloses a space for accommodating the gate conductive material. By providing the metal protective layer 51, the subsequently filled gate conductive material can be protected, and the diffusion of the gate conductive material can be prevented. The material of the metal protective layer 51 can be titanium (Ti), titanium nitride (TiN), etc.

[0163] The gate conductive layer 52 fills the space formed by the metal protective layer 51, thus the gate conductive layer 52 and the metal protective layer 51 together constitute the word line structure 50. The material of the gate conductive layer 52 can be at least one of tungsten (W), copper (Cu), gold (Au), and silver (Ag).

[0164] Continue to refer to Figure 13 The top of the word line structure 50 is lower than the top of the word line trench 30. The semiconductor structure also includes a dielectric layer 80, which fills the word line trench 30. The dielectric layer 80 can be made of materials such as silicon oxide, silicon oxynitride, or silicon nitride. By filling the word line trench 30 with the dielectric layer 80, the surface of the semiconductor structure is planarized, thereby ensuring the flatness of the upper structure of the semiconductor structure.

[0165] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0166] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure.

[0167] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0168] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0169] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0170] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0171] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method for fabricating the semiconductor structure includes: Provide substrate; Multiple shallow trench isolation structures are formed on the substrate to define the active region, and the active region is subjected to first ion doping to form a first ion-doped region; Word line grooves are formed in the active region; A second ion doping process is performed to form a second ion doped region, wherein the electronegativity of the dopant ion in the second ion doping process is higher than that of the substrate material; A word line structure is formed within the word line trench after the formation of the second ion-doped region, with a portion of the second ion-doped region located between the first ion-doped region and the word line structure.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The substrate is made of silicon, and the dopant ions of the second ion doping include carbon and / or germanium.

3. The method for fabricating a semiconductor structure according to claim 1, characterized in that, A portion of the second ion-doped region is located between the first ion-doped region and the word line structure, including: The top of the word line structure is lower than the top of the second ion-doped region, and the bottom of the first ion-doped region is higher than the bottom of the second ion-doped region.

4. The method for fabricating a semiconductor structure according to claim 3, characterized in that, The top of the second ion-doped region is 5nm to 10nm higher than the top of the word line structure, the bottom of the second ion-doped region is 5nm to 10nm lower than the top of the word line structure, and the depth of the second ion-doped region is not less than 15nm.

5. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The second ion-doped region includes at least a portion of the sidewalls of the word line trench, and the process of forming the second ion-doped region by performing second ion doping includes: At least a portion of the sidewalls of the word line trench are subjected to a second ion doping, wherein the implantation dose of the dopant ions in the second ion doping is 15E14 per square centimeter to 40E14 per square centimeter, and the implantation energy of the dopant ions in the second ion doping is 5 keV to 10 keV.

6. The method for fabricating a semiconductor structure according to claim 5, characterized in that, After performing a second ion doping on at least a portion of the sidewalls of the word line trench, the method for fabricating the semiconductor structure further includes: A gate oxide insulating layer is formed in the word line groove, and the gate oxide insulating layer covers the groove wall surface of the word line groove; The process of forming a word line structure within the word line trench after forming the second ion-doped region includes: A metal protective layer is formed on the gate oxide insulating layer, the metal protective layer covering a portion of the gate oxide insulating layer, and the top end of the metal protective layer being lower than the top end of the gate oxide insulating layer; A gate conductive layer is filled within the space enclosed by the metal protective layer, and the gate conductive layer and the metal protective layer constitute the word line structure.

7. The method for fabricating a semiconductor structure according to claim 6, characterized in that, The second ion-doped region further includes at least a portion of the sidewalls of the gate oxide insulating layer, and the second ion doping to form the second ion-doped region before forming a metal protective layer on the gate oxide insulating layer further includes: At least a portion of the sidewalls of the gate oxide insulating layer are subjected to a second ion doping, wherein the implantation dose of the dopant ions in the second ion doping is 10E14 per square centimeter to 30E14 per square centimeter, and the implantation energy of the dopant ions in the second ion doping is 5 keV to 10 keV.

8. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Before performing the second ion doping to form the second ion-doped region, the method for fabricating the semiconductor structure further includes: A gate oxide insulating layer is formed in the word line groove, and the gate oxide insulating layer covers the groove wall surface of the word line groove; The second ion-doped region includes at least a portion of the sidewalls of the gate oxide insulating layer, and the process of forming the second ion-doped region by performing second ion doping includes: At least a portion of the sidewalls of the gate oxide insulating layer are subjected to a second ion doping, wherein the implantation dose of the dopant ions in the second ion doping is 10E14 per square centimeter to 30E14 per square centimeter, and the implantation energy of the dopant ions in the second ion doping is 5 keV to 10 keV.

9. The method for fabricating a semiconductor structure according to claim 8, characterized in that, The process of forming a word line structure within the word line trench after forming the second ion-doped region includes: A metal protective layer is formed on the gate oxide insulating layer, the metal protective layer covering a portion of the gate oxide insulating layer, and the top end of the metal protective layer being lower than the top end of the gate oxide insulating layer; A gate conductive layer is filled within the space enclosed by the metal protective layer, and the gate conductive layer and the metal protective layer constitute the word line structure.

10. A method for fabricating a semiconductor structure according to any one of claims 1 to 9, characterized in that, The top of the word line structure is lower than the top of the word line trench. After forming the word line structure within the word line trench after forming the second ion-doped region, the method for fabricating the semiconductor structure further includes: A dielectric layer is formed on the word line structure, and the dielectric layer fills the word line grooves.

11. A semiconductor structure, characterized in that, The semiconductor structure includes: A substrate having a shallow trench isolation structure thereon, the shallow trench isolation structure defining an active region on the substrate, the active region including a first ion-doped region; The character line groove is disposed in the active area; The character line structure is disposed within the character line groove; The second ion-doped region is partially located between the first ion-doped region and the word line structure, and the electronegativity of the doped ions in the second ion-doped region is higher than that of the substrate material. The word line structure is formed within the word line trench after the formation of the second ion-doped region.

12. The semiconductor structure according to claim 11, characterized in that, The substrate is made of silicon, and the dopant ions include carbon and / or germanium.

13. The semiconductor structure according to claim 11, characterized in that, The top of the second ion-doped region is higher than the top of the word line structure, and the bottom of the first ion-doped region is higher than the bottom of the second ion-doped region.

14. The semiconductor structure according to claim 11, characterized in that, The semiconductor structure also includes: A gate oxide insulating layer that covers the groove wall of the word line trench; The second ion-doped region includes at least a portion of the sidewalls of the word line trench and / or at least a portion of the sidewalls of the gate oxide insulating layer.

15. The semiconductor structure according to claim 14, characterized in that, The word line structure includes: A metal protective layer covers a portion of the sidewall of the gate oxide insulating layer, wherein the top of the metal protective layer is lower than the top of the gate oxide insulating layer; The gate conductive layer fills the space enclosed by the metal protective layer.

16. The semiconductor structure according to any one of claims 11 to 15, characterized in that, The top of the word line structure is lower than the top of the word line trench, and the semiconductor structure further includes a dielectric layer that fills the word line trench.

Images