Semiconductor device and semiconductor memory device

Abstract

Embodiments provide a semiconductor device and a semiconductor memory device capable of providing a protection circuit having a suitable layout. A semiconductor device of an embodiment includes a substrate, a plurality of electrode layers, and first to third plugs. The substrate has first and second diffusion layers. The plurality of electrode layers is provided above the substrate and separated from each other in a first direction perpendicular to a surface of the substrate. The first plug is provided in the plurality of electrode layers. The second plug is disposed at a position overlapping the first diffusion layer in a plan view and electrically connected to the first diffusion layer. The third plug is disposed at a position not overlapping the first diffusion layer in the plan view and electrically connected to the first diffusion layer. One of the first and second diffusion layers functions as an anode layer of an ESD protection circuit, and the other of the first and second diffusion layers functions as a cathode layer of the ESD protection circuit.

Description

[0001] [Related Applications]

[0002] This application claims priority to Japanese Patent Application No. 2021-35502 (filed on March 5, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device and a semiconductor memory device. Background Technology

[0004] When designing the layout of ESD (electrostatic discharge) protection circuits within semiconductor devices, it is ideal to use a suitable layout that can reduce surge path resistance or pin capacitance, for example. Summary of the Invention

[0005] The embodiments provide a semiconductor device and a semiconductor memory device capable of having a protection circuit with a suitable layout.

[0006] The semiconductor device of this embodiment includes a substrate, a plurality of electrode layers, and first to third plugs. The substrate has first and second diffusion layers. The plurality of electrode layers are disposed above the substrate and separated from each other in a first direction perpendicular to the substrate surface. The first plug is disposed within the plurality of electrode layers. The second plug is disposed at a position overlapping the first diffusion layer in plan view and is electrically connected to the first diffusion layer. The third plug is disposed at a position not overlapping the first diffusion layer in plan view and is electrically connected to the first diffusion layer. One of the first and second diffusion layers functions as an anode layer of an ESD protection circuit, and the other of the first and second diffusion layers functions as a cathode layer of an ESD protection circuit. Attached Figure Description

[0007] Figure 1 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0008] Figure 2 This is another cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0009] Figure 3 This is another cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0010] Figure 4 This is a top view showing the structure of the semiconductor device of the comparative example of the first embodiment.

[0011] Figure 5 This is a top view showing the structure of the semiconductor device according to the first embodiment.

[0012] Figure 6 This is another cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0013] Figure 7 This is a top view showing the structure of the semiconductor device according to the second embodiment.

[0014] Figure 8 This is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment.

[0015] Figure 9 This is a top view showing the structure of the semiconductor device according to the third embodiment.

[0016] Figure 10 This is a cross-sectional view showing the structure of the semiconductor device according to the third embodiment. Detailed Implementation

[0017] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Figures 1-10 In Chinese, the same symbol is used to mark the same components, and repeated explanations are omitted.

[0018] (First Embodiment)

[0019] Figure 1 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0020] Figure 1 The semiconductor device includes a substrate 1, multiple transistors 2, an interlayer insulating film 3, a multilayer wiring section 4, a source layer 5, multiple electrode layers 6, multiple columnar sections 7, a multilayer wiring section 8, and an insulating film 9. Figure 1 Semiconductor devices, for example, have three-dimensional memory.

[0021] Substrate 1 is, for example, a semiconductor substrate such as a silicon substrate. Figure 1 The X and Y directions, which are parallel to and perpendicular to the surface of substrate 1, and the Z direction, which is perpendicular to the surface of substrate 1, are shown. In this specification, the +Z direction is treated as the upward direction, and the -Z direction as the downward direction. The -Z direction may or may not align with the direction of gravity. The Z direction is an example of the first direction, the Y direction is an example of the second direction, and the X direction is an example of the third direction.

[0022] The substrate 1 includes a plurality of diffusion layers 1a. These diffusion layers 1a are formed within the substrate 1 near the surface of the substrate 1. These diffusion layers 1a function, for example, as the source or drain region of the transistor 2. Additionally, as described below, these diffusion layers 1a function as the anode or cathode layer of a diode constituting an ESD protection circuit.

[0023] Transistor 2 includes a gate insulating film 2a and a gate electrode 2b sequentially formed on substrate 1. The gate insulating film 2a is, for example, a silicon oxide film. The gate electrode 2b is, for example, a polysilicon layer. Transistor 2 controls, for example, the operation of a memory cell array of a three-dimensional memory.

[0024] An interlayer insulating film 3 is formed on the substrate 1, covering the transistor 2. The interlayer insulating film 3 may include, for example, a silicon oxide film or other insulating films. A multilayer wiring portion 4, a source layer 5, an electrode layer 6, a pillar-shaped portion 7, a multilayer wiring portion 8, and an insulating film 9 are formed within the interlayer insulating film 3.

[0025] The multilayer wiring section 4 includes multiple wiring layers and multiple plugs electrically connected to these wiring layers. In this embodiment, the multilayer wiring section 4 has, sequentially above the substrate 1, a wiring layer containing multiple wirings 21, a wiring layer containing multiple wirings 22, and a wiring layer containing multiple wirings 23. Furthermore, the multilayer wiring section 4 of this embodiment includes multiple plugs 11 electrically connecting the substrate 1 or transistor 2 to the wirings 21, multiple plugs 12 electrically connecting the wirings 21 and 22, and multiple plugs 13 electrically connecting the wirings 22 and 23. These plugs 11 to 13 are contact plugs or dielectric plugs.

[0026] The source layer 5 is formed above the multilayer wiring portion 4. The source layer 5 includes, for example, at least one of a semiconductor layer such as a polysilicon layer and a metal layer such as a tungsten layer.

[0027] Electrode layer 6 is formed above source layer 5 and is separated from each other in the Z direction. In this embodiment, electrode layer 6 above source layer 5 sequentially includes source-side select line 6a, multiple word lines 6b, and drain-side select line 6c. Electrode layer 6 includes, for example, a metal layer such as a tungsten layer. Electrode layers 6 are separated from each other via an insulating film such as a silicon oxide film. Figure 1 The figure shows the insulating film as part of the interlayer insulating film 3.

[0028] The columnar portion 7 is formed on the source layer 5 within the electrode layer 6. The columnar portion 7 includes a memory insulating film 7a and a channel semiconductor layer 7b sequentially formed within the electrode layer 6. The memory insulating film 7a may include, for example, a barrier insulating film (e.g., silicon oxide film), a charge storage layer (e.g., silicon nitride film), and a tunnel insulating film (e.g., silicon oxide film) sequentially formed within the electrode layer 6. The channel semiconductor layer 7b is, for example, a polysilicon layer. The channel semiconductor layer 7b is electrically connected to the source layer 5. The columnar portion 7 may further include a core insulating film (e.g., silicon oxide film) formed within the channel semiconductor layer 7b. In this embodiment, the electrode layer 6 and the columnar portion 7 constitute a memory cell array of a three-dimensional memory.

[0029] The multilayer wiring section 8 includes multiple wiring layers and multiple plugs electrically connected to these wiring layers. In this embodiment, the multilayer wiring section 8 has, sequentially above the electrode layer 6, a wiring layer including multiple wirings 24, a wiring layer including multiple wirings 25, and a wiring layer including multiple wirings 26. Furthermore, the multilayer wiring section 8 of this embodiment includes multiple plugs 14 electrically connecting the electrode layer 6 or wirings 23 to wirings 24, multiple plugs 15 electrically connecting the pillar portion 7 (channel semiconductor layer 7b) or wirings 24 to wirings 25, and plugs 16 electrically connecting wirings 25 to wirings 26. These plugs 14 to 16 are contact plugs or interlayer plugs. Wirings 25 include, for example, bit lines.

[0030] An insulating film 9 is formed on the side of the plug 14 that electrically connects the wiring 23 of the multilayer wiring section 4 to the wiring 24 of the multilayer wiring section 8. For example... Figure 1 As shown, the plug 14 is disposed within and penetrates the plurality of electrode layers 6. This plug 14 is an example of a first plug. Furthermore, an insulating film 9 is disposed between the plug 14 and the electrode layers 6, electrically insulating the plug 14 from the electrode layers 6. The insulating film 9 is, for example, a silicon oxide film.

[0031] Figure 2 This is another cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0032] Figure 2 The diagram illustrates the structure of plugs 11-16 and wiring 21-26 within regions R1 and R2 of the semiconductor device according to this embodiment. Region R1 includes... Figure 1 The three-dimensional memory is shown. Region R2 contains the ESD protection circuitry for this three-dimensional memory. Figure 2 This further shows multiple plugs 15', multiple plugs 17, and multiple wiring 27.

[0033] Symbol P1 indicates the columnar portion 7, and the plugs 15' and 15' associated with the columnar portion 7, as well as the wiring 25. Hereinafter, the structure represented by symbol P1 will be denoted as structure P1. For example... Figure 2 As shown, the columnar portion 7 is disposed within region R1, including a lower columnar portion 7L on the source layer 5 and an upper columnar portion 7U on the lower columnar portion 7L. The structure P1 includes, in sequence, a plug 15', a plug 15, and a wiring 25 on the upper columnar portion 7U. This wiring 25 functions as a bit line.

[0034] Symbol P2 shows the plug 14 that electrically connects the multilayer wiring section 4 and the multilayer wiring section 8, and the plugs 11, 12, 13, 15', 15, 16, 17 associated with the plug 14, and the wirings 21, 22, 23, 25, 26, 27. Hereinafter, the structure represented by symbol P2 will be referred to as structure P2. In structure P2, the illustration of wiring 24 is omitted. Figure 2As shown, configuration P2 is disposed within region R1 and sequentially includes plug 11, wiring 21, plug 12, wiring 22, plug 13, wiring 23, plug 14, (wiring 24), plug 15', plug 15, wiring 25, plug 16, wiring 26, plug 17, and wiring 27 on substrate 1. As described above, plug 14 in configuration P2 is an example of the first plug.

[0035] Furthermore, the constituent elements of structure P2 are interconnected. Figure 2 The plugs may be formed within the same XZ section, but they may not be formed within the same XZ section. For example, the plug 17 constituting P2 may be formed directly above the plug 11 constituting P2, or it may be positioned offset from the position directly above the plug 11 constituting P2.

[0036] Symbol P3 indicates plugs 11, 12, 13, 14, 15, 16, 17 and wiring 21, 22, 23, 25, 26, 27 related to the ESD protection circuit. Hereinafter, the configuration represented by symbol P3 will be referred to as configuration P3. In configuration P3, the diagram of wiring 24 is omitted. (See diagram for example.) Figure 2 As shown, configuration P3 is disposed within region R2 and sequentially includes plug 11, wiring 21, plug 12, wiring 22, plug 13, wiring 23, plug 14, (wiring 24), plug 15, wiring 25, plug 16, wiring 26, plug 17, and wiring 27 on substrate 1. Plug 14 in configuration P3 is an example of the second plug.

[0037] Furthermore, the constituent elements of structure P3 are interconnected. Figure 2 The plugs may be formed within the same XZ section, but they may not be formed within the same XZ section. For example, the plug 17 constituting P3 may be positioned directly above the plug 11 constituting P3, or it may be positioned offset from the position directly above the plug 11 constituting P3.

[0038] The length of the plug 14 in the Z direction in structure P3 differs from the length of the plug 14 in the Z direction in structure P2 by the amount of the plug 15' in structure P2. However, the plug 14 in structure P2 and the plug 14 in structure P3 are arranged at the same height, that is, arranged in a manner that cuts through the same XY cross section. Figure 1 and Figure 2 In this context, plugs positioned at the same height are represented by the same symbol. For example... Figure 1In this design, the plug 14 within the electrode layer 6 (the plug 14 within structure P2) and the plug 14 on the electrode layer 6 are represented by the same symbol "14". In other words, the plug 14 within the electrode layer 6 (the plug 14 within structure P2) is positioned to the side of the plug 14 on the electrode layer 6. The same applies to the plug 14 within structure P3. Furthermore, the Z-direction length of the plug 14 within structure P2 and the Z-direction length of the plug 14 within structure P3 are longer than the Z-direction length of the columnar portion 7 within structure P1.

[0039] In this embodiment, the plug 14 in structure P3 is formed in the same steps as the plug 14 in structure P2. Therefore, the Z-direction length of the plug 14 in structure P3 is the same as that of the plug 14 in structure P2. Therefore, for the ESD protection circuit of this embodiment, there is a concern that the resistance of the plug 14 in structure P3 may increase. A solution to this problem will be described below.

[0040] Figure 2 The following describes the insulating films 3a, 3b, 3c, 3d, and 3e comprising the interlayer insulating film 3 sequentially formed on the substrate 1. Insulating films 3a, 3c, and 3e may comprise, for example, silicon oxide films or other insulating films. Insulating film 3b may be, for example, a barrier SiN film (silicon nitride film), formed at a height close to the lower end of the plug 14 within structure P3. Insulating film 3d may be, for example, an etch-stopping SiN film, formed at a height close to the upper end of the plug 14 within structure P3.

[0041] Figure 3 This is another cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0042] Figure 3 The structure of the ESD protection circuit within the semiconductor device of this embodiment is shown. The semiconductor device of this embodiment includes a plurality of anode layers 31 and a cathode layer 32 as a diffusion layer 1a for the ESD protection circuit. The anode layer 31 and cathode layer 32 of this embodiment have the following characteristics: Figure 5 The shapes shown are as follows. That is, the anode layer 31 has a rectangular planar shape, and the cathode layer 32 has a trapezoidal planar shape (see reference). Figure 5 ). Figure 3 The diagram shows two of the plurality of anode layers 31 and two portions constituting the single cathode layer 32. Furthermore, the semiconductor device of this embodiment may also include a plurality of anode layers 31 and a plurality of cathode layers 32.

[0043] The anode layer 31 and the cathode layer 32 are formed in the substrate 1 near the surface of the substrate 1. The anode layer 31 is, for example, P. + Impurity diffusion layer. Cathode layer 32, for example, is N. +Impurity diffusion layer. Anode layer 31 and cathode layer 32 constitute diode D for ESD protection circuit. One of anode layer 31 and cathode layer 32 is an example of a first diffusion layer, and the other of anode layer 31 and cathode layer 32 is an example of a second diffusion layer.

[0044] like Figure 3 As shown, the semiconductor device of this embodiment further includes plugs 11, 21, 12, 22, 13, 23, 14, 24, 15, 25, 16, and 26 sequentially formed on the anode layer 31 and the cathode layer 32. Each of these plugs 11 to 16 or each of these wires 21 to 26 is electrically connected to the anode layer 31 or the cathode layer 32. Figure 2 The structure P3 shown contains Figure 3 The plugs 11-16 and wiring 21-26 are shown. As described above, Figure 3 The plug 14 shown is an example of the second plug.

[0045] According to this embodiment, this ESD protection circuit can protect the three-dimensional memory, which is the protected circuit, from electrostatic discharge. The ESD protection circuit is an example of a protection circuit.

[0046] Next, refer to Figure 4 and Figure 5 The semiconductor device of this embodiment is compared with the semiconductor device of a comparative example. Furthermore, Figures 1-3 The structure shown is in Figure 4 The semiconductor device of the comparative example shown is similar to Figure 5 The semiconductor device shown in this embodiment is common to all other semiconductor devices.

[0047] Figure 4 This is a top view showing the structure of the semiconductor device of the comparative example of the first embodiment.

[0048] Figure 4 The layout of the plug 14, wiring 26, anode layer 31 and cathode layer 32 of this comparative example is shown. Figure 4 In the diagram, the shape of wiring 26 is represented by dashed lines, and the shapes of anode layer 31 and cathode layer 32 are represented by solid lines. Figure 3 Show along Figure 4 The XZ section of line A-A' is shown.

[0049] As described above, the semiconductor device of this comparative example includes a plurality of anode layers 31 and a cathode layer 32. These anode layers 31 extend in the Y direction and are adjacent to each other in the X direction, separating the cathode layer 32. On the other hand, the cathode layer 32 includes a plurality of portions 32a extending in the Y direction, a portion 32b extending in the X direction, and a portion 32c extending in the X direction. The plurality of portions 32a are adjacent to each other in the X direction, separating the anode layers 31. Portion 32b is connected to the -Y direction end of each portion 32a, and portion 32c is connected to the +Y direction end of each portion 32a. Portions 32a, 32b, and 32c are examples of the first, second, and third portions, respectively.

[0050] In this comparative example, the anode layer 31 has a rectangular planar shape extending in the Y direction. On the other hand, the cathode layer 32 has a trapezoidal planar shape extending in the X direction and has multiple openings. The anode layer 31 is formed within the cathode layer 32 in a shape that accommodates these openings. Therefore, the anode layer 31 is surrounded by the cathode layer 32 when viewed from above. In this comparative example, each anode layer 31 is electrically connected to an I / O (input / output) pin of the semiconductor device, and the cathode layer 32 is electrically connected to the VCC power supply line of the semiconductor device.

[0051] In this comparative example, the wiring 26 extends in the Y direction and is adjacent to each other in the X direction. As described above, these wirings 26 are disposed within the same wiring layer and electrically connected to the plug 14. In this comparative example, each wiring 26 is disposed above an anode layer 31 or above a portion 32a.

[0052] In this comparative example, the plug 14 is positioned directly above the anode layer 31 or portion 32a. That is, the plug 14 in this comparative example is positioned to overlap with the anode layer 31 or portion 32a in the Z direction. Therefore, Figure 4 The plug 14 shown is positioned within the solid lines representing the shape of each anode layer 31, or between the solid lines representing the shape of each portion 32a. However, in this comparative example, the plug 14 is not positioned directly above portion 32b or portion 32c. That is, the plug 14 in this comparative example is not positioned in the Z-direction to overlap with portion 32b or portion 32c. Furthermore, the plug 14 in this comparative example is not positioned in the Z-direction to not overlap with the anode layer 31 and the cathode layer 32.

[0053] Figure 5 This is a top view showing the structure of the semiconductor device according to the first embodiment.

[0054] Figure 5 and Figure 4Similarly, the layout of the plug 14, wiring 26, anode layer 31, and cathode layer 32 in this embodiment is shown. The layout of the wiring 26, anode layer 31, and cathode layer 32 in this embodiment is the same as that in the comparative example. In this embodiment, each anode layer 31 is electrically connected to the I / O pin of the semiconductor device, and the cathode layer 32 is electrically connected to the VCC power supply wiring of the semiconductor device.

[0055] In this embodiment, the plug 14 is disposed not only directly above the anode layer 31 or portion 32a, but also directly above portion 32b or portion 32c. That is, the plug 14 in this embodiment is disposed not only at a position overlapping the anode layer 31 or portion 32a in the Z direction, but also at a position overlapping the portion 32b or portion 32c in the Z direction. Furthermore, the plug 14 in this embodiment is also disposed at a position in the Z direction that does not overlap with the anode layer 31 and the cathode layer 32. For example, in... Figure 5 In the planar configuration shown, the plug 14 of this embodiment is also disposed in the -Y direction of part 32b or the +Y direction of part 32c.

[0056] Furthermore, in the semiconductor device of this embodiment, the layer represented by symbol 31 may be designated as a "cathode layer" and the layer represented by symbol 32 may be designated as an "anode layer". In this case, the cathode layer may also be electrically connected to the VSS power supply wiring of the semiconductor device.

[0057] Here, we will try to be more specific about... Figure 5 The semiconductor device shown in this embodiment and Figure 4 The semiconductor devices shown in the comparative examples are compared.

[0058] Figure 1 In the illustrated three-dimensional memory, if the number of word lines 6b is increased to increase the memory capacitance, the Z-direction length of the plug 14 within the electrode layer 6 (the plug 14 within structure P2) will increase. Consequently, the Z-direction length of the plug 14 in the ESD protection circuit (the plug 14 within structure P3) will also increase. Therefore, the total length of the contact plugs or dielectric plugs from the bonding pads of the semiconductor device to the anode layer 31 and cathode layer 32 of the ESD protection circuit, i.e., the contact length, will increase.

[0059] Increasing contact length leads to increased contact resistance in surge paths, decreased contact fuse withstand voltage, or increased parasitic capacitance between adjacent plugs. Since these plugs serve as the main paths for ESD (electrostatic discharge) paths, the number of plugs in ESD paths tends to increase with increasing memory capacitance. On the other hand, in most cases, even with increased memory capacitance, the areas of the anode layer 31 and cathode layer 32 do not increase. In recent years, the interfaces of 3D memories have become increasingly faster, and based on this perspective, it is also necessary to reduce I / O pin capacitance by reducing parasitic capacitance.

[0060] Comparative example ( Figure 4 In order to guide the surge... Figure 3 The diode D is shown, and a plug 14 is positioned directly above the anode layer 31 or portion 32a. However, the area of ​​the anode layer 31 or portion 32a is limited, so when the number of plugs 14 increases, a sufficient number of plugs 14 cannot be positioned directly above the anode layer 31 or portion 32a. Furthermore, reducing the I / O pin capacitance requires reducing the number of diodes D, which also limits the area of ​​the anode layer 31 or portion 32a. Therefore, in the comparative example, a sufficient number of plugs 14 cannot be positioned, resulting in a higher resistance of the plugs 14. Since the Z-direction length of the plug 14 is relatively long, the resistance of the plug 14 has a significant impact on the contact resistance.

[0061] Therefore, in this embodiment, the plug 14 is disposed not only directly above the anode layer 31 or portion 32a, but also directly above portions 32b or 32c. Furthermore, the plug 14 in this embodiment is disposed at a position in the Z direction that does not overlap with the anode layer 31 and the cathode layer 32. Thus, a sufficient number of plugs 14 can be disposed, thereby reducing the resistance of the plugs 14. In this embodiment, a sufficient number of plugs 14 can be disposed even without increasing the area of ​​the anode layer 31 or portion 32a. In this way, according to this embodiment, the area other than directly above the anode layer 31 or portion 32a is also used as a plug placement area, thereby enabling a suitable layout of the ESD protection circuit that can reduce surge path resistance or pin capacitance.

[0062] Furthermore, the plug 14 of this embodiment may be positioned at any one of the following locations: overlapping with portion 32b or portion 32c in the Z direction, or not overlapping with the anode layer 31 and the cathode layer 32 in the Z direction. Additionally, the plug 14 of this embodiment may be positioned at any one of the following locations: overlapping with portion 32b in the Z direction, or overlapping with portion 32c in the Z direction. Furthermore, the cathode layer 32 of this embodiment may have both portion 32b and portion 32c, or may have only one of portion 32b and portion 32c.

[0063] and then, Figure 3 The ESD protection circuit shown can prevent surges from being directed to... Figure 3 All diodes D shown can also direct the surge only to Figure 3 A portion of diode D is shown. For example, in order to use... Figure 3 The right-side anode layer 31 shown is not used. Figure 3 The left anode layer 31 shown can also be configured not to be electrically connected to the surge path. In this case, the surge will not be directed to the diode D of the left anode layer 31. In this embodiment, N anode layers 31 adjacent to each other in the X direction can also be used every other N, instead of just N / 2 anode layers 31 (N is a positive integer).

[0064] Figure 6 This is another cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0065] Figure 6 Show along Figure 5 The YZ section of line B-B' is shown. Figure 6 The diagram shows plugs 11-16, wiring 21-26, anode layer 31, cathode layer 32, etc. In this embodiment, as... Figure 6 As shown, not only is plug 14 configured in a wide range, but plugs 11, 12, 13, 15, and 16 are also configured in a wide range. This significantly reduces the contact resistance of plugs 11 to 16.

[0066] As described above, the plug 14 in this embodiment is disposed not only directly above the anode layer 31 or portion 32a, but also directly above portion 32b or portion 32c. Furthermore, the plug 14 in this embodiment is also disposed at a position in the Z direction that does not overlap with the anode layer 31 and the cathode layer 32. Therefore, according to this embodiment, a suitably arranged ESD protection circuit can be provided within the semiconductor device.

[0067] (Second Implementation)

[0068] Figure 7 This is a top view showing the structure of the semiconductor device according to the second embodiment.

[0069] Figure 7 and Figure 5 Similarly, the layout of the plug 14, wiring 26, anode layer 31, and cathode layer 32 of this embodiment is shown. The semiconductor device of this embodiment will be described focusing on its differences from the semiconductor device of the first embodiment, and descriptions of commonalities with the semiconductor device of the first embodiment will be omitted as appropriate.

[0070] Figure 7 Two wirings, 26, are shown.

[0071] A wiring 26 includes a plurality of regions 26a extending in the Y direction above the anode layer 31, and a region 26b extending in the X direction above portions 32b, etc. In this wiring 26, the plurality of regions 26a are adjacent to each other in the X direction, and the region 26b is connected to the -Y direction end of each region 26a. This wiring 26 is an example of a first wiring, and regions 26a and 26b of this wiring 26 are examples of the first and second regions, respectively.

[0072] Another wiring 26 includes a plurality of regions 26a extending in the Y direction above portion 32a, and a region 26b extending in the X direction above portion 32c, etc. In this wiring 26, the plurality of regions 26a are adjacent to each other in the X direction, and the region 26b is connected to the +Y direction end of each region 26a. This wiring 26 is an example of a second wiring, and regions 26a and 26b of this wiring 26 are examples of the third and fourth regions, respectively.

[0073] These wirings 26 all have a comb-shaped planar shape extending in the X direction. Region 26b of one wiring 26 and region 26b of another wiring 26 are arranged on opposite sides of regions 26a of these wirings 26, that is, arranged in the -Y direction and +Y direction of regions 26a of these wirings 26, respectively.

[0074] In this embodiment, the area of ​​region 26b of these wirings 26 can be set to be relatively large. As a result, multiple plugs 14 electrically connected to region 26b can be arranged below region 26b, thereby further reducing surge path resistance or pin capacitance.

[0075] Figure 8 This is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment.

[0076] Figure 8 Show along Figure 7 The YZ section of line B-B' is shown. Figure 8 The diagram shows plugs 11-16, wiring 21-26, anode layer 31, cathode layer 32, etc. In this embodiment, as... Figure 8 As shown, not only is plug 14 disposed over a wide range, but plugs 11, 12, 13, 15, and 16 are also disposed over a wide range. This significantly reduces the contact resistance of plugs 11-16. Symbols K1 and K2 indicate the breaks in wirings 21-26. In this embodiment, one wiring 21-26 can be used for the anode layer 31, and the other wiring 21-26 can be used for the cathode layer 32.

[0077] Figure 8In this configuration, the breaks in wirings 21-26 are formed approximately directly above the +Y direction end of the anode layer 31. Alternatively, the breaks in wirings 21-25 can be formed approximately directly above the +Y direction end of the anode layer 31, and the break in wiring 26 can be formed approximately directly above the -Y direction end of the anode layer 31. In other words, the break in wiring 26 can also be formed at a position offset from directly above the breaks in wirings 21-25. This reduces the wiring resistance of wiring 26.

[0078] According to this embodiment, similarly to the first embodiment, a suitably arranged ESD protection circuit can be placed within the semiconductor device.

[0079] (Third Implementation)

[0080] Figure 9 This is a top view showing the structure of the semiconductor device according to the third embodiment.

[0081] Figure 9 and Figure 5 and Figure 7 Similarly, the layout of the plug 14, wiring 26, anode layer 31, and cathode layer 32 of this embodiment is shown. The semiconductor device of this embodiment will be described focusing on its differences from the semiconductor devices of the first and second embodiments, and descriptions of commonalities with the semiconductor devices of the first and second embodiments will be appropriately omitted.

[0082] Figure 9 Two wirings, 26, are shown.

[0083] A wiring 26 is disposed in the Z direction of the anode layer 31, portions 32a and 32b, and has a rectangular planar shape. This wiring 26 is an example of a first wiring. Another wiring 26 is disposed in the Z direction of portion 32c and has a rectangular planar shape. This wiring 26 is an example of a second wiring.

[0084] In this embodiment, the area of ​​these wirings 26 can be set to be relatively large. As a result, multiple plugs 14 electrically connected to the wirings 26 can be arranged below them, thereby further reducing surge path resistance or pin capacitance.

[0085] In this embodiment, the plug 14 is positioned directly above portions 32a, 32b, and 32c of the cathode layer 32, or at a location in the Z direction that does not overlap with the anode layer 31 and the cathode layer 32. However, in this embodiment, the plug 14 is not positioned directly above the anode layer 31. This reduces the parasitic capacitance (I / O pin capacitance) between the anode layer 31 and the cathode layer 32. Furthermore, in this embodiment, as described above, multiple plugs 14 can be configured, thus sufficiently reducing surge path resistance even if the plug 14 is not positioned directly above the anode layer 31.

[0086] Figure 10 This is a cross-sectional view showing the structure of the semiconductor device according to the third embodiment.

[0087] Figure 10 Show along Figure 9 The YZ section of line B-B' is shown. Figure 10 The diagram shows plugs 11-16, wiring 21-26, anode layer 31, cathode layer 32, etc. In this embodiment, as... Figure 10 As shown, not only is plug 14 arranged in a wide range, but plugs 11, 12, 13, 15, and 16 are also arranged in a wide range. This significantly reduces the contact resistance of plugs 11-16. Symbols K1 and K2 indicate the breaks in wirings 21-26. In this embodiment, one wiring 21-26 is used for the anode layer 31, and the other wiring 21-26 is used for the cathode layer 32. Figure 10 In this configuration, the wiring 24-26 for the cathode layer 32 is positioned directly above the anode layer 31, thereby reducing the power line resistance.

[0088] According to this embodiment, similarly to the first and second embodiments, a suitably arranged ESD protection circuit can be provided within the semiconductor device.

[0089] Several embodiments have been described above, but these embodiments are provided as examples only and are not intended to limit the scope of the invention. The novel device described in this specification can be implemented in various other forms. Furthermore, various omissions, substitutions, and modifications can be made to the form of the device described in this specification without departing from the spirit of the invention. The scope of the appended claims and their equivalents are intended to encompass such forms or variations as included in the scope or spirit of the invention.

[0090] [Explanation of Symbols]

[0091] 1: Substrate

[0092] 1a: Diffusion layer

[0093] 2: Transistor

[0094] 2a: Gate insulating film

[0095] 2b: Gate electrode

[0096] 3: Interlayer insulating film

[0097] 3a: Insulating film

[0098] 3b: Insulating film

[0099] 3c: Insulating film

[0100] 3d: Insulating film

[0101] 3e: Insulating film

[0102] 4: Multilayer wiring section

[0103] 5: Source Layer

[0104] 6: Electrode layer

[0105] 6a: Source-side selection line

[0106] 6b: Word line

[0107] 6c: Drain-side selection line

[0108] 7: Columnar part

[0109] 7a: Memory insulating film

[0110] 7b: Channel semiconductor layer

[0111] 7L: Lower columnar section

[0112] 7U: Upper columnar part

[0113] 8: Multilayer wiring section

[0114] 9: Insulating film

[0115] 11: Plug

[0116] 12: Plug

[0117] 13: Plug

[0118] 14: Plug

[0119] 15: Plug

[0120] 15': Plug

[0121] 16: Plug

[0122] 17: Plug

[0123] 21: Wiring

[0124] 22: Wiring

[0125] 23: Wiring

[0126] 24: Wiring

[0127] 25: Wiring

[0128] 26: Wiring

[0129] 26a: Area

[0130] 26b: Area

[0131] 27: Wiring

[0132] 31: Anode layer

[0133] 32: Cathode layer

[0134] 32a: Part

[0135] 32b: Partial

[0136] 32c: Partial.

Claims

1. A semiconductor device, characterized in that... include: Substrate, located in layer 1; The source line is located in the second layer above the first layer in a first direction perpendicular to the surface of the substrate; Multiple character lines are disposed in the third layer above the second layer in the first direction, and the multiple character lines are separated from each other in the first direction; The first plug extends through the plurality of word lines in the third layer and is electrically connected to the source line; the plurality of memory cells are disposed between the cross-section of the plurality of word lines and the first plug. The first and second diffusion layers are separately disposed in the substrate in the first layer. One of the first and second diffusion layers functions as the anode layer of the ESD protection circuit, and the other of the first and second diffusion layers functions as the cathode layer of the ESD protection circuit. The second plug is disposed in the second and third layers and overlaps with the first diffusion layer in the first direction, and the second plug is electrically connected to the first diffusion layer; The third plug is disposed in the second and third layers and in a position that does not overlap with the first and second diffusion layers in the first direction, and the third plug is electrically connected to the first diffusion layer; The fourth plug is disposed in the second and third layers and at a position overlapping the second diffusion layer in the first direction, and the fourth plug is disposed between the second plug and the third plug in the second direction intersecting the first direction; Multiple wirings are disposed in a fourth layer between the first layer and the second layer, and the multiple wirings are electrically connected to the third plug and the first diffusion layer which is electrically connected to the second plug; The first upper layer wiring is disposed above the third layer in the first direction and is electrically connected to the second plug and the third plug; as well as The second upper-layer wiring is positioned above the third layer in the first direction, electrically connected to the fourth plug, but not electrically connected to the first upper-layer wiring; and The first plug, the second plug, the third plug, and the fourth plug are disposed in the third layer.

2. The semiconductor device according to claim 1, characterized in that: The first plug, the second plug, and the third plug extend in the first direction; and The third plug is positioned in the first direction at a location overlapping the second diffusion layer.

3. The semiconductor device according to claim 1, characterized in that: The first plug, the second plug, and the third plug extend in the first direction; and The third plug is positioned in the first direction at a location that does not overlap with the first and second diffusion layers.

4. The semiconductor device according to claim 1, characterized in that: In a plane perpendicular to the first direction, the first diffusion layer is surrounded by the second diffusion layer.

5. The semiconductor device according to claim 4, characterized in that: The first diffusion layer has a first diffusion region and a second diffusion region; and In the plane perpendicular to the first direction, the first diffusion region and the second diffusion region are surrounded by the second diffusion layer.

6. The semiconductor device according to claim 5, characterized in that: The first diffusion region and the second diffusion region extend in the second direction parallel to the surface of the substrate, and are separately disposed in the third direction parallel to the surface of the substrate and different from the second direction, and the first diffusion region and the second diffusion region are respectively surrounded by the second diffusion layer.

7. The semiconductor device according to claim 1, characterized in that: The first diffusion layer extends in a second direction parallel to the surface of the substrate; and The second diffusion layer includes a first portion extending in the second direction, and includes at least one of a second portion and a third portion, the second portion being connected to one end of the first portion and extending in a third direction parallel to the surface of the substrate and different from the second direction, the third portion being connected to the other end of the first portion and extending in the third direction.

8. The semiconductor device according to claim 7, characterized in that: The fourth plug is electrically connected to the second diffusion layer; The third plug extends in the first direction and is positioned in the first direction overlapping the first portion of the second diffusion layer; and The fourth plug extends in the first direction and is positioned in the first direction at a location that overlaps with the second portion or the third portion of the second diffusion layer.

9. The semiconductor device according to claim 7, characterized in that: The second diffusion layer also has a fourth portion, which is connected to the second portion and the third portion and extends in the second direction.

10. The semiconductor device according to claim 9, characterized in that: The first part and the fourth part are separately arranged in the third direction.

11. The semiconductor device according to claim 7, characterized in that... Also includes: The first wiring is disposed above the second plug in the first direction and is electrically connected to the second plug; as well as The second wiring is disposed above the third plug in the first direction and is electrically connected to the third plug.

12. The semiconductor device according to claim 11, characterized in that: The first wiring and the second wiring extend in the second direction and are separated in the third direction.

13. The semiconductor device according to claim 11, characterized in that: The first wiring includes: a first region extending in the second direction; and a second region connected to one end of the first region and extending in the third direction.

14. The semiconductor device according to claim 13, characterized in that: The second wiring includes: a third region extending in the second direction; and a fourth region connected to one end of the third region and extending in the third direction; and The fourth region is located on the opposite side of the second region, relative to the first and third regions.

15. The semiconductor device according to claim 11, characterized in that: The first wiring overlaps with the first diffusion layer, the first portion of the second diffusion layer, and the second portion of the second diffusion layer in the first direction; and The semiconductor device further includes a second wiring that overlaps with the third portion of the second diffusion layer in the first direction.

16. The semiconductor device according to claim 11, characterized in that... Also includes: The third wiring is disposed between the substrate and the second plug in the first direction and is electrically connected to the second plug; as well as A fourth wiring is disposed in the first direction between the substrate and the third plug, and is electrically connected to the third plug; and The plurality of word lines have a first word line, which is disposed above the third and fourth wiring lines in the first direction; The plurality of word lines have a second word line, which is disposed in the first direction between the first word line and the first wiring and the second wiring; and The semiconductor device also includes: The fifth wiring is disposed between the second wire and the first and second wires; The sixth wiring is disposed between the first wire, the third wiring, and the fourth wiring; The first plug has: A semiconductor layer extends through the first word line and the second word line, with one end of the semiconductor layer connected to the fifth wiring and the other end of the semiconductor layer connected to the sixth wiring. A first charge storage unit is disposed at the position where the first word line intersects with the semiconductor layer; and The second charge storage unit is located at the intersection of the second word line and the semiconductor layer.

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