One-time hard mask for interconnect formation

Abstract

The present disclosure relates to a disposable hard mask for formation of interconnects. Disclosed herein is an interconnect fabrication method that uses a disposable etch stop hard mask over a gate structure during source / drain contact formation, and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, a dielectric layer having a dielectric constant lower than that of the dielectric layer of the disposable etch stop hard mask) prior to gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a gap, and a dielectric feature disposed over the gate structure, wherein the dielectric feature and the gate structure fill the gap between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and more particularly to disposable hard masks used for interconnect formation. Summary of the Invention

[0002] A first aspect of this disclosure relates to a semiconductor device structure comprising: a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion spaced apart; a gate stack and a gate spacer disposed along the sidewall of the gate stack, wherein the gate stack and the gate spacer fill the gap between a lower portion of the first sidewall CESL portion and a lower portion of the second sidewall CESL portion; and a dielectric feature disposed on the gate stack and the gate spacer, wherein the dielectric feature fills the gap between an upper portion of the first sidewall CESL portion and an upper portion of the second sidewall CESL portion, the dielectric feature comprising a dielectric layer disposed on a dielectric liner between the dielectric layer and the gate spacer, between the dielectric layer and the gate stack, and between the dielectric layer and the CESL.

[0003] A second aspect of this disclosure relates to a semiconductor device structure comprising: a gate structure on a semiconductor layer, wherein the gate structure is located between a first source / drain and a second source / drain in the semiconductor layer; a dielectric feature on a top surface of the gate structure, wherein the width of the dielectric feature is the same as the width of the gate structure, and the dielectric feature includes a fill layer on a liner layer, wherein the liner layer encloses the fill layer and the liner layer is located between the gate structure and the fill layer; and an interlayer dielectric (ILD) layer on the semiconductor layer, wherein the liner layer is located between the fill layer and the ILD layer, and the material of the ILD layer is the same as the material of the fill layer.

[0004] A third aspect of this disclosure relates to a method for forming a semiconductor device, comprising: receiving a device precursor having a gate structure between a first source / drain and a second source / drain, an etch-stop hard mask over the gate structure, a first dielectric layer along a sidewall of the gate structure and along a sidewall of the etch-stop hard mask, and a second dielectric layer over the first dielectric layer; forming source / drain contacts to the first source / drain, wherein the first dielectric layer is between the gate structure and the source / drain contacts and along a sidewall of the etch-stop hard mask and Between the source / drain contacts; a dielectric feature replaces the etch-stop hard mask, the dielectric feature including a bulk dielectric disposed on a dielectric liner, wherein a first dielectric layer is between the dielectric feature and the source / drain contacts, between the first dielectric layer and the second dielectric layer, the dielectric liner is between the first dielectric layer and the bulk dielectric, and the dielectric liner is between the gate structure and the bulk dielectric; and a gate contact is formed extending through the dielectric feature to the gate structure. Background Technology

[0005] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit components and elements. Many integrated circuits are typically fabricated on a single semiconductor wafer, and the individual dies on the wafer are monolithically assembled by sawing along scribe lines between the integrated circuits. The individual dies are typically individually packaged in, for example, multi-chip modules or other types of packages.

[0006] As the semiconductor industry progresses to nanometer technology nodes in pursuit of higher device density, higher performance, and lower costs, challenges arising from manufacturing and design issues have led to the development of three-dimensional designs, such as fin field-effect transistors (FinFETs). FinFETs are fabricated using thin, vertical "fins" (or fin structures) extending from a substrate. The channel of a FinFET is formed within the vertical fin. The gate is provided on top of the fin. Advantages of FinFETs may include reduced short-channel effects and the ability to provide higher current.

[0007] While existing FinFET devices and the methods for manufacturing them are generally sufficient to meet their intended purpose, they are not entirely satisfactory in all respects. Attached Figure Description

[0008] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0009] Figures 1A-1I A perspective view of various stages of forming a FinFET device structure according to some embodiments of the present disclosure is shown.

[0010] Figures 2A-2S Some embodiments of the present disclosure are shown in relation to... Figures 1A-1I Cross-sectional views of the various stages that form the FinFET device structure after the associated stages.

[0011] Figure 3 A cross-sectional view of a FinFET device structure according to some embodiments of the present disclosure is shown.

[0012] Figure 4A and Figure 4B A cross-sectional view of a FinFET device structure according to some embodiments of the present disclosure is shown.

[0013] Figure 5 A cross-sectional view of a FinFET device structure according to some embodiments of the present disclosure is shown.

[0014] Figure 6 A cross-sectional view of a FinFET device structure according to some embodiments of the present disclosure is shown.

[0015] Figure 7 A cross-sectional view of a FinFET device structure according to some embodiments of the present disclosure is shown.

[0016] Figure 8 A cross-sectional view of a FinFET device structure according to some embodiments of the present disclosure is shown.

[0017] Figure 9 A cross-sectional view of a FinFET device structure according to some embodiments of the present disclosure is shown.

[0018] Figures 10A-10B A cross-sectional view of a FinFET device structure according to some embodiments of the present disclosure is shown.

[0019] Figure 11 A cross-sectional view of a FinFET device structure according to some embodiments of the present disclosure is shown.

[0020] Figure 12 A cross-sectional view of a FinFET device structure according to some embodiments of the present disclosure is shown.

[0021] Figure 13 A cross-sectional view of a FinFET device structure according to some embodiments of the present disclosure is shown.

[0022] Figures 14A-14B A cross-sectional view of a FinFET device structure according to some embodiments of the present disclosure is shown.

[0023] Figure 15 A cross-sectional view of a FinFET device structure according to some embodiments of the present disclosure is shown.

[0024] Figure 16 A cross-sectional view of a FinFET device structure according to some embodiments of the present disclosure is shown.

[0025] Figure 17 A cross-sectional view of a FinFET device structure according to some embodiments of the present disclosure is shown.

[0026] Figures 18A-18B A cross-sectional view of a FinFET device structure according to some embodiments of the present disclosure is shown.

[0027] Figure 19 A cross-sectional view of a FinFET device structure according to some embodiments of the present disclosure is shown. Detailed Implementation

[0028] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0029] Some variations of the embodiments are described. In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. It should be understood that additional operations may be provided before, during, and after the method, and some of the described operations may be replaced or eliminated for other embodiments of the method.

[0030] Fins can be patterned using any suitable method. For example, one or more photolithography processes can be used to pattern the fins, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins.

[0031] Examples for forming FinFET device structures are provided. Figures 1A-1I A perspective view is shown of various stages of forming a FinFET device structure 100a according to some embodiments of the present disclosure.

[0032] refer to Figure 1A A substrate 102 is provided. The substrate 102 may be made of silicon or other semiconductor materials. Alternatively or additionally, the substrate 102 may include other elemental semiconductor materials such as germanium. In some embodiments, the substrate 102 is made of a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the substrate 102 is made of an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide. In some embodiments, the substrate 102 includes an epitaxial layer. For example, the substrate 102 has an epitaxial layer on a bulk semiconductor.

[0033] A dielectric layer 104 and a mask layer 106 are formed on a substrate 102, and a photoresist layer 108 is formed on the mask layer 106. The photoresist layer 108 is patterned by a patterning process. The patterning process includes photolithography and etching. The photolithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, and drying (e.g., hard baking). The etching process may include dry etching or wet etching.

[0034] The dielectric layer 104 serves as a buffer layer between the substrate 102 and the mask layer 106. Additionally, the dielectric layer 104 can function as a stop layer when the mask layer 106 is removed. The dielectric layer 104 may be made of silicon oxide. The mask layer 106 may be made of silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials. In some embodiments, more than one mask layer 106 is formed on the dielectric layer 104.

[0035] The dielectric layer 104 and the mask layer 106 are formed by a deposition process, such as chemical vapor deposition (CVD), high-density plasma chemical vapor deposition (HDPCVD), spin coating, sputtering, or other applicable processes.

[0036] like Figure 1B As shown, according to some embodiments, the dielectric layer 104 and the mask layer 106 are patterned by using a patterned photoresist layer 108 as a mask. As a result, a patterned pad layer 104 and a patterned mask layer 106 are obtained. Subsequently, the patterned photoresist layer 108 is removed.

[0037] Next, an etching process is performed on the substrate 102 to form the fin structure 110 by using a patterned dielectric layer 104 and a patterned mask layer 106 as masks. The etching process can be a dry etching process or a wet etching process.

[0038] In some embodiments, a dry etching process is used to etch the substrate 102. The dry etching process includes using a fluorine-based etchant gas, such as SF6 or C. x F y NF3, or a combination thereof. The etching process can be a time-controlled process and continues until the fin structure 110 reaches a predetermined height. In some other embodiments, the fin structure 110 has a width that gradually increases from top to bottom.

[0039] like Figure 1C As shown, according to some embodiments, an insulating layer 112 is formed to cover the fin structure 110 above the substrate 102. In some embodiments, the insulating layer 112 is made of silicon oxide, silicon nitride, silicon oxynitride, fluorinated silicate glass (FSG), low-k dielectric material, or other suitable materials. The insulating layer 112 can be deposited by chemical vapor deposition (CVD), spin-coating glass, or other suitable processes. Subsequently, the insulating layer 112 is thinned or planarized to expose the top surface of the patterned mask layer 106. In some embodiments, the insulating layer 112 is thinned by a chemical mechanical polishing (CMP) process.

[0040] like Figure 1D As shown, according to some embodiments, a portion of the insulating layer 112, the patterned dielectric layer 104, and the patterned mask layer 106 are removed by an etching process. As a result, an isolation structure 114 is obtained. The isolation structure 114 may be a shallow trench isolation (STI) structure surrounding the fin structure 110. The lower portion of the fin structure 110 is surrounded by the isolation structure 114, and the upper portion of the fin structure 110 protrudes relative to the isolation structure 114. In other words, a portion of the fin structure 110 is embedded in the isolation structure 114. The isolation structure 114 prevents electrical interference and crosstalk.

[0041] like Figure 1E As shown, according to some embodiments, a dummy gate structure 120 is formed across the fin structure 110 and extends over the isolation structure 114. In some embodiments, the dummy gate structure 120 includes a dummy gate dielectric layer 116 and a dummy gate electrode layer 118 formed on the dummy gate dielectric layer 116. In some embodiments, the dummy gate dielectric layer 116 comprises silicon oxide, and the dummy gate electrode layer 118 comprises polysilicon. After forming the dummy gate structure 120, a gate spacer layer 122 is formed on the opposite sidewall surface of the dummy gate structure 120. The gate spacer layer 122 may be a single layer or multiple layers.

[0042] To improve the speed of the FinFET device structure 100a, the gate spacer layer 122 is made of a low-k dielectric material. In some embodiments, the low-k dielectric material has a dielectric constant (k value) of less than 4. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bisbenzocyclobutene (BCB), or polyimide.

[0043] In some other embodiments, the gate spacer layer 122 is made of an extremely low-k (ELK) dielectric material having a dielectric constant (k) of less than about 2.5. In some embodiments, the ELK dielectric material includes carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bisbenzocyclobutene (BCB), polytetrafluoroethylene (PTFE) (Teflon), or silicon oxide polymer (SiOC). In some embodiments, the ELK dielectric material includes existing dielectric materials in porous forms, such as hydrogen silsesquioxane (HSQ), porous methyl silsesquioxane (MSQ), porous polyarylene ether (PAE), or porous silicon oxide (SiO2).

[0044] like Figure 1F As shown, according to some embodiments, a source / drain (S / D) structure 124 is formed on the fin structure 110. In some embodiments, a portion of the fin structure 110 adjacent to the dummy gate structure 120 is recessed to form a groove having a bottom formed by the fin structure 110 and sidewalls formed by the isolation structure 114, and a strained material is grown in the groove by an epitaxial (epi) process to form the S / D structure 124. Furthermore, the lattice constant of the strained material may be different from the lattice constant of the substrate 102. In some embodiments, the S / D structure 124 includes Ge, SiGe, InAs, InGaAs, InSb, GaAs, GaSb, InAlP, or InP, etc.

[0045] like Figure 1GAs shown, according to some embodiments, a contact etch stop layer (CESL) 126 is formed on substrate 102, and a first interlayer dielectric (ILD) layer 128 is formed on CESL 126. In some other embodiments, CESL 126 is made of silicon nitride, silicon oxynitride, and / or other suitable materials. CESL 126 can be formed by plasma-enhanced CVD, low-pressure CVD, ALD, or other suitable processes.

[0046] The first ILD layer 128 may comprise a multilayer made of a variety of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borosilicate glass (BPSG), low-k dielectric materials, or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bisbenzocyclobutene (BCB), or polyimide. The first ILD layer 128 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, or other suitable processes.

[0047] A polishing process can be performed on the first ILD layer 128 until the top surface of the dummy gate structure 120 is exposed. In some embodiments, the first ILD layer 128 is planarized by a chemical mechanical polishing (CMP) process.

[0048] like Figure 1H As shown, according to some embodiments, the dummy gate structure 120 is removed to form a trench 130 in the first ILD layer 128. The dummy gate dielectric layer 116 and the dummy gate electrode layer 118 are removed by an etching process, such as a dry etching process or a wet etching process.

[0049] like Figure 1I As shown, according to some embodiments, gate structures 140 are formed in trenches 130. Each gate structure 140 includes a gate dielectric layer 134 and a gate electrode layer 138.

[0050] The gate dielectric layer 134 can be a single layer or multiple layers. The gate dielectric layer 134 is made of silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), a dielectric material with a high dielectric constant (high-k), or a combination thereof. The high dielectric constant (high-k) material can be hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), or other suitable materials. In some embodiments, the gate dielectric layer 134 is deposited by plasma-enhanced chemical vapor deposition (PECVD) or by spin coating.

[0051] The gate electrode layer 138 is made of a conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or other suitable materials. In some embodiments, the gate structure 140 further includes a work function layer. The work function layer is made of a metallic material, which may include an N-work function metal or a P-work function metal. N-work function metals include tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbonitride (TaCN), silicon tantalum nitride (TaSiN), manganese (Mn), zirconium (Zr), or combinations thereof. P-work function metals include titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru), or combinations thereof.

[0052] The gate electrode layer 138 is formed by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), metal-organic CVD (MOCVD), or plasma-enhanced CVD (PECVD).

[0053] Figures 2A-2S Some embodiments according to this disclosure are shown in Figures 1A-1I Cross-sectional views of each stage of the formation of the FinFET device structure 100a after the initial stage. Figure 2A It is along Figure 1I A cross-sectional view taken from line A-A'.

[0054] like Figure 2A As shown, a gate structure 140, including a gate dielectric layer 134 and a gate electrode layer 138, is formed on the fin 110. A gate spacer layer 122 is formed on the opposite sidewall of the gate structure 140. A CESL 126 is formed near the gate spacer layer 122.

[0055] like Figure 2B As shown, according to some embodiments, a portion of the gate structure 140 and a portion of the gate spacer layer 122 are removed. As a result, a trench 141 is formed over the gate structure 140 and the gate spacer layer 122. The sidewalls of the CESL 126, the top surface of the gate structure 140, and the top surface of the gate spacer layer 122 are exposed by the trench 141.

[0056] like Figure 2C As shown, according to some embodiments, a portion of the gate electrode layer 138 of the gate structure 140 is removed. As a result, a recess 143 is formed on the gate electrode layer 138. The top surface of the gate electrode layer 138 is lower than the top surface of the gate spacer layer 122 and the top surface of the gate dielectric layer 134.

[0057] like Figure 2DAs shown, according to some embodiments, a protective layer 144 is formed on the top surface of the gate structure 140 and in a recess 143. The protective layer 144 serves to protect the underlying layers from contamination or damage. In some embodiments, the protective layer 144 is selectively formed on the top surface of the gate electrode layer 138 and not on the gate dielectric layer 134. The top surface of the protective layer 144 is substantially coplanar with the top surface of the gate dielectric layer 134 and the top surface of the gate spacer layer 122. In some other embodiments, the protective layer 144 extends from the top surface of the gate electrode layer 138 to the top surface of the gate dielectric layer 134.

[0058] In some embodiments, the protective layer 144 is formed by a deposition process, which includes providing a precursor on the top surface of the gate electrode layer 138. Prior to the deposition process, a surface treatment process is used to activate the top surface of the gate electrode layer 138. In some embodiments, the surface treatment process includes using hydrogen (H2) gas. When hydrogen (H2) gas is used, hydrogen radicals are formed on the top surface of the gate electrode layer 138. Hydrogen radicals are selectively formed on the top surface of the gate electrode layer 138 to promote the formation of the protective layer 144.

[0059] The precursors used in the deposition process may include tungsten (W)-containing materials, such as tungsten hexafluoride (WF6) or tungsten hexachloride (WCl6). The precursors react with hydrogen radicals to form a protective layer 144 on the gate electrode layer 138.

[0060] In some embodiments, the protective layer 144 is made of a conductive material such as tungsten (W). The protective layer 144 is electrically connected to the gate electrode layer 138 of the gate structure 140.

[0061] It should be noted that because the protective layer 144 is selectively formed on the gate structure 140 and no additional mask layer is used to define the location of the protective layer 144, the alignment of the protective layer 144 is easier. The protective layer 144 is not formed by photolithography. Therefore, manufacturing time and cost are reduced.

[0062] like Figure 2E As shown, according to some embodiments, a hard mask layer 146 is formed on the protective layer 144, CESL 126, and the first ILD layer 128. The hard mask layer 146 and the first ILD layer 128 are made of different materials. In some embodiments, the hard mask layer 146 has higher etch selectivity than the first ILD layer 128.

[0063] In some embodiments, the dielectric constant of the hard mask layer 146 is greater than that of the first ILD layer 128. Because the dielectric constant (k-value) of the hard mask layer 146 is greater than that of the first ILD layer 128, the gate structure 140 and the S / D contact structure ( Figure 2L The capacitance between gate structure 140 and S / D contact structure 156 (formed later) is increased. Therefore, the performance of the FinFET device structure is improved. To reduce the capacitance between gate structure 140 and S / D contact structure 156 (formed later), Figure 2L The capacitance between the two layers is such that the hard mask layer 146 is replaced by another material with a lower dielectric constant, as described herein.

[0064] In some embodiments, the hard mask layer 146 is made of silicon nitride, silicon oxynitride, amorphous carbon material, silicon carbide, other suitable nitrogen-containing material, other suitable dielectric material, or combinations thereof. In some embodiments, the hard mask layer 146 is formed by a deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable processes. In some embodiments, a plurality of slits 147 are formed in the hard mask layer 146. The slits 147 are formed due to the deposition process. In some embodiments, each slit 147 has a first width W1 ranging from about 0.1 nm to about 3 nm.

[0065] like Figure 2F As shown, according to some embodiments, a portion of the hard mask layer 146 is removed. The slit 147 remains within the hard mask layer 146. In some embodiments, this portion of the hard mask layer 146 is removed by a polishing process such as chemical mechanical polishing (CMP). In some embodiments, the hard mask layer 146 has a first height H1 ranging from approximately 5 nm to approximately 60 nm. A second height H2 is measured from the top surface of the hard mask layer 146 to the bottom surface of the gate structure 140. In some embodiments, the ratio (H1:H2) of the first height H1 to the second height H2 is in the range of approximately 1:2 to approximately 2:3.

[0066] like Figure 2G As shown, according to some embodiments, a second ILD layer 148 is formed over the hard mask layer 146, CESL 126, and the first ILD layer 128. The material and formation process of the second ILD layer 148 may be the same as or similar to those of the first ILD layer 128. In some embodiments, the second ILD 148 has a first thickness T1, which is in the range of approximately 50 nm to approximately 250 nm.

[0067] like Figure 2HAs shown, according to some embodiments, a photoresist material is formed on a second ILD layer 148 and then patterned to form a patterned photoresist layer 149. The patterned photoresist layer 149 has openings to expose a portion of the second ILD layer 148. In some embodiments, the openings of the patterned photoresist layer 149 have a second width W2 in the range of approximately 300 nm to approximately 3000 nm. In some embodiments, the patterned photoresist layer 149 has a thickness T2, and the thickness T2 is in the range of approximately 5 nm to approximately 20 nm.

[0068] like Figure 2I As shown, a portion of the second ILD layer 148 and a portion of the first ILD layer 128 are removed to expose a source / drain structure 124 disposed between the gate structures 140. According to some embodiments, removing this portion of the second ILD layer 148 and the first ILD layer 128 also exposes a portion of the hard mask layer 146 with a slot 147. As a result, a trench 151 is formed. The CESL 126 and the hard mask layer 146 are exposed by the trench 151. In some embodiments, the top surface of the source / drain region in the fin structure 110 is exposed.

[0069] It should be noted that the hard mask layer 146 has higher etch selectivity than the first ILD layer 128 and the second ILD layer 148. Therefore, after the etching process, the first ILD layer 128 is removed, while the hard mask layer 146 is retained. The hard mask layer 146 protects the underlying layers from damage during the formation of the trench 151.

[0070] like Figure 2J As shown, according to some embodiments, an adhesive layer 152 is formed in the trench 151. The adhesive layer 152 is conformally formed in the trench 151. Furthermore, the adhesive layer 152 is formed in and embedded in the slot 147. The adhesive layer 152 is used to improve the adhesion between the conductive layer 154 (formed later) and the CESL 126. It should be noted that the trench 151 is not completely filled by the adhesive layer 152.

[0071] In some embodiments, the adhesive layer 152 is made of a conductive material, such as Ti, TiN, TaN, Ru, Co, W, W(CO)6, or other suitable materials. In some embodiments, the adhesive layer 152 is formed by a deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable processes.

[0072] like Figure 2KAs shown, according to some embodiments, a conductive layer 154 is formed in the trench 151, on the adhesive layer 152, and on the patterned photoresist layer 149. In some embodiments, the conductive layer 154 is made of Ru, Co, W, Cu, Mo, or other suitable conductive materials. In some embodiments, the conductive layer 154 is formed by a deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable processes.

[0073] like Figure 2L As shown, according to some embodiments, a portion of the conductive layer 154, the adhesive layer 152, and the patterned photoresist layer 149 are removed. As a result, the top surface of the adhesive layer 152 is substantially coplanar with the top surface of the CESL 126 and the top surface of the conductive layer 154. In some embodiments, this portion of the conductive layer 154, the adhesive layer 152, and the patterned photoresist layer 149 are removed by a polishing process such as chemical mechanical polishing (CMP). As a result, an S / D contact structure 156 is formed on the S / D structure 124. The S / D contact structure 156 is electrically connected to the S / D structure 124. The S / D contact structure 156 includes a U-shaped adhesive layer 152 and a conductive layer 154 filling the middle of the U-shaped adhesive layer 152.

[0074] It should be noted that a portion of the adhesive layer 152 is not removed and remains embedded in the hard mask layer 146. Since the adhesive layer 152 has higher etch resistance than the hard mask layer 146, if this portion of the adhesive layer 152 is embedded in the hard mask layer 146, the hard mask layer 152 would be difficult to remove by subsequent etching processes to form the gate contact structure. Therefore, both the hard mask layer 146 and the adhesive layer 152 are removed simultaneously in subsequent processes and replaced with other materials to prevent the adhesive layer 152 above the gate structure 140 from blocking the etching process.

[0075] like Figure 2M As shown, according to some embodiments, the hard mask layer 146 with the adhesive layer 152 embedded is removed to expose the top surface of the protective layer 144. As a result, a trench 157 is formed to expose the sidewalls of the CESL 126, the top surface of the protective layer 144, the top surface of the gate dielectric layer 134, and the top surface of the gate spacer layer 122.

[0076] like Figure 2NAs shown, according to some embodiments, a liner layer 158 is formed in trench 157, on the top surface of CESL 126, and on the first ILD layer 128. The liner layer 158 is conformally formed in trench 157 and has a U-shaped structure in trench 157. Furthermore, trench 157 is not completely filled by the liner layer 158. A protective layer 144 is located between the liner layer 158 and the gate structure 140. The outer sidewall of the gate spacer layer 122 is aligned with the outer sidewall of the liner layer 158.

[0077] In some embodiments, the liner layer 158 is composed of silicon carbide (SiC), silicon carbide (SiOC), silicon carbonitride (SiOCN), silicon nitride (SixNy), silicon carbonitride (SiCN), aluminum oxide (AlOx), and hafnium oxide (HfO). x Zirconium oxide (ZrO) x The liner layer 158 is made of a dielectric material having a low dielectric constant (low-k) or other suitable material. In some embodiments, the liner layer 158 is formed by performing a deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable processes. In some embodiments, the thickness of the liner layer 158 is in the range of about 1 nm to about 4 nm.

[0078] like Figure 2O As shown, according to some embodiments, a filler layer 160 is formed on top of a liner layer 158. The liner layer 158 is located between CESL 126 and the filler layer 160. The liner layer 158 and the filler layer 160 are made of different materials. The liner layer 158 has a U-shaped structure in the trench 157, and the filler layer 160 fills the middle portion of the U-shaped structure of the liner layer 158. In some embodiments, the dielectric constant of the liner layer 158 is greater than the dielectric constant of the filler layer 160.

[0079] The material properties of the filler layer 160 differ from those of the hard mask layer 146. It should be noted that, as previously mentioned, the hard mask layer 146 exhibits higher etch selectivity than the first ILD layer 128 and the second ILD layer 148. The hard mask layer 146 protects the underlying layers from... Figure 2IThe hard mask layer 146 is protected from damage during the formation of trench 151, but after the formation of S / D contact structure 156, it can be replaced by liner layer 158 and filler layer 160. The refilled filler layer 160 and first ILD layer 128 have substantially the same etch selectivity. In some embodiments, filler layer 160 and first ILD layer 128 are made of the same material, thus having substantially the same etch selectivity. Furthermore, liner layer 158 has a higher etch selectivity than filler layer 160. Since a portion of the adhesive layer 152 embedded in hard mask layer 146 is removed along with hard mask layer 146, the problem associated with the difficulty in removing adhesive layer 152 during gate contact structure formation is solved.

[0080] It should be noted that the dielectric constant of the fill layer 160 is less than that of the hard mask layer 146. Due to the smaller dielectric constant (k value) of the fill layer 160, as previously mentioned, the capacitance between the gate structure 140 and the S / D contact structure 156 is reduced.

[0081] In some embodiments, the filler layer 160 is made of silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), a dielectric material having a low dielectric constant (low-k), or a combination thereof. In some embodiments, the filler layer 160 is formed by performing a deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable processes.

[0082] like Figure 2P As shown, according to some embodiments, a portion of the filler layer 160 is removed. The liner layer 158 is not removed and remains on the top surface of the CESL 126, the top surface of the S / D contact structure 156, and the top surface of the first ILD layer 128. Therefore, for each pair of gate spacer layers 122 extending along the sidewall of the gate structure 140, the liner layer 158 extends from the sidewall of one of the CESL 126 pairs of gate spacer layers 122 to the top surface of the other CESL 126 pair of gate spacer layers 122. The bottom surface of the liner layer 158 is lower than the top surface of the first ILD layer 128, and the bottom surface of the filler layer 160 is lower than the top surface of the first ILD layer 128.

[0083] like Figure 2Q As shown, according to some embodiments, an etch stop layer 162 is formed on the fill layer 160, and a third ILD layer 164 is formed on the etch stop layer 162. The material and formation process of the etch stop layer 162 are the same as or similar to those of CESL 126. The material and formation process of the third ILD layer 164 are the same as or similar to those of the first ILD layer 128.

[0084] like Figure 2R As shown, according to some embodiments, a via 165 is formed through the third ILD layer 164, the etch stop layer 162, the fill layer 160, and the liner layer 158 to expose the protective layer 144. The via 165 has a tapered width from top to bottom. The via 165 is formed by performing an etching process that includes multiple etching processes.

[0085] like Figure 2S As shown, according to some embodiments, a barrier layer 166 and a conductive layer 168 are formed in the via 165 to form a gate contact structure 170. The gate contact structure 170 is formed on the protective layer 144, and the gate contact structure 170 is electrically connected to the gate structure 140 through the protective layer 144.

[0086] A liner layer 158 is located between CESL 126 and etch stop layer 162, and also between S / D contact structure 156 and fill layer 160. The liner layer 158 is located between gate spacer layer 122 and fill layer 160. The liner layer 158 is in direct contact with guard layer 144 and gate spacer layer 122. The liner layer 158 extends from a first portion onto a second portion, the first portion being on gate structure 140 and the second portion being on S / D contact structure 156. Fill layer 160 is in direct contact with CESL 126, S / D contact structure 156, and etch stop layer 162.

[0087] The gate contact structure 170 extends through the liner layer 158 and the fill layer 160, and also extends through the interface between the liner layer 158 and the fill layer 160. The gate contact structure 170 has a tapered width from top to bottom, and the width of the protective layer 144 is greater than the width of the bottom surface of the gate contact structure 170.

[0088] It should be noted that the gate contact structure 170 passes through the fill layer 160 directly above the gate structure 140, and the dielectric constant of the fill layer 160 is lower than that of the hard mask layer 146. Therefore, the capacitance between the gate structure 140 and the S / D contact structure 156 is reduced. Furthermore, since the adhesive layer 152 is removed together with the hard mask layer 146, no adhesive layer 152 remains above the gate structure 140, thus solving the problem associated with the difficulty in removing the adhesive layer 152.

[0089] In some embodiments, the barrier layer 166 is made of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), cobalt tungsten (CoW), or other suitable materials. In some embodiments, the barrier layer 166 is formed by performing a deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable processes.

[0090] In some embodiments, the conductive layer 168 is made of tungsten (W), cobalt (Co), titanium (Ti), aluminum (Al), copper (Cu), tantalum (Ta), platinum (Pt), molybdenum (Mo), silver (Ag), manganese (Mn), zirconium (Zr), ruthenium (Ru), or other suitable materials. In some embodiments, the conductive layer 168 is formed by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, or other suitable processes.

[0091] Figure 3 A cross-sectional view of a FinFET device structure 100b according to some embodiments of the present disclosure is shown. Figure 3 The FinFET device structure 100b is similar to Figure 2F The FinFET device structure 100b differs from FinFET device structure 100a in that the S / D contact structure 156 does not include the adhesive layer 152. The materials and methods used to form FinFET device structure 100b are similar to or the same as those used to form FinFET device structure 100a, and will not be repeated here. Note that the processes associated with forming the adhesive layer 152 may not be performed to form FinFET device structure 100b.

[0092] Figure 4A and Figure 4B A cross-sectional view of a FinFET device structure 100c according to some embodiments of the present disclosure is shown. Figure 4A The FinFET device structure 100c is similar to Figure 2P The FinFET device structure 100a differs from the FinFET device structure 100c in that the liner layer 158 is removed from the top surface of the CESL 126, the top surface of the S / D contact structure 156, and the top surface of the first ILD layer 128. Therefore, the top surfaces of the CESL 126, the S / D contact structure 156, and the first ILD layer 128 are... Figure 2P The associated processing was subsequently exposed. Furthermore, as... Figure 4B As shown, according to some embodiments of this disclosure, a gate contact structure 170 is formed through the third ILD layer 164, the etch stop layer 162, the fill layer 160, and the liner layer 158. The etch stop layer 162 is in direct contact with the fill layer 160, CESL 126, and the first ILD layer 128 of the FinFET device structure 100c. The materials and methods used to form the FinFET device structure 100c are similar to or the same as those used to form the FinFET device structure 100a, and will not be repeated here.

[0093] Figure 5A cross-sectional view of a FinFET device structure 100d according to some embodiments of the present disclosure is shown. Figure 5 The FinFET device structure 100d is similar to Figure 4B The FinFET device structure 100b differs from the FinFET device structure 100d in that the S / D contact structure 156 does not include the adhesive layer 152. The materials and methods used to form the FinFET device structure 100b are similar to or the same as those used to form the FinFET device structure 100c, and will not be repeated here. Note that the processes associated with forming the adhesive layer 152 may not be performed to form the FinFET device structure 100d.

[0094] Figure 6 A cross-sectional view of a FinFET device structure 100e according to some embodiments of the present disclosure is shown. Figure 6 The FinFET device structure 100e is similar to Figure 2S The FinFET device structure 100e differs from FinFET device structure 100a in that it does not include the etch stop layer 162. Therefore, the fill layer 160 and the liner layer 158 are in direct contact with the third ILD layer 164. The materials and methods used to form FinFET device structure 100e are similar to or the same as those used to form FinFET device structure 100a, and will not be repeated here.

[0095] Figure 7 A cross-sectional view of a FinFET device structure 100f according to some embodiments of the present disclosure is shown. Figure 7 The FinFET device structure 100f is similar to Figure 3 The FinFET device structure 100b differs from the FinFET device structure 100f in that it does not include the etch stop layer 162. Therefore, the fill layer 160 and the liner layer 158 are in direct contact with the third ILD layer 164. The materials and methods used to form the FinFET device structure 100f are similar to or the same as those used to form the FinFET device structure 100b, and will not be repeated here.

[0096] Figure 8 A cross-sectional view of a FinFET device structure 100g according to some embodiments of the present disclosure is shown. Figure 8 The FinFET device structure is similar to 100g Figure 4BThe FinFET device structure 100c differs from the FinFET device structure 100g in that it does not include the etch stop layer 162. Therefore, the fill layer 160, liner layer 158, CESL 126, and first ILD layer 128 are in direct contact with the third ILD layer 164. The materials and methods used to form the FinFET device structure 100g are similar to or the same as those used to form the FinFET device structure 100c, and will not be repeated here.

[0097] Figure 9 A cross-sectional view of a FinFET device structure 100h according to some embodiments of the present disclosure is shown. Figure 9 The FinFET device structure 100h is similar to Figure 5 The FinFET device structure 100d differs from the FinFET device structure 100h in that it does not include the etch stop layer 162. Therefore, the fill layer 160, liner layer 158, CESL 126, and first ILD layer 128 are in direct contact with the third ILD layer 164. The materials and methods used to form the FinFET device structure 100h are similar to or the same as those used to form the FinFET device structure 100d, and will not be repeated here.

[0098] Figure 10A and Figure 10B A cross-sectional view of a FinFET device structure 100i according to some embodiments of the present disclosure is shown. Figure 10A The FinFET device structure 100i is similar to Figure 2M The FinFET device structure 100i differs from the FinFET device structure 100i in that a portion of CESL 126 is removed when the hard mask layer 146 is removed. Therefore, CESL 126 has a recessed top surface. Consequently, the top surface or a portion of the top surface of CESL 126 is lower than the top surface of the first ILD layer 128. Furthermore, the top surface or a portion of the top surface of CESL 126 is lower than the top surface of the S / D contact structure 156. The materials and methods used to form the FinFET device structure 100i are similar to or the same as those used to form the FinFET device structure 100a, and will not be repeated here.

[0099] like Figure 10B As shown, according to some embodiments of this disclosure, a gate contact structure 170 is formed through the third ILD layer 164, the etch stop layer 162, the fill layer 160, and the liner layer 158. The liner layer 158 is formed on the recessed top surface of the CESL 126, and some portions of the etch stop layer 162 (or the third ILD layer 164, in the absence of the etch stop layer 162) extend below the top surface of the first ILD layer 128 and / or the top surface of the fill layer 160.

[0100] Figure 11 A cross-sectional view of a FinFET device structure 100j according to some embodiments of the present disclosure is shown. Figure 11 The FinFET device structure 100j is similar to Figure 10B The FinFET device structure 100i is different from the FinFET device structure 100j in that the S / D contact structure 156 does not include the adhesive layer 152. The materials and methods used to form the FinFET device structure 100j are similar or the same as those used to form the FinFET device structure 100i, and will not be repeated here.

[0101] Figure 12 A cross-sectional view of a FinFET device structure 100k according to some embodiments of the present disclosure is shown. Figure 12 The FinFET device structure 100k is similar to Figure 10B The FinFET device structure 100k differs from FinFET device structure 100i in that it does not include the etch stop layer 162. Therefore, the fill layer 160 and the liner layer 158 are in direct contact with the third ILD layer 164. The materials and methods used to form FinFET device structure 100k are similar to or the same as those used to form FinFET device structure 100i, and will not be repeated here.

[0102] Figure 13 A cross-sectional view of a FinFET device structure 100l according to some embodiments of the present disclosure is shown. Figure 13 The FinFET device structure 100l is similar to Figure 11 The FinFET device structure 100j differs from FinFET device structure 100l in that it does not include the etch stop layer 162. Therefore, the fill layer 160 and the liner layer 158 are in direct contact with the third ILD layer 164. The materials and methods used to form FinFET device structure 100l are similar to or the same as those used to form FinFET device structure 100j, and will not be repeated here.

[0103] Figure 14A and Figure 14B A cross-sectional view of a FinFET device structure 100m according to some embodiments of the present disclosure is shown. Figure 14A The FinFET device structure is similar to 100µm Figure 2L The FinFET device structure 100a differs in that the top of the conductive layer 154 of the S / D contact structure 156 is removed during processing, thereby providing a recessed top surface of the conductive layer 154 of the S / D contact structure 156. The materials and methods used to form the FinFET device structure 100m are similar to or the same as those used to form the FinFET device structure 100a, and will not be repeated here.

[0104] like Figure 14B As shown, a liner layer 158 is formed on the recessed top surface of the S / D contact structure 156. According to some embodiments of this disclosure, a gate contact structure 170 is formed through the third ILD layer 164, the etch stop layer 162, the fill layer 160, and the liner layer 158. The top surface of the conductive layer 154 of the S / D contact structure 156 is lower than the top surface of the first ILD layer 128 and the top surface of the CESL 126. The liner layer 158 is formed on the recessed top surface of the conductive layer 154 of the S / D contact structure 156.

[0105] Figure 15 A cross-sectional view of a FinFET device structure 100n according to some embodiments of the present disclosure is shown. Figure 15 The FinFET device structure 100n is similar to Figure 14B The FinFET device structure 100m differs from the FinFET device structure 100n in that the S / D contact structure 156 does not include the adhesive layer 152. The materials and methods used to form the FinFET device structure 100n are similar to or the same as those used to form the FinFET device structure 100m, and will not be repeated here.

[0106] Figure 16 A cross-sectional view of a FinFET device structure 100o according to some embodiments of the present disclosure is shown. Figure 16 The FinFET device structure is similar to 100° Figure 14B The FinFET device structure 100m differs from the FinFET device structure 100o in that it does not include the etch stop layer 162. Therefore, the fill layer 160 and the liner layer 158 are in direct contact with the third ILD layer 164. The materials and methods used to form the FinFET device structure 100o are similar to or the same as those used to form the FinFET device structure 100m, and will not be repeated here.

[0107] Figure 17 A cross-sectional view of a FinFET device structure 100p according to some embodiments of the present disclosure is shown. Figure 17 The 100p FinFET device structure is similar to Figure 15 The FinFET device structure 100n differs from the FinFET device structure 100p in that it does not include the etch stop layer 162. Therefore, the fill layer 160 and the liner layer 158 are in direct contact with the third ILD layer 164. The materials and methods used to form the FinFET device structure 100p are similar to or the same as those used to form the FinFET device structure 100n, and will not be repeated here.

[0108] Figure 18A and Figure 18B A cross-sectional view of a FinFET device structure 100q according to some embodiments of the present disclosure is shown. According to some embodiments of the present disclosure, Figure 18A The FinFET device structure 100q is similar to Figure 2L The FinFET device structure 100a differs in that the top of the conductive layer 154 and the top of the adhesive layer 152 of the S / D contact structure 156 are removed, thereby providing a conductive layer 154 with a recessed top surface and an adhesive layer 152 with a recessed top surface. The materials and methods used to form the FinFET device structure 100q are similar to or the same as those used to form the FinFET device structure 100a, and will not be repeated here.

[0109] like Figure 18B As shown, a liner layer 158 is formed on the recessed top surface of the S / D contact structure 156. According to some embodiments of this disclosure, a gate contact structure 170 is formed through the third ILD layer 164, the etch stop layer 162, the fill layer 160, and the liner layer 158. The top surface of the S / D contact structure 156 is lower than the top surface of the first ILD layer 128. More specifically, the top surfaces of the adhesive layer 152 and the conductive layer 154 are lower than the top surfaces of the first ILD layer 128 and the CESL 126. The liner layer 158 is formed on and conformally conforms to the recessed top surface of the S / D contact structure 156.

[0110] Figure 19 A cross-sectional view of a FinFET device structure 100r according to some embodiments of the present disclosure is shown. Figure 19 The FinFET device structure 100r is similar to Figure 18B The FinFET device structure 100r differs from the FinFET device structure 100q in that it does not include the etch stop layer 162. Therefore, the fill layer 160 and the liner layer 158 are in direct contact with the third ILD layer 164. The materials and methods used to form the FinFET device structure 100r are similar to or the same as those used to form the FinFET device structure 100q, and will not be repeated here.

[0111] Figures 2A-2S The FinFET device structure 100a is shown, while Figure 3 , 4AImages 4B, 5, 6, 7, 8, 9, 10A, 10B, 11, 12, 13, 14A, 14B, 15, 16, 17, 18A, 18B, and 19 illustrate various FinFET device structures 100b, 100c, 100d, 100e, 100f, 100g, 100h, 100i, 100j, 100k, 100l, 100m, 100n, 100o, 100p, 100q, and 100r. The FinFET device structures of this disclosure provide a liner layer 158 and a fill layer 160 over a gate structure, the fill layer 160 being made of a material different from the hard mask layer 146. The hard mask layer 146 is first formed over the gate structure 140 and protects the gate structure 140 during the formation of the S / D structure 156. During the formation of the S / D contact structure 156, the adhesive layer 152 can be formed within the hard mask layer 146. Since both the hard mask layer 146 and the embedded adhesive layer 152 are removed simultaneously, no adhesive layer remains above the gate structure 140. Therefore, the problem associated with the difficulty in removing the adhesive layer 152 is solved. Furthermore, the hard mask layer 146 is removed and replaced by a liner layer 158 and a fill layer 160 made of a low-k material. Therefore, the capacitance between the gate structure and the S / D contact structure is reduced.

[0112] Embodiments and methods for forming FinFET device structures are provided. These embodiments can also be implemented to form gate-all-around (GAA) device structures. In such embodiments, the fin structure 110 may include a stack of semiconductor layers having alternating first and second semiconductor layers. In such embodiments, in Figure 1H and / or Figure 1I Prior to forming the gate structure 140, a channel release process can be performed to selectively remove either the first or second semiconductor layer, thereby forming a suspended semiconductor layer on the substrate 102. For example, if the first semiconductor layer is silicon-germanium and the second semiconductor layer is silicon, the channel release process can selectively remove the silicon-germanium layer, thereby suspending the silicon layer on the substrate 102. In some embodiments, the suspended semiconductor layer provides a channel for the GAA device structure, wherein the channel extends between the source and drain (e.g., S / D structure 124). In such embodiments, the suspended semiconductor layer may be referred to as a channel layer and / or a channel structure. In some embodiments, the suspended semiconductor layer is a nanostructure, such as a nanowire, nanosheet, nanorod, or other suitable nanostructure. In some embodiments, the gate structure 140 encloses and / or surrounds the suspended semiconductor layer such that the GAA device structure has a gate that can control one or more channels from more than one side.

[0113] To facilitate transistor operation, source / drain contacts are formed to the source / drain and gate contacts are formed to the gate electrode of a gate structure disposed between the source / drain. An etch-stop hard mask can be formed over the gate structure to protect the gate structure while forming the source / drain contacts. The gate structure may include gate spacers disposed along the sidewalls of a gate stack, wherein the gate stack has a gate dielectric and a gate electrode disposed over the gate dielectric. Sometimes, the metal material used to form the source / drain contacts may undesirably fill one or more gaps in the etch-stop hard mask, which may lead to under-etching problems during the formation of the gate contacts (i.e., during via-to-metal gate (MG) etching). For example, the metal material may prevent sufficient etching of the etch-stop hard mask beneath it or between the metal material and the dielectric layer. Furthermore, sometimes, to provide sufficient etch selectivity, the etch-stop hard mask includes a high-capacitance material, such as a high-k dielectric material, which can increase the capacitive coupling (and thus the capacitance) between the source / drain contacts and the gate structure and / or the gate contacts.

[0114] This disclosure provides a source / drain contact formation method and / or gate contact formation method to overcome these challenges by utilizing a one-time etch-stop hard mask during source / drain contact formation and replacing the one-time etch-stop hard mask with a low-capacitance material after source / drain contact formation and before gate contact formation. In some embodiments, fabrication may begin with a receiving device precursor having a substrate, a gate structure disposed between the source / drain (all source / drain disposed over the substrate and wherein the gate structure has gate spacers disposed along the sidewalls of the gate stack, including a hard mask disposed over a metal gate stack (i.e., gate dielectric and gate electrode), an etch-stop hard mask disposed over the gate structure, and a first dielectric layer disposed over the source / drain. The etch-stop hard mask includes a bulk dielectric, and the first dielectric layer may include an interlayer dielectric layer (ILD) and a contact etch-stop layer (CESL). The etch-stop hard mask includes a dielectric material that can provide sufficient etch selectivity during subsequent etch processes, such as a high-k dielectric material that can exhibit high capacitance. A slit may be formed in the etch-stop hard mask. A first dielectric layer extends along the sidewalls of the gate structure and the etch-stop hard mask. In some embodiments, the thickness of the first dielectric layer is approximately the same as the sum of the height of the gate structure and the height of the etch-stop hard mask. Fabrication may continue by depositing a second dielectric layer over the etch-stop hard mask and performing a patterning process to form a source / drain contact opening extending through the second dielectric layer and the first dielectric layer to expose at least one of the source / drain electrodes. The source / drain contact opening further fully or partially exposes the etch-stop hard mask. Fabrication may continue by forming source / drain contacts to at least one of the source / drain electrodes, which may include depositing a contact liner partially filling the source / drain contact opening, depositing a body contact layer over the contact liner filling the remaining portion of the source / drain contact opening, and performing a planarization process to remove excess contact liner, excess body contact layer, and the second dielectric layer, thereby exposing the etch-stop hard mask and the first dielectric layer. The contact liner may fill the slit in the etch-stop hard mask and remain therein after the planarization process.

[0115] Fabrication allows for the continued removal of the etch-stop hard mask (including any contact liner residue disposed therein), thereby forming an opening to expose the gate structure. A hard mask is then formed in the opening, for example, by depositing a dielectric liner over the first dielectric layer, source / drain contacts, and gate structure, wherein the dielectric liner partially fills the opening; depositing a bulk dielectric layer over the dielectric liner to fill the remaining portion of the opening; and performing a planarization process to remove excess bulk dielectric layer, thereby exposing the dielectric liner. In some embodiments, the planarization process removes excess dielectric liner over the first dielectric layer and source / drain contacts. In some embodiments, the dielectric liner serves as a planarization stop layer, such that the dielectric liner remains over the first dielectric layer and source / drain contacts. The dielectric liner and / or the bulk dielectric layer comprise a dielectric material having a lower capacitance than the dielectric material of the etch-stop hard mask. In some embodiments, the bulk dielectric layer comprises the same material as the first dielectric layer, such as the same material as the ILD layer. Fabrication may continue by forming a third dielectric layer over a hard mask, a first dielectric layer, and source / drain contacts, and performing a patterning process to form a gate contact opening extending through the third dielectric layer and the hard mask to expose a gate structure (e.g., the gate electrode of the gate structure). In some embodiments, the gate contact opening extends through and / or into the hard mask of the gate structure (e.g., a gate protection layer). In some embodiments, the gate protection layer is a metal layer, such as a tungsten layer. The third dielectric layer may include an interlayer dielectric layer and a CESL. A gate contact is formed to the gate structure, which may include depositing a contact liner partially filling the gate opening, depositing a body contact layer over the contact liner to fill the remaining portion of the gate contact opening, and performing a planarization process to remove excess contact liner and excess body contact layer, thereby exposing the third dielectric layer.

[0116] In some embodiments, when an etch-stop hard mask is replaced with a hard mask (i.e., a dielectric liner plus a dielectric body), the dielectric liner is not removed by a planarization process, and the dielectric liner remains between the first and third dielectric layers and between the source / drain contacts and the first dielectric layer. In some embodiments, the dielectric liner extends continuously from a hard mask over a first gate structure to a second hard mask over a second gate structure. In some embodiments, the source / drain contacts are formed without a contact liner, and thus can be referred to as barrier-free source / drain contacts. In some embodiments, when an etch-stop hard mask is replaced with a hard mask, the dielectric liner is removed by a planarization process. In some embodiments, the source / drain contacts are formed without a contact liner. In some embodiments, the third dielectric layer does not include the CESL. In some embodiments, the first dielectric layer is partially removed during the removal of the etch-stop hard mask. For example, the top of the CESL and / or the source / drain contact spacer (which may include a dielectric material) is lightly etched such that the CESL and / or the source / drain contact spacer has a curved top surface. In some embodiments, a slight etching exposes the apex corners of the source / drain contacts. In some embodiments, the source / drain contacts do not include a contact liner, the third dielectric layer does not include a CESL, and / or the third dielectric layer does not include a CESL. In some embodiments, the contact body is recessed during manufacturing, for example, by a planarization process. In some embodiments, the source / drain contacts do not include a contact liner, the third dielectric layer does not include a CESL, and / or the third dielectric layer does not include a CESL. In some embodiments, the contact body and contact liner are recessed during manufacturing, for example, by a planarization process. In such embodiments, the third dielectric layer may not include a CESL. From such embodiments, it is clear that a CESL can be eliminated from the gate contact to gate (also known as via to MG) process.

[0117] In some embodiments, the FinFET device structure includes a fin structure formed on a substrate and a dummy gate structure formed on the fin structure. A dielectric layer is formed on the dummy gate structure, and the dummy gate structure is replaced by the gate structure. Subsequently, a portion of the gate structure is removed, a trench is formed on the gate structure, and a hard mask layer is formed in the trench. An S / D contact structure is formed on the S / D structure. During the formation of the S / D contact structure, the gate structure is protected by the hard mask layer. The hard mask layer is then removed and replaced by a liner layer and a fill layer. Since the dielectric constant of the fill layer is lower than that of the hard mask layer, the capacitance between the gate structure and the S / D contact structure is reduced. Therefore, the performance of the FinFET device structure is improved.

[0118] In some embodiments, a FinFET device structure is provided. The FinFET device structure includes a fin structure formed on a substrate and a gate structure formed on the fin structure. The FinFET device structure also includes an interlayer dielectric (ILD) layer formed adjacent to the gate structure and a liner layer formed on the gate structure. The bottom surface of the liner layer is lower than the top surface of the ILD layer. The FinFET device structure includes a fill layer formed on the gate structure and the liner layer. The bottom surface of the fill layer is lower than the top surface of the ILD layer, and the liner layer and the fill layer are made of different materials.

[0119] In some embodiments, a FinFET device structure is provided. The FinFET device structure includes a fin structure formed on a substrate and a gate structure formed on the fin structure. The FinFET device structure includes a gate spacer layer formed adjacent to the gate structure and an etch stop layer formed adjacent to the gate spacer layer. The FinFET device structure includes a liner layer formed on the gate structure and a fill layer formed on the liner layer. The liner layer is located between the gate spacer layer and the fill layer, and the bottom surface of the fill layer is lower than the top surface of the etch stop layer.

[0120] In some embodiments, a method for forming a FinFET device structure is provided. The method includes forming a gate structure on a fin structure and forming a source / drain (S / D) structure adjacent to the gate structure. The method includes forming a hard mask layer on the gate structure and removing the hard mask layer to form a trench. The method also includes forming a liner layer on the gate structure and in the trench, and forming a fill layer on the liner layer and in the trench. The fill layer and the hard mask layer are made of different materials.

[0121] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various alterations, substitutions, and changes can be made to this document without departing from the spirit and scope of this disclosure.

[0122] Example 1. A semiconductor device structure, comprising:

[0123] A contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion that are spaced apart;

[0124] A gate stack and a gate spacer, the gate spacer being disposed along the sidewall of the gate stack, wherein the gate stack and the gate spacer fill the gap between the lower portion of the first sidewall CESL portion and the lower portion of the second sidewall CESL portion; and

[0125] A dielectric feature is disposed above the gate stack and the gate spacer, wherein the dielectric feature fills the spacer between the upper portion of the first sidewall CESL portion and the upper portion of the second sidewall CESL portion, the dielectric feature including a dielectric layer disposed above a dielectric liner, the dielectric liner being between the dielectric layer and the gate spacer, between the dielectric layer and the gate stack, and between the dielectric layer and the CESL.

[0126] Example 2. The semiconductor device structure according to Example 1, wherein the dielectric liner extends over the top surface of the first sidewall CESL portion and the top surface of the second sidewall CESL portion.

[0127] Example 3. The semiconductor device structure according to Example 1 further includes a gate contact structure extending through the dielectric layer and the dielectric liner, wherein the gate contact structure is electrically connected to the gate stack.

[0128] Example 4. The semiconductor device structure according to Example 3 further includes a metal protective layer located between the gate contact structure and the gate stack, wherein the dielectric liner is located between the dielectric layer and the metal protective layer.

[0129] Example 5. The semiconductor device structure according to Example 1, wherein the dielectric layer is a first dielectric layer, and the semiconductor device structure further includes:

[0130] The second dielectric layer, wherein the CESL is between the dielectric liner of the dielectric feature and the second dielectric layer, and the CESL is between at least one of the dielectric liner and the gate spacer.

[0131] Example 6. The semiconductor device structure according to Example 5, wherein the first dielectric layer and the second dielectric layer comprise the same material.

[0132] Example 7. The semiconductor device structure according to Example 5, wherein the dielectric liner extends above the top surface of the second dielectric layer.

[0133] Example 8. The semiconductor device structure according to Example 1 further includes an S / D contact structure electrically connected to the source / drain (S / D) structure, wherein the CESL is between the S / D structure and the dielectric feature and between at least one of the S / D structure and the gate spacer.

[0134] Example 9. A semiconductor device structure according to Example 8, wherein the dielectric liner extends over the top surface of the S / D contact structure.

[0135] Example 10. A semiconductor device structure, comprising:

[0136] A gate structure, on a semiconductor layer, wherein the gate structure is located between a first source / drain and a second source / drain in the semiconductor layer;

[0137] A dielectric feature is present on the top surface of the gate structure, wherein the width of the dielectric feature is the same as the width of the gate structure, and the dielectric feature includes a fill layer on a liner layer, wherein the liner layer encloses the fill layer and the liner layer is located between the gate structure and the fill layer; and

[0138] An interlayer dielectric (ILD) layer is placed above the semiconductor layer, wherein the liner layer is placed between the fill layer and the ILD layer, and the material of the ILD layer is the same as the material of the fill layer.

[0139] Example 11. The semiconductor device structure according to Example 10, wherein the dielectric constant of the liner layer is greater than the dielectric constant of the fill layer.

[0140] Example 12. The semiconductor device structure according to Example 10, wherein:

[0141] The gate structure includes a gate electrode on a gate dielectric, a gate spacer along a sidewall portion of the gate dielectric, and a metal protective layer on the gate electrode and between the sidewall portions of the gate dielectric; and

[0142] The liner layer is located between the filler layer and the gate dielectric, the gate spacer, and the metal protective layer.

[0143] Example 13. The semiconductor device structure according to Example 10 further includes an etch stop layer between the ILD layer and the dielectric feature and between the ILD layer and the gate structure, and further wherein the liner layer is between the fill layer and the ILD layer.

[0144] Example 14. The semiconductor device structure according to Example 13, wherein the etch stop layer has a top surface below the top surface of the ILD layer, and the liner layer is formed on the top surface of the etch stop layer.

[0145] Example 15. The semiconductor device structure according to Example 10 further includes a source / drain contact structure to the second source / drain, wherein the liner layer extends over the top surface of the source / drain contact structure.

[0146] Example 16. The semiconductor device structure according to Example 10 further includes a gate contact structure to the gate structure, wherein the gate contact structure extends through the fill layer and the liner layer.

[0147] Example 17. A method for forming a semiconductor device, comprising:

[0148] A receiving device precursor having a gate structure between a first source / drain and a second source / drain, an etch-stop hard mask over the gate structure, a first dielectric layer along the sidewall of the gate structure and along the sidewall of the etch-stop hard mask, and a second dielectric layer over the first dielectric layer.

[0149] A source / drain contact is formed to the first source / drain, wherein the first dielectric layer is between the gate structure and the source / drain contact and between the etch stop hard mask and the source / drain contact;

[0150] The etch-stop hard mask is replaced with a dielectric feature, the dielectric feature including a bulk dielectric disposed on a dielectric liner, wherein a first dielectric layer is between the dielectric feature and the source / drain contact, a first dielectric layer is between the dielectric feature and a second dielectric layer, the dielectric liner is between the first dielectric layer and the bulk dielectric, and the dielectric liner is between the gate structure and the bulk dielectric; and

[0151] A gate contact is formed, which extends through the dielectric feature into the gate structure.

[0152] Example 18. The method according to Example 17, wherein the material of the bulk dielectric is the same as the material of the second dielectric layer.

[0153] Example 19. The method according to Example 17, wherein the source / drain contact formed to the first source / drain includes:

[0154] Remove the second dielectric layer to form a source / drain contact opening exposing the first source / drain, wherein the sidewalls of the source / drain contact opening are formed by the first dielectric layer; and

[0155] The source / drain contact openings are filled with a conductive material.

[0156] Example 20. The method according to Example 17, wherein the etch-stop hard mask has a slit, and the slit is filled with a conductive material during the formation of the source / drain contacts to the first source / drain.

Claims

1. A semiconductor device structure, comprising: A contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion that are spaced apart. A gate stack and a gate spacer, the gate spacer being disposed along the sidewall of the gate stack, wherein the gate stack and the gate spacer fill the gap between the lower portion of the first sidewall CESL portion and the lower portion of the second sidewall CESL portion; A dielectric feature is disposed over the gate stack and the gate spacer, wherein the dielectric feature fills the spacer between the upper portion of the first sidewall CESL portion and the upper portion of the second sidewall CESL portion, the dielectric feature including a dielectric layer disposed over a dielectric liner, the dielectric liner being between the dielectric layer and the gate spacer, between the dielectric layer and the gate stack, and between the dielectric layer and the CESL; and An S / D contact structure electrically connected to a source / drain (S / D) structure, wherein the dielectric liner extends over the top surface of the S / D contact structure.

2. The semiconductor device structure according to claim 1, wherein, The dielectric liner extends over the top surface of the first sidewall CESL portion and the top surface of the second sidewall CESL portion.

3. The semiconductor device structure according to claim 1, further comprising a gate contact structure extending through the dielectric layer and the dielectric liner, wherein, The gate contact structure is electrically connected to the gate stack.

4. The semiconductor device structure according to claim 3, further comprising a metal protective layer located between the gate contact structure and the gate stack, wherein, The dielectric liner is located between the dielectric layer and the metal protective layer.

5. The semiconductor device structure according to claim 1, wherein, The dielectric layer is a first dielectric layer, and the semiconductor device structure further includes: The second dielectric layer, wherein the CESL is between the dielectric liner of the dielectric feature and the second dielectric layer, and the CESL is between the second dielectric layer and at least one of the gate spacers.

6. The semiconductor device structure according to claim 5, wherein, The first dielectric layer and the second dielectric layer comprise the same material.

7. The semiconductor device structure according to claim 5, wherein, The dielectric liner extends above the top surface of the second dielectric layer.

8. The semiconductor device structure according to claim 1, wherein, The CESL is located between the S / D structure and the dielectric feature, and between the S / D structure and at least one of the gate spacers.

9. A semiconductor device structure, comprising: A gate structure on a semiconductor layer, wherein the gate structure is located between a first source / drain and a second source / drain in the semiconductor layer; A dielectric feature is present on the top surface of the gate structure, wherein the width of the dielectric feature is the same as the width of the gate structure, and the dielectric feature includes a fill layer on a liner layer, wherein the liner layer encloses the fill layer and the liner layer is between the gate structure and the fill layer. An interlayer dielectric (ILD) layer is placed above the semiconductor layer, wherein the liner layer is placed between the fill layer and the ILD layer, and the material of the ILD layer is the same as the material of the fill layer; and The liner extends over the top surface of the second source / drain contact structure.

10. The semiconductor device structure according to claim 9, wherein, The dielectric constant of the lining layer is greater than that of the filler layer.

11. The semiconductor device structure according to claim 9, wherein: The gate structure includes a gate electrode on a gate dielectric, a gate spacer along a sidewall portion of the gate dielectric, and a metal protective layer on the gate electrode and between the sidewall portions of the gate dielectric. and The liner layer is located between the filler layer and the gate dielectric, the gate spacer, and the metal protective layer.

12. The semiconductor device structure of claim 9, further comprising an etch stop layer, the etch stop layer being between the ILD layer and the dielectric feature and between the ILD layer and the gate structure, wherein, The lining layer is located between the filler layer and the ILD layer.

13. The semiconductor device structure according to claim 12, wherein, The etch stop layer has a top surface that is lower than the top surface of the ILD layer, and the liner layer is formed on the top surface of the etch stop layer.

14. The semiconductor device structure according to claim 9, further comprising a gate contact structure to the gate structure, wherein, The gate contact structure extends through the filler layer and the liner layer.

15. A method for forming a semiconductor device, comprising: A receiving device precursor having a gate structure between a first source / drain and a second source / drain, an etch-stop hard mask over the gate structure, a first dielectric layer along the sidewall of the gate structure and along the sidewall of the etch-stop hard mask, and a second dielectric layer over the first dielectric layer. A source / drain contact is formed to the first source / drain, wherein the first dielectric layer is between the gate structure and the source / drain contact and between the etch stop hard mask and the source / drain contact; The etch-stop hard mask is replaced with a dielectric feature, the dielectric feature including a bulk dielectric disposed on a dielectric liner, wherein a first dielectric layer is between the dielectric feature and the source / drain contact, a first dielectric layer is between the dielectric feature and a second dielectric layer, the dielectric liner is between the first dielectric layer and the bulk dielectric, and the dielectric liner is between the gate structure and the bulk dielectric; and A gate contact is formed, the gate contact extending through the dielectric feature into the gate structure; The source / drain contacts formed to the first source / drain include: Remove the second dielectric layer to form a source / drain contact opening exposing the first source / drain, wherein the sidewalls of the source / drain contact opening are formed by the first dielectric layer; and The source / drain contact openings are filled with a conductive material; and The dielectric liner extends above the top surface of the source / drain contact.

16. The method according to claim 15, wherein, The material of the bulk dielectric is the same as the material of the second dielectric layer.

17. The method according to claim 15, wherein, The etch-stop hard mask has a slit, and the slit is filled with a conductive material during the formation of the source / drain contacts to the first source / drain.

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