Channel structure for GAA device and preparation method thereof

Abstract

The present invention provides a channel structure for a GAA device, comprising: a substrate; a first stress structure layer formed in a first region on the substrate; and a channel stack; the channel stack is formed on the first stress structure layer and a second region of the substrate; wherein the first region is a region for forming an NMOS device, and the second region is a region for forming a PMOS device; the first stress structure layer is used to provide the stress required by the channel stack in the first region. The problem that the source region and the drain region of the NMOS device region are difficult to provide the high stress required by the channel stack is solved, and the effect of improving the success rate of stress provision in the NMOS device region is achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a channel structure for a GAA device and a preparation method thereof. Background Art

[0002] The existing ESD stress technology currently requires epitaxy on multiple complex planes of GAA, which is prone to defects and difficult to obtain the required high stress. Therefore, developing a process that can provide prestress for GAA devices has become a technical focus that technicians in this field need to solve urgently. Summary of the invention

[0003] The present invention provides a channel structure for a GAA device and a preparation method thereof, so as to solve the problem that the source region and the drain region of an NMOS device are difficult to provide the high stress required by the channel stack.

[0004] According to a first aspect of the present invention, there is provided a channel structure for a GAA device, comprising:

[0005] substrate;

[0006] a first stress structure layer formed in a first region on the substrate; and

[0007] A channel stack; the channel stack is formed on the first stress structure layer and the second region of the substrate;

[0008] The first region is a region for forming an NMOS device, and the second region is a region for forming a PMOS device; the first stress structure layer is used to provide the stress required by the channel stack in the first region.

[0009] Optionally, the channel structure further includes:

[0010] A second stress structure layer; the second stress structure layer is formed on the second region of the substrate and is located between the substrate and the channel stack; wherein the second stress structure layer is used to provide the stress required by the channel stack in the second region.

[0011] Optionally, a first protective layer is further included between the first stress structure layer and / or the second stress structure layer and the channel stack.

[0012] Optionally, the material of the first stress structure layer is SiC, and the material of the second stress structure layer is SiGe.

[0013] Optionally, the material of the first protective layer is Si.

[0014] Optionally, the thickness of the first stress structure layer and the second stress structure layer are both above a critical thickness.

[0015] According to a second aspect of the present invention, there is provided a method for preparing a channel structure for a GAA device, the method comprising the following steps:

[0016] providing a substrate;

[0017] forming a first stress structure layer in a first region on the substrate;

[0018] A channel stack is formed; the channel stack is formed on the first stress structure layer and the second region of the substrate.

[0019] Optionally, forming a first stress structure layer in the first region on the substrate specifically includes:

[0020] Coating a first photoresist on the substrate, exposing and developing the first photoresist to form a first patterned photoresist;

[0021] Using the first patterned photoresist as a mask, etching the surface layer of the substrate in the first area to form a first cavity;

[0022] A first stress structure layer is filled in the first cavity, and the first patterned photoresist is removed.

[0023] Optionally, before forming the first stress structure layer in the first region on the substrate, the method further includes:

[0024] A second stress structure layer is formed; the second stress structure layer is formed in the second region on the substrate and directly contacts the substrate.

[0025] Optionally, the forming of the second stress structure layer specifically includes:

[0026] epitaxially growing a second structural layer on the substrate;

[0027] coating a second photoresist on the second structural layer, exposing and developing the second photoresist to form a second patterned photoresist;

[0028] The second stress structure layer in the first area is etched away using the second patterned photoresist as a mask to form a second cavity, and the remaining second stress structure layer in the second area is retained to form the second stress structure layer.

[0029] Optionally, the method for preparing the channel structure for the GAA device specifically includes: forming a first stress structure layer in the first region on the substrate, specifically including:

[0030] forming a first stress structure layer in the second cavity;

[0031] The second patterned photoresist is removed.

[0032] Optionally, the method for preparing a channel structure for a GAA device further comprises, before forming the channel stack:

[0033] A first protection layer is formed on the first stress structure layer and the second stress structure layer.

[0034] According to a third aspect of the present invention, there is provided a method for preparing a GAA device, comprising: the method for preparing a channel structure for a GAA device according to any one of the second aspect of the present invention.

[0035] According to a fourth aspect of the present invention, a GAA device is provided, comprising the channel structure for a GAA device according to any one of the first aspect of the present invention.

[0036] According to a fifth aspect of the present invention, there is provided an electronic device comprising the GAA device according to the fourth aspect of the present invention.

[0037] The present invention provides a channel structure for a GAA device, which provides prestress for the channel layer in the NMOS device region by introducing a first stress structure layer between the channel stack in the NMOS device region and the substrate, thereby reducing the demand for stress provided to the source region and the drain region in the NMOS device region in the subsequent process, solving the problem that the source region and the drain region in the NMOS device region are difficult to provide the high stress required by the channel stack, and achieving the effect of improving the success rate of stress provision in the NMOS device region. The difficulty of making the source region and the drain region in the NMOS device region in the subsequent process is reduced.

[0038] Furthermore, the technical solution provided by the present invention reduces the demand for stress provided to the source and drain regions of the NMOS device region and the PMOS device region in the subsequent process by introducing the first stress structure layer and the second stress structure layer between the channel stack and the substrate in the NMOS device region and the PMOS device region, solves the problem that the source and drain regions of the NMOS device region and the PMOS device region are difficult to provide the high stress required for the channel stack, and achieves the effect of improving the success rate of stress provision in the NMOS device region and the PMOS device region. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0040] Figure 1 It is a schematic flow chart of a method for manufacturing a channel structure for a GAA device provided by an embodiment of the present invention;

[0041] Figure 2 Schematic diagram of a device structure at different process stages according to a method for manufacturing a channel structure for a GAA device provided by a specific embodiment of the present invention. Figure 1 ;

[0042] Figure 3 Schematic diagram of a device structure at different process stages according to a method for manufacturing a channel structure for a GAA device provided by a specific embodiment of the present invention. Figure 2 ;

[0043] Figure 4 Schematic diagram of a device structure at different process stages according to a method for manufacturing a channel structure for a GAA device provided by a specific embodiment of the present invention. Figure 3 ;

[0044] Figure 5 Schematic diagram of a device structure at different process stages according to a method for manufacturing a channel structure for a GAA device provided by another specific embodiment of the present invention Figure 1 ;

[0045] Figure 6 Schematic diagram of a device structure at different process stages according to a method for manufacturing a channel structure for a GAA device provided by another specific embodiment of the present invention Figure 2 ;

[0046] Figure 7 Schematic diagram of a device structure at different process stages according to a method for manufacturing a channel structure for a GAA device provided by another specific embodiment of the present invention Figure 3 ;

[0047] Description of reference numerals:

[0048] 101-substrate;

[0049] 102-channel layer;

[0050] 103-sacrificial layer;

[0051] 104-first stress structure layer;

[0052] 105- second stress structure layer;

[0053] 106- source region and / or drain region;

[0054] 107- inner isolation layer;

[0055] 108- false fence;

[0056] 109 - inner wall;

[0057] 110-Isolation layer. DETAILED DESCRIPTION

[0058] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0059] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0060] The current existing ESD stress technology requires epitaxy on multiple complex planes of GAA, which is prone to defects and difficult to obtain the required high stress.

[0061] In view of this, the inventors of the present application discovered through repeated experiments that before forming the channel stack, a stress structure layer is formed on the substrate, and the protective layer and the channel stack are epitaxially grown based on the stress structure layer to produce a superlattice structure with different pre-stresses in the n / p region, which can provide sufficient stress for the channel region.

[0062] The technical solution provided by the present invention provides stress for the channel region in advance, simplifies the process difficulty, and makes it unnecessary to consider the stress problem that the source and drain need to provide when epitaxially growing the source and drain, thereby improving the success rate of the stress.

[0063] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0064] Please refer to Figure 3 and Figure 6According to a specific embodiment of the present invention, a channel structure for a GAA device is provided, comprising:

[0065] Substrate 101;

[0066] A first stress structure layer 104 is formed in a first region on the substrate 101; in a specific implementation example, the material of the first stress structure layer 104 is SiC or GaN, and of course, it can also be composed of other semiconductor materials with a lattice constant lower than Si, and the present invention is not limited thereto. Any material implementation form of the first stress structure layer 104 that can achieve the purpose of the present invention is within the protection scope of the present invention; and

[0067] A channel stack; the channel stack is formed on the first stress structure layer 104 and the second region of the substrate 101; the channel stack includes alternately stacked sacrificial layers 103 and channel layers 102;

[0068] The first region is a region for forming an NMOS device, and the second region is a region for forming a PMOS device; the first stress structure layer 104 is used to provide the stress required by the channel stack in the first region.

[0069] In one embodiment, the first stress structure layer 104 is flush with the substrate 101 in the second region, and the channel structure is as follows: Figure 3 shown.

[0070] Since defects are prone to occur during the epitaxial growth of the source and drain regions, it is difficult to obtain the required high stress. The present invention provides a channel structure for a GAA device. By introducing a first stress structure layer 104 between the channel stack in the region of the NMOS device and the substrate 101, prestress is provided for the channel layer 102 in the region of the NMOS device. Therefore, when the source and drain regions in the region of the NMOS device are epitaxially grown, there is no need to consider the stress provided by the source and drain regions, thereby improving the success rate of stress provision and reducing the difficulty of manufacturing the source and drain regions.

[0071] It can be seen that the technical solution provided by the present invention provides pre-stress for the channel layer 102 in the region of the NMOS device by introducing the first stress structure layer 104 between the channel stack in the region of the NMOS device and the substrate 101, thereby solving the problem that the source region and the drain region in the region of the NMOS device are difficult to provide the high stress required for the channel stack, and achieving the effect of improving the success rate of stress provision in the region of the NMOS device.

[0072] According to another specific embodiment provided by the present invention, the channel structure further includes:

[0073] The second stress structure layer 105 is formed on the second region of the substrate 101 and is located between the substrate 101 and the channel stack; wherein the second stress structure layer 105 is used to provide the stress required by the channel stack in the second region. In a specific embodiment, the material of the second stress structure layer 105 is SiGe or InAs, and of course, it can also be composed of other semiconductor materials with a lattice constant greater than Si. The present invention is not limited to this, and any implementation form of the material of the second stress structure layer 105 that can achieve the purpose of the present invention is within the protection scope of the present invention.

[0074] In one embodiment, the second stress structure layer 105 is flush with the first stress structure layer 104, and the channel structure is as follows: Figure 6 shown.

[0075] The technical solution provided by the present invention provides pre-stress for the channel layer 102 in the region of the NMOS device and the channel layer 102 in the region of the PMOS device by introducing a first stress structure layer 104 between the channel stack in the region of the NMOS device and the substrate 101, and introducing a second stress structure layer 105 between the channel stack in the region of the PMOS device and the substrate 101, thereby solving the problem that it is difficult to provide the high stress required by the channel layer 102 in the source region and the drain region in the region of the NMOS device and the region of the PMOS device, and at the same time achieving the effect of improving the success rate of stress provision in the region of the NMOS device and the region of the PMOS device.

[0076] In one embodiment, a first protective layer is further included between the first stress structure layer 104 and / or the second stress structure layer 105 and the channel stack; in a specific implementation, the material of the first protective layer is Si, and of course it can also be composed of other materials, and the present invention is not limited thereto, and any implementation form of the material of the first protective layer that can achieve the purpose of the present invention is within the protection scope of the present invention;

[0077] In the first specific embodiment, the first protective layer is formed between the substrate 101 and the first stress structure layer 104 and the channel stack in the second region; in the second specific embodiment, the first protective layer is formed between the first stress structure layer 104 and the second stress structure layer 105 and the channel stack;

[0078] In one embodiment, the thickness of the first stress structure layer 104 and the second stress structure layer 105 are both above a critical thickness; the critical thickness refers to: the maximum thickness that the first stress structure layer or the second stress structure layer can reach when it grows together; when the thickness of the corresponding structure layer is less than the critical thickness, the stress of the corresponding structure layer cannot be released; when the thickness of the corresponding structure layer is greater than the critical thickness, adaptation misalignment occurs;

[0079] Secondly, please refer to Figure 1-3 ,as well as Figure 5-6 , wherein the flow chart of the method for preparing the channel structure of the GAA device is as follows Figure 1 As shown,

[0080] Please refer to Figure 2-Figure 3 According to a specific embodiment of the present invention, a method for preparing a channel structure for a GAA device is also provided, the method comprising the following steps:

[0081] S11: providing a substrate 101;

[0082] S12: forming a first stress structure layer 104 in the first region on the substrate 101, and forming the first stress structure layer 104 to form a device such as Figure 2 As shown;

[0083] S13: forming a channel stack; the channel stack is formed on the first stress structure layer 104 and the second region of the substrate 101, and the device after the channel stack is formed is as follows Figure 3 shown.

[0084] The technical solution provided by the present invention adopts a process of forming a first stress structure layer 104 in the first region before forming a channel stack, thereby solving the problem that the source region and the drain region of the NMOS device region are difficult to provide the high stress required for the channel stack, and achieving the effect of improving the success rate of stress provision in the NMOS device region.

[0085] In one embodiment, step S12, forming a first stress structure layer 104 in a first region on the substrate 101, specifically includes steps S121-S123,

[0086] S121: coating a first photoresist on the substrate 101, exposing and developing the first photoresist to form a first patterned photoresist;

[0087] S122: using the first patterned photoresist as a mask to etch the surface layer of the substrate 101 in the first area to form a first cavity;

[0088] S123: filling the first cavity with a first stress structure layer 104 and removing the first patterned photoresist.

[0089] In other implementations, in step S12, before step S121, further comprising: forming a second protective layer on the substrate 101; thus step S12 specifically comprises: steps S121 to S124,

[0090] Step S121: forming a second protective layer on the substrate 101;

[0091] Step S122: coating a first photoresist on the second protective layer, exposing and developing the first photoresist to form a first patterned photoresist;

[0092] Step S123: using the first patterned photoresist as a mask to etch the surface layer of the substrate 101 and the second protective layer in the first area to form a first cavity;

[0093] Step S124: filling the first cavity with the first stress structure layer 104, and removing the second protection layer and the first patterned photoresist.

[0094] The method of removing the second protective layer and the first patterned photoresist may be an etching method or a CMP polishing method;

[0095] In the aforementioned embodiment, after the first cavity is formed in step S123, the second protective layer is still retained on the substrate 101 in the second region; therefore, in the aforementioned embodiment, when the first stress structure layer 104 is filled in the first cavity in step S124, due to the presence of the second protective layer on the substrate 101 in the second region, the first stress structure layer 104 is selectively epitaxially formed on the substrate 101 in the first cavity.

[0096] Please refer to Figure 5-Figure 6 According to another specific embodiment of the present invention, step S12, before forming the first stress structure layer 104 in the first region on the substrate 101, further includes:

[0097] A second stress structure layer 105 is formed; the second stress structure layer 105 is formed in the second region on the substrate 101 and directly contacts the substrate 101. After the second stress structure layer 105 is formed, the device is as follows Figure 5 shown.

[0098] The technical solution provided by the present invention adopts a process method of forming a first stress structure layer 104 in a first region and forming a second stress structure layer 105 in a second region before forming a channel stack, thereby solving the problem that the source region and the drain region of the NMOS device region and the PMOS device region are difficult to provide the high stress required by the channel layer 102, and at the same time, achieving the effect of improving the success rate of stress provision in the NMOS device region and the PMOS device region.

[0099] In one embodiment, the forming of the second stress structure layer 105 specifically includes:

[0100] epitaxially growing a second structural layer on the substrate 101;

[0101] coating a second photoresist on the second structural layer, exposing and developing the second photoresist to form a second patterned photoresist;

[0102] The second stress structure layer 105 in the first area is etched away using the second patterned photoresist as a mask to form a second cavity, and the remaining second stress structure layer 105 in the second area is retained to form the second stress structure layer 105 .

[0103] In one embodiment, the method for preparing a channel structure for a GAA device specifically includes: forming a first stress structure layer 104 in a first region on the substrate 101, specifically including:

[0104] forming a first stress structure layer 104 in the second cavity;

[0105] The second patterned photoresist is removed.

[0106] In this specific embodiment, the first stress structure layer 104 is formed in the first region on the substrate 101. The method of introducing the second protective layer in the above-mentioned specific embodiment can be referred to, which will not be described in detail here. The channel structure formed according to this specific embodiment is as follows: Figure 6 shown.

[0107] In one embodiment, the method for preparing a channel structure for a GAA device further comprises, before forming a channel stack:

[0108] A first protection layer (not shown) is formed on the first stress structure layer 104 and the second stress structure layer 105 .

[0109] Please refer to Figure 4 and Figure 7 , step S13, after forming the channel stack, further comprising: steps S14-S23 to form a GAA device;

[0110] According to the aforementioned first specific embodiment, steps S14-S23 include:

[0111] Step S13, after forming the channel stack, further includes: steps S14-S23 to form a GAA device;

[0112] S14: etching the channel stack, the surface layer of the substrate 101 in the second region, and the surface layer of the first stress structure layer 104 in the first region to form a plurality of fin structures;

[0113] S15: forming a plurality of dummy gate 108 stacks; the dummy gate 108 stacks are formed on each fin structure and span across each fin structure; the dummy gate 108 stacks include the dummy gate 108 and the inner isolation layer 110107;

[0114] S16: etching the fin structure of the source region and / or the drain region 106 to form a source-drain cavity;

[0115] S17: forming an inner sidewall 109; the inner sidewall 109 is formed at both ends of the sacrificial layer 103 along a first direction; the first direction refers to the direction in which the first area and the second area are arranged on the paper;

[0116] S18: epitaxially grow a source region and / or a drain region 106 in the source-drain cavity. After the source region and / or the drain region 106 are formed, the structure is as follows: Figure 4 As shown;

[0117] S19: forming an interlayer dielectric layer; the interlayer dielectric layer is formed on the top of the source region and / or the drain region 106 and crosses the source region and / or the drain region 106;

[0118] S20: removing the dummy gate 108;

[0119] S21: releasing the channel layer 102 to form a channel cavity;

[0120] S22: forming a high-dielectric-constant dielectric layer and a metal gate layer; the high-dielectric-constant dielectric layer and the metal gate layer are formed in the channel cavity, and the metal gate layer is formed on the high-dielectric-constant dielectric layer;

[0121] S23: forming an etch stop layer and forming device contacts; the etch stop layer is formed on the surface of the device formed after step S22.

[0122] An isolation layer 110 is also formed between the first region and the second region.

[0123] According to the aforementioned second specific embodiment, steps S14-S23 include:

[0124] S14: etching the channel stack, the second stress structure layer 105 in the second region, and the surface layer of the first stress structure layer 104 in the first region to form a plurality of fin structures;

[0125] S15-S23 are consistent with the above, and will not be described in detail here; wherein S18: epitaxially growing the source region and / or drain region 106 in the source-drain cavity, and the structure after forming the source region and / or drain region 106 is as follows Figure 7 shown.

[0126] According to another embodiment of the present invention, a method for preparing a GAA device is provided, comprising: the method for preparing a channel structure for a GAA device according to any one of the aforementioned embodiments of the present invention.

[0127] According to other embodiments of the present invention, a GAA device is further provided, comprising the channel structure for the GAA device described in any one of the aforementioned embodiments of the present invention.

[0128] Again, according to an embodiment of the present invention, an electronic device is provided, comprising the GAA device described in the foregoing embodiment of the present invention.

[0129] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A channel structure for a GAA device, characterized in that: include: substrate; A first stress structure layer formed in a first region on the substrate; as well as Channel stacking; The channel stack is formed on the first stress structure layer and the second region of the substrate; Wherein, the first region is a region for forming an NMOS device, and the second region is a region for forming a PMOS device; the first stress structure layer is used to provide the stress required by the channel stack in the first region; A second stress structure layer; the second stress structure layer is formed on the second region of the substrate and is located between the substrate and the channel stack; wherein the second stress structure layer is used to provide the stress required by the channel stack in the second region; The material of the first stress structure layer is SiC, and the material of the second stress structure layer is SiGe.

2. The channel structure for a GAA device according to claim 1, characterized in that: A first protection layer is further included between the first stress structure layer and / or the second stress structure layer and the channel stack.

3. The channel structure for a GAA device according to claim 2, characterized in that: The material of the first protective layer is Si.

4. The channel structure for a GAA device according to claim 1, characterized in that: The thickness of the first stress structure layer and the second stress structure layer are both above a critical thickness.

5. A method for preparing a channel structure for a GAA device, characterized in that: The method comprises the following steps: providing a substrate; forming a first stress structure layer in a first region on the substrate; forming a channel stack; the channel stack is formed on the first stress structure layer and the second region of the substrate; Before forming a first stress structure layer in the first region on the substrate, the method further includes: forming a second stress structure layer; the second stress structure layer is formed in the second region on the substrate and directly contacts the substrate; The material of the first stress structure layer is SiC, and the material of the second stress structure layer is SiGe.

6. The method for preparing a channel structure for a GAA device according to claim 5, characterized in that: Forming a first stress structure layer in a first region on the substrate specifically includes: Coating a first photoresist on the substrate, exposing and developing the first photoresist to form a first patterned photoresist; Using the first patterned photoresist as a mask, etching the surface layer of the substrate in the first area to form a first cavity; A first stress structure layer is filled in the first cavity, and the first patterned photoresist is removed.

7. The method for preparing a channel structure for a GAA device according to claim 6, characterized in that: The forming of the second stress structure layer specifically includes: epitaxially growing a second structural layer on the substrate; coating a second photoresist on the second structural layer, exposing and developing the second photoresist to form a second patterned photoresist; The second stress structure layer in the first area is etched away using the second patterned photoresist as a mask to form a second cavity, and the remaining second stress structure layer in the second area is retained to form the second stress structure layer.

8. The method for preparing a channel structure for a GAA device according to claim 7, characterized in that: Specifically include: Forming a first stress structure layer in a first region on the substrate specifically includes: forming a first stress structure layer in the second cavity; The second patterned photoresist is removed.

9. The method for preparing a channel structure for a GAA device according to claim 8, characterized in that: Before forming the channel stack, the following steps are also included: A first protection layer is formed on the first stress structure layer and the second stress structure layer.

10. A method for preparing a GAA device, characterized in that: include: A method for preparing a channel structure for a GAA device as claimed in any one of claims 5 to 9.

11. A GAA device, characterized in that: The invention comprises a channel structure for a GAA device as described in any one of claims 1 to 4.

12. An electronic device, characterized in that: Includes the GAA device as claimed in claim 11.

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