Semiconductor memory device

Abstract

A semiconductor memory device can include an active layer spaced apart from a substrate, wherein the active layer extends in a direction parallel to the substrate and includes a channel; a bit line extending in a direction perpendicular to the substrate and coupled to a first end of the active layer; a capacitor coupled to a second end of the active layer; and a dual word line including a pair of dual work function electrodes extending in a direction crossing the active layer, the active layer interposed between the pair of dual work function electrodes, wherein each dual work function electrode includes a high work function electrode adjacent to the bit line and a low work function electrode adjacent to the capacitor and having a lower work function than the high work function electrode.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0029443, filed on March 5, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various embodiments of the present invention relate to a semiconductor device, and more particularly, to a three-dimensional semiconductor memory device. Background Technology

[0004] Since the integration density of two-dimensional (2D) semiconductor memory devices is primarily determined by the area occupied by the memory cells, it is greatly affected by the level of fine patterning technology. However, due to the need for extremely expensive equipment for pattern miniaturization, the integration density of 2D semiconductor memory devices is gradually increasing, but remains limited. Therefore, three-dimensional semiconductor memory devices incorporating memory cells arranged in three dimensions have been proposed. Summary of the Invention

[0005] Embodiments of the present invention relate to a three-dimensional semiconductor memory device comprising highly integrated memory cells.

[0006] According to one embodiment of the present invention, a semiconductor memory device includes: an active layer spaced apart from a substrate, wherein the active layer extends in a direction parallel to the substrate and includes a channel; a bit line extending in a direction perpendicular to the substrate and coupled to a first end of the active layer; a capacitor coupled to an end of a second end of the active layer; and a double word line including a pair of double power function electrodes extending in a direction intersecting the active layer, the active layer being interposed between the pair of double power function electrodes, wherein each of the double power function electrodes includes: a high power function electrode adjacent to the bit line; and a low power function electrode adjacent to the capacitor and having a lower power function than the high power function electrode.

[0007] According to another embodiment of the present invention, a semiconductor memory device includes: a substrate; an active layer stacked in a direction perpendicular to the surface of the substrate and including a channel; a bit line coupled to a first end of the active layer and oriented in a direction perpendicular to the surface of the substrate; a capacitor coupled to a second end of the active layer and including a memory node stacked in a direction perpendicular to the surface of the substrate; and a dual word line having a first word line and a second word line, the first word line and the second word line being oriented in a direction parallel to the surface of the substrate, each of the active layers being interposed between the first word line and the second word line, wherein each of the first word line and the second word line includes: a high work function electrode adjacent to the bit line; and a low work function electrode adjacent to the memory node and having a lower work function than the high work function electrode. Attached Figure Description

[0008] Figure 1 This is a schematic perspective view illustrating a memory cell of a semiconductor memory device according to an embodiment of the present invention.

[0009] Figure 2 It is shown Figure 1 A cross-sectional view of the storage unit.

[0010] Figure 3 This is a cross-sectional view showing a storage cell according to another embodiment of the present invention.

[0011] Figure 4A This is a schematic perspective view illustrating a semiconductor memory device according to an embodiment of the present invention.

[0012] Figure 4B It is shown Figure 4A A cross-sectional view of the vertical storage cell array MCA_C.

[0013] Figure 5 This is a cross-sectional view showing the edge portion of the double-line character.

[0014] Figure 6 This is a cross-sectional view showing a semiconductor memory device according to another embodiment of the present invention.

[0015] Figure 7 This is a schematic perspective view illustrating a semiconductor memory device according to another embodiment of the present invention.

[0016] Figures 8A to 8F An example of a method for manufacturing double-line characters according to an embodiment of the present invention is shown.

[0017] Figures 9A to 9G This is a cross-sectional view illustrating an example of a method for manufacturing bit lines and capacitors according to an embodiment of the present invention.

[0018] Figure 10A and Figure 10B It is a graph used to compare band diagrams and electric fields. Detailed Implementation

[0019] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure comprehensive and complete, and to fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, the same reference numerals refer to the same parts in the various drawings and embodiments of the invention.

[0020] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be exaggerated to clearly illustrate the features of the embodiments. When the first layer is referred to as being "on" or "on" the substrate of the second layer, it means not only that the first layer is formed directly on the second layer or substrate, but also that the third layer exists between the first layer and the second layer or substrate.

[0021] According to the following embodiments of the present invention, the storage cell density can be increased while reducing parasitic capacitance through vertically stacked storage cells.

[0022] The following embodiments of the invention, described later, relate to a three-dimensional (3D) dynamic random access memory (DRAM) device, and the word line may include a low power function electrode and a high power function electrode. The low power function electrode may be adjacent to a capacitor, while the high power function electrode may be adjacent to a bit line.

[0023] By utilizing the low power function of the low power function electrode, a low electric field can be formed between the word line and the capacitor, thereby improving leakage current.

[0024] The high work function of the high work function electrode not only forms a high threshold voltage for the transistor, but also reduces the height of the memory cell due to the formation of a low electric field, which is advantageous in terms of integration density.

[0025] Figure 1 This is a schematic perspective view showing a memory cell of a semiconductor memory device according to an embodiment of the present invention. Figure 2 It is shown Figure 1 A cross-sectional view of the storage unit.

[0026] See Figure 1 and Figure 2According to an embodiment of the present invention, the memory cell MC of a 3D semiconductor memory device may include: a bit line BL, a transistor TR, and a capacitor CAP. The transistor TR may include: an active layer ACT, a gate dielectric layer GD, and a double word line DWL. The capacitor CAP may include: a memory node SN, a dielectric layer DE, and a plate node PN. The bit line BL may have a cylindrical shape extending in a first direction D1. The active layer ACT may have a strip shape extending in a second direction D2 intersecting the first direction D1. The double word line DWL may have a line shape extending in a third third direction D3 intersecting the first direction D1 and the second direction D2. The plate node PN of the capacitor CAP may be coupled to the plate line PL.

[0027] Bit line BL may be vertically oriented in the first direction D1. Bit line BL may be referred to as a vertically oriented bit line, a vertically extended bit line, or a cylindrical bit line. Bit line BL may include a conductive material. Bit line BL may include, for example, a silicon-based material, a metal-based material, or a combination thereof. Bit line BL may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. Bit line BL may include, for example, polysilicon, titanium nitride, tungsten, or a combination thereof. For example, in one embodiment, bit line BL may include polysilicon or titanium nitride (TiN) doped with N-type impurities. In another embodiment, bit line BL may include a stack of titanium nitride and tungsten (TiN / W).

[0028] The dual word line (DWL) can extend along a third direction (D3), and the active layer (ACT) can extend along a second direction (D2). The active layer (ACT) can be arranged laterally from the bit line (BL). The dual word line (DWL) can include a first word line (WL1) and a second word line (WL2). The first word line (WL1) and the second word line (WL2) can face each other, and the active layer (ACT) is interposed between the first word line (WL1) and the second word line (WL2). A gate dielectric layer (GD) can be formed on the upper and lower surfaces of the active layer (ACT). The first word line (WL1) can be located above the active layer (ACT), and the second word line (WL2) can be located below the active layer (ACT).

[0029] The active layer ACT may include, for example, a semiconductor material or an oxide semiconductor material. For example, the active layer ACT may include silicon, germanium, silicon-germanium, or indium gallium zinc oxide (IGZO). The active layer ACT may include a channel CH, a first source / drain region SR between the channel CH and the bit line BL, and a second source / drain region DR between the channel CH and the capacitor CAP.

[0030] The first source / drain region SR and the second source / drain region DR can be doped with impurities of the same conductivity type. The first source / drain region SR and the second source / drain region DR can be doped with N-type or P-type impurities. The first source / drain region SR and the second source / drain region DR can include at least one impurity selected from arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. A first side of the first source / drain region SR can contact the bit line BL, and a second side of the first source / drain region SR can contact the channel CH. A first side of the second source / drain region DR can contact the memory node SN, and a second side of the second source / drain region DR can contact the channel CH. The second sides of the first source / drain region SR and the second source / drain region DR can overlap with the side portions of the first word line WL1 and the second word line WL2, respectively. The lateral length of the channel CH in the second direction D2 can be less than the lateral length of the first source / drain region SR and the second source / drain region DR in the second direction D2. According to another embodiment of the present invention, the lateral length of the channel CH in the second direction D2 can be greater than the lateral length of the first source / drain region SR and the second source / drain region DR in the second direction D2.

[0031] The transistor TR can be a single-cell transistor and can have a double word line (DWL). In the double word line DWL, the first word line WL1 and the second word line WL2 can have the same potential. For example, the first word line WL1 and the second word line WL2 can form a pair and can be coupled to a memory cell MC. The same word line drive voltage can be applied to the first word line WL1 and the second word line WL2. As described above, the memory cell MC according to an embodiment of the present invention can have a double word line DWL, wherein the first word line WL1 and the second word line WL2 are adjacent to a channel CH. The vertical thickness of the active layer ACT and the channel CH can be the same as the vertical thickness of each of the first word line WL1 and the second word line WL2.

[0032] The upper and lower surfaces of the active layer ACT can be flat. The upper and lower surfaces of the active layer ACT can be parallel to each other in the second direction D2.

[0033] For example, the gate dielectric layer (GD) may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The gate dielectric layer (GD) may include, for example, SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, or a combination thereof.

[0034] Double word line (DWL) materials can include, for example, metals, metal mixtures, metal alloys, or semiconductor materials. Double word line DWL materials can include, for example, titanium nitride, tungsten, polycrystalline silicon, or combinations thereof. For example, a double word line DWL can include a TiN / W stack of sequentially stacked titanium nitride and tungsten. Double word line DWL materials can include N-type work function materials or P-type work function materials. N-type work function materials can have a low work function of approximately 4.5 eV or less, while P-type work function materials can have a high work function of approximately 4.5 eV or higher.

[0035] According to an embodiment of the present invention, a dual word line (DWL) may include a pair of word lines, namely, a first word line WL1 and a second word line WL2, with an active layer (ACT) interposed between the first word line WL1 and the second word line WL2. The dual word line (DWL) may be coupled to a memory cell (MC).

[0036] Each of the first word line WL1 and the second word line WL2 may include a low work function electrode LWG and a high work function electrode HWG. The low work function electrode LWG and the high work function electrode HWG may be laterally positioned in the second direction D2. The low work function electrode LWG and the high work function electrode HWG may be in direct contact. The low work function electrode LWG may be adjacent to the second source / drain region DR, while the high work function electrode HWG may be adjacent to the first source / drain region SR. The low work function electrode LWG and the high work function electrode HWG may be formed of different work function materials. The high work function electrode HWG may have a higher work function than the low work function electrode LWG. The high work function electrode HWG may include a high work function material. The high work function electrode HWG may have a higher work function than the medium bandgap work function of silicon. The low work function electrode LWG may include a low work function material. The low work function electrode LWG may be a material with a lower work function than the medium bandgap work function of silicon. In other words, high work function materials can have a work function higher than approximately 4.5 eV, while low work function materials can have a work function lower than approximately 4.5 eV. The low work function electrode LWG can comprise doped polycrystalline silicon doped with an N-type dopant. The high work function electrode HWG can comprise a metal-based material. The high work function electrode HWG can comprise, for example, tungsten, titanium nitride, or combinations thereof. Although not shown, a barrier material can be further formed between the low work function electrode LWG and the high work function electrode HWG. The high work function electrode HWG can have a larger volume than the low work function electrode LWG; therefore, the dual word line DWL can have low resistance. The high work function electrodes HWG of the first word line WL1 and the second word line WL2 can overlap perpendicularly to each other in a first direction D1, with the channel CH interposed between the high work function electrodes HWG of the first word line WL1 and the second word line WL2. The low power function electrodes LWG of the first word line WL1 and the second word line WL2 can overlap perpendicularly to each other in the first direction D1, and the channel CH is inserted between the low power function electrodes LWG of the first word line WL1 and the low power function electrodes LWG of the second word line WL2. The overlap area between the high power function electrode HWG and the channel CH can be larger than the overlap area between the low power function electrode LWG and the channel CH. The low power function electrode LWG and the high power function electrode HWG can extend in the third direction D3, and the low power function electrode LWG and the high power function electrode HWG can be in direct contact with each other.

[0037] As described above, each of the first word line WL1 and the second word line WL2 can have a dual power function electrode structure including a low power function electrode LWG and a high power function electrode HWG. In other words, the dual word line DWL can have a pair of dual power function electrodes extending in a third direction D3 intersecting with the channel CH, with the channel CH interposed between the pair of dual power function electrodes. This pair of dual power function electrodes can refer to a pair of first word lines WL1 and second word lines WL2.

[0038] The bit-line side ohmic contact (BOC) can be further formed between the first source / drain region SR and the bit line BL. The bit-line side ohmic contact (BOC) can have a height that completely covers the sidewalls of the first source / drain region SR. The bit-line side ohmic contact (BOC) can be formed by depositing a metal layer and performing an annealing process. For example, the bit-line side ohmic contact (BOC) can be formed when the metal of the metal layer reacts with the silicon of the first source / drain region SR. The bit-line side ohmic contact (BOC) can include metal silicides such as titanium silicide, cobalt silicide, nickel silicide, etc.

[0039] The capacitor CAP can be laterally disposed on the second direction D2, starting from the transistor TR. The capacitor CAP may include a memory node SN extending laterally on the second direction D2, starting from the active layer ACT. The capacitor CAP may also include a dielectric layer DE and a board node PN above the memory node SN. The memory node SN, dielectric layer DE, and board node PN can be laterally arranged on the second direction D2. The memory node SN may have a horizontally oriented cylindrical shape. The dielectric layer DE may conformally cover the inner and outer walls of the cylindrical shape of the memory node SN. The board node PN may have a shape extending above the dielectric layer DE to the inner and outer walls of the cylindrical shape of the memory node SN. The board node PN may be coupled to a board line PL. The memory node SN may be electrically connected to a second source / drain region DR.

[0040] The storage node SN can have a 3D structure. The storage node SN can have a lateral 3D structure oriented in the second direction D2. As an example of a three-dimensional structure, the storage node SN can have a cylindrical shape. According to another embodiment of the invention, the storage node SN can have a columnar shape or a pylinder shape. A pylinder shape can refer to a structure combining a columnar shape and a cylindrical shape. The uppermost surface of the storage node SN can be located at the same level as the upper surface of the first word line WL1. The lowermost surface of the storage node SN can be located at the same level as the lower surface of the second word line WL2.

[0041] A board node PN may include an inner node N1 and outer nodes N2, N3, and N4. The inner node N1 and the outer nodes N2, N3, and N4 can be interconnected. The inner node N1 can be located inside the cylindrical structure of the storage node SN. The outer nodes N2 and N3 can be located outside the cylindrical structure of the storage node SN, with the dielectric layer DE inserted between the outer nodes N2 and N3. The outer node N4 can interconnect the inner node N1 with the outer nodes N2 and N3. The outer nodes N2 and N3 can be configured as the outer wall surrounding the cylindrical structure of the storage node SN. The outer node N4 can be used as a board line PL.

[0042] Storage nodes (SN) and board nodes (PN) can include metals, noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, storage nodes (SN) and board nodes (PN) can include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten nitride (TiN / W) stacks, or tungsten nitride / tungsten nitride (WN / W) stacks. Board nodes (PN) can include combinations of metal-based and silicon-based materials. For example, board nodes (PN) can be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In a titanium nitride / germanium silicon / tungsten nitride (TiN / SiGe / WN) stack, silicon and germanium can be used as gap fillers inside the cylindrical structure of the storage node (SN), titanium nitride (TiN) can be used as the plate node (PN) of the capacitor (CAP), and tungsten nitride can be a low-resistance material.

[0043] The dielectric layer DE may include, for example, silicon oxide, silicon nitride, high-k materials, or combinations thereof. High-k materials may have a higher dielectric constant than silicon oxide. Silicon oxide (SiO2) may have a dielectric constant of approximately 3.9, and the dielectric layer DE may include high-k materials having a dielectric constant of approximately 4 or greater. High-k materials may have a dielectric constant of approximately 20 or greater. High-k materials may include: hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). According to another embodiment of the invention, the dielectric layer DE may be formed from a composite layer comprising two or more layers of the aforementioned high-k materials.

[0044] The dielectric layer DE can be formed of zirconium-based oxide. The dielectric layer DE can have a stacked structure including zirconium oxide (ZrO2). The stacked structure including zirconium oxide (ZrO2) can include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. The ZA stack can have a structure in which alumina (Al2O3) is stacked on top of zirconium oxide (ZrO2). The ZAZ stack can have a structure in which zirconium oxide (ZrO2), alumina (Al2O3), and zirconium oxide (ZrO2) are stacked sequentially. The ZA stack and the ZAZ stack can be referred to as a zirconium oxide base layer (ZrO2-based layer). According to another embodiment of the invention, the dielectric layer DE can be formed of hafnium-based oxide. The dielectric layer DE can have a stacked structure including hafnium oxide (HfO2). Layered structures including hafnium oxide (HfO2) can include HA (HfO2 / Al2O3) stacks or HAH (HfO2 / Al2O3 / HfO2) stacks. HA stacks can have a structure where alumina (Al2O3) is stacked on top of hafnium oxide (HfO2). HAH stacks can have a structure where hafnium oxide (HfO2), alumina (Al2O3), and hafnium oxide (HfO2) are stacked sequentially. HA stacks and HAH stacks can be referred to as hafnium oxide-based layers. In ZA stacks, ZAZ stacks, HA stacks, and HAH stacks, alumina (Al2O3) can have a larger band gap than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Alumina (Al2O3) can have a lower dielectric constant than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, the dielectric layer DE can include a stack of a high-k material and a high-bandgap material having a larger bandgap than the high-k material. The dielectric layer DE can include, for example, silicon oxide (SiO2) as a high-bandgap material other than aluminum oxide (Al2O3). Because the dielectric layer DE includes a high-bandgap material, leakage current can be suppressed. The high-bandgap material can be thinner than the high-k material. According to another embodiment of the invention, the dielectric layer DE can include a laminated structure of alternating layers of high-k and high-bandgap materials. For example, ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3), ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2), HAHA (HfO2 / Al2O3 / HfO2 / Al2O3), or HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2). In the above laminated structure, aluminum oxide (Al2O3) can be thinner than zirconium oxide (ZrO2) and hafnium oxide (HfO2).

[0045] According to another embodiment of the present invention, the dielectric layer DE may include a stacked structure, a laminated structure, or a hybrid structure comprising zirconium oxide, hafnium oxide, and aluminum oxide.

[0046] According to another embodiment of the invention, an interface control layer (not shown) for improving leakage current can be further formed between the storage node SN and the dielectric layer DE. The interface control layer may include titanium oxide (TiO2), tantalum oxide (Ta2O5), or niobium oxide (Nb2O5). The interface control layer may also be formed between the plate node PN and the dielectric layer DE.

[0047] Capacitors (CAP) can include metal-insulator-metal (MIM) capacitors. Storage nodes (SN) and board nodes (PN) can include metal-based materials.

[0048] Capacitors (CAPs) can be replaced by other data storage materials. For example, data storage materials can be phase change materials, magnetic tunnel junctions (MTJs), or variable resistance materials.

[0049] The storage node-side ohmic contact SOC can be further formed between the second source / drain region DR and the storage node SN. The storage node-side ohmic contact SOC can have a height that completely covers the sides of the second source / drain region DR. The storage node-side ohmic contact SOC can be formed by depositing a metal layer and performing an annealing process. For example, the storage node-side ohmic contact SOC can be formed when the metal of the metal layer reacts with the silicon of the second source / drain region DR. The storage node-side ohmic contact SOC can include metal silicides. The storage node-side ohmic contact (SOC) can include titanium silicide, cobalt silicide, nickel silicide, etc.

[0050] As described above, the memory cell MC may include a dual word line DWL with a pair of dual power function electrodes. Each of the first word line WL1 and the second word line WL2 of the dual word line DWL may include a low power function electrode LWG and a high power function electrode HWG. The low power function electrode LWG may be adjacent to the capacitor CAP, while the high power function electrode HWG may be adjacent to the bit line BL. Due to the low power function of the low power function electrode LWG, a low electric field can be formed between the dual word line DWL and the capacitor CAP, thereby improving leakage current. Due to the high power function of the high power function electrode HWG, not only can a high threshold voltage of the transistor TR be formed, but the height of the memory cell MC can also be reduced due to the formation of the low electric field, which is beneficial for improving integration density.

[0051] As a comparative example 1, when the first word line WL1 and the second word line WL2 are formed only by a metal-based material, a high electric field can be formed between the first word line WL1 and the second word line WL2 and the capacitor CAP, thereby reducing the leakage current of the memory cell MC. The deterioration of the leakage current due to the high electric field can be enhanced as the channel CH becomes thinner.

[0052] As a comparative example 2, when the first word line WL1 and the second word line WL2 are formed only of low work function materials, the threshold voltage of the transistor TR can be reduced due to the low work function, thereby generating leakage current.

[0053] According to an embodiment of the present invention, each of the first word line WL1 and the second word line WL2 of the dual word line DWL has a double-function electrode structure to prevent leakage current. This enables the refresh characteristics of the memory cell MC to be ensured and power consumption to be reduced.

[0054] Furthermore, according to embodiments of the present invention, each of the first word line WL1 and the second word line WL2 of the dual word line DWL has a dual-function electrode structure, which is relatively advantageous for increasing the electric field even if the thickness of the channel CH is reduced for the purpose of high integration, thus realizing a large number of stacks.

[0055] Figure 3 This is a cross-sectional view showing a storage cell MC' according to another embodiment of the present invention. Figure 3 In the middle, also Figure 1 and Figure 2 Detailed descriptions of the constituent elements appearing in the text can be omitted.

[0056] See Figure 3 The memory cell MC' may include a bit line BL, a transistor TR, and a capacitor CAP. The transistor TR may include a thin active layer ACT', and the thin active layer ACT' may be thinner than the first word line WL1 and the second word line WL2. In other words, the vertical thickness of the thin active layer ACT' in the first direction D1 may be thinner than the vertical thickness of each of the first word line WL1 and the second word line WL2 in the first direction D1. Accordingly, the thin active layer ACT' with its thin thickness may include a thin channel CH'. The thin channel CH' may be thinner than the vertical thickness of each of the first word line WL1 and the second word line WL2. The thickness of the thin channel CH' may be approximately 10 nm or less (1 nm to 10 nm). The first word line WL1 and the second word line WL2 may intersect with the thin active layer ACT', which is located between the first word line WL1 and the second word line WL2. A pair of first word lines WL1 and second word lines WL2 may be dual word lines DWL, each having a dual function electrode. Each of the first word line WL1 and the second word line WL2 may include a high power function electrode HWG and a low power function electrode LWG.

[0057] Figure 4A This is a schematic perspective view illustrating a semiconductor memory device according to an embodiment of the present invention. Figure 4B It is shown Figure 4A A cross-sectional view of the vertical storage cell array MCA_C. Figure 5 This is a cross-sectional view showing the edge portion of other double-line characters.

[0058] See Figure 4A , Figure 4B and Figure 5 The semiconductor memory device 100 may include a multilayer memory cell array (MCA), the MCA comprising cells arranged in a first direction to a third direction D1, D2, and D3 according to... Figure 1 The storage cells MC. The storage cell array MCA can include a 3D array of storage cells MC. The 3D storage cell array MCA can include a vertical storage cell array MCA_C and a horizontal storage cell array MCA_R. The vertical storage cell array MCA_C can refer to an array of storage cells MC arranged vertically in a first direction D1. The horizontal storage cell array MCA_R can refer to an array of storage cells MC arranged horizontally in a third direction D3. The vertical storage cell array MCA_C can be referred to as a column array of storage cells MC. The horizontal storage cell array MCA_R can be referred to as a row array of storage cells MC. Bit lines BL can be vertically oriented to couple to the vertical storage cell array MCA_C, and double word lines DWL can be horizontally oriented to couple to the horizontal storage cell array MCA_R. The bit lines BL of storage cells MC coupled to the vertical storage cell array MCA_C can be referred to as common bit lines, and vertical storage cell arrays MCA_C adjacent to each other in the third direction D3 can be coupled to different common bit lines. The double word line DWL of the memory cell MC coupled to the horizontal memory cell array MCA_R can be called the common double word line, and adjacent horizontal memory cell arrays MCA_R in the first direction D1 can be coupled to different common double word lines.

[0059] The memory cell array (MCA) may include multiple memory cells (MCs), each of which may include a vertically oriented bit line (BL), a horizontally oriented active layer (ACT), a double word line (DWL), and a horizontally oriented capacitor (CAP). Figure 4A A three-dimensional memory cell array comprising four memory cells (MCs) is shown.

[0060] Adjacent active layers ACT on the first direction D1 can contact a bit line BL. Adjacent active layers ACT on the third direction D3 can share a double word line DWL. Capacitors CAP can be coupled to a corresponding active layer ACT. Capacitors CAP can share a board line PL. Each active layer ACT can be thinner than the first word line WL1 and the second word line WL2 of the double word line DWL.

[0061] In a memory cell array (MCA), two double word lines (DWLs) can be vertically stacked in a first direction D1. Each DWL can include a pair of first word lines WL1 and second word lines WL2. Multiple active layers (ACTs) can be arranged laterally, spaced apart from each other along a second direction D2 between the first word lines WL1 and WL2. The channel CH of the active layer ACTs can be located between the first word lines WL1 and WL2.

[0062] Each of the first word line WL1 and the second word line WL2 in a dual word line (DWL) may include a low work function electrode LWG and a high work function electrode HWG. The low work function electrode LWG may be adjacent to the capacitor CAP, while the high work function electrode HWG may be adjacent to the bit line BL.

[0063] See back Figure 5 In each of the double letter lines DWL, the edge portions on both sides can have a stepped shape, and the stepped shape can define the contact portion CA. Each of the first letter line WL1 and the second letter line WL2 can include edge portions on both sides, i.e., contact portions CA. Each contact portion CA can have a stepped shape.

[0064] Multiple word line pads WLP1 and WLP2 can be coupled to contact portions CA. The first word line pad WLP1 can be coupled to the contact portion CA of the upper-layer first word line WL1 and second word line WL2, while the second word line pad WLP2 can be coupled to the contact portion CA of the lower-layer first word line WL1 and second word line WL2. The upper-layer first word line WL1 and second word line WL2 can be interconnected with each other through the first word line pad WLP1. The lower-layer first word line WL1 and second word line WL2 can be interconnected with each other through the second word line pad WLP2.

[0065] The semiconductor memory device 100 may further include a substrate PERI beneath the memory cell array MCA, and the substrate PERI may include peripheral circuitry. Hereinafter, the substrate PERI will be simply referred to as the peripheral circuitry portion PERI. The bit lines BL of the memory cell array MCA may be oriented perpendicular to the surface of the peripheral circuitry portion PERI, and the double word lines DWL may be oriented parallel to the surface of the peripheral circuitry portion PERI.

[0066] The Peripheral Circuit I (PERI) can be located at a lower level than the Cell Array (MCA). This can be referred to as a Cell Over Peripheral (COP) structure. The PERI may include at least one or more control circuits for driving the MCA. These control circuits may include N-channel transistors, P-channel transistors, CMOS circuits, or combinations thereof. They may also include address decoder circuits, read circuits, write circuits, etc. Furthermore, the PERI may include planar channel transistors, recessed channel transistors, buried gate transistors, fin-channel transistors (FinFETs), etc.

[0067] For example, the peripheral circuitry PERI may include sub-word line drivers SWD1 and SWD2, and a sense amplifier SA. The upper-layer dual word line (DWL) can be coupled to sub-word line driver SWD1 via a first word line pad WLP1 and a metal interconnect MI1. The lower-layer dual word line (DWL) can be coupled to sub-word line driver SWD2 via a second word line pad WLP2 and a metal interconnect MI2. The bit line BL can be coupled to the sense amplifier SA via a metal interconnect MI3. The metal interconnect MI3 may have a multilayer metal interconnect (MLM) structure including multiple vias and multiple metal lines.

[0068] Figure 6 This is a schematic cross-sectional view illustrating a memory cell array of a semiconductor memory device according to another embodiment of the present invention. Figure 6 A semiconductor memory device 110 with a POC structure is shown. Figure 6 In the middle, the word "pair" can be omitted and also appears. Figure 5 A detailed description of the constituent elements.

[0069] See Figure 6 The semiconductor memory device 110 may include a memory cell array (MCA) and a peripheral circuit section (PERI'). The peripheral circuit section (PERI') may be located at a higher level than the memory cell array (MCA). This may be referred to as a PERI over Cell (POC) structure.

[0070] The peripheral circuitry PERI' may include sub-word line drivers SWD1 and SWD2, and a sense amplifier SA. The upper-layer dual-word line DWL is coupled to sub-word line driver SWD1 via a first word line pad WLP1 and a metal interconnect MI1. The lower-layer dual-word line DWL is coupled to sub-word line driver SWD2 via a second word line pad WLP2 and a metal interconnect MI2. The bit line BL is coupled to the sense amplifier SA via a metal interconnect MI3. The metal interconnect MI3 may have a multilayer metal interconnect structure including multiple vias and multiple metal lines.

[0071] Figure 7 This is a schematic perspective view illustrating a semiconductor memory device according to another embodiment of the present invention. Figure 7 In the middle, the word "pair" can be omitted and also appears. Figures 1 to 6 A detailed description of the constituent elements.

[0072] See Figure 7 The semiconductor memory device 200 may include a peripheral circuit section PERI and a memory cell array MCA10 on top of the peripheral circuit section PERI. The memory cell array MCA10 may include a plurality of memory cells. (See above reference...) Figure 3 The memory cell array MCA10 described herein may include a column array of memory cells and a row array of memory cells. Each memory cell may include a transistor TR and a capacitor CAP, and each transistor TR may include an active layer ACT and a double word line DWL. The double word line DWL may include a low work function electrode LWG and a high work function electrode HWG that are laterally adjacent to each other in a second direction D2. Each capacitor CAP may be coupled to the active layer ACT via a memory node-side ohmic contact SOC. Bit lines BL1 and BL2 may be coupled to the active layer ACT via corresponding bit line-side ohmic contacts BOC.

[0073] The column array of memory cells may include a mirror structure sharing one of the bit lines BL1 and BL2.

[0074] For example, a column array comprising memory cells arranged laterally in the second direction D2 and with bit lines BL1 inserted therebetween can be arranged as a mirror structure that shares bit lines BL1 and is coupled to different board lines PL1 and PL2.

[0075] Figures 8A to 8F An example of a method for manufacturing double-line characters according to an embodiment of the present invention is shown.

[0076] See Figure 8AA stack SB can be formed on a substrate (not shown). The stack SB may include dielectric layers 11 and 15, sacrificial layers 12 and 14, and an active layer 13. The active layer 13 may be disposed between the lower dielectric layer 11 and the upper dielectric layer 15. The lower sacrificial layer 12 may be disposed between the lower dielectric layer 11 and the active layer 13, and the upper sacrificial layer 14 may be disposed between the upper dielectric layer 15 and the active layer 13. The dielectric layers 11 and 15 may include, for example, silicon oxide, and the sacrificial layers 12 and 14 may include silicon nitride. The active layer 13 may include a semiconductor material or an oxide semiconductor material. The active layer 13 may include polysilicon or IGZO. As described above, the stack SB may be stacked multiple times when memory cells are stacked. According to another embodiment of the invention, in order to form a thin active layer and a thin channel, the active layer 13 may be formed thinner than the dielectric layers 11 and 15 and the sacrificial layers 12 and 14.

[0077] The first opening 16 can be formed by etching the stack SB. The first opening 16 can extend vertically. Although not shown, the stack SB can be patterned based on the memory cells before forming the first opening 16.

[0078] See Figure 8B The groove 17 can be formed by selectively etching the sacrificial layers 12 and 14 through the first opening 16. A portion of the active layer 13 can be exposed by the groove 17.

[0079] See Figure 8C A gate dielectric layer 18 may be formed over the exposed portion of the active layer 13. The gate dielectric layer 18 may include, for example, silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or combinations thereof. The gate dielectric layer 18 may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, etc.

[0080] Next, a low work function material 19A can be used to fill the recess 17. The low work function material 19A can fill the first opening 16 and the recess 17 above the gate dielectric layer 18. The low work function material 19A can include a conductive material. The low work function material 19A can have a work function lower than that of silicon. For example, the low work function material 19A can include polycrystalline silicon doped with N-type impurities.

[0081] See Figure 8D A low work function electrode 19L can be formed in the groove 17. To form the low work function electrode 19L, a low work function material 19A can be selectively etched. For example, a wet etching process can be performed on the low work function material 19A.

[0082] See Figure 8E A high work function material 19B can be formed on the low work function electrode 19L to fill the first opening 16 and the groove 17. The high work function material 19B can have a higher work function than the mid-bandgap work function of silicon. The high work function material 19B can have a higher work function than the low work function electrode 19L. The high work function material 19B can have a lower resistance than the low work function electrode 19L. The high work function material 19B can include a metal-based material. For example, the high work function material 19B can include titanium nitride, tungsten, or a combination thereof. According to embodiments of the present invention, the high work function material 19B can include sequentially stacked titanium nitride pads and tungsten.

[0083] See Figure 8F A high work function electrode 19H can be formed in the groove 17. To form the high work function electrode 19H, selective etching of the high work function material 19B can be performed. For example, wet etching of the high work function material 19B can be performed.

[0084] The high work function electrode 19H can contact one side of the low work function electrode 19L. The high work function electrode 19H can have a higher work function than the low work function electrode 19L. The high work function electrode 19H can include a metal-based material. For example, the high work function electrode 19H can include titanium nitride, tungsten, or a combination thereof.

[0085] The first word line WL1 and the second word line WL2 can be formed as an active layer 13 inserted between them. The first word line WL1 and the second word line WL2 can correspond to Figures 1 to 7 The double word line DWL is shown. Each of the first word line WL1 and the second word line WL2 can have a double work function electrode structure including a low work function electrode 19L and a high work function electrode 19H.

[0086] Figures 9A to 9G This is a cross-sectional view illustrating an example of a method for manufacturing bit lines and capacitors according to an embodiment of the present invention.

[0087] First line WL1 and second line WL2 pass through Figures 8A to 8F After the series of processes shown are completed, as follows Figure 9A As shown, a pad layer 20 can be formed on one side of the high work function electrode 19H. The pad layer 20 may include, for example, silicon oxide or silicon nitride. The pad layer 20 may fill other spaces in the recess 17.

[0088] Subsequently, a portion of the gate dielectric layer 18 exposed by the pad layer 20 can be etched to expose the first end E1 of the active layer 13.

[0089] See Figure 9BA first source / drain region 21 can be formed at the first end E1 of the active layer 13. The first source / drain region 21 can be formed by impurity doping. According to another embodiment of the invention, after filling the first opening 16 with polysilicon containing impurities, a heat treatment can be subsequently performed to allow the impurities to diffuse from the polysilicon to the first end E1 of the active layer 13. As a result, the first source / drain region 21 can be formed at the first end E1 of the active layer 13.

[0090] See Figure 9C A bit-line side ohmic contact 22 can be formed over the first source / drain region 21. The bit-line side ohmic contact 22 may include a metal silicide. For example, the metal silicide can be formed by sequentially depositing a metal layer over the first source / drain region 21 and performing an annealing process, and unreacted metal layers can be removed. When silicon in the first source / drain region 21 reacts with the metal layer, a metal silicide can be formed.

[0091] See Figure 9D A bit line 23 can be formed to contact the bit line side ohmic contact 22. The bit line 23 can fill the first opening 16. The bit line 23 can include, for example, titanium nitride, tungsten, or combinations thereof.

[0092] See Figure 9E The second opening 24 can be formed by etching another part of the laminate SB. The second opening 24 can extend vertically.

[0093] Subsequently, sacrificial layers 12 and 14 and active layer 13 can be selectively recessed through the second opening 24. As a result, a capacitor opening 24L can be formed between dielectric layers 11 and 15. Active layer 13 can be retained as indicated by the reference numeral "ACT", and the second end E2 of active layer ACT can be exposed by the capacitor opening 24L.

[0094] Subsequently, a second source / drain region 25 can be formed at the second end E2 of the recessed active layer ACT. The second source / drain region 25 can be formed by impurity doping. According to another embodiment of the invention, after filling the second opening 24 and the capacitor opening 24L with polysilicon containing impurities, a heat treatment can then be performed to diffuse the impurities from the polysilicon to the second end E2 of the active layer. As a result, the second source / drain region 25 can be formed at the second end E2 of the active layer ACT. A channel CH can be defined between the first source / drain region 21 and the second source / drain region 25.

[0095] Subsequently, a memory node-side ohmic contact 26 can be formed on the second source / drain region 25. The memory node-side ohmic contact 26 may include, for example, a metal silicide. For instance, the metal silicide can be formed by sequentially depositing a metal layer on the second source / drain region 25 and performing an annealing process, and unreacted metal layers can be removed. A metal silicide can be formed when silicon in the second source / drain region 25 reacts with the metal layer.

[0096] See Figure 9F A storage node 27 can be formed to contact the ohmic contact 26 on the storage node side. The storage node 27 can be formed by depositing a conductive material and performing an etch-back process. The storage node 27 may include titanium nitride. The storage node 27 may have a laterally oriented cylindrical shape.

[0097] See Figure 9G After the dielectric layers 11 and 15 are recessed, the dielectric layer 28 and the board node 29 can be sequentially formed on the storage node 27.

[0098] Figure 10A and Figure 10B It is a graph used to compare band diagrams and electric fields. Figure 10A and Figure 10B The energy band diagrams of a single-metal gate structure and a dual-metal / polysilicon gate structure in the "1" hold state were compared during DRAM operation. Here, the "1" hold state refers to the cases where the word line is low, the bit line is low, and the board line is high.

[0099] See Figure 10A and Figure 10B As can be seen, a relatively low electric field is formed between the word line and the capacitor in the bimetallic / polysilicon gate structure, while maintaining a potential barrier.

[0100] As can be seen from the above, the 3D DRAM cell with a dual-metal / polysilicon gate structure achieves both a sufficiently high threshold voltage and low leakage current.

[0101] According to an embodiment of the present invention, since the word line has a dual power function electrode structure with low power function electrodes and high power function electrodes, power consumption can be reduced while ensuring the refresh characteristics of the memory cell.

[0102] According to an embodiment of the present invention, since a dual word line with a dual function electrode structure is formed, a memory cell including a thin-body channel can be highly integrated.

[0103] Although the invention has been described with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A semiconductor memory device, comprising: An active layer spaced apart from a substrate, wherein the active layer extends in a direction parallel to the substrate and includes channels; Bit lines that extend in a direction perpendicular to the substrate and are coupled to a first end of the active layer; A capacitor, coupled to the end of the second terminal of the active layer; and A double-word line includes a pair of double-function electrodes extending in a direction intersecting the active layer, the active layer being interposed between the pair of double-function electrodes. Each of the dual-function electrodes includes: High work function electrode, which is adjacent to the bit line; and A low work function electrode, which is adjacent to the capacitor and has a lower work function than the high work function electrode.

2. The semiconductor memory device according to claim 1, wherein, The low work function electrode has a work function lower than that of silicon with a medium bandgap, and The high work function electrode has a higher work function than the medium bandgap work function of the silicon.

3. The semiconductor memory device according to claim 1, wherein, The low work function electrode comprises N-type doped polycrystalline silicon.

4. The semiconductor memory device according to claim 1, wherein, The high work function electrode comprises a metal-based material.

5. The semiconductor memory device according to claim 1, wherein, The high work function electrode comprises titanium nitride, tungsten, or a stack of titanium nitride and tungsten.

6. The semiconductor memory device according to claim 1, wherein, The high work function electrode has a larger volume than the low work function electrode.

7. The semiconductor memory device according to claim 1, wherein, Both the high work function electrode and the low work function electrode overlap perpendicularly with the active layer.

8. The semiconductor memory device according to claim 7, wherein, The overlap area between the high work function electrode and the active layer is greater than the overlap area between the low work function electrode and the active layer.

9. The semiconductor memory device according to claim 1, wherein, The channel of the active layer includes: The thin channel is thinner than the high work function electrode and the low work function electrode.

10. The semiconductor memory device according to claim 1, wherein, The active layer includes semiconductor materials or oxide semiconductor materials.

11. The semiconductor memory device according to claim 1, wherein, The active layer includes polycrystalline silicon, germanium, silicon-germanium, or indium gallium zinc oxide (IGZO).

12. The semiconductor memory device according to claim 1, wherein, The active layer further includes: The first source / drain region, coupled to the bit line, and The second source / drain region is coupled to the capacitor.

13. The semiconductor memory device of claim 12, further comprising: The bit line-side ohmic contact is located between the bit line and the first source / drain region, and An ohmic contact is located on the storage node side between the capacitor and the second source / drain region.

14. The semiconductor memory device according to claim 1, further comprising: Word line pads, which are coupled to the dual word lines.

15. The semiconductor memory device according to claim 1, wherein, The capacitor includes: A cylindrical storage node coupled to the end of the second end of the active layer.

16. A semiconductor memory device, comprising: Substrate; An active layer, which is stacked in a direction perpendicular to the surface of the substrate and includes channels; Bit lines, which are coupled to a first end of the active layer and oriented in a direction perpendicular to the surface of the substrate; A capacitor coupled to a second end of the active layer, and a storage node stacked in a direction perpendicular to the surface of the substrate; as well as A dual word line, comprising a first word line and a second word line, wherein the first word line and the second word line are oriented in a direction parallel to the surface of the substrate, and each of the active layers is interposed between the first word line and the second word line. Both the first character line and the second character line include: High work function electrode, which is adjacent to the bit line; and A low work function electrode, which is adjacent to the storage node and has a lower work function than the high work function electrode.

17. The semiconductor memory device according to claim 16, wherein, The low work function electrode has a work function lower than that of silicon with a medium bandgap, and The high work function electrode has a higher work function than the medium bandgap work function of the silicon.

18. The semiconductor memory device according to claim 16, wherein, The low work function electrode comprises N-type doped polycrystalline silicon, and The high work function electrode comprises a metal-based material.

19. The semiconductor memory device according to claim 16, wherein, The high work function electrode comprises titanium nitride, tungsten, or a stack of titanium nitride and tungsten.

20. The semiconductor memory device according to claim 16, wherein, The channel of the active layer includes: The thin channel is thinner than the high work function electrode and the low work function electrode.

21. The semiconductor memory device according to claim 16, wherein, The active layer includes: Semiconductor materials or oxide semiconductor materials.

22. The semiconductor memory device according to claim 16, wherein, The active layer includes polycrystalline silicon, germanium, silicon-germanium, or indium gallium zinc oxide (IGZO).

23. The semiconductor memory device of claim 16, wherein, The active layer further includes: The first source / drain region, coupled to the bit line, and The second source / drain region is coupled to the capacitor.

24. The semiconductor memory device of claim 23, further comprising: The bit line-side ohmic contact is located between the bit line and the first source / drain region, and An ohmic contact is located on the storage node side between the capacitor and the second source / drain region.

25. The semiconductor memory device of claim 16, further comprising: Word line pads, which are coupled together with the first word line and the second word line.

26. The semiconductor memory device according to claim 16, wherein, Each of the capacitors includes: A cylindrical storage node, coupled to the end of the second end of the active layer. A dielectric layer, which is located above the storage node, and A plate node, which is located above the dielectric layer.

27. The semiconductor memory device according to claim 16, wherein, The substrate includes: The peripheral circuitry section is used to control the storage unit.

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