Semiconductor memory device

Abstract

Embodiments provide a semiconductor memory device that is easily highly integrated. The semiconductor memory device of the embodiments includes a substrate, a plurality of conductive layers arranged in a first direction and extending in a second direction, a semiconductor layer extending in the first direction and opposing the plurality of conductive layers, and n contact electrode regions arranged in a third direction. n is a power of 2. The contact electrode regions have a plurality of contact electrodes arranged in the second direction. The plurality of conductive layers includes a first conductive layer and a second conductive layer that is an n-th conductive layer counted from the first conductive layer. The plurality of contact electrodes includes a first contact electrode connected to the first conductive layer, a second contact electrode connected to the second conductive layer, and a third contact electrode provided between the first contact electrode and the second contact electrode. The first contact electrode, the second contact electrode, and the third contact electrode are arranged in the second direction or the third direction.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2021-033117 (filed on March 3, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Technology

[0004] A known semiconductor memory device includes: a substrate; a plurality of conductive layers stacked in a direction intersecting with the surface of the substrate; a semiconductor layer opposite to the plurality of conductive layers; and a gate insulating layer disposed between the conductive layers and the semiconductor layer. The gate insulating layer may be, for example, a data storage section having a charge storage layer with insulating properties such as silicon nitride (Si3N4) or a conductive charge storage layer such as a floating gate. Summary of the Invention

[0005] The problem to be solved by the present invention is to provide a semiconductor memory device that is easy to integrate.

[0006] One embodiment of a semiconductor memory device includes: a substrate; a plurality of conductive layers arranged in a first direction intersecting the surface of the substrate and extending in a second direction intersecting the first direction; a semiconductor layer extending in the first direction and opposite to the plurality of conductive layers; and n contact electrode regions arranged in a third direction intersecting the first and second directions, where n is an integer greater than or equal to 2. n is a power of 2. The contact electrode regions include a plurality of contact electrodes arranged in the second direction. The plurality of conductive layers includes a first conductive layer and a second conductive layer, the second conductive layer being the nth conductive layer counting from the first conductive layer. The plurality of contact electrodes included in the n contact electrode regions include: a first contact electrode connected to the first conductive layer; a second contact electrode connected to the second conductive layer; and a third contact electrode disposed between the first and second contact electrodes. The first, second, and third contact electrodes are arranged in either the second or third direction.

[0007] One embodiment of a semiconductor memory device includes: a substrate; a plurality of conductive layers arranged in a first direction intersecting the surface of the substrate and extending in a second direction intersecting the first direction; a semiconductor layer extending in the first direction and opposite to the plurality of conductive layers; and n contact electrode regions arranged in a third direction intersecting the first and second directions, where n is an integer greater than or equal to 2. n is not a power of 2. Each contact electrode region includes a plurality of contact electrodes arranged in the second direction. For example, the smallest power of 2 greater than n is set to m. The plurality of conductive layers includes a first conductive layer and a second conductive layer, the second conductive layer being the m-th conductive layer counting from the first conductive layer. The plurality of contact electrodes included in the n contact electrode regions include: a first contact electrode connected to the first conductive layer; a second contact electrode connected to the second conductive layer; and a third contact electrode disposed between the first and second contact electrodes. The first, second, and third contact electrodes are arranged in either the second or third direction.

[0008] One embodiment of a semiconductor memory device includes: a substrate; a first conductive layer separated from the substrate in a first direction intersecting with the surface of the substrate; a second conductive layer disposed between the first conductive layer and the substrate; a third conductive layer closer to the substrate than the second conductive layer, or farther from the substrate than the first conductive layer; a semiconductor layer extending in the first direction and opposite to the first, second, and third conductive layers; a first contact electrode extending in the first direction and connected to the first conductive layer; a second contact electrode extending in the first direction and connected to the second conductive layer; and a third contact electrode extending in the first direction and connected to the third conductive layer. The first, second, and third conductive layers extend in a second direction intersecting the first direction. The third contact electrode is disposed between the first and second contact electrodes in the second direction. Attached Figure Description

[0009] Figure 1 This is a schematic top view of the memory die MD according to the first embodiment.

[0010] Figure 2 yes Figure 1 A schematic enlarged view of part A and part B.

[0011] Figure 3 yes Figure 2 A schematic enlarged view of part C.

[0012] Figure 4 It is Figure 3 The diagram shows a schematic cross-section of the structure cut along line D-D' and viewed in the direction of the arrow.

[0013] Figure 5 yes Figure 4 A schematic enlarged view of the part shown as E.

[0014] Figure 6 It is Figure 2 The diagram shows a schematic cross-section of the structure cut along line F-F' and viewed in the direction of the arrow.

[0015] Figure 7 It is Figure 2 The diagram shows a schematic cross-section of the structure cut along line G-G' and viewed in the direction of the arrow.

[0016] Figure 8 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0017] Figure 9 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0018] Figure 10 This is a schematic top view used to illustrate the manufacturing method.

[0019] Figure 11 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0020] Figure 12 This is a schematic top view used to illustrate the manufacturing method.

[0021] Figure 13 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0022] Figure 14 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0023] Figure 15 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0024] Figure 16 This is a schematic top view used to illustrate the manufacturing method.

[0025] Figure 17 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0026] Figure 18 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0027] Figure 19 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0028] Figure 20 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0029] Figure 21 This is a schematic top view used to illustrate the manufacturing method.

[0030] Figure 22 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0031] Figure 23 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0032] Figure 24 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0033] Figure 25 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0034] Figure 26 This is a schematic top view used to illustrate the manufacturing method.

[0035] Figure 27 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0036] Figure 28 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0037] Figure 29 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0038] Figure 30 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0039] Figure 31 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0040] Figure 32 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0041] Figure 33 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0042] Figure 34 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0043] Figure 35 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0044] Figure 36 This is a schematic top view of the semiconductor memory device involved in the scale.

[0045] Figure 37 It is Figure 36 The diagram shows a schematic cross-section of the structure cut along line H-H' and viewed in the direction of the arrow.

[0046] Figure 38 It is Figure 36 The diagram shows a schematic cross-section of the structure cut along line I-I' and viewed in the direction of the arrow.

[0047] Figure 39 It is a schematic top view used to illustrate the manufacturing method of the semiconductor memory device involved in the comparative example.

[0048] Figure 40 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0049] Figure 41 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0050] Figure 42 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0051] Figure 43 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0052] Figure 44 This is a schematic top view used to illustrate the manufacturing method.

[0053] Figure 45 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0054] Figure 46 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0055] Figure 47 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0056] Figure 48 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0057] Figure 49 This is a schematic top view used to illustrate the manufacturing method.

[0058] Figure 50 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0059] Figure 51 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0060] Figure 52 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0061] Figure 53 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0062] Figure 54This is a schematic top view showing a portion of the structure of the semiconductor memory device according to the second embodiment.

[0063] Figure 55 This is a schematic top view used to illustrate the manufacturing method of the semiconductor memory device.

[0064] Figure 56 This is a schematic top view used to illustrate the manufacturing method.

[0065] Figure 57 This is a schematic top view used to illustrate the manufacturing method.

[0066] Figure 58 This is a schematic top view used to illustrate the manufacturing method.

[0067] Figure 59 This is a schematic top view used to illustrate the manufacturing method.

[0068] Figure 60 This is a schematic top view showing a portion of the structure of the semiconductor memory device according to the third embodiment.

[0069] Figure 61 This is a schematic top view used to illustrate the manufacturing method of the semiconductor memory device.

[0070] Figure 62 This is a schematic top view used to illustrate the manufacturing method.

[0071] Figure 63 This is a schematic top view used to illustrate the manufacturing method.

[0072] Figure 64 This is a schematic top view used to illustrate the manufacturing method.

[0073] Figure 65 This is a schematic top view showing a portion of the structure of the semiconductor memory device according to the fourth embodiment.

[0074] Figure 66 This is a schematic top view used to illustrate the manufacturing method of the semiconductor memory device.

[0075] Figure 67 This is a schematic top view used to illustrate the manufacturing method.

[0076] Figure 68 This is a schematic top view used to illustrate the manufacturing method.

[0077] Figure 69 This is a schematic top view used to illustrate the manufacturing method.

[0078] Figure 70This is a schematic top view used to illustrate the manufacturing method. Detailed Implementation

[0079] The semiconductor memory device according to the embodiments is described in detail below with reference to the accompanying drawings. The following embodiments are merely examples and are not intended to limit the invention. Furthermore, the following drawings are schematic, and for ease of explanation, some structures may be omitted. Additionally, common parts in multiple embodiments are labeled with the same reference numerals, and descriptions may sometimes be omitted.

[0080] Furthermore, in this specification, the term "semiconductor memory device" sometimes refers to a memory die, and sometimes to a storage system that includes a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). It may also refer to a host-based structure, such as a smartphone, tablet computer, or personal computer.

[0081] Furthermore, in this specification, when referring to the first structure and the second structure as "electrically connected," the first structure may be directly connected to the second structure, or the first structure may be connected to the second structure via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, the first transistor and the third transistor are considered to be "electrically connected" even if the second transistor is in the off state.

[0082] Furthermore, in this specification, when referring to the first structure as "connected between the second and third structures", it sometimes means that the first, second, and third structures are connected in series, and the second structure is connected to the third structure via the first structure.

[0083] In addition, in this specification, the specified direction parallel to the upper surface of the substrate is called the X direction, the direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and the direction perpendicular to the upper surface of the substrate is called the Z direction.

[0084] In addition, in this specification, the direction along a specified surface is sometimes referred to as the first direction, the direction along the specified surface that intersects with the first direction is referred to as the second direction, and the direction that intersects with the specified surface is referred to as the third direction. These first, second, and third directions may correspond to one of the X, Y, and Z directions, or they may not correspond.

[0085] Furthermore, in this specification, the terms "upper" and "lower" are used with reference to the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction closer to the substrate along the Z direction is called "lower." Also, regarding a certain structure, when referring to a lower surface or lower end, it refers to the surface or end of the structure on the substrate side; when referring to an upper surface or upper end, it refers to the surface or end of the structure on the side opposite to the substrate. Additionally, the surface intersecting the X or Y direction is called a side surface, etc.

[0086] In addition, in this specification, when referring to structures, components, etc., the terms "width", "length" or "thickness" in a specified direction are sometimes used to refer to the width, length or thickness of a section observed by SEM (Scanning electron microscopy), TEM (Transmission electron microscopy), etc.

[0087] [First Implementation Method]

[0088] [structure]

[0089] Figure 1 This is a schematic top view of a memory die (MD). Figure 2 yes Figure 1 A schematic enlarged view of part A and part B. Figure 3 yes Figure 2 A schematic enlarged view of part C. Figure 4 It is Figure 3 The diagram shows a schematic cross-section of the structure cut along line D-D' and viewed in the direction of the arrow. Figure 5 yes Figure 4 A schematic enlarged view of the part shown as E. Figure 6 It is Figure 2 The diagram shows a schematic cross-section of the structure cut along line F-F' and viewed in the direction of the arrow. Figure 7 It is Figure 2 The diagram shows a schematic cross-section of the structure cut along line G-G' and viewed in the direction of the arrow.

[0090] For example, Figure 1 As shown, the memory die MD includes a semiconductor substrate 100. The semiconductor substrate 100 is, for example, a semiconductor substrate made of P-type silicon (Si) containing P-type impurities such as boron (B). The surface of the semiconductor substrate 100 is provided with: an N-type well region containing N-type impurities such as phosphorus (P), a P-type well region containing P-type impurities such as boron (B), a semiconductor substrate region without N-type and P-type well regions, and an insulating region.

[0091] In addition, the memory die MD has four memory cell array regions R arranged along the X and Y directions. MCA Storage cell array region R MCA Includes two memory hole regions R arranged in the X direction MH and set in these memory hole areas R MH The connection region R between HU .

[0092] Storage cell array region R MCA The system contains multiple storage blocks (BLKs) arranged in the Y direction. For example, such as... Figure 2 As shown, a memory block BLK has multiple string cells SU arranged along the Y direction. An inter-block insulating layer ST, such as silicon oxide (SiO2), is disposed between two adjacent memory blocks BLK in the Y direction. For example, as... Figure 3 As shown, a silicon oxide (SiO2) inter-string insulating layer SHE is provided between two adjacent string units SU in the Y direction.

[0093] For example, such as Figure 4 As shown, the memory hole region R of memory block BLK MH It includes a plurality of conductive layers 110 arranged along the Z direction, a plurality of semiconductor layers 120 extending along the Z direction, and a plurality of gate insulating films 130 respectively disposed between the plurality of conductive layers 110 and the plurality of semiconductor layers 120.

[0094] The conductive layer 110 is a generally plate-shaped conductive layer extending along the X direction. The conductive layer 110 may also comprise a stack of barrier conductive films such as titanium nitride (TiN) and metal films such as tungsten (W). Alternatively, the conductive layer 110 may also comprise, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101, such as silicon oxide (SiO2), is disposed between the plurality of conductive layers 110 arranged along the Z direction. Furthermore, the conductive layer 110 functions as the gate electrode and word line of a memory cell, or the gate electrode and select gate line of a select transistor.

[0095] A semiconductor layer 112 is disposed below the conductive layer 110. The semiconductor layer 112 may, for example, contain polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). Furthermore, an insulating layer 101, such as silicon oxide (SiO2), is disposed between the semiconductor layer 112 and the conductive layer 110. Additionally, the semiconductor layer 112 functions as part of the source line.

[0096] Semiconductor layer 120, for example Figure 3 As shown, the semiconductor layer 120 is arranged in a prescribed pattern in the X and Y directions. The semiconductor layer 120 functions as the channel region for multiple memory cells and selection transistors. The semiconductor layer 120 is, for example, a semiconductor layer such as polysilicon (Si). Figure 4 As shown, it has a generally cylindrical shape and an insulating layer 125 such as silicon oxide is provided in the central part. In addition, the outer peripheral surfaces of the semiconductor layer 120 are surrounded by conductive layers 110, which are opposite to the conductive layers 110.

[0097] An impurity region 121 containing N-type impurities such as phosphorus (P) is provided at the upper end of the semiconductor layer 120. Figure 4 In the example, a dashed line represents the boundary line between the upper end of the semiconductor layer 120 and the lower end of the impurity region 121. The impurity region 121 is separated by contacts Ch and Vy. Figure 3 ) is connected to bit line BL.

[0098] The lower end of semiconductor layer 120 is connected to semiconductor layer 112.

[0099] The gate insulating film 130 has a generally cylindrical shape covering the outer peripheral surface of the semiconductor layer 120. The gate insulating film 130 is, for example, as shown in... Figure 5 As shown, a tunnel insulating film 131, a charge storage film 132, and a barrier insulating film 133 are stacked between a semiconductor layer 120 and a conductive layer 110. The tunnel insulating film 131 and the barrier insulating film 133 are, for example, insulating films such as silicon oxide (SiO2). The charge storage film 132 is, for example, a film capable of storing charge such as silicon nitride (Si3N4). The tunnel insulating film 131, the charge storage film 132, and the barrier insulating film 133 have a generally cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor layer 120, excluding the contact portion between the semiconductor layer 120 and the semiconductor layer 112.

[0100] In addition, Figure 5 An example is shown where the gate insulating film 130 has a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may also have a floating gate such as polysilicon containing N-type or P-type impurities.

[0101] For example, such as Figure 2 As shown, the connection region R of storage block BLK HU It includes a portion of a conductive layer 110 and two rows of contact electrodes (CCGs) arranged in the Y direction. Figure 2 In the diagram, these two contact electrode columns CCG are denoted as CCG(0) and CCG(1).

[0102] like Figure 6 and Figure 7As shown, the contact electrode array CCG includes multiple contact electrodes CC arranged along the X direction. These multiple contact electrodes CC extend along the Z direction and are connected to the conductive layer 110 at their lower ends. The contact electrodes CC may, for example, comprise a laminated film containing a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). In addition, an insulating layer 103 such as silicon oxide (SiO2) is provided on the outer peripheral surface of the contact electrodes CC.

[0103] Additionally, in the following description, the nth conductive layer 110 from the top (where n is an integer greater than or equal to 1) is sometimes referred to as conductive layer 110(n-1). Sometimes, the contact electrode among the plurality of contact electrodes CC that is connected to conductive layer 110(n) is referred to as contact electrode CC(n).

[0104] like Figure 6 As shown, the contact electrode array CCG(0) extends from the region R near the memory hole. MH The contact electrodes are sequentially provided with contact electrodes CC(0), CC(2), CC(6), CC(4), CC(12), CC(14), CC(10), and CC(8).

[0105] like Figure 7 As shown, the contact electrode array CCG(1) extends from the region R near the memory hole. MH The contact electrodes are sequentially provided with contact electrodes CC(1), CC(3), CC(7), CC(5), CC(13), CC(15), CC(11), and CC(9).

[0106] In addition, such as Figure 2 As shown, multiple contact electrodes CC(0), CC(2), CC(6), CC(4), CC(12), CC(14), CC(10), and CC(8) in contact electrode array CCG(0) are arranged in the Y direction with multiple contact electrodes CC(1), CC(3), CC(7), CC(5), CC(13), CC(15), CC(11), and CC(9) in contact electrode array CCG(1).

[0107] [Manufacturing Method]

[0108] Next, refer to Figures 8 to 35 This describes the manufacturing method of the memory die (MD). Figure 10 , Figure 12 , Figure 16 , Figure 21 , Figure 26 This is a schematic cross-sectional view used to illustrate the manufacturing method, showing the relationship with... Figure 2 The corresponding plane. Figure 8 , Figure 9 , Figure 11 , Figure 13 , Figure 17, Figure 19 , Figure 22 , Figure 24 , Figure 27 , Figure 29 , Figure 31 , Figure 34 This is a schematic cross-sectional view used to illustrate the manufacturing method, showing the relationship with... Figure 6 The corresponding cross-section. Figure 14 , Figure 15 , Figure 18 , Figure 20 , Figure 23 , Figure 25 , Figure 28 , Figure 30 , Figure 32 , Figure 33 , Figure 35 This is a schematic cross-sectional view used to illustrate the manufacturing method, showing the relationship with... Figure 7 The corresponding cross-section.

[0109] When manufacturing the memory die (MD) involved in this embodiment, for example... Figure 8 As shown, a semiconductor layer 112 is formed. Furthermore, multiple insulating layers 101 and multiple sacrificial layers 111 are alternately formed above the semiconductor layer 112. This process is performed, for example, by a method such as CVD (Chemical Vapor Deposition).

[0110] Next, for example, Figure 9 As shown, multiple semiconductor layers 120 are formed. In this process, for example, in reference... Figure 8 The upper surface of the described structure has an insulating layer 104, such as silicon oxide (SiO2), formed using methods such as CVD. Next, through-holes are formed through the insulating layer 104, multiple insulating layers 101, and multiple sacrificial layers 111 using methods such as RIE (Reactive Ion Etching). Furthermore, a gate insulating film 130 is formed on the inner peripheral surface of these through-holes using methods such as CVD. Figure 5 ) and semiconductor layer 120.

[0111] Next, for example, Figure 10 as well as Figure 11 As shown, multiple contact holes CH(0) are formed at positions corresponding to the contact electrode CC. For example, in the reference... Figure 9 A hard mask 105 is formed on the upper surface of the structure described. Then, through holes are formed through the hard mask 105 and the insulating layer 104 by methods such as RIE, exposing the upper surface of the sacrificial layer 111.

[0112] Additionally, in the following description, the nth (n is an integer greater than or equal to 1) sacrificial layer 111 from the top is sometimes referred to as sacrificial layer 111(n-1). Furthermore, the contact hole among the multiple contact holes CH that exposes the upper surface of sacrificial layer 111(n) and penetrates all the sacrificial layers 111 disposed above it is sometimes referred to as contact hole CH(n).

[0113] Next, for example, Figures 12-14 As shown, a resist layer 151 is formed. The resist layer 151 covers the contact holes CH corresponding to the contact electrode column CCG(0) and exposes the contact holes CH corresponding to the contact electrode column CCG(1).

[0114] Next, for example Figure 15 As shown, in the portion of the contact hole CH not covered by the resist layer 151, one layer each of the sacrificial layer 111 and the insulating layer 101 is removed. Thus, the contact hole CH(1) is formed at the position corresponding to the contact electrode CC in the contact electrode array CCG(1). This process is performed, for example, by a RIE (Residual Electrode Array).

[0115] Next, for example, Figures 16-18 As shown, resist layer 151 is removed, and resist layer 152 is formed. Resist layer 152 covers a plurality of contact holes CH arranged in the X direction, extending from the memory hole region R. MH The 4a+1th and 4a+4th (where a is an integer greater than or equal to 0) contact holes CH are counted from one side, and all other contact holes CH are exposed. In addition, the film thickness (thickness in the Z direction) of the resist layer 152 is greater than the film thickness of the resist layer 151.

[0116] Next, for example, Figure 19 and Figure 20 As shown, in the portion of the contact hole CH not covered by the resist layer 152, two layers each of the sacrificial layer 111 and the insulating layer 101 are removed. Thus, in the plurality of contact holes CH corresponding to the contact electrode array CCG(0), and from the region R near the memory hole... MH The 4a+2nd and 4a+3rd portions corresponding to the first one form contact holes CH(2). Additionally, among the multiple contact holes CH corresponding to the contact electrode column CCG(1), the portion corresponding to the portion near the memory hole region R... MH The 4a+2 and 4a+3 corresponding portions from the first side form contact holes CH(3).

[0117] Next, for example, Figures 21-23 As shown, resist layer 152 is removed, and resist layer 153 is formed. Resist layer 153 covers a plurality of contact holes CH arranged in the X direction, extending from the memory hole region R. MHStarting from one side, the 8a+1, 8a+2, 8a+7, and 8a+8 (where a is an integer greater than or equal to 0) contact holes CH are counted, and all other contact holes CH are exposed. Furthermore, the thickness (thickness in the Z direction) of the resist layer 153 is greater than the thickness of the resist layer 152.

[0118] Next, for example, Figure 24 and Figure 25 As shown, in the portion of the contact hole CH not covered by the resist layer 153, four layers each of the sacrificial layer 111 and the insulating layer 101 are removed. Thus, in the plurality of contact holes CH corresponding to the contact electrode array CCG(0), and from the region R near the memory hole... MH Contact holes CH(4) and CH(6) are formed in the 8a+3 to 8a+6th portions starting from one side. Additionally, in the plurality of contact holes CH corresponding to the contact electrode column CCG(1), the portion corresponding to the portion near the memory hole region R... MH Contact holes CH(5) and CH(7) are formed from the 8a+3 to 8a+6th corresponding portions starting from one side. This process is carried out, for example, by RIE.

[0119] Next, for example, Figures 26-28 As shown, resist layer 153 is removed, and resist layer 154 is formed. Resist layer 154 covers the region R near the memory hole in a plurality of contact holes CH arranged in the X direction. MH Half of the original thickness is exposed, and the contact holes CH are exposed. In addition, the thickness of the resist layer 154 (thickness in the Z direction) is greater than the thickness of the resist layer 153.

[0120] Next, for example, Figure 29 and Figure 30 As shown, in the portion of the contact hole CH not covered by the resist layer 154, eight layers each of the sacrificial layer 111 and the insulating layer 101 are removed. Thus, in the plurality of contact holes CH corresponding to the contact electrode column CCG(0), in the region R far from the memory hole, MH The portion corresponding to half of the contact hole forms contact holes CH(8), CH(10), CH(12), and CH(14). Additionally, among the multiple contact holes CH corresponding to the contact electrode array CCG(1), the portion furthest from the memory hole region R... MH The corresponding half of the portion forms contact holes CH(9), CH(11), CH(13), and CH(15). This process is carried out, for example, by RIE.

[0121] Next, for example, Figure 31 and Figure 32As shown, the resist layer 154 and hard mask 105 are removed, and an insulating layer 103 and a sacrificial layer 106 are formed inside the contact holes CH(0) to CH(15). This process is carried out, for example, by CVD.

[0122] Next, for example, Figure 33 As shown, a conductive layer 110 is formed. In this process, for example, an insulating layer ST between the blocks is formed using methods such as RIE. Figure 2 A trench is formed at the corresponding position, through which multiple insulating layers 101 and multiple sacrificial layers 111 are formed. Then, the multiple sacrificial layers 111 are removed by methods such as wet etching through the trench. Then, multiple conductive layers 110 are formed by methods such as CVD.

[0123] Next, for example, Figure 34 and Figure 35 As shown, contact electrodes CC(0) to CC(15) are formed. In this step, for example, the sacrificial layer 106 is removed. Next, a portion of the insulating layer 103 is removed by a method such as RIE, exposing the upper surfaces of the conductive layers 110(0) to 110(15). Next, contact electrodes CC(0) to CC(15) are formed by a method such as CVD.

[0124] Subsequently, a reference is formed by creating bit lines (BL), etc. Figures 1 to 7 The semiconductor memory device described.

[0125] [Comparative Example]

[0126] [structure]

[0127] Next, refer to Figures 36-38 The structure of the semiconductor memory device involved in the comparative example will be explained. Figure 36 This is a schematic top view of the semiconductor memory device involved in the scale. Figure 37 It is Figure 36 The diagram shows a schematic cross-section of the structure cut along line H-H' and viewed in the direction of the arrow. Figure 38 It is Figure 36 The diagram shows a schematic cross-section of the structure cut along line I-I' and viewed in the direction of the arrow.

[0128] The comparative example uses a contact electrode array CCG' instead of a contact electrode array CCG. Figure 36 In this context, the two contact electrode columns CCG' are denoted as CCG'(0) and CCG'(1).

[0129] Contact electrode array CCG'(0) from near the memory hole region R MHThe contact electrodes are sequentially provided with contact electrodes CC(0), CC(2), CC(4), CC(6), CC(8), CC(10), CC(12), and CC(14).

[0130] Contact electrode array CCG'(1) from the region R near the memory hole MH The contact electrodes are sequentially provided with contact electrodes CC(1), CC(3), CC(5), CC(7), CC(9), CC(11), CC(13), and CC(15).

[0131] [Manufacturing Method]

[0132] Next, refer to Figures 39-53 The manufacturing method of the semiconductor memory device involved in the comparative example is explained. Figure 39 , Figure 44 , Figure 49 This is a schematic top view used to illustrate the manufacturing method, showing the relationship with... Figure 36 The corresponding plane. Figure 40 , Figure 42 , Figure 45 , Figure 47 , Figure 50 , Figure 52 This is a schematic cross-sectional view used to illustrate the manufacturing method, showing the relationship with... Figure 37 The corresponding cross-section. Figure 41 , Figure 43 , Figure 46 , Figure 48 , Figure 51 , Figure 53 This is a schematic cross-sectional view used to illustrate the manufacturing method, showing the relationship with... Figure 38 The corresponding cross-section.

[0133] When manufacturing the semiconductor memory device involved in the comparative example, the process is performed from the reference... Figure 8 The described process is referenced. Figure 14 and Figure 15 The procedures described.

[0134] Next, for example, Figures 39-41 As shown, resist layer 151 is removed, and resist layer 152' is formed. Resist layer 152' covers one of the plurality of contact holes CH arranged in the X direction, from the region R near the memory hole. MH The 2b+1th contact hole CH (where b is an integer greater than or equal to 0) is started from one side, and all other contact holes CH are exposed. In addition, the film thickness (thickness in the Z direction) of the resist layer 152' is greater than the film thickness of the resist layer 151.

[0135] Next, for example, Figure 42 and Figure 43As shown, in the portion of the contact hole CH not covered by the resist layer 152', two layers each of the sacrificial layer 111 and the insulating layer 101 are removed. Thus, in the plurality of contact holes CH corresponding to the contact electrode column CCG'(0), and from the region R near the memory hole... MH The 2b+2th corresponding portion from one side forms the contact hole CH(2). Additionally, among the multiple contact holes CH corresponding to the contact electrode column CCG'(1), the portion from the region R near the memory hole... MH The 2b+2th corresponding part from the first side forms the contact hole CH(3).

[0136] Next, for example, Figures 44-46 As shown, the resist layer 152' is removed, and a resist layer 153' is formed. The resist layer 153' covers one of the plurality of contact holes CH arranged in the X direction, from the region R near the memory hole. MH The 4b+1 and 4b+2 (b is an integer greater than 0) contact holes CH are started from one side, and all other contact holes CH are exposed. In addition, the film thickness (thickness in the Z direction) of the resist layer 153' is greater than the film thickness of the resist layer 152'.

[0137] Next, for example, Figure 47 and Figure 48 As shown, in the portion of the contact hole CH not covered by the resist layer 153', four layers each of the sacrificial layer 111 and the insulating layer 101 are removed. Thus, in the plurality of contact holes CH corresponding to the contact electrode column CCG'(0), and from the region R near the memory hole... MH The 4b+3rd and 4b+4th corresponding portions from one side form contact holes CH(4) and CH(6). Additionally, among the multiple contact holes CH corresponding to the contact electrode column CCG'(1), the portion from the region R near the memory hole... MH The 4b+3rd and 4b+4th portions from the first side form contact holes CH(5) and CH(7). This process is carried out, for example, by RIE.

[0138] Next, for example, Figures 49-51 As shown, the resist layer 153' is removed, and a resist layer 154' is formed. The resist layer 154' covers the memory hole region R in a plurality of contact holes CH arranged in the X direction. MH Half of the original thickness is exposed, and the contact holes CH are exposed. In addition, the thickness of the resist layer 154' (thickness in the Z direction) is greater than the thickness of the resist layer 153'.

[0139] Next, for example, Figure 52 and Figure 53As shown, in the portion of the contact hole CH not covered by the resist layer 154', eight layers of both the sacrificial layer 111 and the insulating layer 101 are removed. Thus, in the plurality of contact holes CH corresponding to the contact electrode column CCG'(0), in the region R far from the memory hole, MH The portion corresponding to half of the contact holes forms contact holes CH(8), CH(10), CH(12), and CH(14). Additionally, among the multiple contact holes CH corresponding to the contact electrode array CCG'(1), the portion furthest from the memory hole region R... MH The corresponding half of the portion forms contact holes CH(9), CH(11), CH(13), and CH(15). This process is carried out, for example, by RIE.

[0140] Then, by executing the reference Figure 31 and Figure 32 The described processes and subsequent processes form a reference. Figures 36-38 The semiconductor memory device described.

[0141] [Effect]

[0142] In the manufacturing methods involved in the comparative examples, in reference Figures 39-41 Explanation of procedures and references Figures 44-46 In the described process, resist layers 152' and 153' are formed respectively. Here, in order to reduce the bonding area R... HU The desired area is to form a smaller pattern for the resist layers 152' and 153'. However, in reference... Figure 42 and Figure 43 Explanation of procedures and references Figure 47 and Figure 48 In the described process, it is desirable to effectively protect the hard mask 105 using the resist layers 152' and 153'. Therefore, it is desirable to increase the film thickness (thickness in the Z direction) of the resist layers 152' and 153' to a certain extent. However, if the film thickness of the resist layers 152' and 153' is large, it can sometimes be difficult to form a small pattern on the resist layers 152' and 153'.

[0143] Therefore, in the manufacturing method according to the first embodiment, when referring to Figures 16-18 Explanation of procedures and references Figures 21-23 In the process described, resist layers 152 and 153 are formed respectively.

[0144] Here, as referenced Figure 39 As explained, the resist layer 152' covers the 2b+1th contact hole CH counting from one side in the X direction (e.g., the negative side of the X direction), and exposes the 2b+2th contact hole CH. That is, in the resist layer 152', the line and space pattern is set at a spacing of twice the spacing of the contact hole CH.

[0145] On the other hand, as referenced Figure 16 As explained, the resist layer 152 covers the 4a+1th and 4a+4th contact holes CH counting from one side in the X direction (e.g., the negative side of the X direction), and exposes the 4a+2nd and 4a+3rd contact holes CH. That is, in the resist 152, the lines and spacing patterns are arranged at a spacing of 4 times the spacing of the contact holes CH.

[0146] Additionally, as referenced Figure 44 As explained, the resist layer 153' covers the 4b+1th and 4b+2nd contact holes CH counting from one side in the X direction (e.g., the negative side of the X direction), and exposes the 4b+3rd and 4b+4th contact holes CH. That is, in the resist layer 153', the lines and spacing patterns are arranged at a spacing of 4 times the spacing of the contact holes CH.

[0147] On the other hand, as referenced Figure 21 As explained, the resist layer 153 covers the 8a+1th, 8a+2nd, 8a+7th, and 8a+8th contact holes CH counting from one side in the X direction (e.g., the negative side of the X direction), and exposes the 8a+3rd to 8a+6th contact holes CH. That is, in the resist layer 153, the lines and spacing patterns are arranged at a spacing of 8 times the spacing of the contact holes CH.

[0148] That is, in the first embodiment, by merging two openings formed in the resist layer into one opening, the spacing of the resist pattern is reduced to twice its original size. According to this method, even when the film thickness of the resist layers 152 and 153 is relatively large, the bonding region R can be reduced. HU The area.

[0149] In addition, such as Figure 37 and Figure 38 As shown, in the semiconductor memory device involved in the comparative example, the closer to the memory hole region R... MH The contact electrode CC is more likely to connect with the conductive layer 110 disposed on the upper layer. On the other hand, in the semiconductor memory device according to the first embodiment, the arrangement of the contact electrode CC in the X direction and its relationship with the conductive layer 110 are different from those in the comparative example.

[0150] For example, such as Figure 2 and Figure 6As shown, in the semiconductor memory device according to the first embodiment, a contact electrode CC (6) is disposed between contact electrode CC (2) and contact electrode CC (4). Furthermore, contact electrodes CC (4), CC (12), CC (14), and CC (10) are disposed between contact electrode CC (6) and contact electrode CC (8). Additionally, a contact electrode CC (14) is disposed between contact electrode CC (10) and contact electrode CC (12).

[0151] For example, Figure 2 and Figure 7 As shown, in the semiconductor memory device according to the first embodiment, a contact electrode CC (7) is disposed between contact electrode CC (3) and contact electrode CC (5). Additionally, contact electrodes CC (5), CC (13), CC (15), and CC (11) are disposed between contact electrode CC (7) and contact electrode CC (9). Furthermore, a contact electrode CC (13) is disposed between contact electrode CC (11) and contact electrode CC (13).

[0152] In addition, for example, Figure 2 , Figure 6 and Figure 7 As shown, in the semiconductor memory device according to the first embodiment, contact electrodes CC(6) and CC(7) are disposed between contact electrodes CC(0) to CC(3) and contact electrodes CC(4) and CC(5). In addition, contact electrodes CC(12) to CC(15) are disposed between contact electrodes CC(0) to CC(7) and contact electrodes CC(8) to CC(11).

[0153] [Second Implementation]

[0154] [structure]

[0155] Next, refer to Figure 54 The semiconductor memory device involved in the second embodiment is described. Figure 54 This is a schematic top view showing a portion of the structure of the semiconductor memory device according to the second embodiment.

[0156] The semiconductor memory device according to the second embodiment is configured in essentially the same way as the semiconductor memory device according to the first embodiment. However, as shown in reference... Figure 2 As explained, in the semiconductor memory device according to the first embodiment, in the connection region R HU Two contact electrode arrays (CCGs) arranged in the Y direction are provided. In contrast, in the semiconductor memory device according to the second embodiment, in the connection region R... HUThe device has three contact electrode rows CCG2 arranged in the Y direction. Each of these three contact electrode rows CCG2 has multiple contact electrodes CC arranged in the X direction.

[0157] exist Figure 54 In the example, contact electrode arrays CCG2(2), CCG2(0), and CCG2(1) are arranged sequentially from the negative side of the Y direction.

[0158] The contact electrode array CCG2(0) has contact electrodes CC(8), CC(4), CC(0), and CC(12) sequentially from one side of the X direction (e.g., the negative side of the X direction).

[0159] The contact electrode array CCG2(1) has contact electrodes CC(9), CC(5), CC(1), and CC(13) sequentially from one side in the X direction.

[0160] The contact electrode array CCG2(2) has contact electrodes CC(10), CC(6), CC(7), CC(3), CC(2), CC(14), CC(15), and CC(11) sequentially from one side in the X direction.

[0161] In addition, multiple contact electrodes CC(8), CC(4), CC(0), CC(12) in contact electrode array CCG2(0) are arranged in the Y direction with multiple contact electrodes CC(9), CC(5), CC(1), CC(13) in contact electrode array CCG2(1) and multiple contact electrodes CC(10), CC(6), CC(2), CC(14) in contact electrode array CCG2(2).

[0162] [Manufacturing Method]

[0163] Next, refer to Figures 55-59 The manufacturing method of the semiconductor memory device according to the second embodiment will be described. Figures 55-59 This is a schematic top view used to illustrate the manufacturing method, showing the relationship with... Figure 54 The corresponding plane.

[0164] When manufacturing the semiconductor memory device according to the second embodiment, the following steps are performed: Figure 8 Explanation of procedures and references Figure 9 The procedures described.

[0165] Next, for example, Figure 55 As shown, multiple contact holes CH(0) are formed at positions corresponding to the contact electrode CC.

[0166] Next, for example, Figure 56As shown, a resist layer 251 is formed. The resist layer 251 covers the contact holes CH corresponding to the contact electrode array CCG2(0). In addition, the resist layer 251 covers the 1st, 2nd, 5th, and 6th contact holes CH, which are the 8 contact holes CH corresponding to the contact electrode array CCG2(2), counting from the negative side in the X direction. In addition, the resist layer 251 exposes the other contact holes CH.

[0167] In addition, for example Figure 56 As shown, in the portion of the contact hole CH not covered by the resist layer 251, one layer each of the sacrificial layer 111 and the insulating layer 101 is removed. This process is performed, for example, by a re-emulator (RIE).

[0168] Next, for example, Figure 57 As shown, a resist layer 252 is formed. The resist layer 252 covers the contact holes CH corresponding to the contact electrode array CCG2(0). Additionally, the resist layer 252 covers the contact holes CH corresponding to the contact electrode array CCG(1). Furthermore, the resist layer 252 exposes the other contact holes CH.

[0169] In addition, for example Figure 57 As shown, in the portion of the contact hole CH not covered by the resist layer 252, two layers each of the sacrificial layer 111 and the insulating layer 101 are removed. This process is performed, for example, by a re-emulator (RIE).

[0170] Next, for example, Figure 58 As shown, a resist layer 253 is formed. The resist layer 253 covers the 1st and 3rd contact holes CH, counting from the negative X-direction, of the four contact holes CH corresponding to contact electrode array CCG2(0). Additionally, the resist layer 253 covers the 1st and 3rd contact holes CH, counting from the negative X-direction, of the four contact holes CH corresponding to contact electrode array CCG2(1). Furthermore, the resist layer 253 covers the 1st, 4th, 5th, and 8th contact holes CH, counting from the negative X-direction, of the eight contact holes CH corresponding to contact electrode array CCG2(2). The resist layer 253 exposes the remaining contact holes CH.

[0171] In addition, for example Figure 58 As shown, in the portion of the contact hole CH not covered by the resist layer 253, four layers each of the sacrificial layer 111 and the insulating layer 101 are removed. This process is performed, for example, by a re-emulator (RIE).

[0172] Next, for example, Figure 59As shown, a resist layer 254 is formed. The resist layer 254 covers the 2nd and 3rd contact holes CH, counting from the negative X-direction, of the four contact holes CH corresponding to contact electrode array CCG2(0). Additionally, the resist layer 254 covers the 2nd and 3rd contact holes CH, counting from the negative X-direction, of the four contact holes CH corresponding to contact electrode array CCG2(1). Furthermore, the resist layer 254 covers the 2nd to 5th contact holes CH, counting from the negative X-direction, of the eight contact holes CH corresponding to contact electrode array CCG2(2). The resist layer 254 exposes the remaining contact holes CH.

[0173] In addition, for example, Figure 59 As shown, in the portion of the contact hole CH not covered by the resist layer 254, eight layers of both the sacrificial layer 111 and the insulating layer 101 are removed. This process is performed, for example, by a re-emulator (RIE).

[0174] [Third Implementation Method]

[0175] [structure]

[0176] Next, refer to Figure 60 The semiconductor memory device according to the third embodiment will be described. Figure 60 This is a schematic top view showing a portion of the structure of the semiconductor memory device according to the third embodiment.

[0177] The semiconductor memory device according to the third embodiment is configured in essentially the same way as the semiconductor memory device according to the first embodiment. However, as shown in the reference... Figure 2 As explained, in the semiconductor memory device according to the first embodiment, in the connection region R HU Two contact electrode arrays (CCGs) arranged in the Y direction are provided. In contrast, in the semiconductor memory device according to the third embodiment, in the connection region R... HU The device has three contact electrode rows (CCG3) arranged in the Y direction. Each of these three contact electrode rows (CCG3) has multiple contact electrodes (CC) arranged in the X direction.

[0178] exist Figure 60 In the example, contact electrode arrays CCG3(2), CCG3(0), and CCG3(1) are arranged sequentially from the negative side of the Y direction.

[0179] The contact electrode array CCG3(0) has contact electrodes CC(3), CC(12), CC(8), CC(0), and CC(4) sequentially from one side of the X direction (e.g., the negative side of the X direction).

[0180] The contact electrode array CCG3(1) has contact electrodes CC(15), CC(11), CC(13), CC(9), CC(1), and CC(5) sequentially from one side in the X direction.

[0181] The contact electrode array CCG3(2) has contact electrodes CC(7), CC(14), CC(10), CC(2), and CC(6) sequentially from one side in the X direction.

[0182] In addition, multiple contact electrodes CC(3), CC(12), CC(8), CC(0), and CC(4) in contact electrode array CCG3(0) are arranged in the Y direction with multiple contact electrodes CC(11), CC(13), CC(9), CC(1), and CC(5) in contact electrode array CCG3(1) and multiple contact electrodes CC(7), CC(14), CC(10), CC(2), and CC(6) in contact electrode array CCG3(2).

[0183] [Manufacturing Method]

[0184] Next, refer to Figures 61-64 The manufacturing method of the semiconductor memory device according to the third embodiment will be described. Figures 61-64 This is a schematic top view used to illustrate the manufacturing method, showing the relationship with... Figure 60 The corresponding plane.

[0185] When manufacturing the semiconductor memory device according to the third embodiment, the following steps are performed: Figure 8 Explanation of procedures and references Figure 9 Explanation of procedures and references Figure 55 The described procedures. Among them, refer to... Figure 55 In the described process, a plurality of contact holes CH(0) are formed at positions corresponding to the contact electrode CC involved in this embodiment.

[0186] Next, for example, Figure 61 As shown, a resist layer 351 is formed. The resist layer 351 covers the 2nd to 5th contact holes CH, counting from the negative side in the X direction, of the 5 contact holes CH corresponding to the contact electrode array CCG3(0). Additionally, the resist layer 351 covers the 2nd to 5th contact holes CH, counting from the negative side in the X direction, of the 5 contact holes CH corresponding to the contact electrode array CCG3(2). Furthermore, the resist layer 351 exposes the remaining contact holes CH.

[0187] In addition, for example, Figure 61 As shown, in the portion of the contact hole CH not covered by the resist layer 351, one layer each of the sacrificial layer 111 and the insulating layer 101 is removed. This process is performed, for example, by a re-emulator (RIE).

[0188] Next, for example, Figure 62 As shown, a resist layer 352 is formed. The resist layer 352 covers the 2nd to 5th contact holes CH, counting from the negative side in the X direction, of the 5 contact holes CH corresponding to the contact electrode array CCG3(0). Additionally, the resist layer 352 covers the 3rd to 6th contact holes CH, counting from the negative side in the X direction, of the 6 contact holes CH corresponding to the contact electrode array CCG3(1). Furthermore, the resist layer 352 exposes the remaining contact holes CH.

[0189] In addition, for example, Figure 62 As shown, in the portion of the contact hole CH not covered by the resist layer 352, two layers each of the sacrificial layer 111 and the insulating layer 101 are removed. This process is performed, for example, by a re-emulator (RIE).

[0190] Next, for example, Figure 63 As shown, a resist layer 353 is formed. The resist layer 353 covers the 1st, 3rd, and 4th contact holes CH, counting from the negative X-direction, of the 5 contact holes CH corresponding to contact electrode array CCG3(0). Additionally, the resist layer 353 covers the 2nd, 4th, and 5th contact holes CH, counting from the negative X-direction, of the 6 contact holes CH corresponding to contact electrode array CCG3(1). Furthermore, the resist layer 353 covers the 3rd and 4th contact holes CH, counting from the negative X-direction, of the 5 contact holes CH corresponding to contact electrode array CCG3(2). The resist layer 353 exposes the remaining contact holes CH.

[0191] In addition, for example, Figure 63 As shown, in the portion of the contact hole CH not covered by the resist layer 353, four layers each of the sacrificial layer 111 and the insulating layer 101 are removed. This process is performed, for example, by a re-emulator (RIE).

[0192] Next, for example, Figure 64 As shown, a resist layer 354 is formed. The resist layer 354 covers the 1st, 4th, and 5th contact holes CH, counting from the negative X-direction, of the 5 contact holes CH corresponding to contact electrode array CCG3(0). Additionally, the resist layer 354 covers the 5th and 6th contact holes CH, counting from the negative X-direction, of the 6 contact holes CH corresponding to contact electrode array CCG3(1). Furthermore, the resist layer 354 covers the 1st, 4th, and 5th contact holes CH, counting from the negative X-direction, of the 5 contact holes CH corresponding to contact electrode array CCG3(2). The resist layer 354 exposes the remaining contact holes CH.

[0193] In addition, for example, Figure 64As shown, in the portion of the contact hole CH not covered by the resist layer 354, eight layers of both the sacrificial layer 111 and the insulating layer 101 are removed. This process is performed, for example, by a re-emulator (RIE).

[0194] [Fourth Implementation Method]

[0195] [structure]

[0196] Next, refer to Figure 65 The semiconductor memory device involved in the fourth embodiment is described. Figure 65 This is a schematic top view showing a portion of the structure of the semiconductor memory device according to the fourth embodiment.

[0197] The semiconductor memory device according to the fourth embodiment is configured in essentially the same way as the semiconductor memory device according to the first embodiment. However, as shown in the reference... Figure 2 As explained, in the semiconductor memory device according to the first embodiment, in the connection region R HU Two contact electrode arrays (CCGs) arranged in the Y direction are provided. In contrast, in the semiconductor memory device according to the fourth embodiment, in the connection region R... HU The device has four contact electrode rows CCG4 arranged in the Y direction. Each of the four contact electrode rows CCG4 has multiple contact electrodes CC arranged in the X direction.

[0198] exist Figure 65 In the example, contact electrode arrays CCG4(1), CCG4(0), CCG4(2), and CCG4(3) are arranged sequentially from the negative side of the Y direction.

[0199] The contact electrode array CCG4(0) has contact electrodes CC(12), CC(8), CC(0), CC(4), CC(20), and CC(16) sequentially from one side of the X direction (e.g., the negative side of the X direction).

[0200] The contact electrode array CCG4(1) has contact electrodes CC(13), CC(9), CC(1), CC(5), CC(21), and CC(17) sequentially from one side in the X direction.

[0201] The contact electrode array CCG4(2) has contact electrodes CC(14), CC(10), CC(2), CC(6), CC(22), and CC(18) sequentially from one side in the X direction.

[0202] The contact electrode array CCG4(3) has contact electrodes CC(15), CC(11), CC(3), CC(7), CC(23), and CC(19) sequentially from one side in the X direction.

[0203] In addition, multiple contact electrodes CC(12), CC(8), CC(0), CC(4), CC(20), and CC(16) in contact electrode array CCG4(0) are arranged in the Y direction with multiple contact electrodes CC(13), CC(9), CC(1), CC(5), CC(21), and CC(17) in contact electrode array CCG4(1), multiple contact electrodes CC(14), CC(10), CC(2), CC(6), CC(22), and CC(18) in contact electrode array CCG4(2), and multiple contact electrodes CC(15), CC(11), CC(3), CC(7), CC(23), and CC(19) in contact electrode array CCG4(3).

[0204] [Manufacturing Method]

[0205] Next, refer to Figures 66-70 The manufacturing method of the semiconductor memory device according to the fourth embodiment will be described. Figures 66-70 This is a schematic top view used to illustrate the manufacturing method, showing the relationship with... Figure 65 The corresponding plane.

[0206] When manufacturing the semiconductor memory device according to the fourth embodiment, the following steps are performed: Figure 8 Explanation of procedures and references Figure 9 Explanation of procedures and references Figure 55 The described procedures. Among them, refer to... Figure 55 In the described process, a plurality of contact holes CH(0) are formed at positions corresponding to the contact electrode CC involved in this embodiment.

[0207] Next, for example, Figure 66 As shown, a resist layer 451 is formed. The resist layer 451 covers the contact holes CH corresponding to the contact electrode array CCG4(0) and the contact holes CH corresponding to the contact electrode array CCG4(2). In addition, the resist layer 451 exposes the other contact holes CH.

[0208] In addition, for example, Figure 66 As shown, in the portion of the contact hole CH not covered by the resist layer 451, one layer each of the sacrificial layer 111 and the insulating layer 101 is removed. This process is performed, for example, by a re-emulator (RIE).

[0209] Next, for example, Figure 67 As shown, a resist layer 452 is formed. The resist layer 452 covers the contact holes CH corresponding to the contact electrode array CCG4(0) and the contact holes CH corresponding to the contact electrode array CCG4(1). In addition, the resist layer 452 exposes the other contact holes CH.

[0210] In addition, for example, Figure 67 As shown, in the portion of the contact hole CH not covered by the resist layer 452, two layers each of the sacrificial layer 111 and the insulating layer 101 are removed. This process is performed, for example, by a RIE (Residual Insulator).

[0211] Next, for example, Figure 68 As shown, a resist layer 453 is formed. The resist layer 453 covers the 2nd, 3rd, and 6th contact holes CH, counting from the negative side in the X direction, of the 6 contact holes CH corresponding to contact electrode columns CCG4(0) to CCG4(3). In addition, the resist layer 453 exposes the other contact holes CH.

[0212] In addition, for example, Figure 68 As shown, in the portion of the contact hole CH not covered by the resist layer 453, four layers each of the sacrificial layer 111 and the insulating layer 101 are removed. This process is performed, for example, by a re-emulator (RIE).

[0213] Next, for example, Figure 69 As shown, a resist layer 454 is formed. The resist layer 454 covers the 3rd to 6th contact holes CH, counting from the negative side in the X direction, of the 6 contact holes CH corresponding to contact electrode columns CCG4(0) to CCG4(3). In addition, the resist layer 454 exposes the other contact holes CH.

[0214] In addition, for example, Figure 69 As shown, in the portion of the contact hole CH not covered by the resist layer 454, eight layers of both the sacrificial layer 111 and the insulating layer 101 are removed. This process is performed, for example, by a re-emulator (RIE).

[0215] Next, for example, Figure 70 As shown, a resist layer 455 is formed. The resist layer 455 covers the first to fourth contact holes CH, counting from the negative side in the X direction, of the six contact holes CH corresponding to contact electrode columns CCG4(0) to CCG4(3). In addition, the resist layer 454 exposes the other contact holes CH.

[0216] In addition, for example, Figure 70 As shown, in the portion of the contact hole CH not covered by the resist layer 454, 16 layers of both the sacrificial layer 111 and the insulating layer 101 are removed. This process is performed, for example, by a re-emulator (RIE).

[0217] [Other Implementation Methods]

[0218] The semiconductor memory devices according to the first to fourth embodiments have been described above. However, the structure and manufacturing method of the semiconductor memory devices according to the first to fourth embodiments are merely illustrative, and the specific structure and manufacturing method can be appropriately adjusted.

[0219] For example, let R be a region of connection. HU The number of contact electrode rows arranged along the Y direction is c (c is an integer greater than or equal to 1).

[0220] In the first embodiment, c = 2. Furthermore, in the fourth embodiment, c = 4. Thus, in both the first and fourth embodiments, c is a power of 2.

[0221] Here, as referenced Figures 12-15 As explained, the manufacturing method according to the first embodiment includes the following steps: forming a line and spacing pattern extending in the X direction on a resist layer and performing RIE, etc., so that the depths of the plurality of contact holes CH arranged in the Y direction are different. Hereinafter, this step will be referred to as the "Y-direction step formation process". Additionally, as referred to... Figures 16-30 As explained, the manufacturing method according to the first embodiment includes the following steps: forming a line and spacing pattern extending in the Y direction on a resist layer and performing RIE, etc., so that the depths of the plurality of contact holes CH arranged in the X direction are different. Hereinafter, this step will be referred to as the "X-direction step formation process".

[0222] When c is a power of 2, as illustrated in the first and fourth embodiments, the contact hole CH can be formed by a combination of a step formation process in the Y direction and a step formation process in the X direction.

[0223] In this case, if the step formation process in the X direction begins after the entire step formation process in the Y direction is completed, then the connection region R... HU A certain contact electrode array contains multiple contact electrodes CC(nc). For example, refer to... Figure 65 The described contact electrode array CCG4(0) includes contact electrodes CC(0), CC(4), CC(8), CC(12), CC(16), and CC(20). Additionally, a certain contact electrode array may contain multiple contact electrodes CC(nc+1). For example, refer to... Figure 65 The described contact electrode array CCG4(1) includes contact electrodes CC(1), CC(5), CC(9), CC(13), CC(17), and CC(21). Similarly, the other contact electrode arrays each include one of multiple contact electrodes CC(nc+2) to multiple contact electrodes CC(nc+c-1).

[0224] Furthermore, in this case, if the step formation process in the X direction is performed before the step formation process in the Y direction is completely completed, it will not become a connection region R. HUThe c rows of contact electrodes each contain a structure consisting of one of multiple contact electrodes CC(nc) to multiple contact electrodes CC(nc+c-1). However, even in this case, the following conditions still apply. For example, if the electrode is located in the connection region R... HU One of the contact electrodes CC is designated as contact electrode CCI. Furthermore, the conductive layer 110 connected to contact electrode CCI is designated as conductive layer 110I. Additionally, a conductive layer 110 that is c units higher or c units lower than conductive layer 110I is designated as conductive layer 110II. Furthermore, the contact electrode CC connected to conductive layer 110II is designated as contact electrode CCII. In this case, contact electrodes CCI and CCII are arranged in the X or Y direction. Alternatively, there may be cases where other contact electrodes CC are placed between contact electrodes CCI and CCII.

[0225] Furthermore, in the second embodiment, c = 3. Also, in the third embodiment, c = 3. Thus, in both the second and third embodiments, c is not a power of 2.

[0226] Here, for example, in the manufacturing method according to the second embodiment, as referred to Figures 56-59 As explained, a resist layer pattern different from simple lines and spacing is used. These resist layer patterns can be defined, for example, as follows: For example, a minimum power of 2, d (4 in the second embodiment), greater than c (3 in the second embodiment), is defined. Furthermore, the resist layer pattern is assumed to be d when the number of contact electrode columns (CCGs) arranged in the Y direction is d. Additionally, the resist layer pattern corresponding to c contact electrode columns is fixed, and the pattern corresponding to the remaining dc (1 in the second embodiment) contact electrode columns (CCGs) is moved in the X direction to a position parallel to other contact electrode columns (CCGs). For example, from... Figure 54 The 3rd, 4th, 7th, and 8th contact electrodes CC of the contact electrode column CCG2(2) starting from the negative side in the X direction correspond to the contact electrodes CC of the remaining dc contact electrode columns CCG mentioned above.

[0227] The following will refer to Figure 56 , Figure 57 , Figure 61 or Figure 62 The described process is called the "step formation process corresponding to the Y direction". Additionally, refer to... Figure 58 , Figure 59 , Figure 63 or Figure 64 The process described is called "step formation process corresponding to the X direction".

[0228] When c is not a power of 2, as illustrated in the second and third embodiments, the contact hole CH can be formed by a combination of a step formation process corresponding to the Y direction and a step formation process corresponding to the X direction.

[0229] In this case, if the step difference formation process corresponding to the Y direction is completed before the step difference formation process corresponding to the X direction is started, then the connection region R HU The c contact electrode rows each contain one of the multiple contact electrodes CC(nd) to multiple contact electrodes CC(nd+d-1).

[0230] Furthermore, in this case, if the step formation process corresponding to the X direction is performed before the complete step formation process corresponding to the Y direction is finished, it will not become a connection region R. HU The c-column contact array contains a structure comprising one of multiple contact electrodes CC(nd) to multiple contact electrodes CC(nd+d-1). However, even in this case, the following conditions still apply. For example, if the contact electrode is located in the connection region R... HU One of the contact electrodes CC is designated as contact electrode CCIII. Furthermore, a conductive layer 110 connected to contact electrode CCIII is designated as conductive layer 110III. Additionally, a conductive layer 110 that is d units higher or d units lower than conductive layer 110III is designated as conductive layer 110VI. Furthermore, a contact electrode CC connected to conductive layer 110VI is designated as contact electrode CCVI. In this case, contact electrodes CCIII and CCVI may be arranged in the X or Y direction. Additionally, there may be cases where other contact electrodes CC are positioned between contact electrodes CCIII and CCVI.

[0231] Furthermore, for example, in the first to fourth embodiments, one end of the semiconductor layer 120 in the Z direction is connected to the semiconductor layer 112. However, one end of the semiconductor layer 120 in the Z direction may also be connected to the semiconductor substrate 100. Additionally, for example, in the first to fourth embodiments, the contact electrode CC is connected to the upper surface of the conductive layer 110. However, the contact electrode CC may also be connected to the lower surface of the conductive layer 110.

[0232] Additionally, for example, as referenced Figure 10 and Figure 11 As explained, a hard mask 105 is used in the manufacturing methods of the first to fourth embodiments. However, such methods are merely illustrative, and specific methods can be appropriately modified. For example, it is also possible to manufacture the semiconductor memory device according to any embodiment without using the hard mask 105.

[0233] [other]

[0234] While several embodiments of the invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0235] [Explanation of the labels]

[0236] 100… Semiconductor substrate, 110… Conductive layer, 120… Semiconductor layer, 130… Gate insulating film, CCG… Contact electrode array, CC… Contact electrode.

Claims

1. A semiconductor memory device comprising: substrate; Multiple conductive layers are arranged in a first direction intersecting the surface of the substrate and extend in a second direction intersecting the first direction, and are located in a connection region between two memory hole regions arranged in the second direction; A semiconductor layer extending in the first direction, opposite to the plurality of conductive layers, and disposed in a memory hole region; as well as Two contact electrode regions are arranged in a third direction intersecting the first and second directions, and are disposed in the connection region, wherein, One of the two contact electrode regions has a plurality of contact electrodes arranged in the second direction, and The plurality of conductive layers include a first conductive layer, a second conductive layer, and a third conductive layer that is closer to the substrate than the first conductive layer and the second conductive layer. The plurality of contact electrodes included in one of the two contact electrode regions include: The first contact electrode is electrically connected to the first conductive layer; The second contact electrode is electrically connected to the second conductive layer; and A third contact electrode is disposed between the first contact electrode and the second contact electrode and is electrically connected to the third conductive layer. The first contact electrode, the second contact electrode, and the third contact electrode are arranged in the second direction. Three of the plurality of conductive layers are disposed between the first conductive layer and the second conductive layer.

2. The semiconductor memory device according to claim 1, wherein, The plurality of conductive layers includes a fourth conductive layer that is closer to the substrate than the third conductive layer. One of the two contact electrode regions includes a plurality of contact electrodes, including a fourth contact electrode electrically connected to the fourth conductive layer. The first contact electrode or the second contact electrode is disposed between the third contact electrode and the fourth contact electrode. The first contact electrode, the second contact electrode, the third contact electrode, and the fourth contact electrode are arranged in the second direction.

3. A semiconductor memory device comprising: substrate; Multiple conductive layers are arranged in a first direction intersecting the surface of the substrate and extend in a second direction intersecting the first direction, and are located in a connection region between two memory hole regions arranged in the second direction; A first semiconductor layer extends in the first direction, is opposite to the plurality of conductive layers, and is disposed in a memory hole region; as well as Two contact electrode regions are arranged in a third direction intersecting the first and second directions, and are disposed in the connection region, wherein, One of the two contact electrode regions has a plurality of contact electrodes arranged in the second direction. The plurality of conductive layers include a first conductive layer, a second conductive layer, and a third conductive layer that is further away from the substrate than the first conductive layer and the second conductive layer. The plurality of contact electrodes included in one of the two contact electrode regions include: The first contact electrode is electrically connected to the first conductive layer; The second contact electrode is electrically connected to the second conductive layer; and A third contact electrode is disposed between the first contact electrode and the second contact electrode and is electrically connected to the third conductive layer. The first contact electrode, the second contact electrode, and the third contact electrode are arranged in the second direction. Three of the plurality of conductive layers are disposed between the first conductive layer and the second conductive layer.

4. The semiconductor memory device according to claim 3, wherein, The plurality of conductive layers includes a fourth conductive layer that is closer to the substrate than the first conductive layer and the second conductive layer. One of the two contact electrode regions includes a plurality of contact electrodes, including a fourth contact electrode connected to the fourth conductive layer. The fourth contact electrode is disposed between the third contact electrode and the second contact electrode. The first contact electrode, the second contact electrode, the third contact electrode, and the fourth contact electrode are arranged in the second direction.

5. A semiconductor memory device comprising: substrate; Multiple conductive layers are arranged in a first direction intersecting the surface of the substrate and extend in a second direction intersecting the first direction, and are located in a connection region between two memory hole regions arranged in the second direction; A first semiconductor layer extends in the first direction, is opposite to the plurality of conductive layers, and is disposed in a memory hole region; as well as Two contact electrode regions are arranged in a third direction intersecting the first and second directions, and are disposed in the connection region, wherein, One of the two contact electrode regions has a plurality of contact electrodes arranged in the second direction. The plurality of conductive layers include a first conductive layer, a second conductive layer, and a third conductive layer that is closer to the substrate than the first conductive layer and the second conductive layer. The plurality of contact electrodes included in one of the two contact electrode regions include: The first contact electrode is electrically connected to the first conductive layer; The second contact electrode is electrically connected to the second conductive layer; and A third contact electrode is disposed between the first contact electrode and the second contact electrode and is electrically connected to the third conductive layer. The first contact electrode, the second contact electrode, and the third contact electrode are arranged in the second direction. Seven of the plurality of conductive layers are disposed between the first conductive layer and the second conductive layer.

6. A semiconductor memory device comprising: substrate; Multiple conductive layers are arranged in a first direction intersecting the surface of the substrate and extend in a second direction intersecting the first direction, and are located in a connection region between two memory hole regions arranged in the second direction; A first semiconductor layer extends in the first direction, is opposite to the plurality of conductive layers, and is disposed in a memory hole region; as well as Two contact electrode regions are arranged in a third direction intersecting the first and second directions, and are disposed in the connection region, wherein, One of the two contact electrode regions has a plurality of contact electrodes arranged in the second direction. The plurality of conductive layers include a first conductive layer, a second conductive layer, and a third conductive layer that is further away from the substrate than the first conductive layer and the second conductive layer. The plurality of contact electrodes included in one of the two contact electrode regions include: The first contact electrode is electrically connected to the first conductive layer; The second contact electrode is electrically connected to the second conductive layer; and A third contact electrode is disposed between the first contact electrode and the second contact electrode and is electrically connected to the third conductive layer. The first contact electrode, the second contact electrode, and the third contact electrode are arranged in the second direction. Seven of the plurality of conductive layers are disposed between the first conductive layer and the second conductive layer.

7. The semiconductor memory device according to any one of claims 1 to 6, wherein, Another contact electrode region among the two contact electrode regions has a plurality of contact electrodes arranged in the second direction, and The plurality of conductive layers include a fifth conductive layer, a sixth conductive layer, a seventh conductive layer that is closer to the substrate than the fifth and sixth conductive layers, and an eighth conductive layer that is closer to the substrate than the seventh conductive layer, wherein, The plurality of contact electrodes included in the other contact electrode region of the two contact electrode regions include: The fifth contact electrode is electrically connected to the fifth conductive layer; The sixth contact electrode electrically connected to the sixth conductive layer; and A seventh contact electrode is disposed between the fifth contact electrode and the sixth contact electrode and electrically connected to the seventh conductive layer; and The 8th contact electrode is electrically connected to the 8th conductive layer. The fifth contact electrode or the sixth contact electrode is disposed between the seventh contact electrode and the eighth contact electrode. The fifth contact electrode, the sixth contact electrode, the seventh contact electrode, and the eighth contact electrode are arranged in the second direction. Three of the plurality of conductive layers are disposed between the fifth conductive layer and the sixth conductive layer.

8. The semiconductor memory device according to any one of claims 1 to 6, wherein, Another contact electrode region among the two contact electrode regions has a plurality of contact electrodes arranged in the second direction, and The plurality of conductive layers include a fifth conductive layer, a sixth conductive layer, a seventh conductive layer that is further away from the substrate than the fifth and sixth conductive layers, and an eighth conductive layer that is closer to the substrate than the fifth and sixth conductive layers, wherein, The plurality of contact electrodes included in the other contact electrode region of the two contact electrode regions include: The fifth contact electrode is electrically connected to the fifth conductive layer; The sixth contact electrode electrically connected to the sixth conductive layer; and A seventh contact electrode is disposed between the fifth contact electrode and the sixth contact electrode and electrically connected to the seventh conductive layer; and The eighth contact electrode is disposed between the seventh contact electrode and the sixth contact electrode and is electrically connected to the eighth conductive layer. The fifth contact electrode, the sixth contact electrode, the seventh contact electrode, and the eighth contact electrode are arranged in the second direction. Three of the plurality of conductive layers are disposed between the fifth conductive layer and the sixth conductive layer.

9. The semiconductor memory device according to any one of claims 1 to 6, wherein, Another contact electrode region among the two contact electrode regions has a plurality of contact electrodes arranged in the second direction, and The plurality of conductive layers includes a fifth conductive layer, a sixth conductive layer, and a seventh conductive layer that is closer to the substrate than the fifth and sixth conductive layers, wherein, The plurality of contact electrodes included in the other contact electrode region of the two contact electrode regions include: The fifth contact electrode is electrically connected to the fifth conductive layer; The sixth contact electrode electrically connected to the sixth conductive layer; and The seventh contact electrode is disposed between the fifth contact electrode and the sixth contact electrode and is electrically connected to the seventh conductive layer. The fifth contact electrode, the sixth contact electrode, and the seventh contact electrode are arranged in the second direction. Seven of the plurality of conductive layers are disposed between the fifth conductive layer and the sixth conductive layer.

10. The semiconductor memory device according to any one of claims 1 to 6, wherein, Another contact electrode region among the two contact electrode regions has a plurality of contact electrodes arranged in the second direction, and The plurality of conductive layers includes a fifth conductive layer, a sixth conductive layer, and a seventh conductive layer that is further away from the substrate than the fifth and sixth conductive layers, wherein, The plurality of contact electrodes included in the other contact electrode region of the two contact electrode regions include: The fifth contact electrode is electrically connected to the fifth conductive layer; The sixth contact electrode electrically connected to the sixth conductive layer; and The seventh contact electrode is disposed between the fifth contact electrode and the sixth contact electrode and is electrically connected to the seventh conductive layer. The fifth contact electrode, the sixth contact electrode, and the seventh contact electrode are arranged in the second direction. Seven of the plurality of conductive layers are disposed between the fifth conductive layer and the sixth conductive layer.

11. The semiconductor memory device according to any one of claims 1 to 6, wherein, One of the two contact electrode regions comprises: A first insulating layer is disposed on the outer peripheral surface of the first contact electrode; A second insulating layer disposed on the outer peripheral surface of the second contact electrode; and A third insulating layer is disposed on the outer peripheral surface of the third contact electrode.

12. The semiconductor memory device according to claim 11, wherein, The first contact electrode comprises a metal film. The first insulating layer comprises silicon oxide.

13. The semiconductor memory device according to claim 11, wherein, The first insulating layer is in contact with the first conductive layer.

14. The semiconductor memory device according to any one of claims 1 to 6, wherein, It also includes a second semiconductor layer disposed in the memory hole region. The first semiconductor layer is electrically connected to the second semiconductor layer at one end in the first direction.

15. The semiconductor memory device according to claim 14, wherein, The second semiconductor layer comprises polycrystalline silicon containing phosphorus or boron.

16. The semiconductor memory device according to any one of claims 1 to 6, wherein, It also includes a second semiconductor layer disposed in the memory hole region on the side adjacent to the connection region. One end of the first semiconductor layer in the first direction is connected to the bit line via a contact. The second semiconductor layer is not connected to the contact at one end in the first direction.

17. The semiconductor memory device according to any one of claims 1 to 6, wherein, The width of the first semiconductor layer in the second direction is shorter than the width of the first contact electrode in the second direction.

18. The semiconductor memory device according to any one of claims 1 to 6, wherein, The first contact electrode is electrically connected to the wiring via the first contact.

19. The semiconductor memory device according to claim 18, wherein, One end of the first semiconductor layer in the first direction is electrically connected to the bit line via a second contact. The width of the bit line in the second direction is shorter than the width of the wiring in the second direction.

20. The semiconductor memory device according to any one of claims 1 to 6, wherein, The first contact electrode is electrically connected to the wiring via the first contact and the second contact.

21. The semiconductor memory device according to any one of claims 1 to 6, wherein, The first contact electrode is connected to the lower surface of the first conductive layer. The second contact electrode is connected to the lower surface of the second conductive layer. The third contact electrode is connected to the lower surface of the third conductive layer.

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