Semiconductor memory devices

Abstract

This disclosure relates to a semiconductor memory device. The semiconductor memory device includes a tunnel insulating layer, a data storage layer, and a barrier insulating layer sequentially disposed therefrom. The tunnel insulating layer includes a metal-organic framework (MOF) having a lower dielectric constant than that of the barrier insulating layer.

Description

Technical Field

[0001] The various embodiments of this disclosure generally relate to a semiconductor memory device, and more specifically, to a non-volatile semiconductor memory device. Background Technology

[0002] Non-volatile memory devices can retain data even when power supply is interrupted. Flash memory devices are a type of non-volatile memory device and are used in a variety of portable electronic devices. A flash memory cell may include a tunnel insulating layer, a data storage layer, and a barrier insulating layer. Summary of the Invention

[0003] According to embodiments of this disclosure, a semiconductor memory device is provided, comprising: a stacked body including alternately stacked interlayer insulating layers and word lines; a channel layer passing through the stacked body; a barrier insulating layer located between each word line and the channel layer; a data storage layer located between the barrier insulating layer and the channel layer; and a tunnel insulating layer located between the channel layer and the data storage layer. The tunnel insulating layer includes a metal-organic framework (MOF) having a lower dielectric constant than that of the barrier insulating layer.

[0004] According to embodiments of the present disclosure, a semiconductor memory device is provided, comprising: a gate electrode above a semiconductor substrate; a barrier insulating layer between the semiconductor substrate and the gate electrode; a data storage layer between the semiconductor substrate and the barrier insulating layer; and a tunnel insulating layer between the semiconductor substrate and the data storage layer. The tunnel insulating layer comprises a metal-organic framework (MOF) having a dielectric constant lower than that of the barrier insulating layer. Attached Figure Description

[0005] Figure 1 This is a schematic circuit diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0006] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E and Figure 2F These are diagrams illustrating various embodiments of a semiconductor memory device.

[0007] Figure 3 This is a diagram illustrating a tunnel insulation layer according to an embodiment of the present disclosure.

[0008] Figure 4 This is an energy band diagram of a memory cell according to an embodiment of the present disclosure in a state where no electric field is applied.

[0009] Figure 5 It is an energy band diagram used to describe the programming operations of a memory cell according to an embodiment of the present disclosure.

[0010] Figure 6 It is an energy band diagram used to describe the erase operation of a memory cell according to an embodiment of the present disclosure.

[0011] Figure 7 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0012] Figure 8 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure. Detailed Implementation

[0013] The specific structural and functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments based on the concept of this disclosure. Embodiments based on the concept of this disclosure may be implemented in various forms and should not be construed as limited to the specific embodiments set forth herein.

[0014] The various embodiments of this disclosure are directed to semiconductor memory devices that can reduce operating voltage and increase operating speed.

[0015] Figure 1 This is a schematic circuit diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0016] Reference Figure 1 The semiconductor memory device can be a three-dimensional (3D) non-volatile memory device or a two-dimensional (2D) non-volatile memory device. According to an embodiment, the non-volatile memory device can be a NAND flash memory device.

[0017] NAND flash memory devices may include a string of memory cells CS that connects the bit line BL and the common source line CSL. The accompanying drawings illustrate a single string of memory cells CS, but multiple strings of memory cells may be connected in parallel between the bit line BL and the common source line CSL.

[0018] The memory cell string CS may include a source selection transistor SST, multiple memory cells MC, and a drain selection transistor DST disposed between the common source line CSL and the bit line BL.

[0019] A source-select transistor (SST) controls the electrical connection between multiple memory cells (MC) and a common source line (CSL). A single SST can be positioned between the common source line (CSL) and multiple memory cells (MC). Although not shown in the accompanying drawings, two or more source-select transistors connected in series can be positioned between the common source line (CSL) and multiple memory cells (MC). The SST can be connected to the source-select line (SSL). The operation of the SST can be controlled by a source-gate signal applied to the source-select line (SSL).

[0020] Multiple memory cells MC can be positioned between the source select transistor SST and the drain select transistor DST. The memory cells MC between the source select transistor SST and the drain select transistor DST can be connected in series. The memory cells MC can be connected to corresponding word lines WL. The operation of the memory cells MC can be controlled by a cell gate signal applied to the word line WL.

[0021] The drain select transistor (DST) controls the electrical connection between multiple memory cells (MC) and bit lines (BL). The DST can be connected to the drain select line (DSL). The operation of the DST can be controlled by a drain-gate signal applied to the drain select line (DSL).

[0022] Each memory cell (MC) can store a single bit of data or multiple bits of data.

[0023] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E and Figure 2F These are diagrams illustrating various embodiments of a semiconductor memory device.

[0024] Figure 2A , Figure 2B and Figure 2C This is a perspective view illustrating various embodiments of a 3D NAND flash memory device. (Refer to...) Figure 2A , Figure 2B and Figure 2C The semiconductor memory device may include a stacked body 100, a channel layer 127A, 127B or 127C, a tunnel insulating layer 125A, 125B or 125C, a data storage layer 123A, 123B or 123C, and a barrier insulating layer 121A, 121B or 121C.

[0025] The stacked body 100 may include an interlayer insulating layer 101 and word lines 103. Each of the interlayer insulating layer 101 and word lines 103 may be parallel to the XY plane. The interlayer insulating layer 101 and word lines 103 may be stacked in the Z-axis direction perpendicular to the XY plane. The interlayer insulating layer 101 and word lines 103 may be alternately arranged.

[0026] The word lines 103 can be insulated from each other through the interlayer insulation layer 101. The word lines 103 can be used as a reference. Figure 1 The described memory cell MC has a gate electrode. Word line 103 may include at least one of a doped semiconductor, a metal, a metal nitride, and a metal silicide. Interlayer insulating layer 101 may include a silicon oxide layer.

[0027] The laminated body 100 can be penetrated by a hole 111 extending in the Z-axis direction. The sidewalls of the interlayer insulating layer 101 can be defined along the sidewalls of the hole 111.

[0028] according to Figure 2A In the embodiment shown, the sidewall of the character line 103 can be defined along the sidewall of the hole 111.

[0029] according to Figure 2B and Figure 2C In the illustrated embodiment, each word line 103 may have a sidewall disposed further away from the central axis of the hole 111 than the interlayer insulating layer 101. Therefore, the recessed region 115 may be defined between interlayer insulating layers 101 that are adjacent to each other along the Z-axis direction.

[0030] The channel layers 127A, 127B, or 127C may include a semiconductor such as silicon. The channel layers 127A, 127B, or 127C may extend in the Z-axis direction. The channel layers 127A, 127B, or 127C may be formed Figure 1 The channel region of the memory cell string CS shown. Channel layers 127A, 127B, or 127C may be surrounded by interlayer insulating layer 101 and word line 103.

[0031] Barrier insulating layers 121A, 121B, or 121C may be inserted between channel layers 127A, 127B, or 127C and the laminate body 100. Barrier insulating layers 121A, 121B, or 121C may comprise a single layer or multiple layers.

[0032] Data storage layers 123A, 123B, or 123C may be interposed between barrier insulating layers 121A, 121B, or 121C and channel layers 127A, 127B, or 127C. Data storage layers 123A, 123B, or 123C may include charge trapping layers or floating gate layers.

[0033] Tunnel insulation layers 125A, 125B, or 125C may be inserted between data storage layers 123A, 123B, or 123C and trench layers 127A, 127B, or 127C. Tunnel insulation layers 125A, 125B, or 125C may include a metal-organic framework (MOF).

[0034] The semiconductor memory device may further include a core insulating layer 129 filling the central region of the via 111. Channel layers 127A, 127B, or 127C may surround the sidewalls of the core insulating layer 129. Figures 2A to 2C As shown, the core insulation layer 129 can be omitted, and the channel layer can extend to fill the central region of the hole 111.

[0035] The trench layer 127A, 127B or 127C, the tunnel insulation layer 125A, 125B or 125C, the data storage layer 123A, 123B or 123C, and the barrier insulation layer 121A, 121B or 121C can be formed in various structures.

[0036] Reference Figure 2A The barrier insulation layer 121A, data storage layer 123A, and tunnel insulation layer 125A can extend along the sidewall of the channel layer 127A in the Z-axis direction. Each of the barrier insulation layer 121A, data storage layer 123A, and tunnel insulation layer 125A can be disposed between each word line 103 and the channel layer 127A, and can extend into the space between each interlayer insulation layer 101 and the channel layer 127A.

[0037] The barrier insulating layer 121A may include a silicon oxide layer, but embodiments of this disclosure are not limited thereto. In embodiments, the barrier insulating layer 121A may include a silicon oxide layer and a metal oxide layer between the silicon oxide layer and the laminated body 100. The metal oxide layer may include an oxide having a dielectric constant higher than that of the silicon oxide layer. In embodiments, the metal oxide layer may include an aluminum oxide layer.

[0038] The data storage layer 123A may include a charge trapping layer extending along the sidewall of the channel layer 127A in the Z-axis direction. In one embodiment, the charge trapping layer may include a silicon nitride layer.

[0039] Reference Figure 2B The channel layer 127B may include a vertical portion 127VP extending in the Z-axis direction and a protrusion 127PP protruding from the vertical portion 127VP toward each word line 103.

[0040] Each of the barrier insulation layer 121B, data storage layer 123B, and tunnel insulation layer 125B may extend into the recessed region 115. Each of the barrier insulation layer 121B, data storage layer 123B, and tunnel insulation layer 125B may be conformally formed along the recessed region 115 and may have a curved structure. Each of the barrier insulation layer 121B, data storage layer 123B, and tunnel insulation layer 125B may surround a protrusion 127PP of the channel layer 127B.

[0041] Barrier insulation layer 121B may include reference Figure 2A The barrier insulating layer 121A is made of the same material as described, and the data storage layer 123B may include materials similar to those referenced. Figure 2A The data storage layer 123A described is made of the same material.

[0042] The charge trapping layer, serving as the data storage layer 123B, is formed within the curved structure, thereby reducing the movement of stored charge in the charge trapping layer along the Z-axis. This improves the operational reliability of the semiconductor memory device.

[0043] Despite Figure 2B Not shown in the figure, but in the embodiment, the protrusion 127PP of the trench layer 127B can be omitted, and the tunnel insulation layer 125B can be extended to fill the central region of the recessed region 115.

[0044] Reference Figure 2C The data storage layers 123C may be spaced apart from each other in the Z-axis direction. Each data storage layer 123C may be locally formed between interlayer insulating layers 101 that are adjacent to each other in the Z-axis direction. The separation of the data storage layers 123C from each other in the Z-axis direction prevents the movement of charges stored in the data storage layers 123C in the Z-axis direction. Each data storage layer 123C may include a charge trapping layer or a floating gate layer. In an embodiment, the charge trapping layer may include a silicon nitride layer. In an embodiment, the floating gate layer may include silicon.

[0045] The barrier insulating layer 121C may include column portions between each interlayer insulating layer 101 and tunnel insulating layer 125, and curved portions between each word line 103 and each data storage layer 123C. The column portions of the barrier insulating layer 121C may be in direct contact with the tunnel insulating layer 125C, and the curved portions of the barrier insulating layer 121C may be conformally formed along the recessed region 115. The barrier insulating layer 121C may include a first oxide layer 131, a nitride layer 133, and a second oxide layer 135, but embodiments of this disclosure are not limited thereto. In embodiments, the barrier insulating layer 121C may include, with reference to, a column portion between each interlayer insulating layer 101 and tunnel insulating layer 125, and a curved portion between each word line 103 and each data storage layer 123C. Figure 2A The barrier insulation layer 121A described is made of the same material.

[0046] In the above description, a first oxide layer 131 may be conformally formed along the sidewalls of the hole 111 and the recessed region 115. A second oxide layer 135 may be interposed between the first oxide layer 131 and the tunnel insulating layer 125C. A nitride layer 133 may be interposed between the first oxide layer 131 and the second oxide layer 135. The first oxide layer 131 and the second oxide layer 135 may comprise silicon dioxide.

[0047] Figure 2D and Figure 2E These are cross-sectional views illustrating various embodiments of a 3D NAND flash memory device. In the following text, descriptions will be omitted. Figures 2A to 2C The description content is redundant.

[0048] Reference Figure 2D and Figure 2E The semiconductor memory device may include a stacked body 100, a channel layer 127D or 127E, a tunnel insulating layer 125D or 125E, a data storage layer 123D or 123E, and a barrier insulating layer 121D or 121E.

[0049] The interlayer insulating layer 101 and word lines 103 of the laminated body 100 can be penetrated by a hole 111 extending in the Z-axis direction. The sidewalls of the word lines 103 can be defined along the sidewalls of the hole 111. Each interlayer insulating layer 101 can have a sidewall disposed further away from the central axis of the hole 111 than the word lines 103. Therefore, a recessed region 117 can be defined between adjacent word lines 103 along the Z-axis direction.

[0050] In one embodiment, the central region of the hole 111 may be filled with the core insulating layer 129. The channel layer 127D or 127E may surround the core insulating layer 129.

[0051] The barrier insulating layer 121D or 121E between the stacked body 100 and the channel layer 127D or 127E may comprise a single layer or multiple layers. The data storage layer 123D or 123E between the channel layer 127D or 127E and the barrier insulating layer 121D or 121E may comprise a charge trapping layer. The tunnel insulating layer 125D or 125E between the channel layer 127D or 127E and the data storage layer 123D or 123E may comprise a metal-organic framework (MOF).

[0052] Each of the barrier insulating layer 121D or 121E and the data storage layer 123D or 123E may include a portion parallel to the sidewall of the word line 103. Each of the barrier insulating layer 121D or 121E and the data storage layer 123D or 123E may have a curved portion conformally formed along the recessed region 117. A charge trapping layer is formed in the curved structure as the data storage layer 123D or 123E, thereby reducing the phenomenon of charge stored in the charge trapping layer moving in the Z-axis direction. Figure 2D and Figure 2E In the illustrated embodiment, the charge trapping region may include an area surrounded by word lines 103 in the data storage layer 123D or 123E, and may extend to an area surrounding the edge of each word line 103. Therefore, the data storage region can be expanded.

[0053] Reference Figure 2D The tunnel insulation layer 125D may extend parallel to the data storage layer 123D. The tunnel insulation layer 125D may have a portion parallel to the sidewall of the word line 103 and a curved portion conformally formed along the recessed region 117.

[0054] The trench layer 127D may include a vertical portion 127VP' extending in the Z-axis direction and a protrusion 127PP' projecting from the vertical portion 127VP' toward each interlayer insulation layer 101. The tunnel insulation layer 125D may surround the protrusion 127PP' of the trench layer 127D.

[0055] Reference Figure 2E The tunnel insulation layer 125E may include a vertical portion 125VP extending in the Z-axis direction and a protrusion 125PP projecting from the vertical portion 125VP toward each interlayer insulation layer 101. The protrusion 125PP of the tunnel insulation layer 125E may fill the central region of the recessed region 117.

[0056] The trench layer 127E can extend in the Z-axis direction, thus being parallel to the vertical portion 125VP of the tunnel insulation layer 125E.

[0057] Reference Figure 2D and Figure 2E Because the edge field f generated by the voltage applied to word line 103 can be shielded by the tunnel insulating layer 125D or 125E formed in the recessed region 117, interference between adjacent memory cells in the Z-axis direction can be reduced. Therefore, variations in the threshold voltage of the memory cells can be reduced, and operational disturbances such as programming disturbances can be decreased. Thus, the operational reliability of the semiconductor memory device can be improved.

[0058] Figure 2FThis is a cross-sectional view illustrating an implementation of a 2D NAND flash memory device.

[0059] Reference Figure 2F The semiconductor memory device may include a semiconductor substrate 231, a gate electrode 203, a tunnel insulating layer 225, a data storage layer 223, and a barrier insulating layer 221.

[0060] The semiconductor substrate 231 may include an active region. Although not shown in the figures, the active region may be segmented by an isolation layer. Figure 2F An example is shown of a cross-section taken by cutting the active region of the semiconductor substrate 231.

[0061] Gate electrodes 203 may be disposed above semiconductor substrate 231. Gate electrodes 203 may be spaced apart from each other by trench 241 along the direction extending from the active region. Although not shown in the figure, the upper portion of each gate electrode 203 extends in a direction intersecting with the active region, thereby forming a word line.

[0062] Impurity regions 231I can be formed in the semiconductor substrate 231 on the opposite side of the gate electrode 203. The portion of the active region that overlaps with each gate electrode 203 and is disposed between the impurity regions 231I can be defined as a channel region 231C.

[0063] The tunnel insulating layer 225, the data storage layer 223, and the barrier insulating layer 221 can be sequentially stacked between each gate electrode 203 and the semiconductor substrate 231.

[0064] The barrier insulating layer 221 can be interposed between each gate electrode 203 and the semiconductor substrate 231. The barrier insulating layer 221 may include components similar to those referenced. Figure 2A The barrier insulating layer 121A described may be made of the same material, or may include layers thereof. Figure 2C The structure of the first oxide layer 131, the nitride layer 133, and the second oxide layer 135 is described.

[0065] Data storage layer 223 can be interposed between barrier insulating layer 221 and semiconductor substrate 231. Data storage layer 223 may include charge trapping layer or floating gate layer. Data storage layer 223 may be locally formed over semiconductor substrate 231 between impurity regions 231I and may be spaced apart from another data storage layer 223. In other words, data storage layers 223 adjacent to each other in the direction extending from the active region of semiconductor substrate 231 can be separated from each other by trench 241. However, embodiments of the present disclosure are not limited thereto. Although not shown in the drawings, in embodiments, the charge trapping layer as data storage layer 223 may extend continuously along the active region of semiconductor substrate 231 and overlap with impurity regions 231I.

[0066] A tunnel insulating layer 225 can be interposed between the data storage layer 223 and the semiconductor substrate 231. The tunnel insulating layer 225 may include a metal-organic framework (MOF). In one embodiment, the tunnel insulating layer 225 may be penetrated by a trench 241, but the embodiments disclosed herein are not limited thereto. Although not shown in the figures, in one embodiment, the tunnel insulating layer 225 may extend continuously along the active region of the semiconductor substrate 231 and overlap with the impurity region 231I.

[0067] As mentioned above (refer to) Figures 2A to 2E The tunnel insulation layer according to embodiments of this disclosure may include a metal-organic framework (MOF). MOFs are porous compounds formed by a chemical combination of metal ions and organic ligands or a chemical combination of metal clusters and organic ligands. MOFs are materials whose dielectric constant can be controlled to be smaller than that of silicon dioxide (SiO2). Because MOFs can be formed by atomic layer deposition (ALD) with excellent step coverage, embodiments of this disclosure can improve the thickness uniformity of the tunnel insulation layer. Because the dielectric constant of the MOF can be controlled to be equal to or less than 2, the tunneling of charge caused by programming and erasing voltages can be increased. Therefore, embodiments of this disclosure can improve the speed of programming and erasing operations. Because the dielectric constant of the tunnel insulation layer with MOF can be controlled to be low, the shielding edge field (refer to…) can be improved. Figure 2D and Figure 2E (Description) of efficiency.

[0068] Figure 3 This is a diagram illustrating a tunnel insulation layer according to an embodiment of the present disclosure.

[0069] Reference Figure 3 The tunnel insulation layer consists of a metallic center M coordinated to the organic ligand L. n+ The resulting metal-organic framework (MOF) can have porosity (P). When setting up an MOF, the coordination number, ligand length, and metal center (M) can be controlled. n+ The reaction environment for binding with the organic ligand L is controlled in various ways. Therefore, the size of the pores P can be controlled differently, and the dielectric constant of the MOF can be controlled to a low value in the range of 1 to 2.

[0070] MOF's metallic center M n+ It can include Zn 2+ Zr 4+ Al 3+ wait.

[0071] The organic ligand L of MOF can include 2-methylimidazolium, 2-aminoterephthalic acid, 1, 3, 5-benzenetricarboxylic acid ester, etc.

[0072] MOFs can include the MOF series, ZIF series, UIO series, SIM series, MIL series, HKUST series, etc. For example, as part of the MOF series, MOFs named MOF-1, MOF-177, etc., can be used as tunnel insulation layers.

[0073] Metal salts that can be used to form MOFs include Zn4O(CO2)6, Zn3O(CO2)6, Cr3O(CO2)6, In3O(CO2)6, Ga3O(CO2)6, Cu2O(CO2)4, Zn2O(CO2)4, Fe2O(CO2)4, Mo2O(CO2)4, Cr2O(CO2)4, Co2O(CO2)4, Ru2O4(CO2)4, Zr6O4(OH4), and Zr6O4(CO2). 12 , Zr6O8(CO2)8, In(C5Ho4N2)4, Na(OH)2(SO3)3, Cu2(CNS)4, Zn(C3H3N2)4, Ni4(C3H3N2)8, Zn3O3(CO2)3, Mg3O3(CO2)3, Co3O3(CO2)3, Ni3O3(CO2)3, Mn3O3(CO2)3, Fe3O3(CO2)3, Cu3O3(CO2)3, Al(OH)(CO2)2, VO(CO2)2, Zn(NO3)2, Zn(O2CCH3), Co(NO3)2, CO(O2CCH3), etc.

[0074] Organic ligands used to form MOFs include oxalic acid, fumaric acid, terephthalic acid (H2BDC), H2BDC-Br, H2BDC-OH, H2BDC-NO2, H2BDC-NH2, H4DOT, H2BDC-(Me)2, H2BDC-(Cl)2, H2BDC-(COOH)2, H2BDC-(OC3H5)2, H2BDC-(OC7H7)2, H3BTC, H3BTE, H3BBC, H4ATC, H3THBTS, H3ImDC, H3BTP, DTOA, H3BTB, H3TATB, H4ADB, TIPA, ADP, H6BTETCA, DCDPBN, BPP34C10DA, and Ir(H2DPBYDC)(PPy). 2+ H4DH9PhDC, H4DH11PhDC, H6TPBTM, H6BTEI, H6BTPI, H6BHEI, H6BTTI, H6PTEI, H6TTEI, H6BNETPI, H6BHEHPI, HMeIM, etc.

[0075] Figure 4This is an energy band diagram of a memory cell according to an embodiment of the present disclosure in a state where no electric field is applied.

[0076] Reference Figure 4 The trench region CH, tunnel insulation layer TI, data storage layer DS, and barrier insulation layer BI can be set sequentially. The thickness of each of the trench region CH, tunnel insulation layer TI, data storage layer DS, and barrier insulation layer BI can be varied according to their materials.

[0077] The channel region CH can be defined as... Figures 2A to 2E One of the channel layers shown and in Figure 2F The tunnel insulating layer TI is shown as the channel region of the semiconductor substrate. Figures 2A to 2F One of the tunnel insulation layers shown. The data storage layer DS can be... Figures 2A to 2F One of the data storage layers shown. The barrier insulation layer BI can be Figures 2A to 2F One of the barrier insulating layers shown.

[0078] The band gaps of the tunnel insulation layer TI and the blocking insulation layer BI can be larger than the band gap of the data storage layer DS. The band gap indicates the difference between the valence band level Ev and the conduction band level Ec.

[0079] The dielectric constant of the tunnel insulating layer TI formed by MOF can be controlled to be less than the dielectric constant of the barrier insulating layer BI. The barrier insulating layer BI may include at least one of silicon dioxide and a high dielectric material having a higher dielectric constant than silicon dioxide. The tunnel insulating layer TI may be formed by MOF, and the dielectric constant of MOF may be controlled to be equal to or less than half the dielectric constant of silicon dioxide.

[0080] Figure 5 It is an energy band diagram used to describe the programming operations of a memory cell according to an embodiment of the present disclosure.

[0081] Reference Figure 5 An electric field can be formed in the direction from the barrier insulating layer BI to the channel region CH by the programming voltage applied during programming operation, and the band bending can be caused by the electric field.

[0082] When a programming voltage is applied, the electric fields in the tunnel insulating layer TI, the data storage layer DS, and the barrier insulating layer BI can be affected by the dielectric constant of each of these layers. Because the tunnel insulating layer TI has a lower dielectric constant than the barrier insulating layer BI, the electric field applied to the tunnel insulating layer TI can be relatively higher than that applied to the barrier insulating layer BI. Therefore, electron tunneling in the barrier insulating layer BI can be reduced. Furthermore, because electron tunneling in the tunnel insulating layer TI can be increased, the programming speed can be improved.

[0083] According to embodiments of this disclosure, the tunnel insulating layer TI is formed of MOF, thereby allowing the dielectric constant of the tunnel insulating layer TI to be equal to or less than half the dielectric constant of the blocking insulating layer BI. Furthermore, the dielectric constant of the tunnel insulating layer TI can be reduced to be equal to or less than 2. Because the voltage drop V1 in the tunnel insulating layer TI increases as the dielectric constant of the tunnel insulating layer TI decreases, electron tunneling in the tunnel insulating layer TI can be ensured even with a reduced electric field, thereby ensuring programming operation characteristics in low electric fields.

[0084] Figure 6 It is an energy band diagram used to describe the erase operation of a memory cell according to an embodiment of the present disclosure.

[0085] Reference Figure 6 An electric field can be formed in the direction from the channel region CH to the blocking insulating layer BI by the erase voltage applied during the erase operation, and the band bending can be caused by the electric field.

[0086] Holes in the channel region CH can be injected into the data storage layer DS through the electric field created by the erase voltage, and electrons can be released from the data storage layer DS into the channel region CH. Because the tunnel insulating layer TI has a lower dielectric constant than the barrier insulating layer BI, the number of electrons injected from the word line into the barrier insulating layer BI can be reduced during the erase operation, based on a principle similar to that of programming operations. Since the voltage drop V2 in the tunnel insulating layer TI increases as the dielectric constant of TI decreases, the erase operation characteristics can be ensured even with a reduced electric field, based on a principle similar to that of programming operations.

[0087] As described above, the embodiments of this disclosure form the tunnel insulating layer TI as a MOF, thereby reducing the dielectric constant of the tunnel insulating layer TI to be equal to or less than half the dielectric constant of the blocking insulating layer BI. Furthermore, the dielectric constant of the tunnel insulating layer TI can be reduced to be equal to or less than 2. Therefore, the embodiments of this disclosure can increase the efficiency of charge tunneling in the tunnel insulating layer TI, improve the operating speed of memory cells, and reduce charge tunneling in the blocking insulating layer BI.

[0088] Figure 7 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0089] Reference Figure 7 The memory system 1100 includes a memory device 1120 and a memory controller 1110.

[0090] The memory device 1120 may be a multi-chip package configured with multiple flash memory chips. The memory device 1120 may be a 2D NAND flash memory device or a 3D NAND flash memory device. The memory device 1120 may have memory cells comprising a tunnel insulating layer, a data storage layer, and a barrier insulating layer sequentially disposed therefrom. The tunnel insulating layer may include a metal-organic framework (MOF) having a lower dielectric constant than the barrier insulating layer.

[0091] The memory controller 1110 controls the memory device 1120 and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 can be used as the working memory of the CPU 1112, which performs overall control operations for data exchange with the memory controller 1110. The host interface 1113 may be configured with a data exchange protocol for a host connected to the memory system 1100. The error correction block 1114 can detect errors in data read from the memory device 1120 and correct the detected errors. The memory interface 1115 can interface with the memory device 1120. The memory controller 1110 may also include a read-only memory (ROM) for storing code data for connection to the host interface.

[0092] The aforementioned memory system 1100 may be a memory card or solid-state drive (SSD) in which the memory device 1120 and the memory controller 1110 are combined with each other. For example, when the memory system 1100 is an SSD, the memory controller 1110 may communicate with an external device (e.g., a host) via one of various interface protocols such as Universal Serial Bus (USB), Multimedia Card (MMC), Peripheral Component Interconnect-Fast (PCI-E), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), or Integrated Drive Electronics (IDE).

[0093] Figure 8 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure.

[0094] Reference Figure 8 The computing system 1200 may include a CPU 1220, random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260. When the computing system 1200 is a mobile device, it may also include a battery for providing operating voltage to the computing system 1200, and may also include an application chipset, a graphics processor, mobile DRAM, etc.

[0095] The memory system 1210 may be configured with a memory device 1212 and a memory controller 1211.

[0096] The memory device 1212 can be a 2D NAND flash memory device or a 3D NAND flash memory device. The memory device 1212 can have memory cells comprising a tunnel insulating layer, a data storage layer, and a barrier insulating layer disposed sequentially. The tunnel insulating layer may include a metal-organic framework (MOF) having a lower dielectric constant than the barrier insulating layer.

[0097] This disclosure can reduce the operating voltage and increase the operating speed of a semiconductor memory device by using a tunnel insulating layer including a metal-organic framework (MOF).

[0098] Cross-reference of related applications

[0099] This application claims priority to Korean Patent Application No. 10-2021-0028914, filed on March 4, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A stacked body, the stacked body comprising alternating layers of interlayer insulation and word lines; A channel layer that penetrates the stacked body; A barrier insulating layer is provided between each of the word lines and the channel layer; A data storage layer, the data storage layer being between the barrier insulating layer and the trench layer; as well as A tunnel insulation layer, the tunnel insulation layer being located between the trench layer and the data storage layer; The tunnel insulation layer comprises a metal-organic framework (MOF) having a lower dielectric constant than the barrier insulation layer. The dielectric constant of the MOF is equal to or less than half the dielectric constant of the barrier insulating layer.

2. The semiconductor memory device according to claim 1, wherein, The MOF has a dielectric constant ranging from 1 to 2.

3. The semiconductor memory device according to claim 1, wherein, The barrier insulating layer comprises at least one of silicon dioxide (SiO2) and a dielectric material having a dielectric constant higher than that of silicon dioxide.

4. The semiconductor memory device according to claim 1, wherein, Each of the barrier insulation layer, the data storage layer, and the tunnel insulation layer extends into the space between each of the interlayer insulation layers and the trench layer.

5. The semiconductor memory device according to claim 1, wherein, The channel layer has a protrusion that extends toward the letter line into a recessed region between the interlayer insulation layers.

6. The semiconductor memory device according to claim 5, wherein, Each of the barrier insulation layer, the data storage layer, and the tunnel insulation layer surrounds the protrusion of the trench layer and curves along the recessed area.

7. The semiconductor memory device according to claim 1, wherein, The channel layer has a protrusion that extends toward the interlayer insulation layer into the recessed region between the word lines.

8. The semiconductor memory device according to claim 1, wherein, The tunnel insulation layer extends toward the interlayer insulation layer into the recessed area between the word lines.

9. The semiconductor memory device according to claim 1, wherein, The data storage layer includes a silicon nitride layer or silicon.

10. A semiconductor memory device, the semiconductor memory device comprising: A gate electrode, wherein the gate electrode is located above the semiconductor substrate; A barrier insulating layer is provided between the semiconductor substrate and the gate electrode. A data storage layer is provided between the semiconductor substrate and the barrier insulating layer. as well as A tunnel insulating layer is provided between the semiconductor substrate and the data storage layer. The tunnel insulation layer comprises a metal-organic framework (MOF) having a lower dielectric constant than the barrier insulation layer. The dielectric constant of the MOF is equal to or less than half the dielectric constant of the barrier insulating layer.

11. The semiconductor memory device of claim 10, wherein, The MOF has a dielectric constant ranging from 1 to 2.

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