Semiconductor device, method for manufacturing the same, and storage system

Abstract

The application provides a semiconductor device, a manufacturing method thereof and a storage system, and the semiconductor device comprises: a stack structure, the stack structure comprising gate layers and insulating layers which are alternately and sequentially arranged; a plurality of channel regions arranged in the stack structure, each channel region comprising a plurality of channel structures, and the channel structures penetrating through the stack structure; a first row of pseudo channel structures, the first row of pseudo channel structures being located between two channel regions and comprising a plurality of first pseudo channel structures arranged along a first direction, each first pseudo channel structure penetrating through the stack structure, and the first direction being perpendicular to a stacking direction of the stack structure; and a first pseudo channel trench structure, the first pseudo channel trench structure being located in the stack structure and being connected with the plurality of first pseudo channel structures of the first row of pseudo channel structures. Through the semiconductor device, the storage density, yield and reliability of the device are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a semiconductor device, its manufacturing method, and a storage system. Background Technology

[0002] In recent years, the development of flash memory has been particularly rapid. The main characteristics of flash memory are its ability to retain stored information for extended periods without power, along with advantages such as high integration density, fast access speed, and ease of erasing and rewriting. Consequently, it has found widespread application in microcomputers, automation control, and many other fields. Against this backdrop, to address the challenges of planar flash memory and to pursue lower production costs per unit storage cell, 3D NAND flash memory emerged. 3D flash memory forms multiple layers of data storage cells stacked alternately, transforming a planar structure into a three-dimensional structure to improve storage density and integration. 3D flash memory can support higher storage capacity in a smaller space, resulting in significant cost savings, reduced energy consumption, and substantial performance improvements to fully meet the needs of numerous consumer mobile devices and the most demanding enterprise deployments.

[0003] Three-dimensional memory (3D memory) forms a stacked structure by alternating layers of gate and insulating layers. Typically, the stacked structure is divided into multiple memory regions by gate line slots within it. However, due to its structural characteristics and manufacturing process, the yield and reliability of 3D memory require further improvement. Summary of the Invention

[0004] This invention provides a semiconductor device, its manufacturing method, and a storage system, thereby improving the yield and reliability of the semiconductor device.

[0005] To address the aforementioned problems, the present invention provides a semiconductor device comprising: a stacked structure including alternating gate layers and insulating layers; a plurality of channel regions disposed in the stacked structure, each channel region including a plurality of channel structures, the channel structures penetrating the stacked structure; a first row of pseudo-channel structures located between two channel regions and including a plurality of first pseudo-channel structures arranged along a first direction, each first pseudo-channel structure penetrating the stacked structure, the first direction being a stacking direction perpendicular to the stacked structure; and a first pseudo-channel notch structure located in the stacked structure and connecting the plurality of first pseudo-channel structures of the first row of pseudo-channel structures.

[0006] The semiconductor device includes multiple first row pseudo-channel structures, which are distributed along a second direction, which is perpendicular to the stacking direction of the stacked structure and is perpendicular to the first direction.

[0007] Semiconductor devices also include:

[0008] The substrate is located on the side of the stacked structure away from the first pseudo-channel groove structure;

[0009] The first pseudo-channel structure extends into the substrate.

[0010] The first pseudo-channel slot structure passes through at least one gate layer and an insulating layer.

[0011] The first pseudo-channel grooving structure includes a plurality of sub-pseudo-channel grooving structures spaced apart along a first direction. The semiconductor device also includes:

[0012] A top-select gate slot structure is located in the stacked structure, passing through at least one gate layer and an insulating layer, and connecting multiple sub-pseudo-channel slot structures.

[0013] In this case, the depth of the first pseudo-channel slot structure in the third direction is greater than or equal to the depth of the top selected gate slot structure in the third direction, and the third direction is the stacking direction parallel to the stacked structure.

[0014] The top selection gate slot structure includes multiple sub-top selection gate slot structures arranged along a first direction, and multiple sub-pseudo-channel slot structures are connected through the multiple sub-top selection gate slot structures.

[0015] Semiconductor devices also include:

[0016] The substrate is located on the side of the stacked structure away from the first pseudo-channel groove structure;

[0017] A gate line slot structure extends along a first direction, penetrates the stacked structure, and extends into the substrate to divide the stacked structure into several parts.

[0018] Semiconductor devices also include:

[0019] The substrate is located on the side of the stacked structure away from the first pseudo-channel groove structure;

[0020] The second row of pseudo-channel structures is located outside at least two channel regions and includes a plurality of second pseudo-channel structures arranged along the first direction, each of the second pseudo-channel structures penetrating the stacked structure.

[0021] The second pseudo-channel groove structure penetrates the stacked structure and the second pseudo-channel structure and extends into the substrate to divide the stacked structure into several parts.

[0022] To address the aforementioned problems, embodiments of the present invention also provide a method for fabricating a semiconductor device, comprising: providing a semiconductor structure, the semiconductor structure including a stacked layer, a plurality of channel regions disposed in the stacked layer, and a first row of pseudo-channel vias located between two channel regions, the first row of pseudo-channel vias including a plurality of first pseudo-channel vias arranged along a first direction, each first pseudo-channel via penetrating the stacked layer, the stacked layer including a sacrificial layer and an insulating layer alternately stacked; forming a first pseudo-channel groove in the stacked layer, the first pseudo-channel groove communicating with the plurality of first pseudo-channel vias of the first row of pseudo-channel structure; replacing the sacrificial layer with a gate layer through the first pseudo-channel vias and the first pseudo-channel groove to form a stacked structure, the stacked structure including a gate layer and an insulating layer alternately stacked; and filling the first row of pseudo-channel vias and the first pseudo-channel groove to respectively form a first row of pseudo-channel structure and a first pseudo-channel groove structure.

[0023] The step of providing the semiconductor structure further includes forming a plurality of sub-dummy channel slots, wherein the first dummy channel slot includes a plurality of sub-dummy channel slots spaced apart along a first direction, and before forming the first dummy channel slot in the stacked layer, the step further includes:

[0024] A top-select gate slot structure is formed, which is located in the stacked layers and passes through at least one sacrificial layer and an insulating layer. Multiple sub-pseudo-channel slots are connected through the top-select gate slot structure.

[0025] Each channel region includes multiple channel structures, which penetrate the stacked layers. A sacrificial material is formed in the first dummy channel via to provide the semiconductor structure. The specific steps include:

[0026] Provide substrate;

[0027] A stacked layer is formed on a substrate, the stacked layer comprising an alternately stacked sacrificial layer and an insulating layer;

[0028] In the stacked layer, a channel hole and a first row of pseudo channel holes are formed respectively. The channel hole is located in multiple channel regions of the stacked layer. The channel region includes multiple channel holes. Each channel hole penetrates the stacked layer. The first row of pseudo channel holes includes first pseudo channel holes arranged along a first direction. Each first pseudo channel hole penetrates the stacked layer. The first direction is the stacking direction perpendicular to the stacked layer.

[0029] Sacrificial material was filled into the channel holes and the first row of pseudo-channel holes, respectively;

[0030] A masking layer is formed above the first row of pseudo-channel holes, covering the first row of pseudo-channel holes, and the projection of the masking layer and the channel holes on the substrate does not overlap.

[0031] Remove the sacrificial material located in the channel hole;

[0032] Remove the masking layer;

[0033] Fill the channel holes to form a channel structure.

[0034] Specifically, the sacrificial layer is replaced with a gate layer through a first pseudo-channel via and a first pseudo-channel slot to form a stacked structure, including:

[0035] Remove the sacrificial material located in the first pseudo-channel hole;

[0036] The sacrificial layer is removed, and a gate layer is formed at the location of the sacrificial layer to form a stacked structure.

[0037] After providing the semiconductor structure, the following are also included:

[0038] A gate line slot is formed in the stacked layer, the gate line slot extends along a first direction, the gate line slot penetrates the stacked layer and extends into the substrate, so as to divide the stacked layer into several parts;

[0039] Fill the grid line gaps to form a grid line gap structure.

[0040] The first pseudo-channel groove and the grid line gap are formed in the same process.

[0041] The first pseudo-channel slot structure and the grid line slot structure are formed under the same process.

[0042] The step of providing the semiconductor structure further includes forming a second row of dummy channel vias, the second row of dummy channel vias being located outside at least two channel regions and including a plurality of second dummy channel vias arranged along a first direction, each second dummy channel via penetrating the stacked layer; after providing the semiconductor structure, the step further includes:

[0043] A second pseudo-channel groove is formed in the stacked layer. The second pseudo-channel groove penetrates the stacked layer and the second row of pseudo-channel holes and extends into the substrate to divide the stacked layer into several parts.

[0044] The second row of pseudo-channel holes and the second pseudo-channel groove are filled respectively to form the second row of pseudo-channel structure and the second pseudo-channel groove structure.

[0045] The first pseudo-groove and the second pseudo-groove are formed under the same process.

[0046] The first pseudo-groove structure and the second pseudo-groove structure are formed under the same process.

[0047] To address the aforementioned problems, embodiments of the present invention also provide a storage system, including a controller and a three-dimensional memory, wherein the controller is coupled to the three-dimensional memory and is used to control the three-dimensional memory to store data, and the three-dimensional memory includes any of the semiconductor devices described above.

[0048] This invention provides a semiconductor device, its fabrication method, and a memory system. The semiconductor device includes: a stacked structure comprising alternating gate layers and insulating layers; multiple channel regions disposed in the stacked structure, each channel region including multiple channel structures penetrating the stacked structure; a first row of pseudo-channel structures located between two channel regions and including multiple first pseudo-channel structures arranged along a first direction, each first pseudo-channel structure penetrating the stacked structure, the first direction being a stacking direction perpendicular to the stacked structure; and a first pseudo-channel notch structure located in the stacked structure and connecting the multiple first pseudo-channel structures of the first row of pseudo-channel structures. The semiconductor device of this invention improves the storage density, yield, and reliability of the device. Attached Figure Description

[0049] The technical solution and other beneficial effects of the present invention will become apparent from the following detailed description of specific embodiments of the invention, in conjunction with the accompanying drawings.

[0050] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor device according to a first embodiment of the present invention.

[0051] Figure 2a A schematic diagram of the structure forming the first row of pseudo-channel holes is provided for the first embodiment of the present invention;

[0052] Figure 2b for Figure 2a A cross-sectional view along the middle Y1-Y1;

[0053] Figure 3a This is a schematic diagram of the structure of the first embodiment of the present invention, which is filled with channel holes and the first row of dummy channel holes respectively;

[0054] Figure 3b for Figure 3a A cross-sectional view along the middle Y1-Y1;

[0055] Figure 4a This is a schematic diagram of the structure forming the shielding layer in the first embodiment of the present invention;

[0056] Figure 4b for Figure 4a A cross-sectional view along the middle Y1-Y1;

[0057] Figure 5a This is a schematic diagram of the structure for removing sacrificial material located in the channel hole according to the first embodiment of the present invention;

[0058] Figure 5b for Figure 5a A cross-sectional view along the middle Y1-Y1;

[0059] Figure 6a This is a schematic diagram of the channel structure formed in the first embodiment of the present invention;

[0060] Figure 6b for Figure 6a A cross-sectional view along the middle Y1-Y1;

[0061] Figure 7a This is a schematic diagram of the top selection grid slot structure formed in the first embodiment of the present invention;

[0062] Figure 7b for Figure 7a A sectional view along line C1-C1;

[0063] Figure 7c for Figure 7a A sectional view along line C2-C2;

[0064] Figure 7d for Figure 7a A sectional view along line C3-C3;

[0065] Figure 7e for Figure 7a A sectional view along line C4-C4;

[0066] Figure 8a This is a schematic diagram of the structure for removing sacrificial material from the first pseudo-channel hole according to the first embodiment of the present invention;

[0067] Figure 8b for Figure 8a A sectional view along line C1-C1;

[0068] Figure 8c for Figure 8a A sectional view along line C2-C2;

[0069] Figure 8d for Figure 8a A sectional view along line C3-C3;

[0070] Figure 8e for Figure 8a A sectional view along line C4-C4;

[0071] Figure 9a This is a schematic diagram of the structure for removing sacrificial material from the first pseudo-channel hole according to the first embodiment of the present invention;

[0072] Figure 9b for Figure 9a A sectional view along line C1-C1;

[0073] Figure 9c for Figure 9a A sectional view along line C2-C2;

[0074] Figure 9d for Figure 9a A sectional view along line C3-C3;

[0075] Figure 9e for Figure 9a A sectional view along line C4-C4;

[0076] Figure 10a This is a schematic diagram of the structure for forming the gate layer in the first embodiment of the present invention;

[0077] Figure 10b for Figure 10a A sectional view along line C1-C1;

[0078] Figure 10c for Figure 10a A sectional view along line C2-C2;

[0079] Figure 10d for Figure 10a A sectional view along line C3-C3;

[0080] Figure 10e for Figure 10a A sectional view along line C4-C4;

[0081] Figure 11a This is a schematic diagram of the structure of the semiconductor device formed according to the first embodiment of the present invention;

[0082] Figure 11b for Figure 11a A sectional view along line C1-C1;

[0083] Figure 11c for Figure 11a A sectional view along line C2-C2;

[0084] Figure 11d for Figure 11a A sectional view along line C3-C3;

[0085] Figure 11e for Figure 11a A sectional view along line C4-C4;

[0086] Figure 11f for Figure 11a A sectional view along line C5-C5;

[0087] Figure 11g for Figure 11a A sectional view along line C6-C6;

[0088] Figure 12a This is a schematic diagram of the structure for forming the second row of pseudo-channel holes according to the second embodiment of the present invention;

[0089] Figure 13a This is a schematic diagram of the structure of a semiconductor device formed according to the second embodiment of the present invention;

[0090] Figure 13b for Figure 13aA sectional view along line C5-C5;

[0091] Figure 13c for Figure 13a A sectional view along line C6-C6;

[0092] Figure 14 This is a schematic block diagram of a storage system in some embodiments of the present invention. Detailed Implementation

[0093] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0094] It should be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the invention.

[0095] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be an inserted component. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0096] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (where contacts, interconnects, and one or more dielectric layers are formed).

[0097] As used herein, the term "semiconductor device" refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate, such that the array structure extends in a vertical direction relative to the substrate; "vertical" means perpendicular to the direction of the substrate.

[0098] It should be noted that the illustrations provided in the embodiments of the present invention are only schematic representations of the basic concept of the present invention. Although the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the layout of the components may also be more complex.

[0099] Please see Figure 1 This is a schematic flowchart of the semiconductor device fabrication method provided in the first embodiment of the present invention. A detailed flowchart is provided below. Figures 2a to 11g The structural diagram may include the following:

[0100] Step S101: Provide a semiconductor structure (not labeled in the figure), the semiconductor structure includes a substrate 110, a stacked layer 120, a plurality of channel regions A1 disposed in the stacked layer 120, and a first row of pseudo-channel vias 130 located between two channel regions A1. The first row of pseudo-channel vias 130 includes a plurality of first pseudo-channel vias 131 arranged along a first direction (X direction). Each first pseudo-channel via 131 penetrates the stacked layer 120. The stacked layer 120 includes sacrificial layers 1211 and insulating layers 1212 that are alternately stacked.

[0101] Each channel region A1 includes multiple channel structures 141, which penetrate the stacked layer 120. A sacrificial material is disposed in the first dummy channel via 131. Step S101: The step of providing a semiconductor structure specifically includes:

[0102] Step S1011: Provide substrate 110;

[0103] Step S1012: A stacked layer 120 is formed on the substrate 110. The stacked layer 120 includes a sacrificial layer 1211 and an insulating layer 1212 that are alternately stacked.

[0104] Step S1013: A channel hole 140 and a first row of pseudo channel holes 130 are formed in the stacked layer 120. The channel hole 140 is located in a plurality of channel regions A1 of the stacked layer 120. The channel region A1 includes a plurality of channel holes 140. Each channel hole 140 penetrates the stacked layer 120. The first row of pseudo channel holes 130 includes first pseudo channel holes 131 arranged along a first direction (X direction). Each first pseudo channel hole 131 penetrates the stacked layer 120.

[0105] Step S1014: Fill sacrificial material into the channel hole 140 and the first row of pseudo-channel holes 130 respectively;

[0106] Step S1015: A shielding layer 150 is formed above the first row of pseudo-channel holes 130. The shielding layer 150 covers the first row of pseudo-channel holes 130, and the projections of the shielding layer 150 and the channel holes 140 on the substrate 110 do not overlap.

[0107] Step S1016: Remove the sacrificial material located in the channel hole 140;

[0108] Step S1017: Remove the masking layer 150;

[0109] Step S1018: Fill the channel hole 140 to form the channel structure 141.

[0110] In addition, it should be noted that, Figures 2a to 11g Only structures relevant to the embodiments of the present invention are shown. The semiconductor device of the present invention may further include other components and / or structures for realizing the full functionality of the device.

[0111] Figure 2a and Figure 2b The structure formed in steps S1011 to S1013 includes: a substrate 110, a stacked layer 120 disposed in the longitudinal direction (Z direction), a plurality of channel regions A1 disposed in the stacked layer 120, and a first row of pseudo-channel vias 130 located between two channel regions A1. The channel region A1 includes a plurality of channel vias 140, each channel via 140 penetrating the stacked layer 120. The first row of pseudo-channel vias 130 includes first pseudo-channel vias 131 arranged along a first direction (X direction), each first pseudo-channel via 131 penetrating the stacked layer 120.

[0112] Specifically, the substrate 110, as the basis for forming the semiconductor device, can be a film layer of any semiconductor material, such as silicon (Si), germanium (Ge), SiGe substrate, silicon on insulator (SOI), or germanium on insulator (GOI). In other embodiments, the semiconductor substrate can also be a semiconductor layer, or a substrate including other elemental semiconductors or compound semiconductors, and can also be a stacked structure, such as Si / SiGe.

[0113] Specifically, Figure 2a and Figure 2bThe specific formation process of the structure shown can be as follows: After providing the substrate 110, firstly, a stacked layer 120 can be formed on the substrate 110 using a deposition process. The stacked layer 120 includes alternately stacked sacrificial layers 1211 and insulating layers 1212. The number of sacrificial layers 1211 and insulating layers 1212 is controllable, for example, by adjusting the parameters of the deposition process to form the required number of sacrificial layers 1211 and insulating layers 1212. The insulating layer 1212 is used to separate the multiple sacrificial layers 1211. The material of the insulating layer 1212 can be composed of oxides, such as silicon oxide (SiO2), while the material of the sacrificial layers 1211 can be composed of nitrides, such as silicon nitride (SiN). Then, the stacked layer 120, which is alternately stacked in a stepped manner, can be formed using photolithography, trimming, and etching processes. Finally, vias 140 and a first row of pseudo-channels 130 can be formed in the stacked layer 120 using an etching process, such as dry etching. The vias 140 are located in multiple channel regions A1 of the stacked layer 120, each channel region A1 containing multiple vias 140, and each via 140 penetrates the stacked layer 120. The first row of pseudo-channels 130 includes first pseudo-channels 131 arranged along a first direction (X direction), each first pseudo-channel 131 penetrating the stacked layer 120. The vias 140 and the first row of pseudo-channels 130 can be formed using the same process. The multiple vias 140 can be arranged in a matrix.

[0114] In addition, it should be noted that the via 140 can be a single-deck via, or a dual-deck via, which includes an upper via and a lower via, or a multideck via.

[0115] Figure 3a and Figure 3b The structure formed in step S1014 includes: a substrate 110, a stacked layer 120, multiple channel regions A1, and a first row of pseudo-channel vias 130 located between two channel regions A1. The channel vias 140 and the first row of pseudo-channel vias 130 are filled with sacrificial material.

[0116] Specifically, a sacrificial material can be filled into the channel via 140 and the first row of pseudo-channel vias 130 respectively through a deposition process to form the channel via 140 and the first row of pseudo-channel vias 130 filled with sacrificial material. The sacrificial material can be carbon or polysilicon, etc.

[0117] Figure 4a and Figure 4bThe structure formed in step S1015 includes: a substrate 110, a stacked layer 120, multiple channel regions A1, a first row of pseudo-channel vias 130 located between two channel regions A1, and a masking layer 150 located on the first row of pseudo-channel vias 130. The channel vias 140 and the first row of pseudo-channel vias 130 are filled with sacrificial material.

[0118] Specifically, a masking layer 150 can be formed above the first row of pseudo-channel holes 130 through a deposition process. The masking layer 150 covers the first row of pseudo-channel holes 130, and the projections of the masking layer 150 and the channel holes 140 on the substrate 110 do not overlap. That is, the masking layer 150 covers the first row of pseudo-channel holes 130 but does not cover the channel holes 140. The material of the masking layer 150 is different from the sacrificial material. The material of the masking layer 150 can be an oxide (SiO2) or a nitride (SiN), etc.

[0119] Figure 5a and Figure 5b The structure formed in step S1016 includes: a substrate 110, a stacked layer 120, multiple channel regions A1, a first row of pseudo-channel vias 130 located between two channel regions A1, and a masking layer 150 located on the first row of pseudo-channel vias 130. The first row of pseudo-channel vias 130 is filled with a sacrificial material.

[0120] Specifically, the sacrificial material in the via 140 can be removed using semiconductor processes. A masking layer 150 covers the first row of pseudo-channel vias 131. When removing the sacrificial material in the via 140, the sacrificial material in the first row of pseudo-channel vias 130 and the masking layer 150 above them are retained. For example, when the sacrificial material is carbon, it can be removed by ashing (also known as plasma dry resist removal), where the sacrificial material reacts with oxygen during the ashing process. Since the material of the masking layer 150 is different from the sacrificial material—for example, if the material of the masking layer 150 is an oxide or nitride—it is not removed by the ashing process and is retained. Correspondingly, the sacrificial material in the first row of pseudo-channel vias 130 covered by the masking layer 150 is also retained; that is, the first row of pseudo-channel vias 130 is filled with sacrificial material.

[0121] Furthermore, for example, when the sacrificial material is polysilicon, since the masking layer 150 is different from the sacrificial material, wet etching can be used. A suitable etching solution can be selected; for example, the etching solution can react with the polysilicon but hardly react with the material of the masking layer 150. This removes the sacrificial material located in the via 140, while retaining the sacrificial material in the masking layer 150 and the first pseudo-via 131 located below the masking layer 150. There are no particular restrictions on the process for removing the sacrificial material in the via 140, as long as it achieves the removal of the sacrificial material in the via 140 while retaining the sacrificial material in the masking layer 150 and the first pseudo-via 131 located below the masking layer 150.

[0122] Additionally, it should be noted that after removing the sacrificial material located in the channel hole 140, the shielding layer 150 located above the first row of pseudo channel holes 130 can be removed.

[0123] Figure 6a and Figure 6b The structure formed in steps S1017 to S1018 includes: a substrate 110, a stacked layer 120, multiple channel regions A1, and a first row of pseudo-channel vias 130 located between two channel regions A1. Each channel region A1 includes multiple channel structures 141, each channel structure 141 penetrating the stacked layer 120. The first row of pseudo-channel vias 130 includes first pseudo-channel vias 131 arranged along a first direction (X direction), each first pseudo-channel via 131 penetrating the stacked layer 120. The first row of pseudo-channel vias 130 is filled with sacrificial material. The multiple channel structures 141 may be arranged in a matrix.

[0124] Specifically, different materials can be deposited sequentially in the channel hole 140 through multiple deposition processes to form a blocking layer, a charge trapping layer, a tunneling layer, and a poly channel layer in the radial direction from the outside to the inside in the channel hole 140.

[0125] In general, in a three-dimensional memory, a barrier layer is used to block the movement of charge carriers (such as electrons or holes) between the charge trapping layer and the gate layer 1213 (WL). The barrier layer can be made of oxide. The charge trapping layer stores charge in the gate stack, thereby changing the device threshold voltage and distinguishing between the erase and programmed states of the device. The charge trapping layer can be made of nitride (Si3N4). The tunneling layer provides a film layer that enables tunneling for tunneling programming and tunneling erasure. The tunneling layer can be made of oxide. The channel layer provides a path for the movement of charge carriers between the substrate 110 and the tunneling layer. Therefore, the channel layer needs to be made of a conductive material, such as polysilicon.

[0126] Step S102: A first pseudo-channel groove 160 is formed in the stacked layer 120, and the first pseudo-channel groove 160 connects to a plurality of first pseudo-channel holes 131 of the first row of pseudo-channel holes 130.

[0127] The first pseudo-channel groove 160 includes a plurality of sub-pseudo-channel grooves 161 spaced apart along a first direction (X direction). Before step S102: forming the first pseudo-channel groove 160 in the stacked layer 120, the method further includes:

[0128] A top-select gate slot structure 170 is formed in the stacked layer 120. The top-select gate slot structure 170 passes through at least one sacrificial layer 1211 and an insulating layer 1212. Multiple sub-pseudo-channel slots 161 are connected through the top-select gate slot structure 170.

[0129] Figure 7a and Figure 7e The structure forming the top selected gate slot structure 170 includes: a substrate 110, a stacked layer 120, a plurality of channel regions A1, a first row of pseudo-channel vias 130 located between two channel regions A1, and the top selected gate slot structure 170 located in the stacked layer 120. Each channel region A1 includes a plurality of channel structures 141, each channel structure 141 penetrating the stacked layer 120. The first row of pseudo-channel vias 130 includes first pseudo-channel vias 131 arranged along a first direction (X direction), each first pseudo-channel via 131 penetrating the stacked layer 120. The first row of pseudo-channel vias 130 is filled with sacrificial material.

[0130] Specifically, after completing steps S1011 to S1018, the following is formed: Figure 6a and Figure 6bFollowing the semiconductor structure shown, a top select gate (TSG) cut can be formed in the stacked layer 120 using an etching process, such as dry etching. The stacked layer 120 includes a top select gate (TSG) layer, which can serve as a gate transistor controlling whether a data storage string is on. Typically, a top select gate (TSG) cut is formed in the top select gate to divide the top select gate stack into two parts. After forming the top select gate cut, it can be filled to form the top select gate cut structure 170. That is, the formation process of the top select gate slot structure 170 includes: first, forming a top select gate slot (not shown in the figure) in the stacked layer, wherein the top select gate slot may include a plurality of sub-top select gate slots (not shown in the figure) spaced apart along the X direction, each sub-top select gate slot passing through at least one sacrificial layer 1211 and insulating layer 1212 in the Z direction; then, filling each sub-top select gate slot to finally form the top select gate slot structure 170, wherein the top select gate slot structure 170 includes a plurality of sub-top select gate slot structures 171 spaced apart along the X direction. The material of the top select gate slot structure 170 can be an oxide, such as silicon oxide. To divide the top select gate stack into several parts through the top select gate slot structure 170, the top select gate slot structure 170 passes through at least one sacrificial layer 1211 and insulating layer 1212. The depth of the top select gate slot structure 170 in the Z direction is H1. The top selection gate slot structure 170 includes a plurality of sub-top selection gate slot structures 171 arranged along a first direction, which connect to a plurality of sub-pseudo-channel slot structures 162. The depth of the first pseudo-channel slot structure 163 in a third direction is greater than or equal to the depth of the top selection gate slot structure 170 in a third direction, where the third direction is parallel to the stacking direction of the stacked structure.

[0131] Figure 8a and Figure 8eThe structure of the first pseudo-channel groove 160 formed in step S102 includes: a substrate 110, a stacked layer 120, multiple channel regions A1, a first row of pseudo-channel vias 130 located between two channel regions A1, a top selection gate groove structure 170 located in the stacked layer 120, and the first pseudo-channel groove 160. Each channel region A1 includes multiple channel structures 141, each channel structure 141 penetrating the stacked layer 120. The first row of pseudo-channel vias 130 includes first pseudo-channel vias 131 arranged along a first direction (X direction), each first pseudo-channel via 131 penetrating the stacked layer 120. The first row of pseudo-channel vias 130 is filled with sacrificial material. The first pseudo-channel groove 160 extends along a direction and connects to the multiple first pseudo-channel vias 131 below the first row of pseudo-channel vias 130. A first pseudo-channel groove 160 can be formed in the stacked layer 120 by an etching process. The first pseudo-channel groove 160 extends along the direction and connects to a plurality of first pseudo-channel holes 131 below the first row of pseudo-channel holes 130. The depth of the first pseudo-channel groove 160 in the Z direction is H2.

[0132] The first pseudo-channel groove 160 includes a plurality of sub-pseudo-channel grooves 161 spaced apart along a first direction (X direction), and the plurality of sub-pseudo-channel grooves 161 are connected by a top selection grid groove structure 170.

[0133] Specifically, in related technologies, a three-dimensional memory forms a stacked layer 120 by alternately stacking sacrificial layers 1211 and insulating layers 1212. Generally, the stacked layer 120 is divided into multiple memory blocks by gate line slits in the stacked layer 120. The gate line slits are also used for subsequent replacement of the sacrificial layers 1211 in the stacked layer 120 with gate layers 1213. To prevent the stacked layer 120 from collapsing when the sacrificial layers 1211 are subsequently replaced with gate layers 1213, one or more secondary gate line slits can be formed within the memory blocks to strengthen the device structure. To ensure that the gate layers 1213 located within the same memory block are electrically connected at the notch, the secondary gate line slits within the same memory block can be disconnected in a predetermined region to form a notch (H-Cut). For example, the secondary gate line slits may include multiple disconnected sub-gate line slits.

[0134] Based on this, in this embodiment of the invention, a first pseudo-channel slot 160 and a first row of pseudo-channel vias 130 are formed to replace the secondary gate line gaps in the related art. To enable the gate layers 1213 located in the same memory region to be electrically connected at the notch, the first pseudo-channel slot 160 includes a plurality of sub-pseudo-channel slots 161 spaced apart along a first direction (X direction), and the plurality of sub-pseudo-channel slots 161 are connected by a top selected gate slot structure 170. By using the plurality of sub-pseudo-channel slots 161 spaced apart along the first direction (X direction), the structure of the device is strengthened while the gate layers 1213 located in the same memory region are electrically connected at the notch. Simultaneously, multiple sub-pseudo-channel slots 161 are connected through the top selection gate slot structure 170, meaning the top selection gate slot structure 170 and the multiple sub-pseudo-channel slots 161 are in communication, or the projections of the top selection gate slot structure 170 and the multiple sub-pseudo-channel slots 161 on the substrate 110 at least partially overlap, so that the top selection gate is divided into two parts by connecting the multiple sub-pseudo-channel slots 161 through the top selection gate slot structure 170. To ensure that the top selection gate slot structure 170 and the first pseudo-channel slot 160 work together to divide the top selection gate stack into two parts, the depth H2 of the first pseudo-channel slot 160 is greater than or equal to the depth H1 of the top selection gate slot structure 170.

[0135] Step S103: Replace the sacrificial layer 1211 with the gate layer 1213 through the first pseudo-channel via 131 and the first pseudo-channel slot 160 to form a stacked structure 121, the stacked structure 121 including alternately stacked gate layers 1213 and insulating layers 1212.

[0136] Step S103 involves replacing the sacrificial layer with a gate layer through the first pseudo-channel via 131 and the first pseudo-channel slot to form a stacked structure. Specifically, this includes:

[0137] Step S1031: Remove the sacrificial material located in the first pseudo-channel hole 131;

[0138] Step S1032: Remove the sacrificial layer 1211 and form a gate layer 1213 at the location of the sacrificial layer 1211 to form a stacked structure 121, the stacked structure 121 including alternatingly stacked gate layers 1213 and insulating layers 1212.

[0139] Figure 9a and Figure 9eThe structure formed in step S1031 includes: a substrate 110, a stacked layer 120, multiple channel regions A1, a first row of dummy channel vias 130 located between two channel regions A1, a first dummy channel groove 160 located in the stacked layer 120, and a top select gate groove structure 170 located in the stacked layer 120. The sacrificial material in the first row of dummy channel vias 130 can be removed by semiconductor processes, for example, by ashing or wet etching, to remove the sacrificial material in each of the first dummy channel vias 131 in the first row of dummy channel vias 130.

[0140] Figure 10a and Figure 10e The structure formed in step S1032 includes: a substrate 110, a stacked structure 121, a plurality of channel regions A1, a first row of pseudo-channel vias 130 located between two channel regions A1, a first pseudo-channel groove 160 located in the stacked layer 120, and a top selection gate groove structure 170 located in the stacked layer 120. The first pseudo-channel groove 160 connects to a plurality of first pseudo-channel vias 131 of the first row of pseudo-channel vias 130. The channel region A1 includes a plurality of channel structures 141, each channel structure 141 penetrating the stacked layer 120. The first row of pseudo-channel vias 130 includes first pseudo-channel vias 131 arranged along a first direction (X direction), each first pseudo-channel via 131 penetrating the stacked layer 120. The sacrificial layer 1211 can be removed by wet etching, and then a gate layer 1213 can be formed on the site of the sacrificial layer 1211 by deposition process to form a stacked structure 121. The stacked structure 121 includes alternating layers of gate layer 1213 and insulating layer 1212. The gate layer 1213 is made of a conductive material, such as tungsten (W) or polysilicon.

[0141] Step S104: Fill the first row of pseudo-channel holes 130 and the first pseudo-channel groove 160 respectively to form the first row of pseudo-channel structure 132 and the first pseudo-channel groove structure 163 respectively.

[0142] The semiconductor device includes a plurality of first row pseudo-channel structures 132, which are distributed along a second direction (Y direction). The second direction is perpendicular to the stacking direction of the stacked structure 121 and is perpendicular to the first direction. The first pseudo-channel structures 133 extend into the substrate 110. The first pseudo-channel grooving structure 163 passes through at least one gate layer 1213 and an insulating layer 1212. The first pseudo-channel grooving structure 163 includes a plurality of sub-pseudo-channel grooving structures 162 spaced apart along the first direction.

[0143] Figures 11a to 11fThe structure formed in step S104 includes: a substrate 110, a stacked structure 121, multiple channel regions A1, a first row of pseudo-channel structures 132 located between two channel regions A1, a top selected gate cutout structure 170, the first row of pseudo-channel structures 132 connecting multiple first pseudo-channel structures 133 of the first row of pseudo-channel holes 130, the channel region A1 including multiple channel structures 141, each channel structure 141 penetrating the stacked layer 120, the first row of pseudo-channel structures 132 including first pseudo-channel structures 133 arranged along a first direction (X direction), each first pseudo-channel structure 133 penetrating the stacked structure 121.

[0144] Specifically, the first row of pseudo-channel holes 130 and the first pseudo-channel grooves 160 are filled respectively to form the first row of pseudo-channel structures 132 and the first row of pseudo-channel groove structures 163. The materials for the first row of pseudo-channel groove structures 163 and the first row of pseudo-channel structures 132 can be dielectric layers, such as oxides or nitrides. The first row of pseudo-channel structures 132 and the first row of pseudo-channel groove structures 163 can be formed in the same process to further reduce process steps and production costs.

[0145] Specifically, in related technologies, a three-dimensional memory forms a stacked structure 121 by alternately stacking gate layers 1213 and insulating layers 1212. Generally, the stacked structure 121 is divided into multiple memory regions by gate line slots located within it. Gate line slots within the same memory region can be broken in a predetermined area to form a notch (H-Cut), allowing the gate layers 1213 within the same memory region to be electrically connected at the notch. As the number of layers in the stacked structure 121 increases, the width of the gate line slots in the Y direction increases, resulting in a larger size of the device's memory region in the Y direction, thus reducing the device's integration density. Simultaneously, when forming secondary gate line slots within the same memory region, the broken areas affect polymer accumulation at the top during etching, resulting in a "big head" profile at the top of the formed secondary gate line slot and a sharp angle profile at the bottom. When the top of a subgate line slot within the same memory region forms a large-headed shape, it is prone to connecting with adjacent channel structures (CH), resulting in slow programming speed (SLPM) and thus affecting the device's electrical performance. Conversely, when the bottom of a subgate line slot within the same memory region forms a sharp-angled shape, residues at the bottom, such as tungsten (W), may not be completely removed, leading to tungsten residue and leakage problems, which in turn affect the device's electrical performance.

[0146] Additionally, gate line slots located within the same storage region must either penetrate the stacked structure 121 at least, or penetrate the stacked structure 121 and extend into the substrate 110. As the number of layers in the stacked structure 121 increases, the gate line slots need to penetrate deeper into the stacked structure 121. Correspondingly, the width of the gate line slots in the Y direction needs to be wider to ensure that the depth of the gate line slots is at least through the stacked structure 121, or through the stacked structure 121 and extend into the substrate 110.

[0147] In this embodiment of the invention, by forming a first row of pseudo-channel holes 130 and forming a first pseudo-channel slot 160 on the first row of pseudo-channel holes 130 to replace the gate line gaps located in the same storage area, on the one hand, the structure of the stacked layer 120 can be strengthened by forming multiple first pseudo-channel holes 131; on the other hand, the first pseudo-channel slot 160 only penetrates a portion of the stacked structure 121, and its depth in the Z direction is much smaller than the depth of the gate line gaps. When forming a first pseudo-channel slot 160 with a smaller depth in the Z direction, the width of the first pseudo-channel slot 160 in the Y direction can be made narrower. To a certain extent, the width of the first pseudo-channel slot 160 in the Y direction can be reduced, thereby reducing the size of the device's storage area in the Y direction and increasing the device's storage density.

[0148] Furthermore, by forming a first pseudo-channel groove 160 with a shallow depth in the Z-direction and multiple first pseudo-channel holes 131, it is not necessary to form a fracture with a large depth in the Z-direction. This avoids the formation of a big-head profile at the top and a sharp angle at the bottom in the fracture area, thus improving the electrical performance of the device. At the same time, by forming a first pseudo-channel groove 160 with a shallow depth in the Z-direction and multiple first pseudo-channel holes 131, weak points at the notch (H-Cut) are eliminated, and the structure of the device is strengthened. This expands the process window for forming gate line gaps located in the same memory area, thereby improving the device yield.

[0149] In general, the vias 140 located near the grid line slots within the same storage area are referred to as external vias, while those located further away are referred to as internal vias. External vias, being closer to the grid line slots, typically have more open areas, while internal vias, being further away, are more densely packed and have less open area. This difference in open area affects the distribution of the polymer etched to form the external and internal vias, leading to differences in their etching processes. To compensate for these differences, the diameter of external vias generally needs to be larger than that of internal vias to ensure that their depths correspond. By forming a first row of pseudo-channel holes 130 and a first pseudo-channel groove 160, the channel holes 140 near the first row of pseudo-channel holes 130 and the channel holes 140 far from the first row of pseudo-channel holes 130 are arranged in a rectangular array, eliminating the distinction between outer and inner rows of holes. This further reduces the diameter of the channel holes 140 near the first row of pseudo-channel holes 130, reduces the load of outer and inner rows of holes in the channel holes 140, and further improves the storage density of the device.

[0150] Based on the above description, in this embodiment of the invention, by forming a first row of pseudo-channel holes 130 and a first pseudo-channel slot 160 to replace the secondary gate line gaps located in the same storage area in related technologies, the storage density, yield and reliability of the device are improved.

[0151] In step S101, after providing the semiconductor structure, the following is also included:

[0152] A gate line slot 180 is formed in the stacked layer 120. The gate line slot 180 extends along a first direction (X direction), penetrates the stacked layer 120 and extends into the substrate 110, so as to divide the stacked layer 120 into several parts.

[0153] Fill the grid line gaps 180 to form grid line gap structure 181.

[0154] The first pseudo-channel groove 160 and the grid line gap 180 are formed in the same process.

[0155] Please see Figure 8a and Figure 8bFurthermore, gate line slots 180 can be formed in the stacked layer 120, extending along a first direction (X direction), penetrating the stacked layer 120 and extending into the substrate 110 to divide the stacked layer 120 into several parts. After forming the gate line slots 180, a deposition process can be used to fill the gate line slots 180 to form a gate line slot structure 181. In some embodiments, a dielectric layer and a conductive layer can be sequentially filled into the inner wall of the gate line slots 180, with the conductive layer extending into the substrate 110 and communicating with the common source electrode in the substrate 110. In this case, the gate line slot structure 181 can communicate with the common source electrode in the substrate 110. The dielectric layer can be made of oxides, such as silicon oxide or aluminum oxide, and the conductive layer can be made of tungsten or polysilicon. The first pseudo-channel groove 160 is formed in the same process as the gate line slots 180, so as to achieve the purpose of forming the gate line slots 180 without increasing the cost.

[0156] The first pseudo-channel slot structure 163 and the grid line slot structure 181 are formed in the same process.

[0157] A dielectric layer can be filled into the gate line slot 180 to form a gate line slot structure 181. When the material of the gate line slot structure 181 is the same as the material of the first pseudo-channel structure 133, the first pseudo-channel groove structure 163 and the gate line slot structure 181 are formed in the same process, so as to reduce both process steps and costs.

[0158] In a second embodiment of the present invention, the step of providing the semiconductor structure further includes forming a second row of dummy channel vias 190, the second row of dummy channel vias 190 being located outside at least two channel regions A1 and including a plurality of second dummy channel vias 191 arranged along a first direction (X direction), each second dummy channel via 191 penetrating the stacked layer 120. After providing the semiconductor structure, the method further includes:

[0159] A second pseudo-channel groove (not shown in the figure) is formed in the stacked layer 120, the second pseudo-channel groove penetrates the stacked layer 120 and the second row of pseudo-channel holes 190 and extends into the substrate 110 to divide the stacked layer 120 into several parts;

[0160] The second row of pseudo-channel holes 190 and the second pseudo-channel groove are filled respectively to form the second row of pseudo-channel structure 194 and the second pseudo-channel groove structure 193 respectively.

[0161] Figure 12aThe structure of forming a second row of pseudo-channel vias 190 according to a second embodiment of the present invention includes: a substrate 110, a stacked layer 120 disposed in the longitudinal direction (Z direction), a plurality of channel regions A1 disposed in the stacked layer 120, a first row of pseudo-channel vias 130 located between two channel regions A1, and a second row of pseudo-channel vias 190 located outside at least two channel regions A1. The channel region A1 includes a plurality of channel vias 140, each channel via 140 penetrating the stacked layer 120. The first row of pseudo-channel vias 130 includes first pseudo-channel vias 131 arranged along a first direction (X direction), each first pseudo-channel via 131 penetrating the stacked layer 120. The second row of pseudo-channel vias 190 includes second pseudo-channel vias 191 arranged along the first direction (X direction), each second pseudo-channel via 191 penetrating the stacked layer 120. In the process of forming the first row of pseudo-channel holes 130, a second row of pseudo-channel holes 190 can be formed in the stacked layer 120. The second row of pseudo-channel holes 190 is located outside at least two channel regions A1 and includes a plurality of second pseudo-channel holes 191 arranged along the first direction (X direction), each second pseudo-channel hole 191 penetrating the stacked layer 120.

[0162] Figures 13a to 13c The structure forming the second row of pseudo-channel structures 194 includes: a substrate 110, a stacked structure 121 disposed in the longitudinal direction (Z direction), a plurality of channel regions A1 disposed in the stacked structure 121, a first row of pseudo-channel structures 132 located between two channel regions A1, and a second row of pseudo-channel structures 194 located outside at least two channel regions A1. The channel regions A1 include a plurality of channel structures 141, each channel structure 141 penetrating the stacked structure 121. The first row of pseudo-channel structures 132 includes first pseudo-channel structures 133 arranged along a first direction (X direction), each first pseudo-channel structure 133 penetrating the stacked structure 121. The second row of pseudo-channel structures 194 includes second pseudo-channel structures 192 arranged along the first direction (X direction), each second pseudo-channel structure 192 penetrating the stacked structure 121.

[0163] Specifically, similar to the method for forming the first pseudo-channel groove 160, after forming the second row of pseudo-channel vias 190, a second pseudo-channel groove (not shown in the figure) can be formed in the stacked layer 120. The second pseudo-channel groove penetrates the stacked layer 120 and the second row of pseudo-channel vias 190 and extends into the substrate 110 to divide the stacked layer 120 into several portions. Then, the second row of pseudo-channel vias 190 and the second pseudo-channel groove are filled respectively to form the second row of pseudo-channel structures 194 and the second pseudo-channel groove structure 193. The first pseudo-channel groove 160 and the second pseudo-channel groove are formed in the same process. Furthermore, before forming the first row of pseudo-channel structures 132 and the second row of pseudo-channel structures 194, the sacrificial layer 1211 in the stacked layer 120 is replaced with the gate layer 1213 by means of the first pseudo-channel slot 160, the first row of pseudo-channel holes 130, the second pseudo-channel slot and the second row of pseudo-channel holes 190, so as to form the stacked structure 121.

[0164] In addition, it should be noted that, Figure 12a , Figures 13a to 13c Only structures relevant to the embodiments of the present invention are shown. The semiconductor device of the present invention may further include other components and / or structures for realizing the full functionality of the device.

[0165] The first pseudo-groove cutting structure 163 and the second pseudo-groove cutting structure 193 are formed under the same process.

[0166] Specifically, after forming the first pseudo-channel groove 160 and the second pseudo-channel groove, a deposition process can be used to fill the first pseudo-channel groove 160 and the second pseudo-channel groove, respectively, to form the first pseudo-channel groove structure 163 and the second pseudo-channel groove structure 193. That is, the first pseudo-channel groove structure 163 and the second pseudo-channel groove structure 193 are formed under the same process, so as to reduce process steps and production costs.

[0167] Specifically, as described above, in related technologies, a three-dimensional memory forms a stacked structure 121 by alternately stacking gate layers 1213 and insulating layers 1212. Generally, the stacked structure 121 is divided into multiple memory regions by gate line gaps 180 located within it. As the number of layers in the stacked structure 121 increases, the width of the gate line gaps 180 in the Y direction increases, resulting in larger dimensions of the memory cells in the Y direction and a decrease in the device's integration density. In the second embodiment of the present invention, the gate line slots 180 used to divide the stacked structure 121 into multiple memory areas are replaced by forming a second row of pseudo-channel holes 190 and a second pseudo-channel groove. By forming the second pseudo-channel groove on the already formed second row of pseudo-channel holes 190, less stacked layer 120 needs to be removed when forming the second pseudo-channel groove. To a certain extent, this can improve the problem in the related technology that a larger depth of etching the gate line slots 180 requires more width to ensure a certain depth, thereby reducing the width of the second pseudo-channel groove in the Y direction and improving the storage density, yield and reliability of the device.

[0168] Based on the semiconductor device fabrication method of the above-described embodiments of the present invention, the present invention also provides a semiconductor device, comprising: a stacked structure 121, the stacked structure 121 including alternatingly stacked gate layers 1213 and insulating layers 1212; a plurality of channel regions A1 disposed in the stacked structure 121, each channel region A1 including a plurality of channel structures 141, the channel structures 141 penetrating the stacked structure 121; a first row of pseudo-channel structures 132, the first row of pseudo-channel structures 132 being located between two channel regions A1, and including a plurality of first pseudo-channel structures 133 arranged along a first direction (X direction), each first pseudo-channel structure 133 penetrating the stacked structure 121, the first direction (X direction) being a stacking direction perpendicular to the stacked structure 121; and a first pseudo-channel notch structure 163, the first pseudo-channel notch structure 163 being located in the stacked structure 121 and connecting the plurality of first pseudo-channel structures 133 of the first row of pseudo-channel structures 132.

[0169] Based on the above description, in this embodiment of the invention, by forming a first row of pseudo-channel holes 130 and a first pseudo-channel slot 160 to replace the gate line gaps located in the same storage area in related technologies, the storage density, yield and reliability of the device are improved.

[0170] The first pseudo-channel groove structure 163 includes a plurality of sub-pseudo-channel groove structures 162 that are spaced apart along the first direction (X direction).

[0171] The first pseudo-channel slot structure 163 passes through at least one gate layer 1213 and insulating layer 1212.

[0172] The semiconductor device includes a plurality of first row pseudo-channel structures 132, which are distributed along a second direction (Y direction). The second direction is perpendicular to the stacking direction of the stacked structure 121 and is perpendicular to the first direction.

[0173] The first pseudo-channel groove structure 163 includes a plurality of sub-pseudo-channel groove structures 162 spaced apart along a first direction (X direction). The semiconductor device also includes:

[0174] A top-select gate slot structure 170 is located in the stacked structure 121, passing through at least one gate layer 1213 and insulating layer 1212, and connecting multiple sub-pseudo-channel slot structures 161.

[0175] The top selection gate slot structure 170 includes a plurality of sub-top selection gate slot structures 171 arranged along a first direction, which connect to a plurality of sub-pseudo-channel slot structures 162. The depth of the first pseudo-channel slot structure 163 in a third direction is greater than or equal to the depth of the top selection gate slot structure 170 in a third direction, where the third direction is parallel to the stacking direction of the stacked structure.

[0176] Semiconductor devices also include:

[0177] Substrate 110 is located on the side of stacked structure 121 away from the first pseudo-channel groove structure 163;

[0178] The gate line slot structure 181 extends along a first direction (X direction), penetrates the stacked structure 121 and extends into the substrate 110, so as to divide the stacked structure 121 into several parts.

[0179] The first pseudo-channel structure 133 extends into the substrate 110.

[0180] In the first embodiment of the present invention, by forming a first row of pseudo-channel vias 130 and a first pseudo-channel slot 160 to replace the gate line gaps located in the same memory region in related technologies, the storage density, yield, and reliability of the device are improved. Simultaneously, during the process of forming the first pseudo-channel slot 160, a gate line gap 180 is formed. This gate line gap 180 allows the sacrificial layer 1211 in the stacked layer 120 to be replaced with the gate layer 1213, thereby forming the stacked structure 121.

[0181] It should be understood that the structure and fabrication process of each component of the semiconductor device in the embodiments of the present invention can be referred to the above-described embodiments of the semiconductor device fabrication method, and will not be repeated here.

[0182] In a second embodiment of the present invention, the semiconductor device further includes:

[0183] Substrate 110 is located on the side of stacked structure 121 away from the first pseudo-channel groove structure 163;

[0184] The second row of pseudo-channel structures 194 is located outside at least two channel regions A1 and includes a plurality of second pseudo-channel structures 192 arranged along a first direction (X direction), each second pseudo-channel structure 192 penetrating the stacked structure 121.

[0185] The second pseudo-channel groove structure 193 penetrates the stacked structure 121 and the second pseudo-channel structure 192 and extends into the substrate 110 to divide the stacked structure 121 into several parts (e.g., into multiple blocks).

[0186] In the second embodiment of the present invention, the gate line slots used to divide the stacked structure 121 into multiple memory areas (i.e., into multiple blocks) are replaced by forming a second row of pseudo-channel structures 194 and a second pseudo-channel groove structure 193. By forming the second pseudo-channel groove on the already formed second row of pseudo-channel holes 190, less stacked structure 121 needs to be removed when forming the second pseudo-channel groove structure 193. To a certain extent, this can improve the problem in the related technology that a larger depth of etched gate line slots requires more width to ensure a certain depth, thereby reducing the width of the second pseudo-channel groove structure 193 in the Y direction and improving the storage density, yield and reliability of the device.

[0187] It should be understood that the structure and fabrication process of each component of the semiconductor device in the embodiments of the present invention can be referred to the above-described embodiments of the semiconductor device fabrication method, and will not be repeated here. It should be understood that the further limiting conditions of each structure in the first embodiment of the present invention described above can be applied to the second embodiment of the present invention to further improve the storage density, yield and reliability of the device. For details, please refer to the description in the first embodiment of the present invention, and will not be repeated here.

[0188] Based on the above-described semiconductor devices and their fabrication methods, embodiments of the present invention also provide a three-dimensional memory, which includes an array storage structure and peripheral circuitry, wherein the array storage structure includes any of the semiconductor devices described above.

[0189] Specifically, the 3D NAND Flash memory includes an array memory structure and peripheral circuitry, with the aforementioned semiconductor device located within the array memory structure. The array memory structure stores information, while the peripheral circuitry can be located above, below, or around the array memory structure, and is used to control the corresponding array memory structure. Furthermore, this semiconductor device can also be applied to other microelectronic devices, such as non-volatile flash memory (Nor Flash), without specific limitations. Moreover, the semiconductor device in this embodiment of the invention can be a 3D memory or a part of a peripheral memory, without particular limitation.

[0190] Based on the above-described semiconductor devices and their fabrication methods, embodiments of the present invention also provide a storage system, including a controller and a three-dimensional memory, wherein the controller is coupled to the three-dimensional memory and is used to control the three-dimensional memory to store data, and the three-dimensional memory includes any of the semiconductor devices described above.

[0191] Specifically, such as Figure 14 As shown, the storage system 300 includes a controller 310 and one or more three-dimensional memories 320, wherein each three-dimensional memory 320 includes one or more array storage structures 321 and peripheral circuitry 322. The storage system 300 can communicate with the host 400 via the controller 310, wherein the controller 310 can be connected to one or more three-dimensional memories 320 via channels in the three-dimensional memories 320. Each three-dimensional memory 320 can be managed by the controller 310 via channels in the three-dimensional memory 320.

[0192] Based on the above description, embodiments of the present invention disclose a semiconductor device, its fabrication method, and a memory system. The semiconductor device includes: a stacked structure comprising alternating gate layers and insulating layers; multiple channel regions disposed in the stacked structure, each channel region including multiple channel structures penetrating the stacked structure; a first row of pseudo-channel structures located between two channel regions and including multiple first pseudo-channel structures arranged along a first direction, each first pseudo-channel structure penetrating the stacked structure, the first direction being a stacking direction perpendicular to the stacked structure; and a first pseudo-channel notch structure located in the stacked structure and connecting the multiple first pseudo-channel structures of the first row of pseudo-channel structures. The semiconductor device of the present invention improves the storage density, yield, and reliability of the device.

[0193] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of the present invention; those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that, include: A stacked structure, the stacked structure comprising alternating layers of gate layers and insulating layers; Multiple channel regions are disposed in the stacked structure, each channel region includes multiple channel structures, and the channel structures penetrate the stacked structure; The first row of pseudo-channel structures is located between the two channel regions and includes a plurality of first pseudo-channel structures arranged along a first direction. Each first pseudo-channel structure penetrates the stacked structure, and the first direction is the stacking direction perpendicular to the stacked structure. The first pseudo-channel groove structure is located in the stacked structure and is connected to the plurality of first pseudo-channel structures of the first row of pseudo-channel structures. The first pseudo-channel groove structure includes a plurality of sub-pseudo-channel groove structures spaced apart along a first direction.

2. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor device includes a plurality of first pseudo-channel structures, which are distributed along a second direction, the second direction being perpendicular to the stacking direction of the stacked structure and perpendicular to the first direction.

3. The semiconductor device as described in claim 1, characterized in that, The semiconductor device further includes: A substrate, wherein the substrate is located on the side of the stacked structure away from the first pseudo-channel groove structure; The first pseudo-channel structure extends into the substrate.

4. The semiconductor device as claimed in claim 1, characterized in that, The first pseudo-channel slot structure passes through at least one layer of the gate layer and the insulating layer.

5. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor device further includes: A top-select gate slot structure is located in the stacked structure, passes through at least one gate layer and the insulating layer, and connects the plurality of sub-pseudo-channel slot structures.

6. The semiconductor device as claimed in claim 5, characterized in that, The depth of the first pseudo-channel slot structure in the third direction is greater than or equal to the depth of the top selected gate slot structure in the third direction, wherein the third direction is the stacking direction parallel to the stacked structure.

7. The semiconductor device as claimed in claim 5, characterized in that, The top selection gate slot structure includes a plurality of sub-top selection gate slot structures arranged along the first direction, and the plurality of sub-pseudo-channel slot structures are connected through the plurality of sub-top selection gate slot structures.

8. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor device further includes: A substrate, wherein the substrate is located on the side of the stacked structure away from the first pseudo-channel groove structure; A gate line slot structure extends along the first direction, penetrates the stacked structure and extends into the substrate, thereby dividing the stacked structure into several parts.

9. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor device further includes: A substrate, wherein the substrate is located on the side of the stacked structure away from the first pseudo-channel groove structure; The second row of pseudo-channel structures is located outside at least two of the channel regions and includes a plurality of second pseudo-channel structures arranged along a first direction, each of the second pseudo-channel structures penetrating the stacked structure. A second pseudo-channel groove structure extends through the stacked structure and the second pseudo-channel structure and into the substrate to divide the stacked structure into several parts.

10. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor structure is provided, the semiconductor structure including a stacked layer, a plurality of channel regions disposed in the stacked layer, and a first row of pseudo-channel vias located between two of the channel regions, the first row of pseudo-channel vias including a plurality of first pseudo-channel vias arranged along a first direction, each of the first pseudo-channel vias penetrating the stacked layer, the stacked layer including sacrificial layers and insulating layers alternately stacked; the first direction is a stacking direction perpendicular to the stacked layer; A first pseudo-channel groove is formed in the stacked layer. The first pseudo-channel groove connects to the plurality of first pseudo-channel holes in the first row of pseudo-channel holes. The first pseudo-channel groove includes a plurality of sub-pseudo-channel grooves spaced apart along a first direction. The sacrificial layer is replaced with a gate layer through the first pseudo-channel via and the first pseudo-channel slot to form a stacked structure, the stacked structure comprising the gate layer and the insulating layer alternately stacked; The first row of pseudo-channel holes and the first pseudo-channel groove are filled respectively to form the first row of pseudo-channel structure and the first pseudo-channel groove structure respectively.

11. The method for fabricating a semiconductor device as described in claim 10, characterized in that, Before forming the first pseudo-channel groove in the stacked layers, the method further includes: A top-select gate slot structure is formed, which is located in the stacked layers, passes through at least one sacrificial layer and the insulating layer, and connects the plurality of sub-pseudo-channel slots through the top-select gate slot structure.

12. The method for fabricating a semiconductor device as described in claim 10, characterized in that, Each of the aforementioned channel regions includes multiple channel structures, the channel structures extending through the stacked layers, and a sacrificial material is formed in the first dummy channel via. The step of providing the semiconductor structure specifically includes: Provide substrate; A stacked layer is formed on the substrate, the stacked layer comprising sacrificial layers and insulating layers alternately stacked; In the stacked layer, a channel hole and a first row of pseudo channel holes are formed respectively. The channel hole is located in a plurality of channel regions of the stacked layer. The channel region includes a plurality of channel holes, each of which penetrates the stacked layer. The first row of pseudo channel holes includes first pseudo channel holes arranged along a first direction, each of which penetrates the stacked layer. The first direction is a stacking direction perpendicular to the stacked layer. Sacrificial material is filled into the channel holes and the first row of dummy channel holes, respectively; A shielding layer is formed above the first row of pseudo-channel holes, the shielding layer covers the first row of pseudo-channel holes, and the shielding layer and the projection of the channel holes on the substrate do not overlap; Remove the sacrificial material located in the channel hole; Remove the masking layer; The channel holes are filled to form a channel structure.

13. The method for fabricating a semiconductor device as described in claim 12, characterized in that, The step of replacing the sacrificial layer with a gate layer through the first pseudo-channel via and the first pseudo-channel slot to form a stacked structure specifically includes: Remove the sacrificial material located in the first pseudo-channel hole; The sacrificial layer is removed, and a gate layer is formed at the location of the sacrificial layer to form a stacked structure.

14. The method for fabricating a semiconductor device as described in claim 12, characterized in that, Following the provision of the semiconductor structure, the method further includes: A gate line slot is formed in the stacked layer, the gate line slot extends along a first direction, the gate line slot penetrates the stacked layer and extends into the substrate, so as to divide the stacked layer into several parts; The grid line gaps are filled to form a grid line gap structure.

15. The method for fabricating a semiconductor device as described in claim 14, characterized in that, The first pseudo-channel groove and the grid line gap are formed in the same process.

16. The method for fabricating a semiconductor device as described in claim 14, characterized in that, The first pseudo-channel slot structure and the gate wire slot structure are formed under the same process.

17. The method for fabricating a semiconductor device as described in claim 12, characterized in that, The step of providing the semiconductor structure further includes forming a second row of dummy channel vias, the second row of dummy channel vias being located outside at least two of the channel regions and including a plurality of second dummy channel vias arranged along a first direction, each second dummy channel via penetrating the stacked layer, and after providing the semiconductor structure, further including: A second pseudo-channel groove is formed in the stacked layer, the second pseudo-channel groove penetrating the stacked layer and the second row of pseudo-channel holes and extending into the substrate, so as to divide the stacked layer into several parts; The second row of pseudo-channel holes and the second pseudo-channel groove are filled respectively to form the second row of pseudo-channel structure and the second pseudo-channel groove structure.

18. The method for fabricating a semiconductor device as described in claim 17, characterized in that, The first pseudo-groove and the second pseudo-groove are formed under the same process.

19. The method for fabricating a semiconductor device as described in claim 17, characterized in that, The first pseudo-groove structure and the second pseudo-groove structure are formed under the same process.

20. A storage system, characterized in that, The device includes a controller and a three-dimensional memory, the controller being coupled to the three-dimensional memory and used to control the storage of data in the three-dimensional memory, the three-dimensional memory comprising a semiconductor device as described in any one of claims 1 to 9.

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