A memory and a method for manufacturing the same, a storage system

Abstract

The application discloses a memory and a preparation method and a storage system thereof. The memory comprises a semiconductor layer, a first stack structure (including a storage area and a non-storage area) located on the semiconductor layer, a stop structure penetrating the first stack structure of the non-storage area, a second stack structure located on the first stack structure and the stop structure, and a first channel structure penetrating the second stack structure and the stop layer. Therefore, in a channel hole etching process of forming the first channel structure, the etching selectivity ratio of the stop structure to the first stack structure is less than 1, so that the stop structure can slow down the etching rate of the channel hole, and the channel hole is not etched too deep to affect the subsequent process or product yield, so that the stop structure can improve the etching process of the non-storage area channel hole.

Description

Technical Field

[0001] This application generally relates to the field of electronic devices, and more specifically, to a memory and its fabrication method and storage system. Background Technology

[0002] NAND flash memory devices are non-volatile memory products with low power consumption, light weight, and high performance, and are widely used in electronic products. Planar NAND devices have reached their practical expansion limits. To further increase storage capacity and reduce the cost per bit, 3D NAND flash memory was proposed. In a 3D NAND flash memory structure, multiple layers of data storage cells are vertically stacked to achieve a stacked memory structure. 3D NAND flash memory devices generally include a storage area for storage functions and a non-storage area used for other functions.

[0003] Due to the structural differences between the vias in the storage area and the non-storage area, the etching process of vias in the non-storage area becomes more difficult. Therefore, how to improve the etching process of vias in the non-storage area is an urgent problem to be solved. Summary of the Invention

[0004] The purpose of this application is to provide a memory and its fabrication method and storage system, which aims to improve the etching process of non-memory area channel holes.

[0005] In a first aspect, embodiments of this application provide a memory, including:

[0006] Semiconductor layer;

[0007] A first stacked structure is located on the semiconductor layer and includes a memory region and a non-memory region;

[0008] A stopping structure, extending through the first stacking structure of the non-memory area;

[0009] The second stacking structure is located on the first stacking structure and the stop structure;

[0010] The first channel structure extends through the second stacked structure and the stop structure;

[0011] Wherein, the etching selectivity ratio of the stop structure relative to the first stacked structure is less than 1.

[0012] Furthermore, the stop structure includes a dielectric layer, which comprises an oxide.

[0013] Furthermore, the stopping structure also includes:

[0014] A stop layer, wherein the dielectric layer is located between the stop layer and the first stacked structure;

[0015] Wherein, the etching selectivity ratio of the stop layer relative to the dielectric layer is less than 1.

[0016] Furthermore, there are multiple stopping structures, and each of the multiple stopping structures corresponds one-to-one with a multiple of the first channel structures.

[0017] Furthermore, the memory also includes:

[0018] A second channel structure extends through the second stack structure and the first stack structure of the storage area, and the critical dimension of the first channel structure is larger than the critical dimension of the second channel structure.

[0019] Furthermore, the memory also includes:

[0020] A third stacking structure is located on the second stacking structure and includes the storage area and the non-storage area;

[0021] The third channel structure extends through the third stack structure in the non-memory area and is connected to the first channel structure;

[0022] The fourth channel structure extends through the third stack structure of the storage area and is connected to the second channel structure.

[0023] Furthermore, the non-storage area includes a virtual area and a marker area, the first channel structure is located in the virtual area, and the stop structure is located in the virtual area and the marker area.

[0024] Furthermore, the memory also includes:

[0025] A first marking structure extends through the second stacking structure and the stop structure located in the marking area;

[0026] The second marking structure extends through the third stacked structure of the marking area, and the second marking structure is misaligned with the first marking structure.

[0027] Furthermore, the memory also includes:

[0028] The bottom selection of the gate isolation structure extends through the first stacked structure of the storage area;

[0029] The bottom selection gate isolation structure is made of the same material as the stop structure.

[0030] Furthermore, the stop structure has a first top surface, the bottom selection gate isolation structure has a second top surface, and the first top surface and the second top surface are on the same plane.

[0031] Secondly, embodiments of this application provide a method for fabricating a memory, the method comprising:

[0032] Provide substrate;

[0033] A first stacked layer is formed on the substrate, the first stacked layer including a storage region and a non-storage region;

[0034] A stop structure is formed for the first stacked layer that extends through the non-storage area;

[0035] A second stack layer is formed on the first stack layer and the stop structure;

[0036] A first channel structure is formed that extends through the second stacked layer and the stop structure;

[0037] Wherein, the etch selectivity ratio of the stop structure relative to the first stacked layer is less than 1.

[0038] Furthermore, there are multiple stopping structures, and each of the multiple stopping structures corresponds one-to-one with a multiple of the first channel structures.

[0039] Furthermore, the method for fabricating the memory also includes:

[0040] In the process of forming the stop structure, a bottom selection gate isolation structure is formed through the first stacked layer of the storage area.

[0041] Furthermore, the step of forming the stop structure and the bottom selection gate isolation structure includes:

[0042] Using the same photomask, a first trench is formed through the first stacked layer of the non-storage area, and a second trench is formed through the first stacked layer of the storage area;

[0043] Filler is deposited in the first trench and the second trench, as well as on the upper surface of the first stacked layer;

[0044] The filler located on the upper surface of the first stacked layer is removed to form the stop structure and the bottom select gate isolation structure.

[0045] Furthermore, the filler includes a dielectric layer, which includes an oxide layer.

[0046] Furthermore, the filler also includes a stop layer, and the dielectric layer is located between the stop layer and the first stacked layer;

[0047] Wherein, the etching selectivity ratio of the stop layer relative to the dielectric layer is less than 1.

[0048] Furthermore, the method for fabricating the memory also includes:

[0049] In the process of forming the first channel structure, a second channel structure is formed that penetrates the second stacked layer and the storage area of ​​the first stacked layer;

[0050] The critical dimension of the first channel structure is larger than the critical dimension of the second channel structure.

[0051] Furthermore, the method for fabricating the memory also includes:

[0052] A third stack layer is formed on the second stack layer, the third stack layer including the storage area and the non-storage area;

[0053] A third channel structure is formed through the third stacked layer of the non-memory area, and the third channel structure is connected to the first channel structure;

[0054] A fourth channel structure is formed through the third stacked layer of the storage area, and the fourth channel structure is connected to the second channel structure.

[0055] Furthermore, the non-memory area includes a virtual area and a marker area, with the first channel structure and the third channel structure located in the virtual area; the method for fabricating the memory further includes:

[0056] A first marking structure is formed that extends through the second stacked layer and the first stacked layer located in the marking area;

[0057] A second marker structure is formed through the third stacked layer of the marker region, and the second marker structure is misaligned with the first marker structure.

[0058] Thirdly, embodiments of this application provide a storage system, including:

[0059] The memory as described in any of the above embodiments;

[0060] A controller, electrically connected to the memory, is used to control the memory to store data.

[0061] This application provides a memory and its fabrication method, as well as a memory system. The memory includes a semiconductor layer, a first stacked structure (including a memory region and a non-memory region) on the semiconductor layer, a stop structure penetrating the first stacked structure in the non-memory region, a second stacked structure on the first stacked structure and the stop structure, and a first channel structure penetrating the second stacked structure and the stop structure. Therefore, in the channel hole etching process forming the first channel structure, the etching selectivity ratio of the stop structure relative to the first stacked structure is less than 1. Thus, the stop structure can slow down the etching rate of the channel hole, preventing the channel hole from being etched too deeply and affecting subsequent processes or product yield. Therefore, the stop structure can improve the etching process of the channel hole in the non-memory region. Attached Figure Description

[0062] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0063] Figure 1 This is a schematic diagram of the memory structure provided in the embodiments of this application. Figure 1 ;

[0064] Figure 2 This is a schematic diagram of the memory structure provided in a further embodiment of this application;

[0065] Figure 3 This is a schematic diagram of the memory structure provided in the embodiments of this application. Figure 2 ;

[0066] Figure 4 This is a schematic diagram of the XY cross-sectional structure of the memory at the stop structure provided in the embodiment of this application;

[0067] Figure 5 This is a schematic flowchart of the method for fabricating a memory provided in an embodiment of this application;

[0068] Figures 6a-6l This is a schematic diagram of the structure of the memory provided in the embodiment of this application during the manufacturing process;

[0069] Figures 7a-7b This is a schematic diagram of the structure of the memory during the fabrication process provided in a further embodiment of this application;

[0070] Figure 8 This is a schematic diagram of the storage system provided in an embodiment of this application. Detailed Implementation

[0071] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0072] It should be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of this application.

[0073] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be an inserted component. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0074] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (where contacts, interconnects, and one or more dielectric layers are formed).

[0075] This article uses a Cartesian coordinate system (X, Y, and Z) to illustrate the various orientations of the memory. For example, with the semiconductor layer as a reference, the XY plane is parallel to the semiconductor layer, and the Z direction is perpendicular to the semiconductor layer.

[0076] It should be noted that the illustrations provided in the embodiments of this application are only schematic representations of the basic concept of this application. Although the illustrations only show the components related to this application and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component in actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0077] Please see Figure 1 , Figure 1 This is a schematic diagram of the memory structure provided in the embodiments of this application. Figure 1 The memory 100 can be a wafer or a 3D memory. 3D memory can be applied to communication products, consumer electronics, automotive products, aerospace products, artificial intelligence products, or big data, etc. Consumer electronics include, but are not limited to, mobile phones, computers, tablets, cameras, smart glasses, or gaming products.

[0078] The memory 100 includes a semiconductor layer 10, a first stacked structure 20A on the semiconductor layer 10, the first stacked structure 20A including a memory region G1 and a non-memory region G2, a stop structure 30 penetrating the non-memory region G2 of the first stacked structure 20A, a second stacked structure 20B located on the first stacked structure 20A and the stop structure 30, and a first channel structure 40 penetrating the second stacked structure 20B and the stop structure 30. The stop structure 30 surrounds a portion of the sidewall of the first channel structure 40; in other words, the stop structure 30 is located between the first channel structure 40 and the first stacked structure 20A. It should be noted that in this embodiment, the direction of "penetration" can be a first direction (Z).

[0079] In one embodiment, the memory 100 may further include an etch stop layer 11 located between the semiconductor layer 10 and the first stacked structure 20A. The etch stop layer 11 may be made of polysilicon and is used to expose the channel layer during the fabrication process and to protect the first stacked structure 20A and the stop structure 30 from damage.

[0080] The first stacked structure 20A may include an interlayer insulating layer 201 and a gate layer 202 alternately stacked along a first direction (Z). The gate layer 202 includes, but is not limited to, tungsten, cobalt, copper, aluminum, doped silicon, or doped silicide. The interlayer insulating layer 201 includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. The first stacked structure 20A may be formed by a replacement process of a first stacked layer consisting of the interlayer insulating layer 201 and an interlayer sacrificial layer (e.g., silicon nitride) alternately stacked. Specifically, at the end of the fabrication process, the interlayer sacrificial layer in the first stacked layer may be replaced with the gate layer 202 to form the first stacked structure 20A.

[0081] In one embodiment, the first stacked structure 20A may include one, two or more pairs of interlayer insulating layers 201 / gate layers 202 as the bottom select gate layer of the 3D NAND.

[0082] The second stacked structure 20B may include the interlayer insulating layer 201 and the gate layer 202, which are alternately stacked along a first direction (Z). When the memory 100 is a dual-stack or multi-stack structure, the second stacked structure 20B and the first stacked structure 20A can form the lower stack of a 3D NAND.

[0083] The memory 100 may also include a second channel structure 50 that runs through the second stack structure 20B and the first stack structure 20A located in the storage area G1. The second channel structure 50 is a storage channel structure, which can realize the storage function.

[0084] Specifically, the second channel structure 50 may include a second channel via 501 penetrating the second stacked structure 20B and the first stacked structure 20A located in the storage region G1, with a storage layer 502, a channel layer 503, and an insulating layer 504 sequentially located in the second channel via 501. The storage layer 502 includes a tunneling layer, a charge trapping layer, and a barrier layer (not shown) sequentially surrounding the channel layer 503. An exemplary material for the barrier layer and the tunneling layer is silicon oxide, and an exemplary material for the charge trapping layer is silicon nitride. An exemplary material for the channel layer 503 is N-type doped or P-type doped polysilicon, but it is understood that other materials may be used for these layers.

[0085] In one embodiment, the memory 100 may further include a third stacked structure 20C located on the second stacked structure 20B. The third stacked structure 20C has the same structure as the second stacked structure 20B, for example, it may include interlayer insulating layers 201 and gate layers 202 stacked alternately along a first direction (Z), and the number of layers of interlayer insulating layers 201 and gate layers 202 stacked in the two may be different. The third stacked structure 20C may serve as the upper stack, and the third stacked structure 20C includes a memory region G1 and a non-memory region G2. The memory 100 may further include a third channel structure 41 extending through the third stacked structure 20C in the non-memory region G2, and the third channel structure 41 has the same structure as and is connected to the first channel structure 40. The memory 100 may further include a fourth channel structure 51 extending through the third stacked structure 20C in the memory region G1, and the fourth channel structure 51 has the same structure as and is connected to the second channel structure 50, for storing data.

[0086] In this embodiment, there are multiple first channel structures 40 and multiple stop structures 30, with each first channel structure 40 corresponding to one stop structure 30. Since the stop structures 30 are located in the non-memory area G2, the first channel structures 40 penetrating the stop structures 30 are also located in the non-memory area G2. The non-memory area G2 may include a virtual area (which may include a stepped area), and the stop structures 30 may be located in the virtual area. The first channel structures 40 and the third channel structures 41 can be virtual channel structures used to support the overall structure.

[0087] In this embodiment, the first channel structure 40 can have the same structure as the second channel structure 50, for example, including a first channel hole 401 penetrating the second stack structure 20B and the stop structure 30, and a storage layer 402, a channel layer 403, and an insulating layer 404 sequentially filled in the first channel hole 401. The difference is that the critical dimension (i.e., the design dimension) of the first channel structure 40 is larger than the critical dimension of the second channel structure 50 to enhance the support effect of the virtual channel structure. For example, the top surface area (or top diameter) of the first channel structure 40 is larger than the top surface area (or top diameter) of the second channel structure 50.

[0088] In this configuration, the channel layers 403 / 503 in the first channel structure 40 and the second channel structure 50 have ends not covered by the storage layers 402 / 502, and these ends are located in the semiconductor layer 10 and electrically connected to the semiconductor layer 10. The semiconductor layer 10 can be polycrystalline silicon, germanium, or monocrystalline silicon, germanium, or polycrystalline silicon containing silicon or germanium compounds.

[0089] In some embodiments, the first channel structure 40 may include the first channel hole 401 and an insulating material filling the first channel hole 401, which is different from the structure of the second channel structure 50.

[0090] In some embodiments, the first channel hole 401 and the second channel hole 501 are etched in the same process. The inventors have discovered that during the simultaneous etching of the first channel hole 401 and the second channel hole 501, because the critical dimension (e.g., top diameter) of the first channel hole 401 is larger than that of the second channel hole 501, the etching rate of the first channel hole 401 is greater than that of the second channel hole 501. This results in the first channel hole 401 being etched too deeply, which in turn affects subsequent processes or product yield.

[0091] The stop structure 30 may include a first trench 301 penetrating the first stacked structure 20A, and a dielectric layer 302 filling the first trench 301. In the etching process forming the first channel via 401 and the second channel via 501, the etching selectivity ratio of the first stacked layer (the structure prior to the formation of the first stacked structure) or the first stacked structure 20A relative to the dielectric layer 302 (or the stop structure 30) is greater than 1. For example, an exemplary material for the dielectric layer 302 is an oxide such as silicon oxide; the material of the dielectric layer 302 may also be a metal (e.g., tungsten) or polysilicon.

[0092] When the dielectric layer 302 is made of oxide and the first stacked layer is made of stacked oxide and nitride, and the etching selectivity of nitride relative to oxide is greater than 1, when etching the first channel hole 401, the etching selectivity of the first stacked layer (oxide and nitride) relative to the stop structure 30 (all oxide) is greater than 1. Therefore, compared with directly etching the first stacked layer, etching the stop structure 30 can reduce the etching rate, thereby avoiding the first channel hole 401 from being etched too deeply, thus improving the etching process of the first channel hole 401 and avoiding the impact on subsequent processes or product yield.

[0093] Please see Figure 2 , Figure 2 This is a schematic diagram of the memory structure provided in a further embodiment of this application. For ease of explanation and understanding, the same structures as those in the above embodiments are referred to by the same reference numerals, and the same structures will not be described again. Only the differences between this embodiment and the above embodiments will be described.

[0094] The stop structure 31 in the memory 200 includes a first trench 310 penetrating the first stacked structure 20A and a dielectric layer 311 and a stop layer 312 sequentially filled in the first trench 310, i.e., the dielectric layer 311 is located between the stop layer 312 and the first stacked structure 20A. The dielectric layer 311 primarily serves an isolation function, and its material can be an oxide such as silicon oxide. The etching selectivity ratio of the first stacked layer or the first stacked structure 20A relative to the stop layer 312 is greater than 1. The stop layer 312 primarily serves to reduce the etching rate of the vias, and its material can be carbon or some metals (e.g., tungsten). Further, the etching selectivity ratio of the stop layer 312 relative to the dielectric layer 311 is less than 1, i.e., the etching rate of the stop layer 312 is less than the etching rate of the dielectric layer 311, which is less than the etching rate of the first stacked layer (or the first stacked structure 20A).

[0095] Please see Figure 3 , Figure 3 This is a schematic diagram of the memory structure provided in the embodiments of this application. Figure 2 For ease of explanation and understanding, the same structures in this embodiment are referred to by the same reference numerals as those in the above embodiments, and the same structures will not be described again. Only the differences between this embodiment and the above embodiments will be explained.

[0096] The memory 100 may further include a third stack structure 20C located on the second stack structure 20B. The third stack structure 20C has the same structure as the second stack structure 20B and can serve as the upper stack. The third stack structure 20C includes the storage area G1 and the non-storage area G2. The non-storage area G2 includes a marker area, and the stop structure 30 may be located in the marker area.

[0097] In this embodiment, the memory 100 further includes a first marker structure 40a and a second marker structure 41a, which are formed in the marker region. The first marker structure 40a includes a first marker hole 401a penetrating the second stacked structure 20B and the stop structure 30 located in the marker region, and a sacrificial layer 402a filled in the first marker hole 401a. The material of the sacrificial layer 402a may include carbon. The second marker structure 41a includes a second marker hole 411a penetrating the third stacked structure 20C in the marker region, and a memory layer, a channel layer, and an insulating layer sequentially filled in the second marker hole 411a. The second marker structure 41a is offset from the first marker structure 40a, that is, offset by a certain distance in the X direction and is not connected.

[0098] In one embodiment, when the second channel structure 50 is formed in the storage area G1, a first marker structure 40a is formed in the non-storage area G2 (or marker area) using the same mask. Similarly, when the fourth channel structure 51 is formed in the storage area G1, a second marker structure 41a is formed in the non-storage area G2 (or marker area) using the same mask. The difference is that the second marker structure 41a is not aligned with the first marker structure 40a, while the fourth channel structure 51 is aligned and connected to the second channel structure 50. Furthermore, the first marker hole 401a is filled with a sacrificial layer 402a. The misalignment of the second marker structure 41a with the first marker structure 40a is used to monitor whether the fourth channel structure 51 and the second channel structure 50 are aligned. For example, if the distance of the second marker structure 41a offset from the first marker structure 40a in the X direction is L0, and the distance of the fourth channel structure 51 and the second marker structure 41a in the X direction is L1, and the distance of the second channel structure 50 and the first marker structure 40a in the X direction is L2, and the difference between L1 and L2 (L2-L1) is within the range of L0±L (L is a value set according to the actual process), then it indicates that the fourth channel structure 51 and the second channel structure 50 are aligned; otherwise, they are not aligned.

[0099] The inventors discovered that because the second marking structure 41a is misaligned with the first marking structure 40a, the sacrificial layer 402a in the first marking structure 40a cannot be removed through the second marking hole 411a and remains in the structure. The residue of the sacrificial layer 402a introduces structural defects and the risk of machine contamination, affecting product yield. However, since the stop structure 30 in this embodiment includes a dielectric layer 302, the dielectric layer 302 can isolate the sacrificial layer 402a from the first stacked structure 20A, thereby reducing the defects and risks caused by the peeling off of the sacrificial layer 402a and improving product yield.

[0100] Please see Figure 4 , Figure 4This is a schematic diagram of the XY cross-sectional structure of the memory at the stop structure provided in the embodiment of this application.

[0101] The first stacking structure 20A includes a storage area G1 and a non-storage area G2, with the non-storage area G2 potentially located around the perimeter of the storage area G1. The non-storage area G2 includes a virtual area G21 and a marker area G22. A first channel structure 40 is located in the virtual area G21, and a first marker structure 40a is located in the marker area G22. A stop structure 30 is located in the non-storage area G2 (both the virtual area G21 and the marker area G22). The first channel structure 40 and the first marker structure 40a respectively penetrate the stop structure 30, meaning that the stop structure 30 each surrounds a portion of the sidewall of either the first channel structure 40 or the first marker structure 40a. A second channel structure 50 is located in the storage area G1 and is arranged in an array.

[0102] The memory 100 also includes a bottom select gate isolation structure 60 extending through a first stacked structure 20A of the memory region G1, used to isolate the gate layer 202 in the first stacked structure 20A. The bottom select gate isolation structure 60 is made of the same material as the stop structure 30 (e.g., including a dielectric layer or a combination of a dielectric layer and a stop layer), and the bottom select gate isolation structure 60 and the stop structure 30 can be fabricated using the same photomask or mask. Further, the stop structure 30 has a first top surface, and the bottom select gate isolation structure 60 has a second top surface, with the first top surface and the second top surface on the same plane, i.e., the tops of the bottom select gate isolation structure 60 and the stop structure 30 are flush.

[0103] Therefore, this embodiment only requires adding a pattern corresponding to the stop structure 30 to the mask of the bottom selected gate isolation structure 60. In other words, no additional photomask is needed. By optimizing the mask of the bottom selected gate isolation structure 60, the stop structure 30 is formed in the non-memory area G2 (including the virtual area G21 and the marker area G22) without affecting the function of the bottom selected gate isolation structure 60. This avoids the first channel structure 40 of the virtual area G21 being etched too deeply. It can also reduce the defects and risks caused by the residual sacrificial layer 402a in the first marker structure 40a of the marker area G22, thereby improving the process and increasing the product yield.

[0104] Please combine Figure 1 , Figure 3 and Figure 4 , Figure 1 It can be seen as Figure 4 A cross-sectional view of the memory 100 along line A-A1. Figure 3 It can be seen as Figure 4 A cross-sectional view of the memory 100 at point B-B1.

[0105] The memory 100 provided in this application embodiment forms a stop structure 30 in the first stacked structure 20A located at the bottom, which slows down the etching rate of the first channel structure 40 in the stop structure 30 at the bottom, thereby avoiding the impact of excessive etching of the first channel structure 40 on subsequent processes and product yield. In addition, when the first marker structure 40a is filled with a sacrificial layer 402a that cannot be removed, the stop structure 30 can reduce defects and equipment risks caused by the residue of the sacrificial layer 402a. The stop structure 30 can also be fabricated with the bottom select gate isolation structure 60 under the same photomask, that is, the pattern corresponding to the stop structure 30 is added to the photomask of the bottom select gate isolation structure 60 without the need to add an additional photomask, thus reducing costs without affecting the function of the bottom select gate isolation structure 60.

[0106] Please see Figure 5 , Figure 5 This is a schematic flowchart illustrating the method for fabricating the memory provided in an embodiment of this application. Please also refer to... Figures 6a-6l , Figures 6a-6l This is a schematic diagram of the structure of the memory provided in the embodiment of this application during the fabrication process. This embodiment takes the fabrication of memory 100 as an example to illustrate the fabrication method of the memory, which includes the following steps S1-S5.

[0107] Please see Figure 5 Steps S1-S2 and Figure 6a .

[0108] Step S1: Provide substrate 101.

[0109] The substrate 101 may be, for example, silicon (Si), germanium (Ge), a SiGe semiconductor layer, silicon on insulator (SOI), or germanium on insulator (GOI). The substrate 101 may also include other elemental semiconductors or compound semiconductors, and may also be a stacked structure, such as Si / SiGe.

[0110] In one embodiment, after step S1, the method for fabricating the memory further includes sequentially depositing an oxide layer 102, a sacrificial stop layer 103, an etch stop layer 104, and an etch stop layer 11 on a substrate 101. The oxide layer 102 and the etch stop layer 104 may be made of silicon oxide, and the sacrificial stop layer 103 and the etch stop layer 11 may be made of polysilicon.

[0111] Step S2: A first stacked layer 21A is formed on the substrate 101. The first stacked layer 21A includes a storage area G1 and a non-storage area G2.

[0112] An interlayer insulating layer 201 and an interlayer sacrificial layer 202a can be alternately deposited on a substrate 101. The interlayer insulating layer 201 can be silicon oxide, and the interlayer sacrificial layer 202a can be made of silicon nitride. The methods for forming the interlayer insulating layer 201 and the interlayer sacrificial layer 202a include, but are not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD).

[0113] Please see Figure 5 Step S3 and Figures 6b-6e .

[0114] Step S3: Form a stop structure 30 through the first stacked layer 21A of the non-memory area G2 and a bottom select gate isolation structure 60 through the first stacked layer 21A of the memory area G1.

[0115] In this embodiment, after the interlayer sacrificial layer 202a in the first stacked layer 21A is replaced with a gate layer, a bottom selected gate layer can be formed. Since both the stop structure 30 and the bottom selected gate isolation structure 60 penetrate the first stacked layer 21A, they can be formed together. In the subsequent etching process for forming the first channel via 401 and the first marker via 401a, the etching selectivity ratio of the stop structure 30 relative to the first stacked layer 21A is less than 1, meaning the etching rate of the stop structure 30 is less than the etching rate of the first stacked layer 21A.

[0116] Specifically, step S3 may include the following steps: 1) As... Figure 6b As shown, using the same photomask, the first stacked layer 21A is etched to form a first trench 301 penetrating the non-memory region G2 and a second trench 601 penetrating the first stacked layer 21A penetrating the memory region G1. 2) As Figure 6c As shown, a filler is deposited in the first trench 301 and the second trench 601, as well as on the upper surface of the first stacked layer 21A. The filler may include a dielectric layer 302, which may include an oxide such as silicon oxide. 3) As... Figure 6d As shown, the filler located on the upper surface of the first stacked layer 21A is removed to form the stop structure 30 in the first trench 301 and the bottom selection gate isolation structure 60 in the second trench 601.

[0117] Figure 6e yes Figure 6d A top-view structural diagram. Figure 6d It can be seen as Figure 6e A cross-sectional structural diagram at C-C1. The first stacked layer 21A may include a storage area G1 and a non-storage area G2 located around the storage area G1. The non-storage area G2 may include a virtual area G21 and a tag area G22.

[0118] Please see Figures 7a-7b , Figures 7a-7b This is a schematic diagram of the structure of a memory during the fabrication process provided in a modified embodiment of this application. The steps of forming the stop structure 31 and the bottom select gate isolation structure 60 may include the following steps: 1) As... Figure 7a As shown, filler is deposited in the first trench 310 and the second trench 601, as well as on the upper surface of the first stacked layer 21A. The filler includes a dielectric layer 311 and a stop layer 312 deposited sequentially. The stop layer 312 can be made of carbon or some metal (e.g., tungsten). In one embodiment, during the etching process forming the first channel via 401 and the first marker via 401a, the etching selectivity of the stop layer 312 relative to the dielectric layer 311 is less than 1. 2) As Figure 7b As shown, the filler on the first stacked layer 21A can then be removed using a chemical mechanical planarization (CMP) process, thereby forming a stop structure 31 and a bottom select gate isolation structure 60.

[0119] Please see Figure 5 Steps S4-S5 and Figures 6f-6i .

[0120] Step S4: Form a second stacked layer 21B on the first stacked layer 21A and the stop structure 30.

[0121] The second stacked layer 21B includes alternating deposited interlayer insulating layer 201 and interlayer sacrificial layer 202a.

[0122] Step S5: Form a first channel structure 40 that extends through the second stacked layer 21B and the stop structure 30.

[0123] In one embodiment, the non-memory area G2 includes a virtual area G21 and a tag area G22, the first channel structure 40 is formed in the virtual area G21, and the memory 100 can be a dual-stack structure. The method for fabricating the memory 100 further includes: 1) in the process of forming the first channel structure 40 (step S5), forming a first marker structure 40a that penetrates the second stacked layer 21B and the first stacked layer 21A located in the marker region G22; 2) forming a third stacked layer 21C on the second stacked layer 21B, the third stacked layer 21C including the memory region G1 and the non-memory region G2 (including the virtual region G21 and the marker region G22); 3) forming a third channel structure 41 that penetrates the third stacked layer 21C through the virtual region G21, the third channel structure 41 being connected to the first channel structure 40; 4) in the process of forming the third channel structure 41, forming a second marker structure 41a that penetrates the third stacked layer 21C through the marker region G22, the second marker structure 41a being misaligned with the first marker structure 40a.

[0124] Specifically, such as Figure 6f As shown, the second stacked layer 21B, the stop structure 30, the etch stop layer 11, the etch barrier layer 104, and a partial sacrificial stop layer 103 are first etched to form a first channel hole 401 and a first marker hole 401a. The bottoms of the first channel hole 401 and the first marker hole 401a are located in the sacrificial stop layer 103. Figure 6g As shown, a sacrificial layer 402a (e.g., carbon) is then filled into the first channel hole 401 and the first marker hole 401a. Following this, a third stacked layer 21C is deposited, and the third stacked layer 21C of the virtual region G21 is etched to form a third channel hole 411 communicating with the first channel hole 401. Simultaneously, the third stacked layer 21C of the marker region G22 is etched to form a second marker hole 411a misaligned with the first marker hole 401a. For example... Figure 6h As shown, the sacrificial layer 402a located in the first channel hole 401 is removed through the third channel hole 411. Figure 6i As shown, a storage layer 402, a channel layer 403, and an insulating layer 404 are sequentially deposited in the first channel hole 401 and the third channel hole 411 to form a first channel structure 40 and a third channel structure 41. At the same time, the same deposition process is sequentially performed in the second marker hole 411a to form a second marker structure 41a that is misaligned with the first marker structure 40a.

[0125] Please see Figure 4 and Figure 6j , Figure 6j It can be seen as Figure 4A schematic cross-sectional view of the memory 100 along line A-A1. The fabrication method of this memory may further include: 1) in the process of forming the first channel structure 40, forming a second channel structure 50 penetrating the second stacked layer 21B and the first stacked layer 21A of the storage region G1; 2) in the process of forming the third channel structure 41, forming a fourth channel structure 51 penetrating the third stacked layer 21C of the storage region G1, wherein the fourth channel structure 51 is connected to the second channel structure 50.

[0126] Specifically, the second stacked layer 21B and the first stacked layer 21A of the virtual region G21 and the memory region G1 are simultaneously etched to form a first channel via 401 and a second channel via 501. Then, a sacrificial layer is filled into the first channel via 401 and the second channel via 501. After forming the third stacked layer 21C, the third stacked layer 21C of the virtual region G21 and the memory region G1 is simultaneously etched to form a third channel via 411 and a fourth channel via 511, wherein the fourth channel via 511 is connected to the second channel via 501. Finally, a memory layer, a channel layer, and an insulating layer are sequentially deposited in the first channel via 401, the second channel via 501, the third channel via 411, and the fourth channel via 511, respectively, to form a first channel structure 40, a third channel structure 41 connected to the first channel structure 40, a second channel structure 50, and a fourth channel structure 51 connected to the second channel structure 50. The first channel structure 40 and the third channel structure 41 have identical structures and both serve as virtual channel structures. The second channel structure 50 and the fourth channel structure 51 have identical structures and both serve as storage channel structures. The critical dimensions of the first channel structure 40 and the third channel structure 41 are larger than those of the second channel structure 50 and the fourth channel structure 51, respectively. For example, the top diameter of the first channel structure 40 is larger than the top diameter of the second channel structure 50, and the top diameter of the third channel structure 41 is larger than the top diameter of the fourth channel structure 51.

[0127] In one embodiment, the memory 100 is a single-stack structure. In the process of forming the first channel structure 40, a second channel structure 50 can be formed penetrating the second stacked layer 21B and the first stacked layer 21A of the memory region G1. Specifically, the second stacked layer 21B, stop structure 30, etch stop layer 11, etch barrier layer 104, and partially sacrificial stop layer 103 can be etched to form a first channel hole 401 and a second channel hole 501, with the bottoms of the first channel hole 401 and the second channel hole 501 located within the sacrificial stop layer 103. Then, a storage functional layer is filled into the first channel hole 401 and the second channel hole 501 to form the first channel structure 40 and the second channel structure 50, respectively. The storage functional layer includes a storage layer and a channel layer sequentially within the first channel hole 401, and may also include an insulating layer deposited on the inner surface of the channel layer. The critical dimension (e.g., top diameter) of the first channel structure 40 is larger than the critical dimension (e.g., top diameter) of the second channel structure 50.

[0128] Please see Figures 6k-6l The method for fabricating this memory may further include: 1) as follows Figure 6k As shown, the substrate 101, the oxide layer 102, and the sacrificial stop layer 103 are removed sequentially to expose a portion of the first channel structure 40 and a portion of the second channel structure 50; 2) as Figure 6l As shown, the exposed storage layers 502 / 402 are removed to expose part of the channel layers 503 / 403, while the etch stop layer 104 is removed; 3) a semiconductor layer 10 connected to the channel layers 503 / 403 is formed on the surface of the etch stop layer 11.

[0129] Specifically, such as Figure 6k As shown, the substrate 101 and oxide layer 102 can be removed first using a chemical mechanical polishing process, and the oxide layer 102 can also be removed using an etching process. Then, tetramethylammonium hydroxide (TMAH) is used for etching to remove the sacrificial stop layer 103. Since the first channel structure 40 and the second channel structure 50 extend into the sacrificial stop layer 103, removing the sacrificial stop layer 103 exposes a portion of the first channel structure 40 and a portion of the second channel structure 50, i.e., a portion of the memory layers 502 / 402 are exposed. Figure 6l As shown, hydrofluoric acid can then be used as an etchant to etch the etch barrier layer 104 and... Figure 6k The memory layers 502 / 402 (ONO) are exposed in the etching process, which stops at the surface of the etch stop layer 11, thus exposing a portion of the channel layer 503 / 403. For example... Figure 1 As shown, a semiconductor layer 10 is finally deposited on the surface of the etch stop layer 11 to achieve connection with the channel layer 503.

[0130] The inventors discovered that because the first channel via 401 and the second channel via 501 are etched simultaneously, and the critical dimension of the first channel via 401 is larger than that of the second channel via 501, the first channel via 401 is prone to being etched too deeply. If the first channel via 401 is etched too deeply and extends into the substrate 101, the etching process for removing the oxide layer 102 will remove part of the memory layer 502 / 402, exposing part of the channel layer 503 / 403. Since the materials of the channel layer 503 / 403 and the sacrificial stop layer 103 can both be polysilicon, the channel layer 503 / 403 is etched simultaneously during the process of removing the sacrificial stop layer 103, leaving part of the inner side of the memory layer 502 / 402 suspended. Therefore, in the actual process of removing the memory layer 502 / 402... Figure 6l The etching solution simultaneously etches from both the outer and inner sides of the storage layers 502 / 402, resulting in excessive etching of the storage layers 502 / 402, such as etching into the first stacked layer 21A. Consequently, when the semiconductor layer 10 is subsequently formed, it will deposit within the first stacked layer 21A. When the interlayer sacrificial layer 202a is replaced by the gate layer, the semiconductor layer 10 will come into contact with the gate layer, causing leakage. Furthermore, the residual sacrificial layer 402a in the first marker structure 40a will cause defects in the surrounding structure and may even peel off, thus contaminating the equipment during the process of removing the sacrificial stop layer 103.

[0131] The memory fabrication method provided in this application embodiment first forms a stop structure 30 penetrating the first stacked layer 21A at a corresponding position before forming the first channel structure 40. This slows down the etching rate of the first channel hole 401 and prevents leakage between the semiconductor layer 10 and the gate layer from occurring due to excessive etching of the first channel hole 401. Before forming the first marker structure 40a, a stop structure 30 penetrating the first stacked layer 21A is formed at a corresponding position. The stop structure 30 includes a dielectric layer, which can isolate the sacrificial layer 402a that cannot be removed from the first marker structure 40a, reducing defects and equipment risks caused by the residual sacrificial layer 402a. Furthermore, the stop structure 30 can be fabricated under the same photomask as the bottom select gate isolation structure 60. Only the pattern of the corresponding stop structure 30 needs to be added to the photomask of the bottom select gate isolation structure 60, without adding an additional photomask. Therefore, it can reduce costs without affecting the function of the bottom select gate isolation structure 60.

[0132] Please see Figure 8 , Figure 8This is a schematic diagram of the structure of a storage system provided in an embodiment of this application. The storage system 900 includes a memory 901 and a controller 902. The memory 901 can be the memory in any of the above embodiments. The controller 902 is electrically connected to the memory 901 and is used to control the memory 901 to store data. The memory 901 can perform data storage operations based on the control of the controller 902.

[0133] In some implementations, the storage system may be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a Multimedia Card in the form of MMC, eMMC, RS-MMC, and Micro MMC, a Secure Digital Card in the form of SD, Mini SD, and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc.

[0134] The memory 901 includes: a semiconductor layer; a first stacked structure located on the semiconductor layer and including a memory region and a non-memory region; a stop structure extending through the first stacked structure in the non-memory region; a second stacked structure located on the first stacked structure and the stop structure; and a first channel structure extending through the second stacked structure and the stop structure; wherein the etch selectivity ratio of the stop structure relative to the first stacked structure is less than 1.

[0135] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application; those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A memory, characterized in that, The memory includes: Semiconductor layer; A first stacked structure is located on the semiconductor layer and includes a memory region and a non-memory region; A stopping structure, extending through the first stacking structure of the non-memory area; A second stacked structure is located on the first stacked structure and the stop structure; the first stacked structure and the second stacked structure respectively include gate layers and interlayer insulating layers alternately stacked along a first direction; A first channel structure passes through the second stacked structure and the stop structure along the first direction; Wherein, the etching selectivity ratio of the stop structure relative to the first stacked structure is less than 1.

2. The memory according to claim 1, characterized in that, The stop structure includes a dielectric layer, which includes an oxide layer.

3. The memory according to claim 2, characterized in that, The stopping structure also includes: A stop layer, wherein the dielectric layer is located between the stop layer and the first stacked structure; Wherein, the etching selectivity ratio of the stop layer relative to the dielectric layer is less than 1.

4. The memory according to claim 1, characterized in that, The number of the stop structures is multiple, and each of the multiple stop structures corresponds one-to-one with a multiple of the first channel structures.

5. The memory according to claim 1, characterized in that, The memory also includes: A second channel structure extends through the second stack structure and the first stack structure of the storage area, and the critical dimension of the first channel structure is larger than the critical dimension of the second channel structure.

6. The memory according to claim 5, characterized in that, The memory also includes: A third stacking structure is located on the second stacking structure and includes the storage area and the non-storage area; The third channel structure extends through the third stack structure in the non-memory area and is connected to the first channel structure; The fourth channel structure extends through the third stack structure of the storage area and is connected to the second channel structure.

7. The memory according to claim 6, characterized in that, The non-storage area includes a virtual area and a marker area, the first channel structure is located in the virtual area, and the stop structure is located in the virtual area and the marker area.

8. The memory according to claim 7, characterized in that, The memory also includes: A first marking structure extends through the second stacking structure and the stop structure located in the marking area; The second marking structure extends through the third stacked structure of the marking area, and the second marking structure is misaligned with the first marking structure.

9. The memory according to claim 1, characterized in that, The memory also includes: The bottom selection of the gate isolation structure extends through the first stacked structure of the storage area; The bottom selection gate isolation structure is made of the same material as the stop structure.

10. The memory according to claim 9, characterized in that, The stop structure has a first top surface, the bottom selection gate isolation structure has a second top surface, and the first top surface and the second top surface are on the same plane.

11. A method for fabricating a memory, characterized in that, The method for fabricating the memory includes: Provide substrate; A first stacked layer is formed on the substrate, the first stacked layer including a storage region and a non-storage region; A stop structure is formed for the first stacked layer that extends through the non-storage area; A second stacked layer is formed on the first stacked layer and the stop structure; the first stacked layer and the second stacked layer respectively include gate layers and interlayer insulating layers alternately stacked along a first direction; A first channel structure is formed that passes through the second stacked layer and the stop structure along the first direction; Wherein, the etch selectivity ratio of the stop structure relative to the first stacked layer is less than 1.

12. The method for fabricating a memory according to claim 11, characterized in that, The number of the stop structures is multiple, and each of the multiple stop structures corresponds one-to-one with a multiple of the first channel structures.

13. The method for fabricating a memory according to claim 11, characterized in that, The method for preparing the memory further includes: In the process of forming the stop structure, a bottom selection gate isolation structure is formed through the first stacked layer of the storage area.

14. The method for fabricating a memory according to claim 13, characterized in that, The steps of forming the stop structure and the bottom selection gate isolation structure include: Using the same photomask, a first trench is formed through the first stacked layer of the non-storage area, and a second trench is formed through the first stacked layer of the storage area; Filler is deposited in the first trench and the second trench, as well as on the upper surface of the first stacked layer; The filler located on the upper surface of the first stacked layer is removed to form the stop structure and the bottom select gate isolation structure.

15. The method for fabricating a memory according to claim 14, characterized in that, The filler includes a dielectric layer, which includes an oxide layer.

16. The method for fabricating a memory according to claim 15, characterized in that, The filler also includes a stop layer, and the dielectric layer is located between the stop layer and the first stacked layer; Wherein, the etching selectivity ratio of the stop layer relative to the dielectric layer is less than 1.

17. The method for fabricating a memory according to claim 11, characterized in that, The method for preparing the memory further includes: In the process of forming the first channel structure, a second channel structure is formed that penetrates the second stacked layer and the storage area of ​​the first stacked layer; The critical dimension of the first channel structure is larger than the critical dimension of the second channel structure.

18. The method for fabricating a memory according to claim 17, characterized in that, The method for preparing the memory further includes: A third stack layer is formed on the second stack layer, the third stack layer including the storage area and the non-storage area; A third channel structure is formed through the third stacked layer of the non-memory area, and the third channel structure is connected to the first channel structure; A fourth channel structure is formed through the third stacked layer of the storage area, and the fourth channel structure is connected to the second channel structure.

19. The method for fabricating a memory according to claim 18, characterized in that, The non-storage area includes a virtual area and a marker area, and the first channel structure and the third channel structure are located in the virtual area; The method for preparing the memory further includes: A first marking structure is formed that extends through the second stacked layer and the first stacked layer located in the marking area; A second marker structure is formed through the third stacked layer of the marker region, and the second marker structure is misaligned with the first marker structure.

20. A storage system, characterized in that, include: The memory as described in any one of claims 1-10; A controller, electrically connected to the memory, is used to control the memory to store data.

Images