3D CMOS image sensor and method for forming the same

Abstract

The present invention provides a 3D CMOS image sensor and a method for forming the same, which relates to the field of image sensors, and includes: a substrate, wherein the substrate includes at least one photodiode; a well region, wherein the well region is formed above the photodiode and connected to the photodiode, and wherein the well region is a thin film cavity structure; a floating diffusion region, wherein the floating diffusion region is formed on the substrate and located above the well region and connected to the well region; and a transmission gate, wherein the transmission gate is floated above the substrate and surrounds the well region, and wherein the transmission gate is a metal gate. By floating the transmission gate and the floating diffusion region above the substrate, the floating diffusion region can freely expand its area and increase the full well capacity. In addition, by using a metal gate as a transmission gate, the gate resistance is reduced, the transmission gate response speed is increased, and the light quantum efficiency is increased. By adopting a thin film cavity structure to form the well region, the well region does not need to be doped with additional ion implantation, which is conducive to reducing the process difficulty.

Description

Technical Field

[0001] The present invention relates to the field of image sensors, and in particular to a 3D CMOS image sensor and a method for forming the same. Background Art

[0002] Generally, an image sensor refers to a device that converts light signals into electrical signals. The main types of image sensor units are charge coupled devices (CCD) and complementary metal oxide semiconductor (CMOS) devices. Compared with traditional CCD sensors, CMOS image sensors have the characteristics of low power consumption, low cost and compatibility with CMOS processes, so they are increasingly widely used.

[0003] CMOS image sensors include a pixel array composed of numerous pixel units, which are the core components of image sensors to realize light sensing. Common CMOS image sensors are 4-transistor (4T) units, and their pixel units usually contain an active pixel structure composed of a photodiode (PD) and 4 transistors.

[0004] The 4T structure commonly used in current CMOS sensor technology has one more transfer gate (TG) and one more floating diffusion (FD) than the 3T structure to obtain better performance and lower noise. However, the added devices reduce the area of ​​the corresponding photodiode, that is, the effective pixel area is reduced. If the floating diffusion area is reduced in order to increase the effective pixel area, the full well capacity will be affected. Therefore, a CMOS image sensor with a 4T structure that does not affect the area of ​​the photodiode is needed. Summary of the invention

[0005] The object of the present invention is to provide a 3D CMOS image sensor and a method for forming the same, so as to solve the problem that the added transfer gate and floating diffusion region in the 4T structure CMOS image sensor reduces the area of ​​the photodiode.

[0006] In order to solve the above technical problems, the present invention provides a 3D CMOS image sensor, comprising:

[0007] a substrate, wherein the substrate includes at least one photodiode;

[0008] A well region, wherein the well region is formed above the photodiode and connected to the photodiode, and the well region is a thin film cavity structure;

[0009] a floating diffusion region, the floating diffusion region being formed on the substrate and located above the well region and connected to the well region; and

[0010] A transmission gate is floated above the substrate and surrounds the well region, and the transmission gate is a metal gate.

[0011] Optionally, a top surface of the well region is higher than a top surface of the transfer gate.

[0012] Optionally, the method further includes a first dielectric layer disposed between the transmission gate and the substrate; and a first opening penetrating the first dielectric layer.

[0013] The longitudinal cross-section of the transmission gate is in an inverted T shape.

[0014] Optionally, also include:

[0015] a first polysilicon layer, wherein the first polysilicon layer covers the sidewalls and the bottom wall of the first opening to form the well region;

[0016] a third dielectric layer, wherein the third dielectric layer is filled in the first opening;

[0017] a second opening, the second opening being formed in the first opening and being located above the third dielectric layer; and,

[0018] A second polysilicon layer is formed, and the second polysilicon layer is filled in the second opening to form the floating diffusion region.

[0019] Optionally, the first polysilicon layer is a P-type doped polysilicon film or a non-doped polysilicon film.

[0020] Based on the same inventive concept, the present invention provides a method for forming a 3D CMOS image sensor, comprising:

[0021] providing a substrate having at least one photodiode formed therein,

[0022] forming a sacrificial layer, wherein the sacrificial layer covers the substrate;

[0023] forming a first opening, wherein the first opening at least penetrates the sacrificial layer and exposes the photodiode;

[0024] A well region and a floating diffusion region are sequentially formed at the position of the first opening, wherein the floating diffusion region is located above the well region, and the well region is a thin film cavity structure;

[0025] etching the sacrificial layer over the substrate between adjacent photodiodes; and,

[0026] The sacrificial layer on the photodiode is removed to form a fourth opening, and a transmission gate surrounding the well region is formed at the position of the fourth opening, wherein the transmission gate is a metal gate.

[0027] Optionally, the step of forming a well region and a floating diffusion region at the position of the first opening includes:

[0028] forming a first polysilicon layer at the position of the first opening, wherein the first polysilicon layer covers the sidewalls and the bottom wall of the first opening;

[0029] forming a third dielectric layer, wherein the third dielectric layer fills the first opening;

[0030] Removing a portion of the thickness of the third dielectric layer in the first opening to form a second opening, wherein a bottom wall of the second opening is higher than a top surface of the sacrificial layer;

[0031] The second opening is filled with a second polysilicon layer to form the floating diffusion region, and the first polysilicon layer below the floating diffusion region constitutes the well region.

[0032] Optionally, the first polysilicon layer is a P-type doped polysilicon film or a non-doped polysilicon film.

[0033] Optionally, before the step of forming the sacrificial layer, a first dielectric layer is formed on the substrate, and the first opening also penetrates the first dielectric layer.

[0034] Optionally, before the step of forming the first opening, a second dielectric layer is formed on the sacrificial layer, and the first opening also penetrates the second dielectric layer.

[0035] Optionally, after the step of etching the sacrificial layer above the substrate between adjacent photodiodes:

[0036] A fourth dielectric layer is formed to isolate the transfer gates of adjacent pixel regions.

[0037] Optionally, the step of forming a transmission gate surrounding the well region includes:

[0038] Etching the fourth dielectric layer and the second dielectric layer above the photodiode to form a third opening, wherein the third opening exposes the sacrificial layer;

[0039] The sacrificial layer is removed through the third opening, the third opening is extended to form a fourth opening, and a transmission gate is formed in the fourth opening.

[0040] Optionally, before forming the transfer gate:

[0041] A second gate oxide layer is formed, wherein the second gate oxide layer covers the top surface of the fourth dielectric layer and the bottom wall and side walls of the fourth opening.

[0042] Optionally, after the step of forming the transmission gate:

[0043] A fifth dielectric layer is formed, where the fifth dielectric layer covers the fourth dielectric layer and the top surface of the transmission gate.

[0044] Optionally, after the step of forming the fifth dielectric layer, the method further includes:

[0045] Conductive plugs are formed above the transfer gate and above the floating diffusion region, respectively.

[0046] Optionally, after the step of forming the first opening and before the step of forming the well region and the floating diffusion region, the method further includes:

[0047] A first gate oxide layer is formed on the sidewalls of the first opening.

[0048] In the 3D CMOS image sensor and the method for forming the same provided by the present invention, the transfer gate and the floating diffusion area are floated above the substrate so as not to occupy the area of ​​the photodiode in the substrate. Compared with the traditional 2D planar structure, the transfer gate and the floating diffusion area can be prevented from occupying the photodiode area, and the floating diffusion area can be freely expanded to increase the full well capacity.

[0049] The present invention allows the metal gate to surround the well region as a transmission gate, and the metal gate reduces the gate resistance and increases the response speed of the transmission gate. Furthermore, the longitudinal cross-section of the transmission gate is an inverted T-shape, so the transmission gate covers a larger area above the photodiode, which is beneficial to reflect the light transmitted from the photodiode back into the photodiode, and is beneficial to increase the light quantum efficiency.

[0050] Furthermore, a thin film cavity structure is used to form a well region. Since the well region and the floating diffusion layer are formed separately and the thin film cavity structure can be formed using a non-doped second polysilicon layer, the well region does not need additional ion implantation doping, which helps to reduce process difficulty. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 FIG. 4 is a schematic structural diagram of a 3D CMOS image sensor according to an embodiment of the present invention.

[0052] Figure 2 FIG. 4 is an enlarged schematic diagram of the structure inside the first opening of the 3D CMOS image sensor according to an embodiment of the present invention.

[0053] Figure 3 is a flow chart of a method for forming a 3D CMOS image sensor according to an embodiment of the present invention.

[0054] Figure 4 It is a schematic diagram of a substrate structure in a method for forming a 3D CMOS image sensor according to an embodiment of the present invention.

[0055] Figure 5It is a structural schematic diagram of forming a first dielectric layer, a sacrificial layer and a second dielectric layer in a method for forming a 3D CMOS image sensor according to an embodiment of the present invention.

[0056] Figure 6 It is a structural schematic diagram of forming a first opening in a method for forming a 3D CMOS image sensor according to an embodiment of the present invention.

[0057] Figure 7 It is a schematic structural diagram of a first gate oxide layer forming a first opening sidewall in a method for forming a 3D CMOS image sensor according to an embodiment of the present invention.

[0058] Figure 8 It is a structural schematic diagram of forming a first polysilicon layer and a third dielectric layer in a method for forming a 3D CMOS image sensor according to an embodiment of the present invention.

[0059] Fig. 9 It is a structural schematic diagram of forming a second opening in the method for forming a 3D CMOS image sensor according to an embodiment of the present invention.

[0060] Fig.10 It is a structural schematic diagram of forming a floating diffusion region in a method for forming a 3D CMOS image sensor according to an embodiment of the present invention.

[0061] Fig.11 It is a structural schematic diagram of etching part of the second dielectric layer and the sacrificial layer in the method for forming a 3D CMOS image sensor according to an embodiment of the present invention.

[0062] Fig.12 It is a structural schematic diagram of forming a fourth dielectric layer in the method for forming a 3D CMOS image sensor according to an embodiment of the present invention.

[0063] Fig.13 It is a structural schematic diagram of forming a third opening in the method for forming a 3D CMOS image sensor according to an embodiment of the present invention.

[0064] Fig.14 FIG. 4 is a schematic structural diagram of forming a fourth opening in a method for forming a 3D CMOS image sensor according to an embodiment of the present invention.

[0065] Fig.15 It is a structural schematic diagram of forming a second gate oxide layer in a method for forming a 3D CMOS image sensor according to an embodiment of the present invention.

[0066] Fig.16 It is a structural schematic diagram of forming a transfer gate in a method for forming a 3D CMOS image sensor according to an embodiment of the present invention.

[0067] Fig.17It is a structural schematic diagram of forming a fifth dielectric layer in the method for forming a 3D CMOS image sensor according to an embodiment of the present invention.

[0068] In the figure,

[0069] 10-substrate; 11-photodiode; 12-ion isolation region; 13-shallow trench isolation structure; 14-first dielectric layer; 15-sacrificial layer 15a-transmission gate; 15b-inversion channel region; 16-second dielectric layer; 17-first opening; 17a-first polysilicon layer; 17b-third dielectric layer; 17c-second opening; 17d-floating diffusion region; 17e-well region; 18-first gate oxide layer; 19-fourth dielectric layer; 20a-third opening; 20b-fourth opening; 20c-first conductive plug; 20d-second conductive plug; 21-second gate oxide layer; 22-fifth dielectric layer. DETAILED DESCRIPTION

[0070] The 3D CMOS image sensor and its forming method proposed by the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0071] For details, please refer to Figure 1 and Figure 2 , Figure 1 is a schematic structural diagram of a 3D CMOS image sensor according to an embodiment of the present invention, Figure 2 FIG. 1 is an enlarged schematic diagram of the structure inside the first opening of the 3D CMOS image sensor according to an embodiment of the present invention. Figure 1 and Figure 2 As shown, the present invention provides a 3D CMOS image sensor, including: a substrate 10, a well region 17e, a floating diffusion region 17d and a transmission gate 15a, wherein the substrate 10 includes a plurality of pixel regions, each of which has a photodiode 11 formed therein; the well region 17e is formed above the photodiode 11 and connected to the photodiode 11, and the well region 17e is a thin film cavity structure; the floating diffusion region 17d is formed above the substrate 10 and is located above the well region 17e and connected to the well region 17e; the transmission gate 15a is floated above the substrate 10 and surrounds the well region 17e; the transmission gate 15a is a metal gate.

[0072] Furthermore, an ion isolation region 12 and a shallow trench isolation structure 13 are formed in the substrate 10, and the shallow trench isolation structure 13 is formed above the ion isolation region 12; the non-contact inversion ion doping region formed around the photodiode 11 serves as the ion isolation region 12, so that the ion isolation region 12 can prevent the depletion layer of the PN junction in the photodiode from extending to the shallow trench isolation structure 13; the ion type of the ion implantation of the photodiode 11 is N-type, and the N-type ions are, for example, P and As, and the implantation concentration of the ion implantation needs to meet the photoelectric signal collection requirements of the photodiode 11. The ion type of the ion implantation of the ion isolation region 12 is P-type, and the P-type ions are, for example, B and BF2, and the ion isolation region is used to isolate the photodiodes of adjacent pixel regions to prevent crosstalk between adjacent photodiodes.

[0073] Furthermore, a first dielectric layer 14 is provided between the transmission gate 15a and the substrate 10, for isolating the transmission gate 15a from the substrate 10. The height of the well region 17e is higher than the height of the transmission gate 15a, that is, the top surface of the well region 17e is higher than the top surface of the transmission gate 15a, and the height of the well region 17e is greater than the sum of the heights of the transmission gate 15a and the first dielectric layer 14. Under the influence of the electric field of the transmission gate 15a, an inversion channel region 15b is formed on both sides of the well region 17e that are in contact with the transmission gate 15a, and the inversion channel region 15b can connect the floating diffusion region 17d and the photodiode 11, so that the electrons collected by the photodiode 11 can be transmitted to the floating diffusion region 17d. If the transmission gate 15a is too thick, the inversion channel region 15b formed in the well region 17e will be too long, reducing the switching speed of the device. If the transmission gate 15a is too thin, the well region 17e will be too small, increasing the difficulty of the ion implantation process.

[0074] Furthermore, the material of the transmission gate 15a is metal, such as tungsten. Using the metal gate surrounding the well region 17e as the transmission gate 15a, firstly, the metal gate reduces the gate resistance and increases the response speed of the transmission gate 15a; secondly, the longitudinal cross-section of the transmission gate 15a is an inverted T-shape, so the transmission gate covers a larger area above the photodiode, which is beneficial to reflect the light transmitted from the photodiode back into the photodiode, and is beneficial to increase the light quantum efficiency.

[0075] Furthermore, the device further includes a second dielectric layer 16 formed on the transmission gate, and the first opening 17 also penetrates the second dielectric layer 16 .

[0076] Furthermore, the projection of the transmission gate 15 a on the photodiode 11 is located within the length range of the photodiode 11 to ensure that the transmission gates 15 a separated by various pixel regions will not crosstalk with each other.

[0077] Furthermore, it also includes a first gate oxide layer 18 disposed between the transmission gate 15a and the well region 17e to isolate the transmission gate 15a from the well region 17e.

[0078] Furthermore, it also includes: a first polysilicon layer 17a, the first polysilicon layer 17a covers the side walls and the bottom wall of the first opening 17 to form the well area 17e; a third dielectric layer 17b, the third dielectric layer 17b is filled in the first opening 17; a second opening 17c, the second opening 17c is formed in the first opening 17 and is located above the third dielectric layer 17b; and a second polysilicon layer, the second polysilicon layer is filled in the second opening 17c to form the floating diffusion area 17d.

[0079] Further, the well region 17e is a thin film cavity structure, and the well region 17e can be a P-type well region, that is, the polysilicon film can be doped with P-type ions, and the P-type ions are P-type self-doping or IMP doping, and the optional ions are B and BF2. The well region 17e can also be a non-doped well region, that is, the polysilicon film is not doped with ions. In this case, the well region 17e is a fully depleted region. When the image sensor is powered on, the N-type ions of the transmission gate form an inversion channel region 15b in the well region 17e. The film thickness of the well region 17e needs to be reduced as much as possible to improve the uniformity of the transmission gate threshold voltage, but if the thickness of the well region 17e is too thin, gaps may be generated in the polysilicon film. It is also possible to deposit a thicker polysilicon film first, and then remove a portion of the polysilicon film by wet etching to reduce the thickness of the well region 17e.

[0080] Furthermore, a first conductive plug 20c is formed on the transmission gate 15a, and a second conductive plug 20d is formed on the floating diffusion area 17d. The transmission gate 15a and the floating diffusion area 17d are connected to other circuits or devices through the first conductive plug 20c and the second conductive plug 20d. The bottom size of the first conductive plug 20c is smaller than the top size of the transmission gate 15a, and the bottom size of the second conductive plug 20d is smaller than the top size of the floating diffusion area 17d, which meets the circuit layout design.

[0081] Figure 3 is a flow chart of a method for forming a 3D CMOS image sensor according to an embodiment of the present invention; this embodiment also provides a method for forming a 3D CMOS image sensor, comprising:

[0082] Step S10, providing a substrate, wherein at least one photodiode is formed in the substrate;

[0083] Step S20, forming a sacrificial layer, wherein the sacrificial layer covers the substrate;

[0084] Step S30, forming a first opening, wherein the first opening at least penetrates the sacrificial layer and exposes the photodiode;

[0085] Step S40, forming a well region and a floating diffusion region at the position of the first opening, wherein the floating diffusion region is located above the well region, and the well region is a thin film cavity structure;

[0086] Step S50, etching the sacrificial layer above the substrate between adjacent photodiodes to separate the pixel areas;

[0087] Step S60 , removing the sacrificial layer on the photodiode to form a fourth opening, and forming a transmission gate surrounding the well region at the location of the fourth opening.

[0088] Figure 4-Figure 17 3D CMOS image sensor manufacturing method of the present invention is a structural diagram of the corresponding steps; Figure 4-Figure 17 The formation process of 3D CMOS image sensor is introduced in detail.

[0089] Please refer to Figure 4 In step S10, a substrate 10 is provided, and the substrate is, for example, at least one of silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI). The substrate 10 includes a plurality of pixel regions, and each pixel region has a photodiode 11 formed thereon.

[0090] Please refer to Figure 5Before step S20, a first dielectric layer 14 is formed on the photodiode; in this embodiment, the first dielectric layer 14 is, for example, an oxide layer, and the first dielectric layer 14 can be formed by, for example, an LPCVD or PECVD process, and the first dielectric layer 14 is used to isolate the transmission gate 15a from the substrate 10. Therefore, the thickness of the first dielectric layer 14 needs to be sufficient to isolate the transmission gate 15a from the substrate 10, so as to avoid leakage between the transmission gate 15a and the substrate 10 when the transmission gate 15a is powered. The thickness of the first dielectric layer 14 should not be too thick, so as to ensure that when the transmission gate 15a is powered, the inversion channel region 15b formed in the well region 17e under the influence of the electric field of the transmission gate 15a can connect the floating diffusion region 17d and the photodiode 11, so that the photoelectrons collected by the photodiode 11 can be transmitted to the floating diffusion region 17d.

[0091] Before forming the first dielectric layer 14, an ion isolation region 12 and a shallow trench isolation structure 13 are also formed in the substrate 10, and the shallow trench isolation structure 13 is formed above the ion isolation region 12; the ion isolation region 12 and the shallow trench isolation structure 13 are both used to isolate adjacent pixel regions. The non-contact inverted ion doping region formed around the photodiode 11 serves as the ion isolation region 12, so that the ion isolation region 12 can prevent the depletion layer of the PN junction in the photodiode from extending to the shallow trench isolation structure 13; the ion type of the ion implantation of the photodiode 11 is N-type, and the N-type ions are, for example, P and As, and the implantation concentration of the ion implantation needs to meet the photoelectric signal collection requirements of the photodiode 11. The ion type of the ion implantation of the ion isolation region 12 is P-type, and the P-type ions are, for example, B and BF2, and the ion isolation region is used to isolate the photodiode region of the adjacent pixel region to prevent crosstalk between adjacent photodiodes.

[0092] Please continue to refer to Figure 5 In step S20, a sacrificial layer 15 is formed, and the sacrificial layer 15 covers the first dielectric layer 14; in this embodiment, the sacrificial layer 15 can be formed by, for example, LPCVD or PECVD process. The position of the sacrificial layer 15 will form a transmission gate 15a in the subsequent step. The thickness of the sacrificial layer 15 determines the thickness of the transmission gate 15a. The thickness of the transmission gate 15a, that is, the top surface of the sacrificial layer 15 is lower than the top surface of the well region 17e, that is, the sum of the thickness of the first dielectric layer 14 and the sacrificial layer 15 is less than the thickness of the well region 17e. If the thickness of the transmission gate 15a is too thick, the inversion channel region 15b will be too long, reducing the switching speed of the device. If the thickness of the transmission gate 15a is too thin, the well region 17e will be too small, increasing the difficulty of the ion implantation process.

[0093] Next reference Figure 5 Before step S30, a second dielectric layer 16 is formed, and the second dielectric layer 16 covers the sacrificial layer 15; in this embodiment, the second dielectric layer 16 is, for example, an oxide layer, which can be formed by LPCVD or PECVD process. The floating diffusion area 17d is formed in the second dielectric layer 16, so the height of the floating diffusion area 17d can be diffused by expanding the thickness of the second dielectric layer 16, thereby affecting the volume of the floating diffusion area 17d. The thickness of the floating diffusion area 17d increases, the volume of the floating diffusion area 17d increases, and the full well capacity increases. In this embodiment, the floating diffusion area 17d can freely expand the area, avoiding the problem in the prior art that the floating diffusion area 17d occupies the area of ​​the photodiode.

[0094] Please refer to Figure 6 In step S30, a first opening 17 is formed, and the first opening 17 penetrates the second dielectric layer 16, the sacrificial layer 15 and the first dielectric layer 14, and exposes the photodiode 11; in this embodiment, the first opening 17 is formed by a dry etching process. Before the dry etching process, a patterned photoresist is formed on the second dielectric layer 16, and the second dielectric layer 16, the sacrificial layer 15 and the first dielectric layer 14 are sequentially etched using the patterned photoresist as a mask, and the etching stops at the surface of the photodiode 11. The first opening 17 is, for example, circular, or other patterns. The size of the first opening 17 will affect the area of ​​the floating diffusion region 17d and thus affect the volume of the floating diffusion region 17d. The larger the size of the first opening 17, the greater the volume of the floating diffusion region 17d, and the full well capacity will increase, but the corresponding signal sensitivity will decrease.

[0095] Please refer to Figure 7Before step S40, a first gate oxide layer 18 is formed on the sidewall of the first opening 17, and the first gate oxide layer 18 at least covers the sidewall of the sacrificial layer 15; in this embodiment, the first gate oxide layer 18 can be formed by an ALD or LPCVD deposition process. Through the deposition process, in addition to forming the first gate oxide layer 18 on the sidewall of the sacrificial layer, the first gate oxide layer 18 is also deposited on the sidewalls of the first dielectric layer 14 and the second dielectric layer 16. These first gate oxide layers 18 will slightly thicken the thickness of the second dielectric layer 16. Since the first gate oxide layer 18 will also be deposited on the photodiode 11 exposed in the first opening 17 when the first gate oxide layer 18 is formed, it is necessary to remove the first gate oxide layer 18 on the photodiode 11 exposed in the first opening 17. The first gate oxide layer 18 on the photodiode 11 exposed in the first opening 17 can be removed by dry etching process, and no additional mask is required. The dry etching has a high etching rate on the bottom wall and the top surface, and a very low etching rate on the side wall. However, the plasma during etching will cause certain damage to the first gate oxide layer 18 on the side wall. A protective layer (not shown in the figure) can be deposited on the side wall of the first gate oxide layer 18 to protect the first gate oxide layer 18. The protective layer is, for example, a polysilicon layer or a silicon nitride layer. The protective layer will also be deposited on the bottom wall and the top surface. During dry etching, the protective layer on the top surface and the bottom wall is first removed, and then the first gate oxide layer 18 on the bottom wall is removed. Then, the protective layer on the side wall is removed by a wet process. The wet process has a high selectivity and has little effect on the first gate oxide layer 18.

[0096] Please refer to Figure 8-Figure 10 In step S40 , a well region 17 e and a floating diffusion region 17 d are formed at the location of the first opening 17 . The floating diffusion region 17 d is located above the well region 17 e . The top surface of the well region 17 e is higher than the top surface of the sacrificial layer 15 .

[0097] The step of forming a well region 17e and a floating diffusion region 17d at the position of the first opening 17 includes:

[0098] Please refer to Figure 8In step S41, a first polysilicon layer 17a is formed in the first opening 17, and the first polysilicon layer 17a covers the top surface of the second dielectric layer 16 and the sidewalls and bottom wall of the first opening; in this embodiment, the first polysilicon layer 17a can be formed by, for example, LPCVD or PECVD process, and the first polysilicon layer 17a is a polysilicon film, and the polysilicon film can be doped with P-type ions, and the P-type ions are P-type self-doping or IMP doping, and the optional ions are B, BF2. The polysilicon film may not be doped with ions. The polysilicon film may not be doped with additional ions, which reduces the difficulty of the ion implantation process. The film thickness of the polysilicon film needs to be reduced as much as possible to improve the uniformity of the transmission gate threshold voltage, but if the thickness of the polysilicon film is too thin, gaps may be generated in the polysilicon film. It is also possible to first deposit a thicker polysilicon film and then use wet etching to remove a portion of the polysilicon film to thin the thickness of the polysilicon film. The final thickness of the polysilicon film is preferably between 10nm and 30nm.

[0099] Please continue to refer to Figure 8 In step S42, a third dielectric layer 17b is formed, and the third dielectric layer 17b covers the first polysilicon layer 17a on the second dielectric layer 16 and the first polysilicon layer 17a in the first opening 17 and fills the first opening 17. In this embodiment, the third dielectric layer 17b is, for example, an oxide layer, which can be formed by LPCVD or PECVD process. The third dielectric layer 17b on the second dielectric layer 16 is removed by chemical mechanical polishing (CMP) process, so that the top surface of the third dielectric layer 17b is flush with the top surface of the first polysilicon layer 17a.

[0100] Please refer to Fig. 9 In step S43, a portion of the thickness of the third dielectric layer 17b is removed to form a second opening 17c, and the bottom wall of the second opening 17c is higher than the top surface of the sacrificial layer 15. In this embodiment, the second opening 17c is formed by a dry etching process. The first polysilicon layer 17a on the second dielectric layer 16 is used as a mask to etch a portion of the thickness of the third dielectric layer 17b, and the second opening 17c is used to form a floating diffusion area 17d. The first polysilicon layer 17a on the side wall of the second opening 17c can be retained or removed. If it is removed, it can be removed by a wet etching process. If it is retained, since the material of the floating diffusion area 17d is N-type polysilicon, and the N-type ion concentration of the floating diffusion area 17d is greater than the ion concentration in the first polysilicon layer 17a, the N-type ions in the floating diffusion area 17d can be self-diffused into the first polysilicon layer 17a on the side wall of the second opening 17c. The first polysilicon layer 17a below the second opening 17c forms a well area 17e.

[0101] Please refer to Fig.10In step S44, the second opening 17c is filled with a second polysilicon layer to form the floating diffusion region 17d, and the polysilicon thin film layer below the floating diffusion region 17d forms a well region 17e. In this embodiment, the second polysilicon layer can be formed by, for example, LPCVD or PECVD process, and the second polysilicon layer is directly doped N-type doped polysilicon, or an undoped polysilicon layer is first formed and then N-type ions are implanted by ion implantation process, and the N-type ions are, for example, P and As. The formed second polysilicon layer covers the second dielectric layer 16, and the second polysilicon layer on the second dielectric layer 16 is removed by chemical mechanical polishing process, so that the top surface of the floating diffusion region 17d is flush with the top surface of the second dielectric layer 16. The depth of the floating diffusion region 17d needs to contact the well region 17e, but cannot be lower than the area of ​​the transmission gate 15a. The thickness of the transmission gate 15a will affect the full well capacity and sensitivity.

[0102] The polysilicon film of the well region 17e can be doped with P-type ions, and the P-type ions are P-type self-doping or IMP doping to form a well region 17e connected to the photodiode; in this embodiment, the P-type ions are, for example, B and BF2, and the depth of the well region 17e needs to contact the photodiode 11. Since the depth of ion implantation is limited, the ions can be accurately diffused to the required depth by high-temperature diffusion. The well region 17e needs to ensure that after the transmission gate 15a is powered, the well region 17e can generate an inversion channel region 15b to conduct the photodiode 11 and the floating diffusion region 17d. The polysilicon film of the well region 17e can also be undoped with ions. At this time, the well region 17e is a fully depleted region, and an inversion channel region 15b can also be formed in the well region 17e to conduct the photodiode 11 and the floating diffusion region 17d. The well region 17e does not need to be doped with additional ions, which reduces the difficulty of the ion implantation process.

[0103] After the step of forming the well region 17e and the floating diffusion region 17d, the following steps are further included:

[0104] Please refer to Fig.11In step S50, the second dielectric layer 16 and the sacrificial layer 15 above the substrate between adjacent photodiodes are etched to separate the sacrificial layer 15 on each pixel area. The width of the etched second dielectric layer 16 and the sacrificial layer 15 needs to ensure that the transmission gates 15a formed subsequently after separating the pixel areas will not crosstalk with each other. The etching stops at the surface of the first dielectric layer 14 without contacting the substrate 10 to prevent the plasma from damaging the substrate 10. In this embodiment, the second dielectric layer 16 and the sacrificial layer 15 are etched by a dry etching process, and the remaining position of the sacrificial layer 15 is subsequently formed to form a transmission gate 15a, and the projection of the transmission gate 15a on the photodiode 11 is located within the length range of the photodiode 11.

[0105] Please refer to Fig.12 Before step S60, a fourth dielectric layer 19 is formed to isolate the transmission gates 15a of adjacent pixel regions. In this embodiment, the fourth dielectric layer 19 is, for example, an oxide layer, which can be formed by LPCVD or PECVD process.

[0106] Please refer to Figure 13-Figure 16 In step S60, the sacrificial layer 15 on the photodiode 11 is removed, and a transmission gate 15a surrounding the well region 17e is formed at the position after the sacrificial layer is removed.

[0107] The steps of removing the sacrificial layer 15 on the photodiode and forming a transmission gate surrounding the well region 17e at the position after the sacrificial layer 15 is removed include:

[0108] Please refer to Fig.13 In step S61, a third opening 20a is formed, and the third opening 20a penetrates the second dielectric layer 16 and the fourth dielectric layer 19, and exposes the sacrificial layer 15; in this embodiment, the third opening 20a is formed by a dry etching process. Before the dry etching process, a patterned photoresist is formed on the fourth dielectric layer 19, and the patterned photoresist is used as a mask to sequentially etch the fourth dielectric layer 19 and the second dielectric layer 16, and stop on the surface of the sacrificial layer 15, so as to form a third opening 20a that penetrates the second dielectric layer 16 and the fourth dielectric layer 19 and exposes the sacrificial layer 15. The shape of the third opening 20a needs to meet the requirements of the subsequent removal of the sacrificial layer 15 and the filling of metal. If the third opening 20a is too small, the subsequent sacrificial layer 15 cannot be completely removed, and the filling rate is problematic when the metal is filled in the subsequent filling, causing bubbles and other problems. If the third opening 20a is too large, too much metal will be consumed to fill the third opening 20a when the metal is filled in the subsequent filling, and the cost is too high.

[0109] Please refer to Fig.14In step S62, the sacrificial layer 15 is removed. In this embodiment, a wet etching process is used to remove the sacrificial layer 15. The etching solution of the wet etching is, for example, hot phosphoric acid. The etching solution of the wet etching reaches the sacrificial layer 15 through the third opening 20a to ensure that all the sacrificial layer 15 is completely removed. The third opening 20a extends to form a fourth opening 20b. The fourth opening 20b exposes the surface of the first dielectric layer 14.

[0110] Please refer to Fig.15 In step S63, a second gate oxide layer 21 is formed, and the second gate oxide layer 21 covers the top surface of the fourth dielectric layer 19 and the bottom wall and side wall of the fourth opening 20b. In this embodiment, the second gate oxide layer 21 is, for example, a gate oxide layer with a high dielectric constant.

[0111] Please refer to Fig.16 In step S64, a transmission gate 15a is formed in the fourth opening 20b. The material of the transmission gate 15a is, for example, tungsten. In this embodiment, when tungsten is deposited, the tungsten fills the fourth opening 20b and covers the second gate oxide layer 21. The second gate oxide layer 21 and the tungsten on the fourth dielectric layer 19 are removed by chemical mechanical polishing. A metal gate is used to surround the well region 17e as the transmission gate 15a. Firstly, the metal gate reduces the gate resistance and increases the response speed of the transmission gate 15a. Secondly, since the metal gate can cover the entire photodiode 11, it can be used as a reflective layer to reflect the light transmitted from the photodiode 11 back into the photodiode 11, thereby increasing the light quantum efficiency.

[0112] Please refer to Fig.17 After step S64, a fifth dielectric layer 22 is formed, and the fifth dielectric layer 22 covers the fourth dielectric layer 19 and the transmission gate 15a. In this embodiment, the fifth dielectric layer 22 is, for example, an oxide layer, which can be formed by LPCVD or PECVD process.

[0113] Please refer to Figure 1In step S70, after isolating the adjacent pixel regions, conductive plugs are formed above the transmission gate 15a and above the floating diffusion region 17d, respectively. First, a first contact hole and a second contact hole are formed above the transmission gate 15a and above the floating diffusion region 17d, respectively; second, metal is deposited in the first contact hole and the second contact hole, and the metal is, for example, tungsten; third, a chemical mechanical polishing process is used to polish and remove the metal above the fifth dielectric layer 22, to form a first conductive plug 20c located on the transmission gate and a second conductive plug 20d located on the floating diffusion region 17d. The transmission gate 15a and the floating diffusion region 17d are connected to other circuits or devices through the first conductive plug 20c and the second conductive plug 20d. The bottom size of the first conductive plug 20c is smaller than the top size of the transmission gate 15a, and the bottom size of the second conductive plug 20d is smaller than the top size of the floating diffusion region 17d, which meets the circuit layout design.

[0114] In summary, in the 3D CMOS image sensor and its formation method provided by the present invention, by floating the transmission gate and the floating diffusion area above the substrate, the area of ​​the photodiode in the substrate is not occupied. Compared with the traditional 2D planar structure, the transmission gate and the floating diffusion area can be prevented from occupying the photodiode area, and the floating diffusion area can be freely expanded to increase the full well capacity. The present invention allows the metal gate to surround the well area as a transmission gate, and the metal gate reduces the gate resistance and increases the response speed of the transmission gate. Further, the longitudinal cross-section of the transmission gate is an inverted T shape, so the transmission gate covers a larger area above the photodiode, which is conducive to reflecting the light transmitted from the photodiode back into the photodiode, which is conducive to increasing the light quantum efficiency. Further, a thin film cavity structure is used to form the well area. Since the well area and the floating diffusion layer are formed separately, and the thin film cavity structure can be formed using a non-doped second polysilicon layer, the well area does not need to be additionally ion implanted, which is conducive to reducing the process difficulty.

[0115] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A 3D CMOS image sensor, characterized in that: include: a substrate, wherein the substrate includes at least one photodiode; A well region, wherein the well region is formed above the photodiode and connected to the photodiode, and the well region is a thin film cavity structure; A floating diffusion region, wherein the floating diffusion region is formed on the substrate and is located above the well region and connected to the well region; as well as, A transmission gate, wherein the transmission gate is floated above the substrate and surrounds the well region, and the transmission gate is a metal gate; A first dielectric layer, the first dielectric layer being located between the transmission gate and the substrate; and a first opening penetrating through the first dielectric layer; a first polysilicon layer, wherein the first polysilicon layer covers the sidewalls and the bottom wall of the first opening to form the well region; a third dielectric layer, wherein the third dielectric layer is filled in the first opening; a second opening, wherein the second opening is formed in the first opening and is located above the third dielectric layer; as well as, A second polysilicon layer is formed, and the second polysilicon layer is filled in the second opening to form the floating diffusion region.

2. The 3D CMOS image sensor according to claim 1, wherein: The longitudinal cross-section of the transmission gate is in an inverted T shape.

3. The 3D CMOS image sensor according to claim 1, wherein: The first polysilicon layer is a P-type doped polysilicon film or a non-doped polysilicon film.

4. A method for forming a 3D CMOS image sensor, characterized in that: include: providing a substrate having at least one photodiode formed therein, forming a sacrificial layer, wherein the sacrificial layer covers the substrate; forming a first opening, wherein the first opening at least penetrates the sacrificial layer and exposes the photodiode; A well region and a floating diffusion region are sequentially formed at the position of the first opening, wherein the floating diffusion region is located above the well region, and the well region is a thin film cavity structure; etching the sacrificial layer above the substrate between adjacent photodiodes; as well as, removing the sacrificial layer on the photodiode to form a fourth opening, and forming a transmission gate surrounding the well region at the position of the fourth opening, wherein the transmission gate is a metal gate; The step of forming a well region and a floating diffusion region at the position of the first opening includes: forming a first polysilicon layer at the position of the first opening, wherein the first polysilicon layer covers the sidewalls and the bottom wall of the first opening; forming a third dielectric layer, wherein the third dielectric layer fills the first opening; Removing a portion of the thickness of the third dielectric layer in the first opening to form a second opening, wherein a bottom wall of the second opening is higher than a top surface of the sacrificial layer; The second opening is filled with a second polysilicon layer to form the floating diffusion region, and the first polysilicon layer below the floating diffusion region constitutes the well region.

5. The method for forming a 3D CMOS image sensor according to claim 4, wherein: The first polysilicon layer is a P-type doped polysilicon film or a non-doped polysilicon film.

6. The method for forming a 3D CMOS image sensor according to claim 4, wherein: Before the step of forming the sacrificial layer, a first dielectric layer is formed on the substrate, and the first opening also penetrates the first dielectric layer.

7. The method for forming a 3D CMOS image sensor according to claim 4, wherein: Before the step of forming the first opening, a second dielectric layer is formed on the sacrificial layer, and the first opening also penetrates the second dielectric layer.

8. The method for forming a 3D CMOS image sensor according to claim 7, wherein: After the step of etching the sacrificial layer above the substrate between adjacent photodiodes: A fourth dielectric layer is formed to isolate the transfer gates of adjacent pixel regions.

9. The method for forming a 3D CMOS image sensor according to claim 8, wherein: The step of forming a transfer gate surrounding the well region comprises: Etching the fourth dielectric layer and the second dielectric layer above the photodiode to form a third opening, wherein the third opening exposes the sacrificial layer; The sacrificial layer is removed through the third opening, the third opening is extended to form a fourth opening, and a transmission gate is formed in the fourth opening.

10. The method for forming a 3D CMOS image sensor according to claim 8, wherein: Before forming the transfer gate step: A second gate oxide layer is formed, wherein the second gate oxide layer covers the top surface of the fourth dielectric layer and the bottom wall and side walls of the fourth opening.

11. The method for forming a 3D CMOS image sensor according to claim 8, wherein: After the step of forming the transfer gate: A fifth dielectric layer is formed, where the fifth dielectric layer covers the fourth dielectric layer and the top surface of the transmission gate.

12. The method for forming a 3D CMOS image sensor according to claim 11, wherein: After the step of forming the fifth dielectric layer, the method further comprises: Conductive plugs are formed above the transfer gate and above the floating diffusion region, respectively.

13. The method for forming a 3D CMOS image sensor according to claim 4, wherein: After the step of forming the first opening and before the step of forming the well region and the floating diffusion region, the method further includes: A first gate oxide layer is formed on the sidewalls of the first opening.

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