Display panel and display device comprising a display panel

Abstract

A display panel and a display device including the same are provided. The display panel includes a main display area, an assembly area, and a peripheral area, the display panel including a substrate; a main pixel circuit and a main display element connected to the main pixel circuit, the main pixel circuit and the main display element positioned on the substrate at the main display area; an auxiliary display element positioned on the substrate at the assembly area; an auxiliary pixel circuit positioned on the substrate at the peripheral area; a connection wiring connecting the auxiliary display element to the auxiliary pixel circuit; and a first conductive layer superposed with the auxiliary display element at the assembly area, the first conductive layer including a plurality of first holes.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2021-0028967, filed on March 4, 2021, with the Korean Intellectual Property Office (KIPO), the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] One or more embodiments relate to display devices and electronic devices, and more specifically, to display devices capable of providing high-quality images and improving the quality of images output through components. Background Technology

[0003] Typically, a display device includes a display element and electronic components for controlling the electrical signals applied to the display element. These electronic components include thin-film transistors (TFTs), storage capacitors, and multiple wirings.

[0004] Recently, display devices have been used for a variety of purposes. Furthermore, due to reductions in thickness and weight, the application range of display devices has expanded. As the application range of display devices has increased, various methods for designing the shape of display devices have been researched. Summary of the Invention

[0005] In the design process for displaying high-quality images, existing display panels and display devices that include display panels will have degraded quality during image capture operations using cameras.

[0006] One or more embodiments of this disclosure relate to a display device capable of providing high-quality images and improving the quality of images output through components. However, the embodiments are illustrative, and this disclosure is not limited thereto.

[0007] Other aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practice of the presented embodiments.

[0008] According to one or more embodiments, a display panel includes a main display area, a component area, and a peripheral area. The display panel includes: a substrate; a main pixel circuit and a main display element connected to the main pixel circuit, the main pixel circuit and the main display element being positioned on the substrate at the main display area; an auxiliary display element being positioned on the substrate at the component area; an auxiliary pixel circuit being positioned on the substrate at the peripheral area; connecting wiring connecting the auxiliary display element to the auxiliary pixel circuit; and a first conductive layer being stacked with the auxiliary display element at the component area, the first conductive layer including a plurality of first holes.

[0009] The auxiliary display element may include auxiliary pixel electrodes. The first conductive layer may be positioned between the substrate and the connection wiring.

[0010] The orthogonal projection image of the first conductive layer on the substrate can be completely superimposed with the auxiliary pixel electrode.

[0011] The area of ​​the first conductive layer can be equal to or smaller than the area of ​​the auxiliary pixel electrode.

[0012] The main pixel circuit may include: a thin-film transistor, including a semiconductor layer, a gate electrode, and an electrode layer connected to the semiconductor layer; and a storage capacitor, including a lower electrode integrally formed with the gate electrode and an upper electrode positioned on the lower electrode. The first conductive layer includes the same material as the gate electrode or the upper electrode.

[0013] The display panel may further include a second conductive layer positioned in the component area between the substrate and the auxiliary display element, the second conductive layer including a plurality of second holes.

[0014] The second conductive layer can be positioned on the first conductive layer.

[0015] The first conductive layer comprises the same material as the gate electrode. The second conductive layer comprises the same material as the upper electrode.

[0016] The first conductive layer and the second conductive layer can be electrically connected to each other.

[0017] The first conductive layer can be electrically connected to the connection wiring.

[0018] The width of each of the plurality of first holes in a certain direction can be in the range of about 0.5 μm to about 5 μm.

[0019] The total area of ​​the multiple first holes can be equal to or less than 50% of the area of ​​the first conductive layer.

[0020] The plurality of first holes may have at least one of polygonal, circular, elliptical and irregular shapes, and the plurality of first holes may be arranged regularly or irregularly.

[0021] Multiple first holes can have a strip shape extending in a certain direction.

[0022] According to one or more embodiments, a display panel includes a main display area, a component area, and a peripheral area. The display panel includes: a substrate; a main pixel circuit and a main display element connected to the main pixel circuit, the main pixel circuit and the main display element being positioned on the substrate at the main display area; an auxiliary pixel circuit and an auxiliary display element connected to the auxiliary pixel circuit, the auxiliary pixel circuit and the auxiliary display element being positioned on the substrate at the component area; a transmitter positioned at one side of the auxiliary pixel circuit and the auxiliary display element at the component area; and a bottom metal layer positioned between the substrate and the auxiliary pixel circuit. The auxiliary pixel circuit includes at least one thin-film transistor. The bottom metal layer is patterned to be stacked with at least one thin-film transistor.

[0023] The bottom metal layer can be stacked with only one thin-film transistor.

[0024] The auxiliary pixel circuit may include a first thin-film transistor and a second thin-film transistor. The bottom metal layer includes a stacked portion that is stacked with the first thin-film transistor and the second thin-film transistor, respectively, and a connection portion that connects the stacked portions.

[0025] A signal or constant voltage can be applied to the bottom metal layer.

[0026] The auxiliary display element may include an auxiliary pixel electrode. The display panel also includes a pixel defining layer having an opening through which a central portion of the auxiliary pixel electrode is exposed, and the pixel defining layer includes a light-shielding material.

[0027] According to one or more embodiments, a display device includes: a display panel including a main display area, a component area, and a peripheral area; and a component positioned below the display panel at the component area. The display panel includes: a substrate; a main pixel circuit and a main display element connected to the main pixel circuit, the main pixel circuit and the main display element being positioned on the substrate at the main display area; an auxiliary display element positioned on the substrate at the component area; an auxiliary pixel circuit positioned on the substrate at the peripheral area; connecting wiring connecting the auxiliary display element to the auxiliary pixel circuit; and a first conductive layer positioned between the substrate and the auxiliary display element at the component area, the first conductive layer including a plurality of first holes.

[0028] The auxiliary display element may include an auxiliary pixel electrode. A first conductive layer is positioned between the substrate and the auxiliary pixel electrode.

[0029] The auxiliary display element may include auxiliary pixel electrodes. The orthogonal projection image of the first conductive layer on the substrate may be completely superimposed on the auxiliary pixel electrodes.

[0030] The first conductive layer can be electrically connected to the connection wiring.

[0031] Other features and advantages disclosed will become more apparent from the accompanying drawings, claims, and detailed description. Attached Figure Description

[0032] The above and other aspects and features of certain embodiments will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0033] Figures 1A to 1C This is a perspective view showing a display device according to an embodiment;

[0034] Figure 2A and Figure 2B This is a cross-sectional view showing a portion of a display device according to one or more embodiments;

[0035] Figure 3 It shows that it can be included in Figure 1A A plan view of the display panel in the display device;

[0036] Figure 4A and Figure 4B This is an equivalent circuit diagram illustrating pixels that may be included in a display device according to an embodiment;

[0037] Figure 5A and Figure 5B It is a plan view showing the arrangement of a portion of a display device according to one or more embodiments;

[0038] Figure 6 This is a cross-sectional view showing a portion of a display device according to an embodiment;

[0039] Figure 7 and Figure 8 This is a cross-sectional view showing a portion of a display device according to one or more embodiments;

[0040] Figures 9A to 9E This is a plan view showing the shape of the first conductive layer according to an embodiment;

[0041] Figure 10 This is a cross-sectional view showing a portion of a display device according to one or more embodiments;

[0042] Figure 11 It is shown Figure 10 A plan view of a portion of a component area in a display device;

[0043] Figure 12 This is a view showing the arrangement of the auxiliary pixel circuitry according to an embodiment; and

[0044] Figure 13 and Figure 14 This is a cross-sectional view showing a portion of a display device according to an embodiment. Detailed Implementation

[0045] Referring now to embodiments, examples of which are illustrated in the accompanying drawings. The same reference numerals throughout denote the same elements. In this respect, embodiments of this disclosure may take different forms and should not be construed as limited to the description set forth herein. Therefore, embodiments are described below only with reference to the drawings to explain aspects of this description. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression “at least one of a, b, and c” means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0046] Because the disclosure allows for various modifications and numerous embodiments, certain embodiments will be shown in the accompanying drawings and described in the detailed description. The effects and features of the disclosure, as well as methods for implementing them, will be illustrated with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the disclosure is not limited to the following embodiments and can be implemented in various forms.

[0047] In the following description, embodiments will be described in detail with reference to the accompanying drawings, wherein the same or corresponding elements are always represented by the same reference numerals and their descriptions may be omitted (e.g., redundant descriptions).

[0048] Although terms such as "first," "second," etc., can be used to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another.

[0049] As used herein, the singular forms “a,” “one,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0050] It will be understood that the terms “comprising,” “having,” and “including” are intended to indicate the presence of a feature or element described in the specification, and not to exclude the possibility that one or more other features or elements may be present or added.

[0051] It will also be understood that when a layer, region, or component is referred to as being "on" another layer, region, or component, the layer, region, or component may be directly on the other layer, region, or component, or may be indirectly on the other layer, region, or component with an intermediary layer, region, or component located between them.

[0052] It will be understood that when a layer, region, or element is referred to as being "connected" to another layer, region, or element, the layer, region, or element may be "directly connected" to the other layer, region, or element, or may be "indirectly connected" to the other layer, region, or element with other layers, regions, or elements situated between them. For example, when a layer, region, or element is referred to as being "electrically connected," the layer, region, or element may be directly electrically connected, or may be indirectly electrically connected with intervening layers, regions, or elements situated between them.

[0053] "A and / or B" is used here to select only A, select only B, or select both A and B. "At least one of A and B" is used to select only A, select only B, or select both A and B.

[0054] Furthermore, the word "may" is used in describing embodiments of this disclosure to refer to "one or more embodiments of this disclosure".

[0055] In the following embodiments, the x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0056] In the accompanying drawings, for clarity, the relative dimensions of elements, layers, and regions may be exaggerated and / or simplified. For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” “up,” “bottom,” “top,” etc., are used herein to describe the relationship of one element or feature as shown in the accompanying drawings to other elements or features. It will be understood that, in addition to the orientations depicted in the accompanying drawings, the spatial relative terms are intended to also cover different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, an element described as “below” or “under” other elements or features will subsequently be oriented “above” or “on” said other elements or features. Thus, the term “below” can cover both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly.

[0057] As used herein, the terms “substantially,” “about,” and similar terms are used as approximate terms rather than terms of degree, and are intended to take into account the inherent biases of measured or calculated values ​​that would be recognized by one of ordinary skill in the art. As used herein, “about” or “approximately” includes the stated value and means: within an acceptable range of deviation for a particular value, as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0058] When an embodiment can be implemented differently, the specific process sequence may differ from the described sequence. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description.

[0059] For ease of description, the dimensions of the elements in the accompanying drawings may be exaggerated or reduced. For example, the disclosure is not limited thereto because the dimensions and thicknesses of the elements in the drawings are arbitrarily shown for ease of description.

[0060] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms (such as those defined in common dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0061] Figures 1A to 1C This is a perspective view showing a display device according to an embodiment.

[0062] Reference Figure 1A The display device 1 includes a display area DA and a peripheral area NDA surrounding the display area DA. The peripheral area NDA may surround the display area DA. The display area DA includes a component area CA and a main display area MDA that at least partially surrounds the component area CA. The component area CA may display auxiliary images, and the main display area MDA may display the main image. The component area CA and the main display area MDA may display images individually or together. The peripheral area NDA may be a non-display area where display elements are not located. The display area DA may be surrounded by the peripheral area NDA (e.g., completely surrounded).

[0063] exist Figure 1AIn this embodiment, the main display area MDA is positioned around at least a portion of a component area CA. In one or more other embodiments, the display device 1 may include two or more component areas CA, and the shapes and sizes of the multiple component areas CA may differ from each other. When viewed in a direction substantially perpendicular to the top surface (e.g., a plan view) of the display device 1, the component area CA may have any of a variety of suitable shapes, such as circular, elliptical, or polygonal shapes (such as quadrilateral, star, or rhombus shapes). Although when viewed in a direction substantially perpendicular to the top surface (e.g., a plan view) of the display device 1, the component area CA may have any of a variety of suitable shapes, such as circular, elliptical, or polygonal shapes (e.g., quadrilateral, star, or rhombus shapes). Figure 1A When viewed from a substantially vertical direction on the top surface of the display device 1, the component region CA is positioned at the center of the upper part (+y direction) of the main display area MDA, which has a substantially quadrilateral shape. However, the component region CA can be positioned on or on the side of the main display area MDA, which has a quadrilateral shape, for example, positioned at the upper right or upper left of the main display area MDA. For example, in a... Figure 1B In the display device 1' shown, the component area CA with a circular shape can be positioned in the main display area MDA, or in a location such as... Figure 1C In the display device 1 shown, a component area CA with a rectangular bar shape can be positioned on the side of the main display area MDA.

[0064] Display devices 1, 1' and 1" can provide images by using multiple primary subpixels Pm located in the main display area MDA and multiple auxiliary subpixels Pa located in the component area CA.

[0065] See below for reference. Figure 2A As described, in the component area CA, component 40, which is an electronic component, can be positioned below the display panel 10 to correspond to the component area CA.

[0066] Component 40 may be an electronic element that uses light and / or sound. For example, the electronic element may be a sensor that measures distance (such as a proximity sensor), a sensor that identifies a user's body parts (e.g., fingerprint, iris, or face), a small light that outputs light, or an image sensor that captures images (e.g., a camera). Electronic elements using light may use light in any of a variety of suitable wavelengths, such as visible light, infrared light, or ultraviolet light. Electronic elements using sound may use ultrasound or sound in another frequency band. In embodiments, component 40 may include sub-components such as a light emitter and a light receiver. The light emitter and light receiver may be integrated or physically separate to form a single component 40. To reduce or minimize limitations on the functionality of component 40, component region CA may include a transmission region TA through which light and / or sound output from component 40 to the outside or traveling from the outside toward component 40 may be transmitted.

[0067] In the case of the display panel and the display device 1, 1' and 1" including the display panel according to the embodiment, when light is transmitted through the component region CA, the light transmittance of the component region CA can be equal to or greater than about 10%, more preferably equal to or greater than about 25%, about 40%, about 50%, about 85% or about 90%.

[0068] Multiple auxiliary subpixels Pa can be located within a component region CA. These auxiliary subpixels Pa can emit light to provide a specific image. The image displayed in the component region CA as an auxiliary image can have a lower resolution than the image displayed in the main display region MDA. That is, the component region CA can include a transmissive region TA through which light and sound can pass, and because pixels (e.g., auxiliary subpixels Pa) may not be located in the transmissive region TA, the number of auxiliary subpixels Pa that can be located per unit area in the component region CA can be less than the number of primary subpixels Pm located per unit area in the main display region MDA.

[0069] In the following text, Figure 1A The inventive concept is described in detail using the display device 1 as an example; however, the inventive concept can also be applied to... Figure 1B Display device 1' and Figure 1C The display device 1 is described as follows. Furthermore, although the organic light-emitting display device is described as display device 1 according to the embodiment, the disclosed display device 1 is not limited thereto. In one or more other embodiments, the display device 1 may be an inorganic light-emitting display device, an inorganic electroluminescent (EL) display device, or a quantum dot light-emitting display device. For example, the emitting layer of the display element included in the display device 1 may include organic materials, inorganic materials, quantum dots, organic materials and quantum dots, or inorganic materials and quantum dots.

[0070] Figure 2A and Figure 2B It is a cross-sectional view showing a portion of a display device according to one or more embodiments.

[0071] Reference Figure 2A The display device 1 may include a display panel 10 and a component 40 stacked with the display panel 10. A cover window for protecting the display panel 10 may also be positioned on the display panel 10.

[0072] The display panel 10 includes a component region CA and a main display region MDA. The component region CA is a region that is superimposed on the component 40 (e.g., superimposed in the z-direction or the thickness direction of the display panel 10), and the main image is displayed at the main display region MDA. The display panel 10 may include a substrate 100, a display layer DISL, a touch screen layer TSL, and an optical functional layer OFL positioned on the substrate 100, and a panel protection member PB positioned below the substrate 100.

[0073] The display layer DISL may include a circuit layer PCL, a display element layer EDL, and a sealing member ENCM such as a thin-film encapsulation layer TFE or a sealing substrate. The circuit layer PCL includes a main thin-film transistor TFTm and an auxiliary thin-film transistor TFTa. The display element layer EDL includes a main light-emitting device (main display element) EDm and an auxiliary light-emitting device (auxiliary display element) EDA, which serve as display elements. Insulating layers IL and IL' may be positioned between the substrate 100 and the display layer DISL, and within the display layer DISL. In one or more embodiments, for example, the insulating layer IL' may be between the substrate 100 and the display layer DISL, and the insulating layer IL may be within the display layer DISL.

[0074] The substrate 100 may be formed of an insulating material such as glass, quartz, and / or polymer resin. The substrate 100 may be a rigid substrate or a flexible substrate that is bendable, foldable, and / or rollable.

[0075] The main light-emitting device (EDm) and the main pixel circuit (PCm) connected to the main light-emitting device (EDm) can be positioned in the main display area (MDA) of the display panel 10. The main pixel circuit (PCm) may include at least one main thin-film transistor (TFTm) and can control the operation of the main light-emitting device (EDm). The main sub-pixel (Pm) can be realized through light emission from the main light-emitting device (EDm).

[0076] The auxiliary light-emitting device EDA can be positioned within the component region CA of the display panel 10 to realize the auxiliary sub-pixel Pa. In the illustrated embodiment, the auxiliary pixel circuit PCa for driving the auxiliary light-emitting device EDA may not be positioned within the component region CA, but may be positioned within the peripheral region NDA, which is a non-display area. Various suitable modifications can be made. In one or more other embodiments, the auxiliary pixel circuit PCa may be positioned within a portion of the main display region MDA, or may be positioned between the main display region MDA and the component region CA. That is, the auxiliary pixel circuit PCa may not be superimposed on the auxiliary light-emitting device EDA.

[0077] The auxiliary pixel circuit PCa may include at least one auxiliary thin-film transistor TFTa and may be connected (e.g., electrically connected) to the auxiliary light-emitting device EDA via a connection wiring TWL. The connection wiring TWL may be formed of a transparent conductive material. The auxiliary pixel circuit PCa may control the operation of the auxiliary light-emitting device EDA. The auxiliary sub-pixel Pa may be realized through light emission from the auxiliary light-emitting device EDA.

[0078] The portion of component area CA containing auxiliary light-emitting device EDa can be defined as auxiliary display area ADA, and the portion of component area CA not containing auxiliary light-emitting device EDa can be defined as transmission area TA.

[0079] The transmissive region TA can be the area through which light and / or signals emitted from component 40 (e.g., component 40 positioned corresponding to component region CA) or incident on component 40 are transmitted. The auxiliary display region ADA and the transmissive region TA can be alternately positioned or arranged (e.g., alternately arranged in the x-direction and / or alternately arranged in the y-direction) within component region CA. The connection wiring TWL connecting the auxiliary pixel circuit PCa to the auxiliary light-emitting device EDA can be positioned within the transmissive region TA. For example, the auxiliary pixel circuit PCa and the auxiliary light-emitting device EDA can be connected to each other via the connection wiring TWL extending in a certain direction (e.g., the x-direction). Because the connection wiring TWL can be formed of a transparent conductive material with high transmittance, the transmittance of the transmissive region TA can be ensured even though the connection wiring TWL is positioned within the transmissive region TA. In the illustrated embodiment, because the auxiliary pixel circuit PCa is not positioned within component region CA, the area of ​​the transmissive region TA can be easily increased, and the transmittance can also be increased.

[0080] like Figure 2A As shown, the display element layer EDL can be covered by a thin-film encapsulation layer TFE or a sealing substrate. In an embodiment, as... Figure 2A As shown, the thin-film encapsulation layer TFE may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, the thin-film encapsulation layer TFE may include a first inorganic encapsulation layer 131 and a second inorganic encapsulation layer 133, and an organic encapsulation layer 132 positioned between the first inorganic encapsulation layer 131 and the second inorganic encapsulation layer 133.

[0081] Each of the first inorganic encapsulation layer 131 and the second inorganic encapsulation layer 133 may include at least one inorganic insulating material, such as silicon oxide (SiO2) or silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y Aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO) x (ZnO) x It can be ZnO and / or ZnO2), and can be formed using methods such as chemical vapor deposition (CVD). The organic encapsulation layer 132 can include polymeric materials. Examples of polymeric materials can include silicone resins, acrylic resins (e.g., polymethyl methacrylate or polyacrylic acid resin), epoxy resins, polyimides, and polyethylene.

[0082] The first inorganic encapsulation layer 131, the organic encapsulation layer 132, and the second inorganic encapsulation layer 133 can be integrally formed to cover the main display area MDA and the component area CA.

[0083] When the display element layer EDL is sealed with a sealing substrate, the sealing substrate may face the substrate 100, and the display element layer EDL may be located between the sealing substrate and the substrate 100. A gap may exist between the sealing substrate and the display element layer EDL. The sealing substrate may include glass. A sealant, such as glass frit, may be positioned between the substrate 100 and the sealing substrate, and may be positioned within the peripheral region NDA. The sealant positioned within the peripheral region NDA may surround the display region DA and may prevent or reduce the penetration of moisture through the side surfaces.

[0084] A touchscreen layer (TSL) can obtain coordinate information based on external input (e.g., touch events). A TSL may include touch electrodes and touch wiring connected to the touch electrodes. The TSL can detect external input using either self-capacitance or mutual capacitance methods.

[0085] The touchscreen layer TSL can be formed on the thin-film encapsulation layer TFE. Alternatively, the touchscreen layer TSL can be formed separately on the touch substrate and then bonded to the thin-film encapsulation layer TFE by an adhesive layer such as optically clear adhesive (OCA). In an embodiment, the touchscreen layer TSL can be formed directly on the thin-film encapsulation layer TFE, and in this case, no adhesive layer may be positioned between the touchscreen layer TSL and the thin-film encapsulation layer TFE.

[0086] The optical functional layer OFL may include an anti-reflective layer. The anti-reflective layer can reduce the reflectivity of light (e.g., external light) incident on the display device 1.

[0087] In one embodiment, the optical functional layer OFL can be a polarizing film. The optical functional layer OFL can have an opening OFL_OP corresponding to the transmission region TA. Therefore, the transmittance of the transmission region TA can be increased (e.g., significantly increased). A transparent material such as optically transparent resin (OCR) can fill the opening OFL_OP. In one or more other embodiments, the optical functional layer OFL can be configured as a filter plate including a black matrix and color filters.

[0088] The panel protection member PB can be attached to the bottom of the substrate 100 and can support and protect the substrate 100. The panel protection member PB can have an opening PB_OP corresponding to the component area CA. Because the panel protection member PB has an opening PB_OP, the light transmittance of the component area CA can be increased. The panel protection member PB can include polyethylene terephthalate or polyimide.

[0089] The component area CA can be larger than the area where component 40 is located. Therefore, the area of ​​the opening PB_OP of the panel protection member PB can be different from the area of ​​the component area CA. Although in Figure 2A The middle component 40 is positioned on one side of the display panel 10 to be spaced apart from the display panel 10, but at least a portion of the component 40 can be inserted into an opening PB_OP formed in the panel protection member PB.

[0090] Furthermore, multiple components 40 may be located within the component region CA. The multiple components 40 may have the same or different functions. For example, the multiple components 40 may include at least two of a camera (e.g., an image acquisition device), a solar cell, a flash, a proximity sensor, an illumination sensor, and an iris sensor.

[0091] Despite Figure 2A The bottom metal layer BML, located below the auxiliary light-emitting device EDa in component region CA, is not shown in the diagram. However, the display device 1 according to the embodiment may include, for example, the bottom metal layer BML. Figure 2B The bottom metal layer BML is shown in the diagram. In an embodiment, the bottom metal layer BML may be positioned in the peripheral region NDA between the substrate 100 and the auxiliary pixel circuit PCa, to be superimposed on the auxiliary pixel circuit PCa (e.g., superimposed in the z-direction or the thickness direction of the substrate 100). The bottom metal layer BML can prevent or substantially prevent external light from reaching the auxiliary pixel circuit PCa. In one or more other embodiments, the bottom metal layer BML may be formed to correspond to the entire display area DA and may have a bottom hole corresponding to the component area CA.

[0092] Figure 3 It shows that it can be included in Figure 1A A plan view of the display panel in a display device.

[0093] Reference Figure 3 Various components of the display panel 10 are positioned on the substrate 100.

[0094] Multiple primary sub-pixels Pm are positioned within the main display area MDA. Each of the primary sub-pixels Pm can be implemented as a light-emitting device using a display element such as an organic light-emitting diode (OLED). A primary pixel circuit PCm for driving the primary sub-pixels Pm can be positioned within the main display area MDA to be superimposed on the primary sub-pixels Pm. Each primary sub-pixel Pm can emit, for example, red, green, blue, or white light. The main display area MDA can be covered by a sealing component and protected from external air or moisture.

[0095] As described above, the component region CA can be located on the side of the main display region MDA, or it can be located inside the display region DA and surrounded by the main display region MDA. Multiple auxiliary sub-pixels Pa are located within the component region CA. Each of the multiple auxiliary sub-pixels Pa can be implemented as a light-emitting device using a display element such as an organic light-emitting diode (OLED). Each auxiliary sub-pixel Pa can emit, for example, red, green, blue, or white light. The component region CA can be covered by a sealing member and protected from external air or moisture.

[0096] The auxiliary pixel circuit PCa used to drive the auxiliary sub-pixel Pa can be located in the peripheral region NDA, close to the component region CA. For example, as Figure 3 As shown, when the component region CA is positioned above the display region DA, the auxiliary pixel circuit PCa can be positioned above the peripheral region NDA. The auxiliary pixel circuit PCa and the display element for implementing the auxiliary sub-pixel Pa can be positioned in a certain direction (e.g., as shown in the diagram). Figure 3 The connecting wires TWL extending in the y-direction shown in the diagram are connected to each other.

[0097] In the embodiment, although the auxiliary pixel circuit PCa is in Figure 3 The auxiliary pixel circuit PCa is positioned above (e.g., directly above) the component region CA, but the disclosure is not limited thereto. In one or more other embodiments, the auxiliary pixel circuit PCa may be positioned below, to the right of, and / or to the left of the component region CA, provided that the connection wiring TWL connecting the auxiliary pixel circuit PCa and the display element for implementing the auxiliary sub-pixel Pa is appropriately modified.

[0098] In one embodiment, the component region CA may include a transmission region TA. The transmission region TA may surround a plurality of auxiliary sub-pixels Pa. Optionally, the transmission region TA and the plurality of auxiliary sub-pixels Pa may be arranged in a grid pattern.

[0099] Because the component area CA includes the transmission area TA, the resolution of the component area CA can be lower than the resolution of the main display area MDA. For example, the resolution of the component area CA can be approximately 1 / 2, 3 / 8, 1 / 3, 1 / 4, 2 / 9, 1 / 8, 1 / 9, or 1 / 16 of the resolution of the main display area MDA. For example, the resolution of the main display area MDA can be approximately 400 ppi or greater, and the resolution of the component area CA can be approximately 200 ppi or approximately 100 ppi.

[0100] The main pixel circuit PCm and the auxiliary pixel circuit PCa, which drive the main sub-pixel Pm and the auxiliary sub-pixel Pa respectively, can be connected (e.g., electrically connected) to external circuitry located in the peripheral region NDA. The first scan drive circuit SDR1, the second scan drive circuit SDR2, the pad (also called a "solder pad") unit PAD, the drive voltage supply line 11, and the common voltage supply line 13 can be located in the peripheral region NDA.

[0101] The first scan drive circuit SDR1 can apply a scan signal to the main pixel circuit PCm for driving the main sub-pixel Pm via the scan line SL. Furthermore, the first scan drive circuit SDR1 can apply an emission control signal to each pixel circuit via the emission control line EL. The second scan drive circuit SDR2 can be symmetrical to the first scan drive circuit SDR1 with respect to the main display area MDA. Some of the main pixel circuits PCm of the main sub-pixel Pm in the main display area MDA can be connected (e.g., electrically connected) to the first scan drive circuit SDR1, and other main pixel circuits PCm can be connected (e.g., electrically connected) to the second scan drive circuit SDR2.

[0102] The pad unit PAD can be positioned on the side of the substrate 100. The pad unit PAD is exposed without being covered by an insulating layer and is connected to the display circuit board 30. The display driver 32 can be positioned on the display circuit board 30.

[0103] The display driver 32 can generate control signals that are transmitted to the first scan drive circuit SDR1 and the second scan drive circuit SDR2. The display driver 32 can generate data signals, and the generated data signals can be transmitted to the main pixel circuit PCm through the fan-out wiring FW and the main data line DLm connected to the fan-out wiring FW.

[0104] The display driver 32 can drive voltage ELVDD (see...) Figure 4A ) is supplied to drive voltage supply line 11, and the common voltage ELVSS (see Figure 4A The driving voltage ELVDD can be applied to the pixel circuits PCm and PCa of the main sub-pixel Pm and the auxiliary sub-pixel Pa through the driving voltage line PL connected to the driving voltage supply line 11, and the common voltage ELVSS can be applied to the counter electrode of the display element connected to the common voltage supply line 13.

[0105] The drive voltage supply line 11 can be positioned below the main display area MDA and can extend in the x direction. The common voltage supply line 13 can be shaped with an open side (e.g., as shown in the image). Figure 3The annular shape of the base 100 shown (the opening side at the side of the base 100) can be around or partially around the main display area MDA (e.g., partially around the main display area MDA).

[0106] Despite Figure 3 The diagram illustrates a component region CA, but multiple component regions CA can be configured. In this case, the multiple component regions CA can be spaced apart from each other, with a first camera positioned corresponding to one component region CA and a second camera positioned corresponding to another component region CA. Optionally, a camera can be positioned corresponding to one component region CA, and an infrared sensor can be positioned corresponding to another component region CA. The shapes and sizes of the multiple component regions CA can differ from each other.

[0107] Figure 4A and Figure 4B This is an equivalent circuit diagram illustrating pixels that may be included in a display device according to an embodiment.

[0108] Reference Figure 4A and Figure 4B The main sub-pixel Pm includes a main pixel circuit PCm and a main organic light-emitting diode (OLED) as a display element connected to the main pixel circuit PCm, and the auxiliary sub-pixel Pa includes an auxiliary pixel circuit PCa and an auxiliary organic light-emitting diode (OLED)' as a display element connected to the auxiliary pixel circuit PCa. Although the auxiliary sub-pixel Pa includes Figure 4A The pixel circuit and the main sub-pixel Pm include Figure 4B The pixel circuitry is described, but the disclosure is not limited thereto. In one or more other embodiments, the main sub-pixel Pm and the auxiliary sub-pixel Pa may include... Figure 4A and Figure 4B At least one of the pixel circuits. For example, both the main sub-pixel Pm and the auxiliary sub-pixel Pa can include... Figure 4B Pixel circuit.

[0109] Figure 4A The auxiliary pixel circuit PCa may include a driving thin-film transistor T1, a switching thin-film transistor T2, and a storage capacitor Cst. The switching thin-film transistor T2 is connected to the auxiliary scan line SLa and the auxiliary data line DLa, and transmits the data signal Dm input through the auxiliary data line DLa to the driving thin-film transistor T1 according to the scan signal Sn input through the auxiliary scan line SLa.

[0110] The storage capacitor Cst is connected to the switching thin-film transistor T2 and the auxiliary drive voltage line PLA, and stores the voltage corresponding to the difference between the voltage received from the switching thin-film transistor T2 and the drive voltage ELVDD supplied to the auxiliary drive voltage line PLA.

[0111] The driving thin-film transistor T1 can be connected to the auxiliary driving voltage line PLA and the storage capacitor Cst, and can control the driving current flowing from the auxiliary driving voltage line PLA through the auxiliary organic light-emitting diode OLED' in response to the value of the voltage stored in the storage capacitor Cst. The auxiliary organic light-emitting diode OLED' can emit light with a certain brightness according to the driving current.

[0112] Despite Figure 4A The auxiliary pixel circuit PCa includes two thin-film transistors and a storage capacitor, but the disclosure is not limited thereto. In one or more other embodiments, the auxiliary pixel circuit PCa may include seven thin-film transistors and a storage capacitor. In one or more other embodiments, the auxiliary pixel circuit PCa may include two or more storage capacitors.

[0113] Reference Figure 4B The main pixel circuit PCm may include a driving thin-film transistor T1, a switching thin-film transistor T2, a compensation thin-film transistor T3, a first initialization thin-film transistor T4, an operation control thin-film transistor T5, an emission control thin-film transistor T6, and a second initialization thin-film transistor T7.

[0114] Despite Figure 4B Each main pixel circuit PCm includes (main) signal lines (e.g., SLm, SL-1, SL+1, EL, and DLm), a (main) initialization voltage line VL, and a (main) drive voltage line PLm, but the disclosure is not limited thereto. In one or more other embodiments, at least one of the (main) signal lines (e.g., SLm, SL-1, SL+1, EL, and DLm) and the (main) initialization voltage line VL may be shared with adjacent pixel circuits.

[0115] The drain electrode of the driving thin-film transistor T1 can be connected (e.g., electrically connected) to the main organic light-emitting diode (OLED) via the emitter control thin-film transistor T6. The driving thin-film transistor T1 receives the data signal Dm according to the switching operation of the switching thin-film transistor T2 and supplies driving current to the main OLED.

[0116] The gate electrode of the switching thin-film transistor T2 is connected to the main scan line SLm, and the source electrode of the switching thin-film transistor T2 is connected to the main data line DLm. The drain electrode of the switching thin-film transistor T2 can be connected to the source electrode of the driving thin-film transistor T1, and can be connected to the main drive voltage line PLm via the operation control thin-film transistor T5.

[0117] The switching thin-film transistor T2 is turned on according to the scan signal Sn received through the main scan line SLm, and performs a switching operation to transmit the data signal Dm transmitted through the main data line DLm to the source electrode of the driving thin-film transistor T1.

[0118] The gate electrode of the compensation thin-film transistor T3 can be connected to the main scan line SLm. The source electrode of the compensation thin-film transistor T3 can be connected to the drain electrode of the driving thin-film transistor T1, and can be connected to the pixel electrode of the main organic light-emitting diode (OLED) via the emission control thin-film transistor T6. The drain electrode of the compensation thin-film transistor T3 can be connected to one electrode of the storage capacitor Cst, the source electrode of the first initialization thin-film transistor T4, and the gate electrode of the driving thin-film transistor T1. The compensation thin-film transistor T3 is turned on according to the scan signal Sn received through the main scan line SLm, and the driving thin-film transistor T1 is diode-connected by connecting the gate electrode of the driving thin-film transistor T1 to the drain electrode.

[0119] The gate electrode of the first initialization thin-film transistor T4 can be connected to the previous scan line SL-1. The drain electrode of the first initialization thin-film transistor T4 can be connected to the initialization voltage line VL. The source electrode of the first initialization thin-film transistor T4 can be connected to one electrode of the storage capacitor Cst, the drain electrode of the compensation thin-film transistor T3, and the gate electrode of the driving thin-film transistor T1. The first initialization thin-film transistor T4 can be turned on according to the previous scan signal Sn-1 received through the previous scan line SL-1, and can perform an initialization operation to initialize the voltage of the gate electrode of the driving thin-film transistor T1 by supplying the initialization voltage Vint to the gate electrode of the driving thin-film transistor T1.

[0120] The gate electrode of the operational control thin-film transistor T5 can be connected to the emitter control line EL. The source electrode of the operational control thin-film transistor T5 can be connected to the main drive voltage line PLm. The drain electrode of the operational control thin-film transistor T5 is connected to the source electrode of the driving thin-film transistor T1 and the drain electrode of the switching thin-film transistor T2.

[0121] The gate electrode of the emission control thin-film transistor T6 can be connected to the emission control line EL. The source electrode of the emission control thin-film transistor T6 can be connected to the drain electrode of the driving thin-film transistor T1 and the source electrode of the compensation thin-film transistor T3. The drain electrode of the emission control thin-film transistor T6 can be connected (e.g., electrically connected) to the pixel electrode of the main organic light-emitting diode (OLED). The operation control thin-film transistor T5 and the emission control thin-film transistor T6 can be synchronously (e.g., simultaneously) turned on according to the emission control signal En received through the emission control line EL, so that the driving voltage ELVDD is supplied to the main organic light-emitting diode (OLED) and the driving current flows through the main organic light-emitting diode (OLED).

[0122] The gate electrode of the second initialization thin-film transistor T7 can be connected to the next scan line SL+1. The source electrode of the second initialization thin-film transistor T7 can be connected to the pixel electrode of the main organic light-emitting diode (OLED). The drain electrode of the second initialization thin-film transistor T7 can be connected to the initialization voltage line VL. The second initialization thin-film transistor T7 can be turned on according to the next scan signal Sn+1 received through the next scan line SL+1, and can initialize the pixel electrode of the main organic light-emitting diode (OLED).

[0123] Despite Figure 4B The first initialization thin-film transistor T4 and the second initialization thin-film transistor T7 are respectively connected to the previous scan line SL-1 and the next scan line SL+1, but the disclosure is not limited thereto. In one or more other embodiments, both the first initialization thin-film transistor T4 and the second initialization thin-film transistor T7 can be connected to the previous scan line SL-1 and can be driven according to the previous scan signal Sn-1.

[0124] The other electrode of the storage capacitor Cst can be connected to the main drive voltage line PLm. Either electrode of the storage capacitor Cst can be connected to the gate electrode of the driving thin-film transistor T1, the drain electrode of the compensation thin-film transistor T3, and / or the source electrode of the first initialization thin-film transistor T4.

[0125] The counter electrode (e.g., cathode) of the main organic light-emitting diode (OLED) receives a common voltage ELVSS. The main organic light-emitting diode (OLED) can receive drive current from the driving thin-film transistor T1 and can emit light.

[0126] In the main pixel circuit PCm and auxiliary pixel circuit PCa according to the embodiment, the number of thin-film transistors and storage capacitors, as well as the circuit design, are not limited to those described above. Figure 4A and Figure 4B The number of thin-film transistors and storage capacitors and the circuit design are described, and their number and circuit design can be changed in various suitable ways.

[0127] Figure 5A and Figure 5B This is a plan view illustrating the arrangement of a portion of a display device according to one or more embodiments. In detail, Figure 5A and Figure 5B The component area CA, a portion of the main display area MDA adjacent to the component area CA, and a portion of the peripheral area NDA are shown.

[0128] Reference Figure 5AMultiple primary subpixels Pm can be located within the main display area MDA. The term "subpixel" (which is the smallest unit used to form an image) as used herein refers to the emitting region that emits light through the display element. When an organic light-emitting diode (OLED) is used as the display element, the emitting region can be defined by an opening in the pixel-defining layer, as will be described below. Each of the multiple primary subpixels Pm can emit any of red, green, blue, and white light.

[0129] In an embodiment, the primary sub-pixel Pm located in the main display area MDA may include a first sub-pixel Pr, a second sub-pixel Pg, and a third sub-pixel Pb. The first sub-pixel Pr, the second sub-pixel Pg, and the third sub-pixel Pb may represent red, green, and blue, respectively. The primary sub-pixel Pm may be... structure( (This is a registered trademark of Samsung Display Co., Ltd. of South Korea) or RGBG matrix structure arrangement.

[0130] For example, the first sub-pixel Pr can be located at the first and third vertices facing each other among the vertices of the virtual quadrilateral, and the center point of the second sub-pixel Pg serves as the center point of the virtual quadrilateral, while the third sub-pixel Pb can be located at the second and fourth vertices, which are the remaining vertices. In an embodiment, the size (i.e., emission size) of the second sub-pixel Pg can be smaller than the size (e.g., emission size) of each of the first sub-pixel Pr and the third sub-pixel Pb.

[0131] This pixel arrangement structure can be called an RGBG matrix structure. Matrix structure or The structure allows for the use of a rendering-driven approach that represents color by sharing adjacent pixels, thus enabling the display of high-resolution images with a relatively small number of pixels.

[0132] Despite Figure 5A Multiple principal sub-pixels Pm in The arrangement can be matrix-structured, but is not limited to this. For example, multiple principal sub-pixels Pm can be arranged in any of a variety of suitable structures, such as stripe, mosaic, or triangular arrangements.

[0133] In the main display area (MDA), the main pixel circuit PCm can be stacked with the main sub-pixel Pm, and the main pixel circuit PCm can be arranged in a matrix in the x and y directions. Here, the main pixel circuit PCm refers to the unit of pixel circuit used to implement a single main sub-pixel Pm.

[0134] Multiple auxiliary subpixels Pa can be positioned within the component region CA. Each of the multiple auxiliary subpixels Pa can emit any one of red, green, blue, and white light. The auxiliary subpixels Pa can include a first subpixel Pr', a second subpixel Pg', and a third subpixel Pb' that emit light of different colors from each other. The first subpixel Pr', the second subpixel Pg', and the third subpixel Pb' can represent red, green, and blue, respectively.

[0135] The number of auxiliary sub-pixels Pa per unit area in the component region CA can be less than the number of primary sub-pixels Pm per unit area in the main display region MDA. The ratio between the number of auxiliary sub-pixels Pa and the number of primary sub-pixels Pm per unit area can be 1:2, 1:4, 1:8, or 1:9. That is, the ratio between the resolution of the component region CA and the resolution of the main display region MDA can be 1 / 2, 1 / 4, 1 / 8, or 1 / 9. Figure 5A In the main display area (MDA), the resolution of the component area (CA) is 1 / 8 of the resolution of the main display area (MDA).

[0136] The auxiliary subpixels Pa located in the component region CA can be arranged in any of a variety of suitable structures. Some of the auxiliary subpixels Pa can be grouped together to form a pixel group, and can be arranged within the pixel group in various suitable structures (such as... Any of the following arrangements (structure, stripe structure, mosaic arrangement structure, or triangular arrangement structure). In this case, the distance between auxiliary sub-pixels Pa located in the pixel group can be the same as the distance between primary sub-pixels Pm.

[0137] Optionally, such as Figure 5A As shown, auxiliary sub-pixels Pa can be distributed within the component region CA. That is, the distance between auxiliary sub-pixels Pa (e.g., between adjacent auxiliary sub-pixels Pa) can be greater than the distance between primary sub-pixels Pm (e.g., between adjacent primary sub-pixels Pm). The portion of the component region CA without located auxiliary sub-pixels Pa can be a transmissive region TA with high light transmittance.

[0138] The auxiliary pixel circuit PCa, used to achieve light emission from the auxiliary sub-pixel Pa, can be located in the peripheral region NDA. Because the auxiliary pixel circuit PCa is not located in the component region CA, the component region CA can ensure a wider transmission region TA.

[0139] The auxiliary pixel circuit PCa can be connected to the auxiliary sub-pixel Pa via connecting wires TWL. Therefore, RC delay occurs as the length of the connecting wires TWL increases. Thus, the length of the connecting wires TWL should be considered when arranging the auxiliary pixel circuit PCa.

[0140] In an embodiment, the auxiliary pixel circuit PCa can be positioned on an extension line connecting the auxiliary sub-pixels Pa arranged in the y-direction. Furthermore, the number of auxiliary pixel circuits PCa arranged in the y-direction can be the same as the number of auxiliary sub-pixels Pa arranged in the y-direction. For example, as... Figure 5A As shown, when two auxiliary sub-pixels Pa are arranged in the y-direction in the component region CA, two auxiliary pixel circuits PCa can be arranged in the y-direction in the peripheral region NDA.

[0141] The connection wiring TWL can extend in the y-direction to connect the auxiliary sub-pixel Pa to the auxiliary pixel circuit PCa respectively. When the connection wiring TWL is connected to the auxiliary sub-pixel Pa, this can mean that the connection wiring TWL is connected (e.g., electrically connected) to the pixel electrode of the display element used to implement the auxiliary sub-pixel Pa.

[0142] The scan line SL may include a main scan line SLm connected to the main pixel circuit PCm and an auxiliary scan line SLa connected to the auxiliary pixel circuit PCa. The main scan line SLm may extend in the x-direction and may be connected to the main pixel circuit PCm located in the same row. The main scan line SLm may not be located in the component region CA. That is, the main scan line SLm may be disconnected and the component region CA may be between the main scan lines SLm. In this case, the main scan line SLm located on the left side of the component region CA may be connected from the first scan drive circuit SDR1 (e.g., see...). Figure 3 The main scan line SLm, located to the right of component region CA, receives signals from the second scan drive circuit SDR2 (e.g., see...). Figure 3 ) Receive signals.

[0143] The auxiliary scan line SLa can extend in the x-direction and can be connected to the auxiliary pixel circuit PCa located in the same row. The auxiliary scan line SLa can be located in the peripheral region NDA.

[0144] The main scan line SLm and the auxiliary scan line SLa can be connected to each other via the scan connection line SWL, and the same signal can be applied to the pixel circuit to drive the main sub-pixel Pm and the auxiliary sub-pixel Pa located in the same row. The scan connection line SWL can be located on different layers or at different locations from the main scan line SLm and the auxiliary scan line SLa, and the scan connection line SWL can be connected to the main scan line SLm and the auxiliary scan line SLa through corresponding contact holes. The scan connection line SWL can be located in the peripheral area NDA.

[0145] The data line DL may include a main data line DLm connected to the main pixel circuit PCm and an auxiliary data line DLa connected to the auxiliary pixel circuit PCa. The main data line DLm may extend in the y-direction and may be connected to the main pixel circuit PCm located in the same column. The auxiliary data line DLa may extend in the y-direction and may be connected to the auxiliary pixel circuit PCa located in the same column.

[0146] The main data line DLm and the auxiliary data line DLa can be spaced apart from each other, and the component area CA is located between the main data line DLm and the auxiliary data line DLa. The main data line DLm and the auxiliary data line DLa can be connected to each other via the data connection line DWL to apply the same signal to the pixel circuitry to drive the main sub-pixel Pm and the auxiliary sub-pixel Pa located in the same column.

[0147] Data connection lines (DWLs) can be positioned to bypass component regions (CAs). For example, the data connection line (DWL) may not overlap with the component region (CA). In an embodiment, the data connection line (DWL) may overlap with the main pixel circuitry (PCm) located in the main display region (MDA). Since the data connection line (DWL) is located in the main display region (MDA), it is not necessary to ensure that a separate space is provided for the data connection line (DWL), thereby minimizing the size of deadspace.

[0148] In one or more other embodiments, the data connection line (DWL) may be located in the intermediate region between the main display area (MDA) and the component area (CA).

[0149] The data connection cable DWL can be positioned on different layers or at different locations from the main data line DLm and the auxiliary data line DLa, and the data connection cable DWL can be connected to the main data line DLm and the auxiliary data line DLa through corresponding contact holes.

[0150] Despite Figure 5A The intermediate connecting wiring TWL is formed integrally from the peripheral region NDA to the auxiliary sub-pixel Pa of the component region CA, but the disclosure is not limited thereto.

[0151] like Figure 5B As shown, the connection wiring TWL may include a first connection wiring TWL1 and a second connection wiring TWL2 formed of different materials from each other.

[0152] The first connection wiring TWL1 can be located in the peripheral region NDA and can be connected to the auxiliary pixel circuit PCa. The first connection wiring TWL1 can include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and can have a single-layer or multi-layer structure comprising the aforementioned materials. Multiple first connection wirings TWL1 can be disposed between the auxiliary pixel circuits PCa. In an embodiment, the first connection wiring TWL1 can include a first-1 connection wiring TWL1a and a first-2 connection wiring TWL1b located on or at different layers. For example, the first-1 connection wiring TWL1a and the data line DL can be located on or at the same layer and can comprise the same material. The first-2 connection wiring TWL1b and the first-1 connection wiring TWL1a can be positioned with an insulating layer between them. The first-first connecting wire TWL1a and the first-second connecting wire TWL1b can be positioned between the auxiliary pixel circuits PCa, and at least a portion of each of the first-first connecting wire TWL1a and the first-second connecting wire TWL1b can be bent in the plan view. Multiple first-first connecting wires TWL1a and multiple first-second connecting wires TWL1b can be positioned on different layers or at different locations, and the first-first connecting wires TWL1a and the first-second connecting wire TWL1b can be arranged alternately among multiple auxiliary pixel circuits PCa.

[0153] The second connection wiring TWL2 can be located within the component region CA and can be connected to the first connection wiring TWL1 at the edge of the component region CA. The second connection wiring TWL2 may include a transparent conductive material.

[0154] The first connection wiring TWL1 and the second connection wiring TWL2 can be located on the same layer or at the same location, or they can be located on different layers or at different locations. When the first connection wiring TWL1 and the second connection wiring TWL2 are located on different layers or at different locations, the first connection wiring TWL1 and the second connection wiring TWL2 can be connected to each other through contact holes.

[0155] The first connection wiring TWL1 can have a higher conductivity than the second connection wiring TWL2. Because the first connection wiring TWL1 is located in the peripheral NDA region, it is not necessary to ensure light transmittance. Therefore, the first connection wiring TWL1 can include a material with lower light transmittance than the material of the second connection wiring TWL2 but higher conductivity. Thus, the resistance value of the connection wiring TWL can be reduced.

[0156] like Figure 5BAs shown, the lengths of the multiple second connection lines TWL2 can be the same. For example, the ends of the multiple second connection lines TWL2 can extend to the boundary of the component region CA opposite to the boundary where the auxiliary pixel circuit PCa is located. This can be used to match the electrical load caused by the second connection lines TWL2. Therefore, the brightness deviation in the component region CA can be minimized or reduced. The number of second connection lines TWL2 in the component region CA can be the same as the number of auxiliary pixel circuits PCa.

[0157] In the illustrated embodiment, the first conductive layer MM1 may be stacked with an auxiliary sub-pixel Pa located in the component region CA. When the first conductive layer MM1 is described as being stacked with the auxiliary sub-pixel Pa (e.g., stacked in the z-direction or the thickness direction of the substrate 100), this may refer to the first conductive layer MM1 being stacked with an auxiliary display element EDa (e.g., stacked in the z-direction or the thickness direction of the substrate 100).

[0158] The first conductive layer MM1 may have multiple pores. In an embodiment, the first conductive layer MM1 may have a mesh structure. The first conductive layer MM1 may include a reflective metal film, which may include silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), their compounds, or mixtures thereof.

[0159] As described above, the auxiliary sub-pixel Pa may include a first sub-pixel Pr', a second sub-pixel Pg', and a third sub-pixel Pb' that emit light of different colors from each other, and the first sub-pixel Pr', the second sub-pixel Pg', and the third sub-pixel Pb' may have different sizes from each other. Because the first conductive layer MM1 is stacked with each of the first sub-pixel Pr', the second sub-pixel Pg', and the third sub-pixel Pb' (e.g., stacked in the z-direction or the thickness direction of the substrate 100), the size (e.g., area) of the first conductive layer MM1 may be different for each of the auxiliary sub-pixels Pa.

[0160] The component region CA includes the transmission region TA as described above, and an image can be captured when an image is formed due to light incident on the component 40 through the transmission region TA.

[0161] In the comparative example, a portion of the light passing through the transmission region TA can be reflected, refracted, and diffracted by a portion of component 40 (e.g., a camera lens), and can re-enter that portion of component 40 (e.g., the camera lens). In this case, the reflected light can be incident on component 40. Because the reflected light has some noise, component 40 will have distorted information. For example, when component 40 is a camera including an image sensor, the image captured by the camera will differ from the actual image. Thus, when the reflected light re-enters the camera lens, a ghosting occurs, where an unexpected double image is formed that differs from the actual image.

[0162] Therefore, in the display device 1 according to the embodiment, the first conductive layer MM1 is stacked with the auxiliary sub-pixel Pa located in the component region CA (e.g., stacked in the z-direction or the thickness direction of the substrate 100). Thus, because light passing through the transmission region TA and being reflected, refracted, and diffracted by the component 40 is scattered by the first conductive layer MM1, reflected light can be prevented or substantially prevented from re-entering the component 40, thereby improving the reliability of the information output from the component 40. In other words, the amount of reflected light that may re-enter the component 40 can be minimized or reduced.

[0163] Figure 6 This is a cross-sectional view showing a portion of a display device according to an embodiment. Figure 7 and Figure 8 It is a cross-sectional view showing a portion of a display device according to one or more embodiments.

[0164] Figure 6 This is a cross-sectional view showing a portion of the display panel 10 according to an embodiment, particularly a cross-sectional view showing a portion of the main display area MDA, a portion of the component area CA, and a portion of the peripheral area NDA.

[0165] The main sub-pixel Pm is located in the main display area MDA, and the auxiliary sub-pixel Pa and the transmissive area TA are located in the component area CA. In the main display area MDA, a main pixel circuit PCm, including a main thin-film transistor TFTm and a main storage capacitor Cst, and a main organic light-emitting diode (OLED) serving as a display element connected to the main pixel circuit PCm, can be located. In the component area CA, an auxiliary organic light-emitting diode OLED' can be located. In the peripheral area NDA, an auxiliary pixel circuit PCa, including an auxiliary thin-film transistor TFTa and an auxiliary storage capacitor Cst', can be located. Connecting wiring TWL, connecting the auxiliary pixel circuit PCa to the auxiliary organic light-emitting diode OLED', can be located in both the component area CA and the peripheral area NDA.

[0166] The structure in which the components of the display panel 10 are stacked will now be described. The display panel 10 may include a stacked substrate 100, a buffer layer 111, a circuit layer PCL, and a display element layer EDL.

[0167] The substrate 100 may be formed of an insulating material such as glass, quartz, or polymer resin. The substrate 100 may be a rigid substrate or a flexible substrate that is bendable, foldable, and / or rollable.

[0168] The buffer layer 111 can be positioned on the substrate 100 and can reduce or prevent the penetration of foreign matter, moisture, or external air from the bottom of the substrate 100 and can planarize the substrate 100. The buffer layer 111 may include inorganic materials (such as oxides or nitrides), organic materials, or a combination of organic and inorganic materials, and may have a single-layer structure or a multi-layer structure including inorganic and organic materials. A barrier layer may also be provided between the substrate 100 and the buffer layer 111 to reduce or prevent the penetration of external air. In embodiments, the buffer layer 111 may include silicon oxide (SiO2) or silicon nitride (SiN). x ) or silicon oxynitride (SiON).

[0169] The circuit layer PCL can be positioned on the buffer layer 111 and may include a main pixel circuit PCm and an auxiliary pixel circuit PCa, a first gate insulating layer 112, a second gate insulating layer 113, an interlayer insulating layer 115, a first planarization layer 117, and a second planarization layer 118. The main pixel circuit PCm may include a main thin-film transistor TFTm and a main storage capacitor Cst, and the auxiliary pixel circuit PCa may include an auxiliary thin-film transistor TFTa and an auxiliary storage capacitor Cst'.

[0170] The main thin-film transistor (TFTm) and the auxiliary thin-film transistor (TFTa) can be positioned on the buffer layer 111. The main thin-film transistor (TFTm) may include a semiconductor layer A1, a gate electrode G1, a source electrode S1, and a drain electrode D1. The main thin-film transistor (TFTm) can be connected to and drive the main organic light-emitting diode (OLED). The auxiliary thin-film transistor (TFTa) can be connected to and drive the auxiliary organic light-emitting diode (OLED). The auxiliary thin-film transistor (TFTa) has a structure similar to that of the main thin-film transistor (TFTm), therefore, the same or similar descriptions as those for the main thin-film transistor (TFTm) can be applied to the auxiliary thin-film transistor (TFTa).

[0171] Semiconductor layer A1 may be positioned on buffer layer 111 and may comprise polycrystalline silicon. In one or more other embodiments, semiconductor layer A1 may comprise amorphous silicon. In one or more other embodiments, semiconductor layer A1 may comprise an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). Semiconductor layer A1 may comprise a channel region and impurity-doped source and drain regions.

[0172] The first gate insulating layer 112 may be configured to cover the semiconductor layer A1. The first gate insulating layer 112 may include materials such as silicon oxide (SiO2) or silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y Aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or (ZnO) x (ZnO) x It can be an inorganic insulating material (ZnO and / or ZnO2). The first gate insulating layer 112 can have a single-layer structure or a multi-layer structure including the inorganic insulating material.

[0173] The gate electrode G1 is positioned on the first gate insulating layer 112 to be stacked with the semiconductor layer A1. The gate electrode G1 may include molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a single-layer structure or a multi-layer structure. For example, the gate electrode G1 may have a single-layer structure including Mo.

[0174] The second gate insulating layer 113 can be configured to cover the gate electrode G1. The second gate insulating layer 113 may include materials such as silicon oxide (SiO2) and silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y Aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or (ZnO) x (ZnO) x It can be an inorganic insulating material (ZnO and / or ZnO2). The second gate insulating layer 113 can have a single-layer structure or a multi-layer structure including inorganic insulating material.

[0175] The upper electrode CE2 of the main storage capacitor Cst and the upper electrode CE2' of the auxiliary storage capacitor Cst' can be positioned on the second gate insulating layer 113.

[0176] In the main display area MDA, the upper electrode CE2 of the main storage capacitor Cst can be stacked with the gate electrode G1 positioned below the upper electrode CE2. The stacked gate electrode G1 and upper electrode CE2, with the second gate insulating layer 113 located between them, can constitute the main storage capacitor Cst. The gate electrode G1 can be the lower electrode CE1 of the main storage capacitor Cst.

[0177] In the peripheral region NDA, the upper electrode CE2' of the auxiliary storage capacitor Cst' can be stacked with the gate electrode G1' of the auxiliary thin-film transistor TFTa. The gate electrode G1' of the auxiliary thin-film transistor TFTa can be the lower electrode CE1' of the auxiliary storage capacitor Cst'.

[0178] Each of the upper electrodes CE2 and CE2' may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may have a single-layer structure or a multi-layer structure including the above materials.

[0179] The interlayer insulating layer 115 can be formed to cover the upper electrodes CE2 and CE2'. The interlayer insulating layer 115 may include materials such as silicon oxide (SiO2) and silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y Aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or (ZnO) x (ZnO) x It can be an inorganic insulating material (ZnO and / or ZnO2). The interlayer insulation layer 115 can have a single-layer structure or a multi-layer structure including inorganic insulating material.

[0180] The source electrode S1 and drain electrode D1 can be positioned on the interlayer insulating layer 115. Each of the source electrode S1 and drain electrode D1 can include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and can have a single-layer structure or a multilayer structure comprising the aforementioned materials. For example, each of the source electrode S1 and drain electrode D1 can have a multilayer structure comprising Ti / Al / Ti.

[0181] The connection wiring TWL connecting to the auxiliary pixel circuit PCa can be positioned on the interlayer insulating layer 115. The connection wiring TWL can extend from the peripheral region NDA to the component region CA, and can connect the auxiliary organic light-emitting diode OLED' to the auxiliary pixel circuit PCa. Furthermore, the data line DL can be positioned on the interlayer insulating layer 115.

[0182] In an embodiment, the connection wiring TWL may include a first connection wiring TWL1 and a second connection wiring TWL2. In addition to... Figure 6 Other Figure 7 and Figure 8 In the cross-sectional view, the connection wiring TWL can also correspond to Figure 5B TWL connection wiring.

[0183] The first connection wiring TWL1 can be located in the peripheral region NDA and can be connected to the auxiliary pixel circuit PCa (e.g., auxiliary thin-film transistor TFTa). The second connection wiring TWL2 can be connected to the first connection wiring TWL1 and can be located in the transmissive region TA of the component region CA. At least a portion of the second connection wiring TWL2 and the first connection wiring TWL1 can be located on or within the same layer and can comprise different materials from each other. The end of the second connection wiring TWL2 can cover the end of the first connection wiring TWL1.

[0184] In one or more other embodiments, the first connection wiring TWL1 and the second connection wiring TWL2 may be located on different layers or at different layers. In an embodiment, the first connection wiring TWL1 (e.g., the first-1 connection wiring TWL1a of the first connection wiring TWL1) may be as follows: Figure 6 The second connection wiring TWL2 is positioned on the interlayer insulating layer 115 as shown, and can be positioned on the first planarization layer 117. In this case, the first connection wiring TWL1 (e.g., the first-1 connection wiring TWL1a of the first connection wiring TWL1) and the second connection wiring TWL2 can be connected to each other by means of contact holes defined in or through the first planarization layer 117.

[0185] The first connection wiring TWL1 may include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a single-layer or multi-layer structure comprising the aforementioned materials. The first connection wiring TWL1 may include a first-1 connection wiring TWL1a and a first-2 connection wiring TWL1b positioned on or at different layers. In an embodiment, the first-1 connection wiring TWL1a and the data line DL may be positioned on or at the same layer and may comprise the same material. The first-2 connection wiring TWL1b and the first-1 connection wiring TWL1a may be positioned with a first planarization layer 117 located between them. The first-2 connection wiring TWL1b and the connection electrodes CM and CM' may be positioned on the first planarization layer 117. In one or more other embodiments, the first-2 connection wiring TWL1b may be positioned on or at the same layer as the upper electrode CE2 or lower electrode CE1 of the main storage capacitor Cst.

[0186] The second connection wiring TWL2 may include a transparent conductive material. For example, the second connection wiring TWL2 may include a transparent conductive oxide (TCO). The second connection wiring TWL2 may include conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and zinc aluminum oxide (AZO).

[0187] The first connection wiring TWL1 can have a higher conductivity than the second connection wiring TWL2. Because the first connection wiring TWL1 is located in the peripheral NDA region and therefore does not need to ensure light transmittance, it can include a material with lower light transmittance than the material of the second connection wiring TWL2 but higher conductivity. Therefore, the resistance value of the connection wiring TWL can be minimized or reduced.

[0188] The first planarization layer 117 and the second planarization layer 118 can be positioned to cover the source electrode S1, the drain electrode D1, and the connection wiring TWL. The first planarization layer 117 and the second planarization layer 118 can have flat top surfaces, such that the main pixel electrode 210 and the auxiliary pixel electrode 210' positioned on the first planarization layer 117 and the second planarization layer 118 are flat.

[0189] Each of the first planarization layer 117 and the second planarization layer 118 may comprise organic or inorganic materials and may have a single-layer or multi-layer structure. Therefore, conductive patterns, such as wiring, can be formed between the first planarization layer 117 and the second planarization layer 118, which can result in high integration. Connecting electrodes CM and CM' and data connection lines DWL can be positioned on the first planarization layer 117.

[0190] The first planarization layer 117 may include benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), general polymers such as polymethyl methacrylate (PMMA) or polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, and / or vinyl alcohol polymers. The first planarization layer 117 may also include silicon oxide (SiO2), silicon nitride (SiN... x ), silicon oxynitride (SiO) x N y Aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and / or zinc oxide (ZnO) x (ZnO) xIt can be an inorganic insulating material (ZnO and / or ZnO2). When the first planarization layer 117 is formed, a layer can be formed, and then the top surface of the layer can be chemically mechanically polished to provide a flat top surface.

[0191] The first planarization layer 117 can be positioned to cover the main pixel circuit PCm and the auxiliary pixel circuit PCa. The second planarization layer 118 can be positioned on the first planarization layer 117 and can have a flat top surface, so that the main pixel electrode 210 and the auxiliary pixel electrode 210' are flat.

[0192] The main organic light-emitting diode (OLED) and the auxiliary organic light-emitting diode (OLED') are positioned on the second planarization layer 118. The main pixel electrode 210 of the main organic light-emitting diode (OLED) and the auxiliary pixel electrode 210' of the auxiliary organic light-emitting diode (OLED') can be connected to the main pixel circuit PCm and the auxiliary pixel circuit PCa respectively through the connection electrodes CM and CM' positioned on the first planarization layer 117.

[0193] Each of the main pixel electrode 210 and the auxiliary pixel electrode 210' may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and / or zinc aluminum oxide (AZO). Each of the main pixel electrode 210 and the auxiliary pixel electrode 210' may include a reflective film comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), their compounds, or mixtures thereof. For example, each of the main pixel electrode 210 and the auxiliary pixel electrode 210' may have a structure in which a film formed of ITO, IZO, ZnO, or In2O3 is positioned above / below the reflective film. In this case, each of the main pixel electrode 210 and the auxiliary pixel electrode 210' may have a stacked structure comprising ITO / Ag / ITO.

[0194] A pixel defining layer 120 positioned on the first planarization layer 117 (e.g., a pixel defining layer 120 positioned on the first planarization layer 117 with a second planarization layer 118 located between them) may cover the edges of the main pixel electrode 210 and the auxiliary pixel electrode 210', and may have a first opening OP1 and a second opening OP2, with the central portions of the main pixel electrode 210 and the auxiliary pixel electrode 210' exposed through the first opening OP1 and the second opening OP2, respectively. The size and shape of the emission regions (i.e., the main sub-pixel Pm and the auxiliary sub-pixel Pa) of the main organic light-emitting diode OLED and the auxiliary organic light-emitting diode OLED' are defined by the first opening OP1 and the second opening OP2.

[0195] The pixel defining layer 120 can increase the distance between the edge of the main pixel electrode 210 and the counter electrode 230 (e.g., a portion of the counter electrode 230) positioned above the main pixel electrode 210, and can increase the distance between the edge of the auxiliary pixel electrode 210' and the counter electrode 230 (e.g., a portion of the counter electrode 230) positioned above the auxiliary pixel electrode 210', to prevent or substantially prevent the occurrence of electric arcs or the like at the edges of the main pixel electrode 210 and the auxiliary pixel electrode 210'. The pixel defining layer 120 can be formed using an organic insulating material such as polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyldisiloxane (HMDSO), and / or phenolic resin using spin coating or the like.

[0196] The main emitting layer 220b and the auxiliary emitting layer 220b' are respectively positioned in the first opening OP1 and the second opening OP2 of the pixel defining layer 120, corresponding to the main pixel electrode 210 and the auxiliary pixel electrode 210', respectively. Each of the main emitting layer 220b and the auxiliary emitting layer 220b' may include a high molecular weight material or a low molecular weight material, and may emit red light, green light, blue light, or white light.

[0197] The organic functional layer 220 may be positioned above and / or below the main emission layer 220b and the auxiliary emission layer 220b'. The organic functional layer 220 may include a first functional layer 220a and / or a second functional layer 220c. The first functional layer 220a or the second functional layer 220c may be omitted.

[0198] The first functional layer 220a can be positioned below the main emitting layer 220b and the auxiliary emitting layer 220b'. The first functional layer 220a can have a single-layer structure or a multi-layer structure including organic materials. The first functional layer 220a can be a hole transport layer (HTL) with a single-layer structure. Optionally, the first functional layer 220a can include a hole injection layer (HIL) and a hole transport layer (HTL). The first functional layer 220a can be integrally formed to correspond to the main organic light-emitting diode (OLED) and the auxiliary organic light-emitting diode (OLED') respectively included in the main display area MDA and the component area CA.

[0199] The second functional layer 220c can be positioned on the main emitting layer 220b and the auxiliary emitting layer 220b'. The second functional layer 220c can have a single-layer structure or a multi-layer structure including organic materials. The second functional layer 220c may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The second functional layer 220c can be integrally formed to correspond to the main organic light-emitting diode OLED and the auxiliary organic light-emitting diode OLED' respectively included in the main display area MDA and the component area CA.

[0200] The counter electrode 230 is positioned on the second functional layer 220c. The counter electrode 230 may include a conductive material with low work function. For example, the counter electrode 230 may include a (semi-)transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. Optionally, the counter electrode 230 may also include a layer formed of ITO, IZO, ZnO, or In2O3 on the (semi-)transparent layer comprising the above-described materials. The counter electrode 230 may be integrally formed to correspond to the main organic light-emitting diode (OLED) and auxiliary organic light-emitting diode (OLED') respectively included in the main display region MDA and the component region CA.

[0201] The layer formed in the main display area MDA from the main pixel electrode 210 to the counter electrode 230 can constitute a main organic light-emitting diode (OLED). The layer formed in the component area CA from the auxiliary pixel electrode 210' to the counter electrode 230 can constitute an auxiliary organic light-emitting diode (OLED').

[0202] An upper layer 250, comprising an organic material, can be formed on the counter electrode 230. The upper layer 250 can protect the counter electrode 230 and improve light extraction efficiency. The upper layer 250 may comprise an organic material having a higher refractive index than that of the counter electrode 230. Optionally, the upper layer 250 can be formed by stacking layers having different refractive indices from each other. For example, the upper layer 250 can be formed by stacking (e.g., by sequentially stacking) a high-refractive-index layer, a low-refractive-index layer, and a high-refractive-index layer. In this case, the refractive index of the high-refractive-index layer may be equal to or greater than 1.7, and the refractive index of the low-refractive-index layer may be equal to or less than 1.3.

[0203] The upper layer 250 may additionally include LiF. Alternatively, the upper layer 250 may additionally include silicon oxide (SiO2) or silicon nitride (SiN). x Inorganic insulating materials.

[0204] The first conductive layer MM1 can be stacked with the auxiliary sub-pixel Pa in the component region CA. This can refer to the first conductive layer MM1 being stacked with the auxiliary display element (i.e., the auxiliary organic light-emitting diode OLED') (e.g., stacked in the z-direction or the thickness direction of the substrate 100). In the illustrated embodiment, because the auxiliary organic light-emitting diode OLED' of the auxiliary sub-pixel Pa is located in the component region CA, and the auxiliary pixel circuit PCa is located in the peripheral region NDA, the first conductive layer MM1 can be stacked with the auxiliary organic light-emitting diode OLED'. In this case, when the first conductive layer MM1 is stacked with the auxiliary organic light-emitting diode OLED', this can refer to the first conductive layer MM1 being stacked with the auxiliary pixel electrode 210' (e.g., stacked in the z-direction or the thickness direction of the substrate 100).

[0205] Multiple first holes H1 can be formed in the first conductive layer MM1. Multiple first holes H1 can pass through the first conductive layer MM1. Multiple first holes H1 can have any of a variety of suitable shapes, such as polygonal shapes (e.g., quadrilateral shapes), circular shapes, elliptical shapes, strip shapes, or irregular shapes. Furthermore, multiple first holes H1 can be arranged in any of a variety of suitable structures (such as matrix structures, checkerboard structures, strip structures, or random structures).

[0206] The first conductive layer MM1 can be positioned between the substrate 100 and the connection wiring (e.g., the second connection wiring TWL2). In an embodiment, as... Figure 6 As shown, the first conductive layer MM1 can be positioned on the first gate insulating layer 112 and can comprise the same material as the gate electrode G1 of the main pixel circuit PCm and the gate electrode G1' of the auxiliary pixel circuit PCa. In one or more other embodiments, the first conductive layer MM1 can be positioned on the second gate insulating layer 113, and in this case, the first conductive layer MM1 can comprise the same material as the upper electrodes CE2 and CE2'. In one or more other embodiments, the first conductive layer MM1 can be positioned between a connection wiring (e.g., a second connection wiring TWL2) and the auxiliary pixel electrode 210'. In this case, the first conductive layer MM1 can comprise the same material as the connection electrodes CM and CM'. As long as the first conductive layer MM1 is positioned between the substrate 100 and the auxiliary pixel electrode 210' to correspond to the auxiliary pixel electrode 210', the first conductive layer MM1 can be implemented in various suitable ways as described above.

[0207] In this embodiment, the width W1 of the first conductive layer MM1 can be the same as the width 210W of the auxiliary pixel electrode 210', or the width W1 of the first conductive layer MM1 can be smaller than the width 210W of the auxiliary pixel electrode 210'. That is, the orthogonal projection image of the first conductive layer MM1 on the substrate 100 can be completely superimposed on the auxiliary pixel electrode 210'. In other words, in a planar view, the first conductive layer MM1 can be completely superimposed on the auxiliary pixel electrode 210'. Therefore, the area of ​​the first conductive layer MM1 can be smaller than the area of ​​the auxiliary pixel electrode 210'. For example, in a planar view, the area of ​​the first conductive layer MM1 can be smaller than the area of ​​the auxiliary pixel electrode 210'.

[0208] In the comparative example, when the width of the first conductive layer is greater than the width of the auxiliary pixel electrode, the pattern of the first conductive layer is exposed outside the auxiliary sub-pixel Pa, thus reducing visibility. To some extent, reflected light is reflected again by the first conductive layer and re-enters the component, exacerbating the ghosting that forms unintended double images.

[0209] The first conductive layer MM1 can be connected (e.g., electrically connected) to wiring or electrodes, allowing signals or constant voltages to be applied to the first conductive layer MM1. (See reference...) Figure 6 The first conductive layer MM1 can be connected (e.g., electrically connected) to the second connection wiring TWL2 via contact holes CNT. In one or more other embodiments, the first conductive layer MM1 can be isolated and not connected to another wiring or electrode. However, in this case, because the static electricity generated by the first conductive layer MM1 may affect adjacent pixel circuitry, the first conductive layer MM1 is preferably subjected to a signal or a constant voltage.

[0210] Figure 7 and Figure 8 It is a cross-sectional view showing a portion of a display device according to one or more embodiments. Figure 7 and Figure 8 It shows Figure 6 Modification of the component region CA (in other words, the first conductive layer MM1 located in the component region CA). Other components and Figure 6 The components are the same, so their descriptions need not be repeated, and the following description can focus mainly on the differences.

[0211] Reference Figure 7A second conductive layer MM2 can also be disposed on the first conductive layer MM1. Multiple second holes H2 can be formed in the second conductive layer MM2. The multiple second holes H2 can pass through the second conductive layer MM2. The multiple second holes H2 can have any of a variety of suitable shapes, such as polygonal shapes (e.g., quadrilateral shapes), circular shapes, elliptical shapes, strip shapes, or irregular shapes. Furthermore, the multiple second holes H2 can be arranged in any of a variety of suitable structures (such as matrix structures, checkerboard structures, strip structures, or random structures). The second conductive layer MM2 and the first conductive layer MM1 can have the same shape or can have different shapes from each other.

[0212] As described above, the width W2 of the second conductive layer MM2 can be equal to or smaller than the width 210W of the auxiliary pixel electrode 210'. The orthogonal projection image of the second conductive layer MM2 on the substrate 100 can be completely superimposed on the auxiliary pixel electrode 210'. In other words, in a planar view, the second conductive layer MM2 can be completely superimposed on the auxiliary pixel electrode 210'. Therefore, the area of ​​the second conductive layer MM2 can be smaller than the area of ​​the auxiliary pixel electrode 210'. For example, in a planar view, the area of ​​the second conductive layer MM2 can be smaller than the area of ​​the auxiliary pixel electrode 210'.

[0213] The second conductive layer MM2 can be positioned on the second gate insulating layer 113. In this case, the second conductive layer MM2 may comprise the same material as the upper electrodes CE2 and CE2'.

[0214] The second conductive layer MM2 can be connected (e.g., electrically connected) to wiring or electrodes, allowing signals or constant voltages to be applied to the second conductive layer MM2. In embodiments, such as Figure 7 As shown, the second conductive layer MM2 can be connected (e.g., electrically connected) to the second connection wiring TWL2 through the second contact hole CNT2, and the first conductive layer MM1 can be connected (e.g., electrically connected) to the second conductive layer MM2 through the first contact hole CNT1.

[0215] Reference Figure 8 The bottom metal layer (BML) can be disposed below the auxiliary pixel circuit PCa located in the peripheral region NDA. The bottom metal layer (BML) can include conductive metals such as aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu).

[0216] The bottom metal layer BML can be connected (e.g., electrically connected) to the conductive line CL. The conductive line CL can be connected (e.g., electrically connected) to one electrode of the auxiliary thin-film transistor TFTa, or it can be connected (e.g., electrically connected) to one electrode of the auxiliary storage capacitor Cst'. Optionally, the conductive line CL can be connected (e.g., electrically connected) to a drive voltage line. The bottom metal layer BML connected to the conductive line CL can protect the auxiliary thin-film transistor TFTa from external static electricity, or it can block the influence of component 40, thereby improving the performance of the auxiliary thin-film transistor TFTa.

[0217] In the illustrated embodiment, the first conductive layer MM1 and the bottom metal layer BML can be positioned on or within the same layer. In this case, the first conductive layer MM1 may comprise the same material as the bottom metal layer BM1. The first conductive layer MM1 can be positioned directly on the substrate 100 and can be positioned below the second connection wiring TWL2. The first conductive layer MM1 can be connected (e.g., electrically connected) to the second connection wiring TWL2 via contact holes CNT.

[0218] Reference Figure 8 A portion of the light passing through the transmission region TA can travel along path "A" and thus be reflected, refracted, and diffracted by component 40 (e.g., a camera lens). The reflected light can travel along path "B" toward the auxiliary sub-pixel Pa. In this case, the light traveling along path "B" can be scattered in the display panel 10 by the first conductive layer MM1.

[0219] In a comparative example where the display device does not include the first conductive layer MM1, light traveling along path "B" towards the auxiliary sub-pixel Pa is reflected again by the auxiliary pixel electrode 210'. In this case, the reflected light re-enters component 40. Because the reflected light includes some noise, component 40 will have distorted information. For example, when component 40 is a camera including an image sensor, the image captured by the camera will differ from the actual image. Thus, when the reflected light re-enters the camera lens, a ghosting occurs, forming an unexpected double image that differs from the actual image.

[0220] For reference Figures 6 to 8 As described, in the display device 1 according to the embodiment, because reflected light is scattered in the display panel 10 by light-scattering layers such as the first conductive layer MM1 and / or the second conductive layer MM2 located in the component region CA, it is possible to prevent or substantially prevent the reflected light from re-entering the component 40. Therefore, the reliability of the information output from the component 40 can be improved.

[0221] Figures 9A to 9E This is a plan view showing the shape of the first conductive layer according to an embodiment. Although in Figures 9A to 9E The shape of the first conductive layer MM1 is described, but the same description can be applied to the second conductive layer MM2.

[0222] Reference Figures 9A to 9E Multiple first holes H1 can be formed in the first conductive layer MM1. The multiple first holes H1 can penetrate the first conductive layer MM1. The multiple first holes H1 can have any of a variety of suitable shapes, such as... Figure 9A and Figure 9E The polygonal shapes shown (e.g., quadrilateral shapes), such as Figure 9B The circular or elliptical shapes shown, such as Figure 9C The bar shape shown and / or such as Figure 9D The irregular shape shown.

[0223] Furthermore, the multiple first holes H1 can be arranged in any of a variety of suitable structures, such as... Figure 9A and Figure 9B The chessboard structure shown is as follows: Figure 9C The strip structure shown and / or as Figure 9D The random structure shown. Optionally, the multiple first holes H1 can be arranged in a matrix or mesh structure in which the same number of first holes H1 are positioned in the same rows and columns.

[0224] In the embodiments, in Figure 9A and Figure 9B In this configuration, the first width WH1 and the second width WH2 of each of the plurality of first holes H1 in a certain direction (e.g., the DR1 direction or the DR2 direction) can both be approximately 0.5 μm. For example, the width of each of the plurality of first holes H1 can range from approximately 0.5 μm to approximately 5 μm. Although in Figure 9A and Figure 9B The first width WH1 and the second width WH2 are the same, but the first width WH1 and the second width WH2 can be different from each other. When the first width WH1 and the second width WH2 are different from each other, the first hole H1 can have a rectangular shape or an elliptical shape.

[0225] Furthermore, the area of ​​the plurality of first holes H1 (e.g., the total area of ​​all of the plurality of first holes H1) can be less than 50% of the total area of ​​the first conductive layer MM1. In the comparative example, the effect of the mesh structure of the first conductive layer MM1 is reduced when the area of ​​the first hole H1 is equal to or greater than 50% of the total area of ​​the first conductive layer MM1.

[0226] Figure 10 It is a cross-sectional view showing a portion of a display device according to one or more embodiments. Figure 11 It is shown Figure 10 A plan view of a portion of the component area of ​​a display device.

[0227] Figure 10 The display device 1 is Figure 2A This is a variant of display device 1, and differs in the structure of the component area CA. The main display area MDA and the stacking structure are different. Figure 2A The main display area MDA and the stacking structure are the same, so their descriptions do not need to be repeated, and the main description component area CA will be used instead.

[0228] The display panel 10 may include a substrate 100, a display layer DISL, a touch screen layer TSL, and an optical functional layer OFL positioned on the substrate 100, and a panel protective member PB positioned below the substrate 100. Figure 10 Within the component region CA, an auxiliary sub-pixel Pa is positioned, comprising an auxiliary display element EDa and an auxiliary pixel circuit PCa. Unlike some embodiments described above, the auxiliary pixel circuit PCa may be positioned below the auxiliary display element EDa to be superimposed on the auxiliary display element EDa (e.g., superimposed in the z-direction or the thickness direction of the substrate 100).

[0229] like Figure 11 As shown, the auxiliary sub-pixel Pa may include a first sub-pixel Pr', a second sub-pixel Pg', and a third sub-pixel Pb' that emit light of different colors from each other. In the component region CA, the auxiliary sub-pixels Pa may be grouped to form an auxiliary display region ADA in which the auxiliary sub-pixels Pa are located, and a transmission region TA in which the transmitter is located. In an embodiment, the auxiliary display region ADA and the transmission region TA may be arranged alternately in a grid shape. Although in Figure 2A In the central component area CA, the portion excluding the auxiliary display element EDa is used as the transmission area TA, but in Figure 11 The transmission region TA in the component region CA can be configured to have a specific shape. In embodiments, the transmission region TA can have any of a variety of suitable shapes, such as polygonal, circular, or irregular shapes.

[0230] The bottom metal layer BML can be positioned between the substrate 100 and the auxiliary pixel circuit PCa, to be superimposed on the auxiliary pixel circuit PCa (e.g., superimposed in the z-direction or the thickness direction of the substrate 100). The bottom metal layer BML can prevent or substantially prevent external light from reaching the auxiliary sub-pixel Pa.

[0231] According to the illustrated embodiment, the bottom metal layer BML can be positioned to correspond to the auxiliary thin-film transistor TFTa included in the auxiliary pixel circuit PCa. In other words, the bottom metal layer BML can be patterned to be positioned in the portion where the auxiliary thin-film transistor TFTa is positioned, rather than in other portions where electrodes, voltage lines, and / or signal lines are positioned.

[0232] Figure 12 This is a view showing the arrangement of the auxiliary pixel circuit according to an embodiment.

[0233] Reference Figure 12 The auxiliary pixel circuit PCa according to the illustrated embodiment may include a driving thin-film transistor T1, a switching thin-film transistor T2, a compensation thin-film transistor T3, a first initialization thin-film transistor T4, an operation control thin-film transistor T5, an emission control thin-film transistor T6, and a second initialization thin-film transistor T7. The connection relationships between thin-film transistors T1 to T7 and their functions are shown in the reference diagram. Figure 4B The described interconnections between thin-film transistors are similar to their functions, so their description need not be repeated.

[0234] In the illustrated embodiment, in the auxiliary pixel circuit PCa, the bottom metal layer BML can be patterned to be stacked only with thin-film transistors T1 to T7.

[0235] In detail, the driving thin-film transistor T1, the switching thin-film transistor T2, the compensation thin-film transistor T3, the first initialization thin-film transistor T4, the operation control thin-film transistor T5, the emission control thin-film transistor T6, and the second initialization thin-film transistor T7 are positioned along the semiconductor layer 1130. The semiconductor layer 1130 may be positioned on a substrate on which a buffer layer made of inorganic insulating material is formed.

[0236] Some portions of semiconductor layer 1130 may correspond to the semiconductor layers of the driving thin-film transistor T1, the switching thin-film transistor T2, the compensation thin-film transistor T3, the first initialization thin-film transistor T4, the operation control thin-film transistor T5, the emission control thin-film transistor T6, and the second initialization thin-film transistor T7. In other words, the semiconductor layers of the driving thin-film transistor T1, the switching thin-film transistor T2, the compensation thin-film transistor T3, the first initialization thin-film transistor T4, the operation control thin-film transistor T5, the emission control thin-film transistor T6, and the second initialization thin-film transistor T7 may be connected to each other in various suitable bending shapes.

[0237] Semiconductor layer 1130 may include a channel region and source and drain regions on or at corresponding sides of the channel region. The source and drain regions may be the source and drain electrodes of a corresponding thin-film transistor. For ease of description, the source and drain regions are referred to as source electrode and drain electrode, respectively.

[0238] The driving thin-film transistor T1 includes a driving gate electrode G1 superimposed on the driving channel region, and a driving source electrode S1 and a driving drain electrode D1 on or at a corresponding side of the driving channel region. The driving channel region superimposed on the driving gate electrode G1 can have a curved shape, such as an omega (Ω) shape, to form a long channel in a narrow space. When the driving channel region is long, the driving range of the gate voltage can be widened, and the grayscale of the light emitted by the organic light-emitting diode (OLED) as a light-emitting device can be better controlled, thereby improving the display quality.

[0239] The switching thin-film transistor T2 includes a switching gate electrode G2 superimposed on the switching channel region, and a switching source electrode S2 and a switching drain electrode D2 on or at a corresponding side of the switching channel region. The switching drain electrode D2 can be connected to the driving source electrode S1.

[0240] The compensation thin-film transistor T3, as a dual thin-film transistor, may include a compensation gate electrode G3 superimposed with two compensation channel regions, and a compensation source electrode S3 and a compensation drain electrode D3 on or at the corresponding side of the compensation gate electrode G3. The compensation thin-film transistor T3 can be connected to the driving gate electrode G1 of the driving thin-film transistor T1 via node connection line 1174.

[0241] The first initialization thin-film transistor T4, which is a dual thin-film transistor, may include a first initialization gate electrode G4 superimposed with two first initialization channel regions, and a first initialization source electrode S4 and a first initialization drain electrode D4 on or at the corresponding side of the first initialization gate electrode G4.

[0242] The operation control thin-film transistor T5 may include an operation control gate electrode G5 superimposed on the operation control channel region, and an operation control source electrode S5 and an operation control drain electrode D5 on or at a corresponding side of the operation control gate electrode G5. The operation control drain electrode D5 may be connected to the drive source electrode S1.

[0243] The emitter control thin-film transistor T6 may include an emitter control gate electrode G6 stacked with the emitter control channel region, and an emitter control source electrode S6 and an emitter control drain electrode D6 on or at a corresponding side of the emitter control gate electrode G6. The emitter control source electrode S6 may be connected to the drive drain electrode D1.

[0244] The second initialization thin-film transistor T7 may include a second initialization gate electrode G7 superimposed on the second initialization channel region, and a second initialization source electrode S7 and a second initialization drain electrode D7 on or at a corresponding side of the second initialization gate electrode G7.

[0245] The aforementioned thin-film transistor can be connected to signal lines SL, SL-1, SL+1, EL, and DL, the first initialization voltage line VL1, the second initialization voltage line VL2, and the drive voltage line PL. Signal lines SL, SL-1, SL+1, EL, and DL, the first initialization voltage line VL1, the second initialization voltage line VL2, and the drive voltage line PL can refer to (auxiliary) signal lines SL, SL-1, SL+1, EL, and DL, (auxiliary) first initialization voltage line VL1, (auxiliary) second initialization voltage line VL2, and (auxiliary) drive voltage line PL. The wiring can be separate from the main pixel circuit PCm, and at least some wiring can be shared.

[0246] The scan line SL, the previous scan line SL-1, the emission control line EL, and the drive gate electrode G1 can be positioned on the semiconductor layer 1130, with an insulating layer located between them.

[0247] The scan line SL can extend in the x-direction. A portion of the scan line SL can correspond to the switching gate electrode G2 and the compensation gate electrode G3. For example, the portion of the scan line SL that overlaps with the channel region of the switching thin-film transistor T2 and the portion that overlaps with the channel region of the compensation thin-film transistor T3 can be the switching gate electrode G2 and the compensation gate electrode G3, respectively.

[0248] The preceding scan line SL-1 can extend in the x-direction, and some portions of it can all correspond to the first initialization gate electrode G4. For example, the portions of the preceding scan line SL-1 that overlap with the channel region of the first initialization thin-film transistor T4 can all be the first initialization gate electrode G4.

[0249] The next scan line SL+1 may extend in the x-direction, and some portions may correspond to the second initialization gate electrode G7. For example, the portion of the next scan line SL+1 that overlaps with the channel region of the second initialization thin-film transistor T7 may be the second initialization gate electrode G7.

[0250] The emitter control line EL extends in the x-direction. Some portions of the emitter control line EL may correspond to the operation control gate electrode G5 and the emitter control gate electrode G6, respectively. For example, portions of the emitter control line EL that overlap with the channel regions of the operation control thin-film transistor T6 and the emitter control thin-film transistor T7 may correspond to the operation control gate electrode G5 and the emitter control gate electrode G6, respectively.

[0251] The driving gate electrode G1, which serves as a floating electrode, can be connected to the compensation thin-film transistor T3 via node connection line 1174.

[0252] The electrode voltage line HL can be positioned on the previous scan line SL-1, the scan line SL, the next scan line SL+1, the emission control line EL, and the drive gate electrode G1, with the insulating layer located between them.

[0253] The electrode voltage line HL can extend in the x-direction to intersect with the data line DL and the drive voltage line PL. A portion of the electrode voltage line HL can cover at least a portion of the drive gate electrode G1 to form the main storage capacitor Cst together with the drive gate electrode G1. For example, the drive gate electrode G1 can be used as the lower electrode CE1 of the main storage capacitor Cst, and a portion of the electrode voltage line HL can be used as the upper electrode CE2 of the main storage capacitor Cst.

[0254] The upper electrode CE2 of the main storage capacitor Cst is connected (e.g., electrically connected) to the drive voltage line PL. In this respect, the electrode voltage line HL can be connected to the drive voltage line PL positioned on the electrode voltage line HL via contact hole 1158. Therefore, the electrode voltage line HL and the drive voltage line PL can have the same voltage level (e.g., constant voltage). For example, the electrode voltage line HL can have a constant voltage of +5V. The electrode voltage line HL can be a horizontal drive voltage line.

[0255] Because the driving voltage line PL extends in the y direction, and the electrode voltage line HL connected (e.g., electrically connected) to the driving voltage line PL extends in the x direction that intersects the y direction, multiple driving voltage lines PL and multiple electrode voltage lines HL can have a grid structure in the display area (e.g., the main display area MDA).

[0256] The data line DL, the drive voltage line PL, the first initialization connection line 1173a, the second initialization connection line 1173b, and the node connection line 1174 can be positioned on the electrode voltage line HL, with the insulating layer located between them.

[0257] The data line DL can extend in the y-direction and can be connected to the switching source electrode S2 of the switching thin-film transistor T2 through contact hole 1154. A portion of the data line DL can be the switching source electrode.

[0258] The drive voltage line PL can extend in the y-direction and is connected to the electrode voltage line HL via contact hole 1158 as described above. Furthermore, the drive voltage line PL can be connected to the operation control thin-film transistor T5 via contact hole 1155. The drive voltage line PL can also be connected to the operation control source electrode S5 via contact hole 1155.

[0259] The first initialization voltage line VL1 can be connected to the first initialization thin-film transistor T4 via the first initialization connection line 1173a, and the second initialization voltage line VL2 can be connected to the second initialization thin-film transistor T7 via the second initialization connection line 1173b. The first initialization voltage line VL1 and the second initialization voltage line VL2 can be connected to each other via a connecting member (e.g., electrical connection) and can have a constant voltage (e.g., -2V).

[0260] One end of the node connection line 1174 can be connected to the compensation drain electrode D3 through the contact hole 1156, and the other end of the node connection line 1174 can be connected to the drive gate electrode G1 through the contact hole 1157. The upper electrode CE2 may have a storage opening SOP, and the contact hole 1157 may be positioned in the storage opening SOP.

[0261] Initialization voltage lines VL1 and VL2 can be positioned on data line DL, drive voltage line PL, initialization connection lines 1173a and 1173b and node connection line 1174, with an insulation layer located between them.

[0262] The first initialization voltage line VL1, the second initialization voltage line VL2, and the main pixel electrode 210 of the main organic light-emitting diode (OLED) can be positioned on or within the same layer and can comprise the same material. The main pixel electrode 210 can be connected to the emission control thin-film transistor T6. The main pixel electrode 210 can be connected to the connection electrode CM (see contact hole 1163) through the contact hole 1163. Figure 6 Furthermore, the connecting electrode CM can be connected to the emitter control drain electrode D6 via contact hole 1153. In one or more other embodiments, the first initialization voltage line VL1, the second initialization voltage line VL2, and the electrode voltage line HL can be located on the same layer or in the same layer.

[0263] In the illustrated embodiment, the bottom metal layer BML can be positioned on the substrate 100. The bottom metal layer BML can be positioned between the substrate 100 and the semiconductor layer 1130. An inorganic insulating film, such as a buffer layer, can be positioned between the bottom metal layer BML and the semiconductor layer 1130.

[0264] The bottom metal layer BML may include multiple stacked portions BML1, BML2, BML3, BML4, BML5, BML6, and BML7 respectively stacked with thin film transistors T1 to T7, and a connecting portion BML-C connecting the multiple stacked portions BML1 to BML7.

[0265] Despite Figure 12All of the multiple overlapping portions BML1 to BML7 are connected by connecting portion BML-C, but the disclosure is not limited thereto. In one or more other embodiments, the multiple overlapping portions BML1 to BML7 may not be connected to each other, but may be spaced apart from each other, and at least two of the overlapping portions BML1 to BML7 may be connected to each other. When all of the multiple overlapping portions BML1 to BML7 are as described... Figure 12 When the connection is made via the connection portion BML-C as shown, the same signal or the same constant voltage can be applied to the bottom metal layer BML through a contact hole B-CNT.

[0266] A constant voltage or signal can be applied to the bottom metal layer BML. In an embodiment, the bottom metal layer BML can be connected to the drive voltage line PL via contact holes B-CNT.

[0267] In the comparative example, when the bottom metal layer is positioned in the region of the component area other than the transmission region, that is, when the bottom metal layer is positioned to correspond to the entire surface of the auxiliary pixel circuit, light incident through the transmission region is reflected by the component (e.g., camera), and the reflected light is reflected again by the bottom metal layer and enters the component again, resulting in a ghosting of the double image on the component.

[0268] Therefore, in the display device according to the embodiment, since the bottom metal layer BML is patterned to correspond to the thin-film transistors T1 to T7, which are the parts for actually performing functions, it is possible to prevent or substantially prevent reflected light from being reflected again by the bottom metal layer BML and re-entering the component. Furthermore, since light re-incidentally incident on the display panel 10 is scattered by using the pattern of the bottom metal layer BML or by using the wiring of the auxiliary pixel circuit PCa with the bottom metal layer BML removed, it is possible to prevent or substantially prevent reflected light from re-entering the component.

[0269] Figure 13 and Figure 14 This is a cross-sectional view showing a portion of a display device according to an embodiment.

[0270] Reference Figure 13 The auxiliary sub-pixel Pa can be located within the component region CA. In the illustrated embodiment, each auxiliary sub-pixel Pa may include an auxiliary pixel circuit PCa and an auxiliary display element (i.e., an auxiliary organic light-emitting diode OLED') stacked on top of each other. The elements of each of the auxiliary pixel circuit PCa and the auxiliary organic light-emitting diode OLED' are... Figure 6 Since the elements are the same or similar, descriptions of elements indicated by the same reference numerals need not be repeated. The following will focus primarily on the differences.

[0271] The third planarization layer 119 can be positioned on the second planarization layer 118. Multiple planarization layers 117, 118, and 119 can be provided as in the illustrated embodiment, which can result in high integration. In the embodiment, the third planarization layer 119 may have an opening corresponding to the transmission region TA. Although in Figure 13 The second planarization layer 118 extends into the transmission region TA and the lower insulating layer (e.g., the first planarization layer 117, the interlayer insulating layer 115, and the second gate insulating layer 113) is not located in the transmission region TA, but the disclosure is not limited thereto.

[0272] In the illustrated embodiment, the pixel defining layer 120 may include a light-shielding material. For example, the pixel defining layer 120 may include an insulating material containing black pigment or black dye (e.g., an organic insulating material). As a light-shielding film, the pixel defining layer 120 can prevent or reduce color mixing between adjacent pixels and can absorb light reflected from component 40 to display panel 10, thereby improving visibility.

[0273] Light incident on the substrate 100 through the transmission region TA can travel along path "A". A portion of the incident light can be reflected by the surface of component 40, and the reflected light can travel along path "B" toward the display panel 10. In this case, the reflected light travels through an opening in the bottom metal layer BML, positioned to correspond only to the auxiliary thin-film transistor TFTa, to the auxiliary pixel circuit PCa, and encounters the complex pattern of the auxiliary pixel circuit PCa and is scattered. In the comparative example, when the bottom metal layer is positioned to correspond to the entire surface of the auxiliary pixel circuit, the reflected light traveling along path "B" is reflected again by the bottom metal layer and re-enters the component. The reflected light has a certain amount of noise, and unwanted information is input into the component, thereby reducing the reliability of the information output from the component.

[0274] Therefore, in the display device 1 according to the embodiment, the reflected light traveling along the path "B" may encounter or be incident on the auxiliary pixel circuit PCa, and may be scattered by the bottom metal layer BML, thereby preventing or substantially preventing the reflected light from re-entering the component 40.

[0275] Reference Figure 14 The thin-film encapsulation layer TFE can be positioned on the upper layer 250. The thin-film encapsulation layer TFE may include a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330.

[0276] Each of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include at least one inorganic insulating material. The inorganic insulating material may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be formed using CVD.

[0277] The organic encapsulation layer 320 may include polymeric materials. Examples of polymeric materials may include acrylic resins, epoxy resins, polyimides, and / or polyethylene. For example, the organic encapsulation layer 320 may include acrylic resins such as polymethyl methacrylate and / or polyacrylic acid. The organic encapsulation layer 320 may be formed by curing monomers and / or applying polymers.

[0278] The touchscreen layer TSL may include a first conductive layer MTL1 and a second conductive layer MTL2, wherein the first conductive layer MTL1 and the second conductive layer MTL2 include sensing electrodes and / or traces. A first insulating layer 410 may be positioned between the thin-film encapsulation layer TFE and the first conductive layer MTL1, and a second insulating layer 420 may be positioned between the first conductive layer MTL1 and the second conductive layer MTL2.

[0279] Each of the first conductive layer MTL1 and the second conductive layer MTL2 may include a conductive material. The conductive material may include molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a single-layer structure or a multi-layer structure including the above materials. In an embodiment, each of the first conductive layer MTL1 and the second conductive layer MTL2 may have a structure in which titanium layers, aluminum layers, and titanium layers are sequentially stacked (Ti / Al / Ti).

[0280] Each of the first insulating layer 410 and the second insulating layer 420 may include inorganic insulating materials and / or organic insulating materials. Inorganic insulating materials may include silicon oxide, silicon oxynitride, or silicon nitride. Organic insulating materials may include acrylic organic materials or imide organic materials.

[0281] The optical functional layer (OFL) can be positioned on the touchscreen layer (TSL). In an embodiment, the optical functional layer (OFL) may include, for example: Figure 14 The anti-reflective layer is shown in the diagram. The optical functional layer OFL can be directly positioned on the touchscreen layer TSL, or it can be as shown in the diagram. Figure 14 The location shown is the third insulating layer 430, situated between the optical functional layer OFL and the touchscreen layer TSL.

[0282] like Figure 14As shown, the optical functional layer OFL may include a filter plate comprising a black matrix 510 and a color filter 520. The filter plate may include a black matrix 510 and a color filter 520 positioned for each pixel, and a coating layer 530 covering the black matrix 510 and the color filter 520.

[0283] The color filter 520 can be positioned in the emission region of the auxiliary sub-pixel Pa. The color filter 520 can include red pigments or dyes, green pigments or dyes, or blue pigments or dyes, depending on the color of the light emitted by the auxiliary organic light-emitting diode OLED.

[0284] The black matrix 510 can be positioned in the non-emitting area and can be around the emitting area (e.g., surrounding the emitting area). The black matrix 510 can have through-holes formed in the transmissive area TA. In embodiments, the black matrix 510 can be stacked with the touch electrodes of the touchscreen layer TSL. For example, as... Figure 14 As shown, the second conductive layer MTL2 of the touchscreen layer TSL, which includes touch electrodes, can be stacked with the black matrix 510. The black matrix 510 may include an insulating material (e.g., an organic insulating material) containing black pigment or black dye.

[0285] Although the main reference Figure 13 and Figure 14 The auxiliary sub-pixel Pa, located in the component region CA, is described, but this structure can also be applied to the primary sub-pixel Pm.

[0286] According to one or more embodiments, a display device capable of providing high-quality images and improving the quality of images output through components can be provided. However, the disclosure is not limited to these effects.

[0287] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to figures, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the claims and their equivalents.

Claims

1. A display panel, the display panel comprising a main display area, a component area, and a peripheral area, the display panel comprising: Base; A main pixel circuit and a main display element connected to the main pixel circuit, the main pixel circuit and the main display element being positioned on the substrate at the main display area; An auxiliary display element is positioned on the substrate at the component area; An auxiliary pixel circuit is positioned on the substrate in the peripheral region; Connect the auxiliary display element to the auxiliary pixel circuit by wiring; as well as A first conductive layer is stacked with the auxiliary display element at the component region between the substrate and the auxiliary display element, and the first conductive layer includes a plurality of first holes.

2. The display panel according to claim 1, wherein, The auxiliary display element includes auxiliary pixel electrodes, and The first conductive layer is positioned between the substrate and the connecting wiring.

3. The display panel according to claim 2, wherein, The orthogonal projection image of the first conductive layer on the substrate is completely superimposed on the auxiliary pixel electrode.

4. The display panel according to claim 2, wherein, The area of ​​the first conductive layer is equal to or smaller than the area of ​​the auxiliary pixel electrode.

5. The display panel according to claim 2, wherein, The main pixel circuit includes: A thin-film transistor includes a semiconductor layer, a gate electrode, and an electrode layer connected to the semiconductor layer; and The storage capacitor includes a lower electrode integrally formed with the gate electrode and an upper electrode positioned on the lower electrode. The first conductive layer comprises the same material as the gate electrode or the upper electrode.

6. The display panel of claim 5, further comprising a second conductive layer positioned at the component region between the substrate and the auxiliary display element, the second conductive layer comprising a plurality of second holes.

7. The display panel according to claim 6, wherein, The second conductive layer is positioned on the first conductive layer.

8. The display panel according to claim 6, in, The first conductive layer comprises the same material as the gate electrode, and The second conductive layer comprises the same material as the upper electrode.

9. The display panel according to claim 6, wherein, The first conductive layer and the second conductive layer are electrically connected to each other.

10. The display panel according to claim 1, wherein, The first conductive layer is electrically connected to the connection wiring.

11. The display panel according to claim 1, wherein, The width of each of the plurality of first holes in a certain direction is in the range of 0.5 μm to 5 μm.

12. The display panel according to claim 1, wherein, The total area of ​​the plurality of first holes is equal to or less than 50% of the area of ​​the first conductive layer.

13. The display panel according to claim 1, wherein, The plurality of first holes have at least one of polygonal, circular, elliptical and irregular shapes, and the plurality of first holes are arranged regularly or irregularly.

14. The display panel according to claim 1, wherein, The plurality of first holes have a strip shape extending in a certain direction.

15. A display panel, the display panel comprising a main display area, a component area, and a peripheral area, the display panel comprising: Base; A main pixel circuit and a main display element connected to the main pixel circuit, the main pixel circuit and the main display element being positioned on the substrate at the main display area; An auxiliary pixel circuit and an auxiliary display element connected to the auxiliary pixel circuit, the auxiliary pixel circuit and the auxiliary display element being positioned on the substrate at the component region, the component region including an auxiliary display region provided with the auxiliary pixel circuit and the auxiliary display element and a transmissive region not provided with the auxiliary pixel circuit and the auxiliary display element; The transmitter is located in the component area on one side of the auxiliary pixel circuit and the auxiliary display element; A bottom metal layer is positioned between the substrate and the auxiliary pixel circuit. as well as The wiring includes the portion located between the transmissive area and the auxiliary display area. The auxiliary pixel circuit includes at least one thin-film transistor, and The bottom metal layer is patterned such that it overlaps only with the at least one thin-film transistor in the component region and not with the portion of the wiring.

16. The display panel according to claim 15, wherein, The auxiliary pixel circuit includes a first thin-film transistor and a second thin-film transistor. The bottom metal layer includes a stacked portion that is stacked with the first thin-film transistor and the second thin-film transistor respectively, and a connecting portion that connects the stacked portion.

17. The display panel according to claim 15, wherein, A signal or constant voltage is applied to the bottom metal layer.

18. The display panel according to claim 15, wherein, The auxiliary display element includes auxiliary pixel electrodes, and The display panel further includes a pixel defining layer with an opening through which the central portion of the auxiliary pixel electrode is exposed, and the pixel defining layer includes a light-shielding material.

19. A display device, the display device comprising: The display panel includes a main display area, a component area, and a peripheral area; as well as The component is positioned below the display panel in the component area. The display panel includes: Base; A main pixel circuit and a main display element connected to the main pixel circuit, the main pixel circuit and the main display element being positioned on the substrate at the main display area; An auxiliary display element is positioned on the substrate at the component area; An auxiliary pixel circuit is positioned on the substrate in the peripheral region; Connecting wiring to connect the auxiliary display element to the auxiliary pixel circuit; and A first conductive layer is positioned at the component region between the substrate and the auxiliary display element, and the first conductive layer includes a plurality of first holes.

20. The display device according to claim 19, wherein, The auxiliary display element includes auxiliary pixel electrodes, and The first conductive layer is positioned between the substrate and the auxiliary pixel electrode.

21. The display device according to claim 19, wherein, The auxiliary display element includes auxiliary pixel electrodes, and Wherein, the orthogonal projection image of the first conductive layer on the substrate is completely superimposed on the auxiliary pixel electrode.

22. The display device according to claim 19, wherein, The first conductive layer is electrically connected to the connection wiring.

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