Semiconductor structure
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-05-31
- Publication Date
- 2026-07-24
AI Technical Summary
In existing technologies, it is difficult to further improve the integration and storage capacity of memory cells, especially when the 2TOC structure extends perpendicular to the substrate, it cannot meet the large storage capacity requirements of semiconductor structures.
By arranging multiple memory cell layers at intervals within a dielectric layer in a direction perpendicular to the substrate, and arranging the source, channel, and drain in each memory cell in a direction parallel to the substrate, using columnar transistors as memory elements, and optimizing the connection method through staggered data lines, the number of parallel memory cells can be increased.
This improves the storage capacity and integration of semiconductor structures, reduces the height of storage cells, decreases fabrication difficulty, and enhances signal transmission efficiency and semiconductor structure performance.
Smart Images
Figure CN115020480B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor structure. Background Technology
[0002] Dynamic random access memory (DRAM) is a semiconductor memory that allows for high-speed, random writing and reading of data, and is widely used in data storage devices. DRAM consists of multiple repeating memory cells, each typically including a capacitor and a transistor. The capacitor stores data, and the transistor controls the reading of data from the capacitor.
[0003] To improve the integration of memory cells and facilitate their development towards integration, related technologies have improved memory cells. For example, a memory cell may include a first transistor and a second transistor that are interconnected, using one of the first transistor and the second transistor as a storage element. However, this structure cannot meet the demand for large storage capacity in semiconductor structures and has limitations in its use. Summary of the Invention
[0004] In view of the above problems, this disclosure provides a semiconductor structure that can improve the integration and storage capacity of the semiconductor structure.
[0005] This disclosure provides a semiconductor structure comprising:
[0006] Base;
[0007] A dielectric layer disposed on the substrate;
[0008] Multiple memory cell layers are spaced apart within the dielectric layer along a first direction, and any two adjacent memory cell layers project onto the substrate. Each memory cell layer includes multiple memory cells spaced apart along a second direction. Each memory cell includes a first transistor and a second transistor connected to the first transistor. The first source, first channel, and first drain of the first transistor are arranged along a third direction, which is parallel to the substrate. The first direction, the second direction, and the third direction are perpendicular to each other, and the second direction and the third direction are located in the same horizontal plane.
[0009] In some embodiments, the first transistor is a columnar transistor, and the first transistor further includes a first gate and a first gate oxide layer, the first gate oxide layer and the first channel sequentially surround a portion of the first gate, and the first source and the first drain are disposed on the first channel at a distance.
[0010] In some embodiments, along the third direction, the first source and the first drain respectively wrap around the two opposite ends of the first channel.
[0011] In some embodiments, the second transistor is a pillar transistor, and the second transistor includes a second gate, a second channel, a second source, a second drain, and a second gate oxide layer; the second source is electrically connected to the exposed portion of the first gate;
[0012] The second gate oxide layer and the second channel sequentially surround a portion of the second gate, and the second source and the second drain are disposed on the second channel at intervals.
[0013] In some embodiments, the second source and the second drain respectively wrap around the two opposite ends of the second channel.
[0014] In some embodiments, the first channel and the second channel are made of the same material, both including any one of indium gallium zinc oxide, silicon, and silicon germanium.
[0015] In some embodiments, the semiconductor structure further includes a first data line, a second data line, a third data line, and a fourth data line;
[0016] Of the first data line and the second data line, one is used to connect the first source or the first drain of all the first transistors located in the same first direction, and the other is used to connect the first drain or the first source of all the first transistors located on the same layer.
[0017] Of the third data line and the fourth data line, one is used to connect the second drain or the second gate of the second transistor located in the same first direction, and the other is used to connect the second gate or the second drain of all the second transistors located on the same layer.
[0018] In some embodiments, the number of the first data line, the second data line, the third data line, and the fourth data line is multiple;
[0019] Multiple first data lines are spaced apart along the second direction, each first data line extending along the first direction and connecting all first source electrodes located in the same first direction;
[0020] Multiple second data lines are spaced apart along the first direction, each second data line extends along the second direction and connects to all the first drains located on the same layer; in two adjacent second data lines, the projection of one second data line on the substrate partially overlaps with the projection of the other second data line on the substrate.
[0021] Multiple third data lines are spaced apart along the second direction, each third data line extends along the first direction and connects to all second drains located in the same first direction;
[0022] Multiple fourth data lines are spaced apart along the first direction, each fourth data line extends along the second direction and connects to all second gates located on the same layer; in two adjacent fourth data lines, the projection of one fourth data line on the substrate partially overlaps with the projection of the other fourth data line on the substrate.
[0023] In some embodiments, along the second direction, each of the second data lines has a first surface and a second surface disposed opposite to each other;
[0024] One of the first and second surfaces of all the second data lines is aligned, and the other forms a step from top to bottom along the first direction; or, all the second data lines are of the same length, and the first and second surfaces of any two adjacent second data lines are not aligned.
[0025] In some embodiments, along the third direction, each of the second data lines has a third surface and a fourth surface disposed opposite to each other;
[0026] One of the third and fourth surfaces of all the second data lines is aligned, and the other forms a step from top to bottom along the first direction.
[0027] In some embodiments, the structure of the fourth data line is the same as that of the second data line.
[0028] In some embodiments, each of the first data lines extends along the second direction and connects all the first sources located on the same layer. In two adjacent first data lines, the projection of one of the first data lines onto the substrate partially overlaps with the projection of the other first data line onto the substrate.
[0029] Each of the second data lines extends along a first direction and is connected to a first drain located in the same first direction;
[0030] Each of the third data lines extends along the second direction and connects all the second drains located on the same layer; in two adjacent third data lines, the projection of one of the third data lines onto the substrate partially coincides with the projection of the other third data line onto the substrate.
[0031] Each of the fourth data lines extends along the first direction and connects to the second gate located in the same first direction.
[0032] In some embodiments, along the second direction, each of the first data lines has a fifth surface and a sixth surface disposed opposite to each other;
[0033] One of the fifth and sixth surfaces of all the first data lines is aligned, and the other forms a step from top to bottom along the first direction; or, all the first data lines are of the same length, and the fifth and sixth surfaces of any two adjacent first data lines are not aligned.
[0034] In some embodiments, along the third direction, each of the first data lines has a seventh surface and an eighth surface disposed opposite to each other;
[0035] One of the seventh and eighth surfaces of all the first data lines is aligned, and the other is formed into a step from top to bottom along the first direction.
[0036] In some embodiments, the structure of the third data line is the same as that of the first data line.
[0037] In some embodiments, the first data line is a read bit line, the second data line is a read word line, the third data line is a write bit line, and the fourth data line is a write word line.
[0038] In some embodiments, an insulating layer is provided between the third data line and the fourth data line.
[0039] Compared with related technologies, the semiconductor structure provided in this disclosure has the following advantages:
[0040] By arranging multiple memory cell layers spaced apart within a dielectric layer in a direction perpendicular to the substrate, and each memory cell layer containing multiple memory cells, with the source, channel, and drain of each memory cell arranged in a direction parallel to the substrate, each memory cell can be placed in parallel. This increases the number of stacked memory cell layers and improves the storage capacity of the semiconductor structure.
[0041] In addition to the technical problems solved by the embodiments of this disclosure, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that the semiconductor structure provided by the embodiments of this disclosure can solve, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation. Attached Figure Description
[0042] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0043] Figure 1 This is a schematic diagram of the structure of the storage unit layer provided in an embodiment of the present disclosure;
[0044] Figure 2 for Figure 1 The main view;
[0045] Figure 3 for Figure 1 Top view;
[0046] Figure 4 This is a schematic diagram of the structure of the storage unit and various data lines provided in the embodiments of this disclosure;
[0047] Figure 5 A schematic diagram of the structure of the first transistor provided in an embodiment of this disclosure;
[0048] Figure 6 Circuit diagrams of the storage unit and various data lines provided in the disclosed embodiments;
[0049] Figure 7 A schematic diagram of the semiconductor structure provided in the embodiments of this disclosure. Figure 1 ;
[0050] Figure 8 for Figure 7 Top view;
[0051] Figure 9 A schematic diagram of the semiconductor structure provided in the embodiments of this disclosure. Figure 2 ;
[0052] Figure 10 A schematic diagram of the semiconductor structure provided in the embodiments of this disclosure. Figure 3 ;
[0053] Figure 11 for Figure 10 Top view;
[0054] Figure 12 A schematic diagram of the semiconductor structure provided in the embodiments of this disclosure. Figure 4 ;
[0055] Figure 13 for Figure 12 Top view;
[0056] Figure 14A schematic diagram of the semiconductor structure provided in the embodiments of this disclosure. Figure 5 ;
[0057] Figure 15 for Figure 14 Top view;
[0058] Figure 16 A schematic diagram of the semiconductor structure provided in the embodiments of this disclosure. Figure 6 ;
[0059] Figure 17 for Figure 16 Top view.
[0060] Figure label:
[0061] 10: Storage unit layer;
[0062] 11: Storage unit;
[0063] 111: First transistor; 1111: First source; 1112: First drain; 1113: First channel; 1114: First gate oxide layer; 1115: First gate;
[0064] 112: Second transistor; 1121: Second source; 1122: Second drain; 1123: Second channel; 1124: Second gate oxide layer; 1125: Second gate;
[0065] 20: First data line; 21: Fifth surface; 22: Sixth surface; 23: Seventh surface; 24: Eighth surface;
[0066] 30: Second data line; 31: First surface; 32: Second surface; 33: Third surface; 34: Fourth surface;
[0067] 40: Third data line;
[0068] 50: Fourth data line;
[0069] 60: Insulation layer. Detailed Implementation
[0070] As described in the background art, in order to facilitate the development of memory cells towards integration, in related technologies, memory cells have gradually evolved from a 1T1C structure to a 2T0C structure, that is, using one of the first transistor and the second transistor as a storage element to reduce the volume occupied by the memory cell. However, the aforementioned memory cells usually extend in a direction perpendicular to the substrate. As a result, it is difficult to fabricate more memory cells on the substrate, and thus cannot meet the requirements of large storage capacity of semiconductor structures, resulting in a limitation in use.
[0071] Based on the above-mentioned technical problems, this disclosure provides a semiconductor structure in which multiple memory cell layers are spaced apart in a direction perpendicular to the substrate within a dielectric layer, and each memory cell layer has multiple memory cells. The source, channel, and drain of each memory cell are arranged in a direction parallel to the substrate. In this way, each memory cell can be placed in parallel, thereby increasing the number of stacked memory cell layers and improving the storage capacity of the semiconductor structure.
[0072] To make the above-mentioned objects, features, and advantages of the embodiments of this disclosure more apparent and understandable, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.
[0073] This disclosure provides a semiconductor structure, with reference to... Figures 1 to 4 The semiconductor structure includes a substrate (not shown in the figure), a dielectric layer (not shown in the figure), and a memory cell layer 10. The substrate provides support and can be made of a semiconductor material, which can be one or more of silicon, germanium, silicon germanide, silicon carbide, silicon-on-insulator, or germanium-on-insulator.
[0074] A dielectric layer is disposed on the substrate to provide support for the memory cell layer 10 and to achieve electrical insulation between each memory cell layer 10. The dielectric layer may include silicon oxide or silicon nitride.
[0075] Multiple storage cell layers 10 are disposed within the media layer. It should be noted that one storage cell layer 10 is... Figure 1 The structure shown within the dashed box.
[0076] In this configuration, multiple storage cell layers 10 are spaced apart within the dielectric layer along a first direction, and any two adjacent storage cell layers 10 project onto the substrate and overlap. This ensures that the multiple storage cell layers 10 are aligned in the first direction, thereby facilitating the fabrication of the storage cell layers 10 and reducing the fabrication difficulty of the storage cell layers 10.
[0077] Each storage cell layer 10 includes a plurality of storage cells 11 spaced apart along a second direction. Each storage cell 11 includes a first transistor 111 and a second transistor 112 connected to the first transistor 111. One of the first transistor 111 and the second transistor 112 is used as a storage element to replace the capacitor in the related technology. In this way, the volume occupied by the storage cell 11 can be reduced, which provides a guarantee for the development of the storage cell 11 towards integration.
[0078] The first source 1111, the first channel 1113, and the first drain 1112 of the first transistor 111 are arranged along a third direction, which is parallel to the substrate. The first direction, the second direction, and the third direction are perpendicular to each other, and the second direction and the third direction are located in the same horizontal plane, which is parallel to the plane on which the substrate is located. In this way, each memory cell 11 can be placed parallel to the substrate. Compared with the related technology where the memory cell 11 is placed perpendicular to the substrate, the height of the memory cell 11 can be reduced. Under the premise of the same height semiconductor structure, the number of stacked memory cell layers 10 can be increased, thereby increasing the number of memory cells 11 and improving the storage capacity of the semiconductor structure.
[0079] The first direction can be a direction perpendicular to the base, i.e. Figure 1 The Z-direction. The second direction can be... Figure 1 In the Y direction, the third direction is Figure 1 The X direction in the equation.
[0080] It should be noted that the first transistor 111 and the second transistor 112 have the same structure. Therefore, the arrangement direction of the second source 1121, the second channel 1123 and the second drain 1122 of the second transistor 112 is also the third direction.
[0081] In some embodiments, such as Figure 5 As shown, the first transistor 111 is a columnar transistor. The first transistor 111 also includes a first gate 1115 and a first gate oxide layer 1114. The first gate 1115 has a columnar structure and extends in a third direction. The first gate oxide layer 1114 and the first channel 1113 sequentially surround a portion of the first gate 1115. That is, the first gate oxide layer 1114 and the first channel 1113 form a hollow columnar body, and the hollow columnar body has an opening at one end. One end of the first gate 1115 is inserted into the area surrounded by the first gate oxide layer 1114 and the first channel 1113 through the opening, and the other end of the first gate 1115 is located outside the area surrounded by the first gate oxide layer 1114 and the first channel 1113. This exposes a portion of the first gate 1115 so that the data lines formed subsequently can be connected to the first gate 1115 to control the opening or closing of the first transistor 111.
[0082] The first source 1111 and the first drain 1112 are disposed at intervals on the first channel 1113, wherein the first source 1111 and the first drain 1112 respectively wrap around the two opposite ends of the first channel 1113. In this way, the contact area between the first source 1111 and the first channel 1113 and the first drain 1112 and the first channel 1113 can be increased, thereby improving the sensitivity of the first transistor 111 and improving the performance of the semiconductor structure.
[0083] by Figure 5 Taking the orientation shown as an example, along the third direction, the first channel 1113 has a first end and a second end that are arranged opposite to each other. The first end can be the left end of the first channel 1113, and the second end is the right end of the first channel 1113.
[0084] In one example, the first source 1111 may be wrapped around the first end and the first drain 1112 may be wrapped around the second end; in another example, the first source 1111 may be wrapped around the second end and the second drain 1122 may be wrapped around the first end.
[0085] In this embodiment, a portion of the first gate 1115 is wrapped by the first channel 1113, which reduces the path of gate leakage and improves the performance of the semiconductor structure.
[0086] In some embodiments, continue to refer to Figure 4 The second transistor 112 is a columnar transistor, which includes a second gate 1125, a second channel 1123, a second source 1121, and a second drain 1122. The second source 1121 is electrically connected to the exposed portion of the first gate 1115 to realize the electrical connection between the first transistor 111 and the second transistor 112.
[0087] The second gate oxide layer 1124 and the second channel 1123 sequentially surround a portion of the second gate 1125. The second source 1121 and the second drain 1122 are disposed at intervals on the second channel 1123, wherein the second source 1121 and the second drain 1122 respectively wrap around two opposite ends of the second channel 1123.
[0088] It should be noted that the configuration of the second source 1121 and the second drain 1122 is similar to that of the first source 1111 and the first drain 1112, and will not be described in detail here.
[0089] In some embodiments, the first channel 1113 and the second channel 1123 are made of the same material, both including any one of indium gallium zinc oxide, silicon, and silicon germanium.
[0090] When the first channel 1113 and the second channel 1123 are both made of indium gallium zinc oxide, indium gallium zinc oxide has a high carrier mobility, which can greatly improve the sensitivity of the first transistor 111 and / or the second transistor 112 and reduce the power consumption of the memory cell 11.
[0091] Indium gallium zinc oxide also has good fluidity, allowing it to be grown at any desired interface, which can reduce the difficulty of semiconductor structure fabrication.
[0092] Indium gallium zinc oxide also has a high off-state current, which can reduce the gate-induced drain leakage current of the semiconductor structure and improve the performance of the semiconductor structure.
[0093] Indium gallium zinc oxide (IGNOW) is transparent, allowing the first transistor 111 to be used in the fabrication of transparent semiconductor devices. IGNOW can also be fabricated at low temperatures, enabling the first transistor 111 to be used in the fabrication of flexible semiconductor devices.
[0094] In some embodiments, such as Figures 6 to 17 As shown, the semiconductor structure also includes a first data line 20, a second data line 30, a third data line 40, and a fourth data line 50, which are used to control the operating state of the first transistor 111 and the second transistor 112.
[0095] In this embodiment, of the first data line 20 and the second data line 30, one is used to connect the first source 1111 or the first drain 1112 of all first transistors 111 located in the same first direction, and the other is used to connect the first drain 1112 or the first source 1111 of all first transistors 111 located on the same layer. In some embodiments, when the first data line 20 is connected to the first source 1111 of all first transistors 111 located in the same first direction, that is, when the first data line 20 is connected to the first source 1111 of all first transistors 111 located in the same column, the second data line 30 is correspondingly connected to the first drain 1112 of all first transistors 111 located on the same layer. In other embodiments, when the first data line 20 is connected to the first drain 1112 of all first transistors 111 located in the same column, the second data line 30 is correspondingly connected to the first source 1111 of the first transistors 111 located on the same layer.
[0096] When the first data line 20 is connected to the first source 1111 of all the first transistors 111 located on the same layer, the second data line 30 is used to connect the first drain 1112 of all the first transistors 111 located on the same column; when the first data line 20 is connected to the first drain 1112 of all the first transistors 111 located on the same layer, the second data line 30 is used to connect the first source 1111 of all the first transistors 111 located on the same column.
[0097] Of the third data line 40 and the fourth data line 50, one is used to connect to the second drain 1122 or the second gate 1125 of the second transistor 112 located in the same first direction, and the other is used to connect to the second gate 1125 or the second drain 1122 of the second transistor 112 located on the same layer. It should be noted that the arrangement of the third data line 40 and the fourth data line 50 can be similar to the arrangement of the first data line 20 and the second data line 30, and will not be elaborated further in this embodiment.
[0098] In this embodiment, the connection method between each data line and the storage unit 11 can be freely designed, which can facilitate the fabrication of the storage unit 11 and improve the applicability of the semiconductor structure.
[0099] In this embodiment, the multiple data lines connecting transistors located on the same layer are staggered vertically in the first direction. In one example, if the first data line is used to connect to the first transistor on the same layer, then the multiple first data lines are staggered vertically in the first direction. In another example, if the second data line is used to connect to the first transistor on the same layer, then the multiple second data lines are staggered vertically in the first direction. This facilitates the connection of data lines connecting transistors on the same layer to other data lines, reducing the difficulty of semiconductor structure fabrication.
[0100] It should be noted that the configuration of the third and fourth data lines is the same as that of the first and second data lines, and will not be described in detail here.
[0101] In some embodiments, there are multiple first data lines 20, second data lines 30, third data lines 40, and fourth data lines 50.
[0102] like Figures 7 to 17 As shown, multiple first data lines 20 are spaced apart along a second direction, and multiple first data lines 20 are spaced apart along a Y direction. Each first data line 20 extends along a first direction and connects to all first sources 1111 located in the same first direction; Figure 7Taking the orientation shown as an example, the first data line 20 extends in a direction perpendicular to the substrate and connects all the first sources 1111 located in the same column. In some embodiments, there are three first data lines 20, wherein, in the second direction, the first data line 20 connects all the first sources 1111 in the first column, the second data line 20 connects all the first sources 1111 in the second column, and the third data line 20 connects all the first sources 1111 in the third column.
[0103] Multiple second data lines 30 are spaced apart along a first direction, that is, multiple second data lines 30 are spaced apart along a direction perpendicular to the substrate. Each second data line 30 extends along a second direction and connects to all first drains 1112 located on the same layer. In two adjacent second data lines 30, the projection of one second data line 30 onto the substrate partially overlaps with the projection of the other second data line 30 onto the substrate.
[0104] by Figure 7 Taking the orientation shown as an example, the projection of the first second data line 30 on the substrate partially coincides with the projection of the second second data line 30 on the substrate. This proves that the first second data line 30 and the second second data line 30 are misaligned. In this way, on the one hand, it can facilitate the connection of other signal lines with the second data line 30, reducing the difficulty of semiconductor structure fabrication; on the other hand, it can reduce the parasitic capacitance between the upper and lower layers of second data lines 30, improving the performance of the semiconductor structure.
[0105] Continue to refer to Figures 7 to 17 Multiple third data lines 40 are spaced apart along the second direction, and each third data line 40 extends along the first direction and connects to all second drains 1122 located in the same first direction.
[0106] Multiple fourth data lines 50 are spaced apart along a first direction, and each fourth data line 50 extends along a second direction and connects to all second gates 1125 located on the same layer; in two adjacent fourth data lines 50, the projection of one fourth data line 50 on the substrate partially overlaps with the projection of the other fourth data line 50 on the substrate.
[0107] In this embodiment, by staggering the adjacent fourth data lines 50, on the one hand, it facilitates the connection between the other signal lines and the fourth data lines 50, reducing the difficulty of fabricating the semiconductor structure; on the other hand, it reduces the parasitic capacitance between the upper and lower fourth data lines 50, improves the turn-on sensitivity of the second transistor 112, and thus improves the performance of the semiconductor structure.
[0108] The misalignment of all second data lines 30 and all fourth data lines 50 can be described by the following implementation methods. It should be noted that the following implementation methods are only examples of several feasible implementation methods, and do not limit the structure and shape of the second data lines 30 or the fourth data lines 50.
[0109] Along the second direction, each second data line 30 has a first surface 31 and a second surface 32 disposed opposite to each other; Figure 7 and Figure 8 Taking the orientation shown as an example, the first surface 31 can be understood as the front surface of the second data line 30, and the second surface 32 can be understood as the rear surface of the second data line 30.
[0110] In one example, the first surfaces 31 and 32 of all the second data lines 30 are aligned, while the other surface forms a step from top to bottom along a first direction. In another example, the first surfaces 31 of all the second data lines 30 are aligned, while the second surfaces 32 are not aligned, and the length of the second data lines 30 increases sequentially from top to bottom, thus forming a step on the second surfaces 32 of all the second data lines 30. In yet another example, the first surfaces 31 of all the second data lines 30 are not aligned, while the second surfaces 32 are aligned, resulting in a step on the first surfaces 31 of all the second data lines 30. This facilitates the fabrication of the remaining data lines and increases the spacing between them, preventing interference with transmitted signals. Furthermore, it reduces the parasitic capacitance between the upper and lower layers of second data lines 30, improving the performance of the semiconductor structure.
[0111] In another example, such as Figure 9 As shown, all the second data lines 30 are of the same length; the first surfaces 31 and second surfaces 32 of any two adjacent second data lines 30 are not aligned. That is, from top to bottom, the second surface 32 of the second data line 30 is behind the second surface 32 of the first data line 30, and the first surface 31 of the third data line 30 is in front of the first surface 31 of the first data line 30. In this way, it can be ensured that the three second data lines 30 are staggered in pairs.
[0112] In yet another example, such as Figure 10 and Figure 11 As shown, along the third direction, each second data line 30 has a third surface 33 and a fourth surface 34 disposed opposite to each other; Figure 10 and Figure 11 Taking the orientation shown as an example, the third surface 33 is the left surface of the second data line 30, and the fourth surface 34 is the right surface of the second data line 30.
[0113] One of the third surfaces 33 and the fourth surfaces 34 of all the second data lines 30 is aligned, and the other forms a step from top to bottom along the first direction. That is, when all the third surfaces 33 are aligned, all the fourth surfaces 34 form a step.
[0114] Since the fourth data line 50 is used to connect the second gate 1125 of all the second transistors 112 in the same layer, in order to facilitate the connection of other data lines with the fourth data line 50, the structure of the fourth data line 50 can be the same as the structure of the second data line 30. The structure of the fourth data line 50 can refer to the structure of the second data line 30. This embodiment will not be described in detail here.
[0115] In some embodiments, such as Figure 16 and Figure 17 As shown, each first data line 20 extends along the second direction and connects to all first sources 1111 located on the same layer. In two adjacent first data lines 20, the projection of one first data line 20 onto the substrate partially overlaps with the projection of the other first data line 20 onto the substrate. Each second data line 30 extends along the first direction and connects to the first drain 1112 located in the same first direction.
[0116] This embodiment sets any two adjacent first data lines 20 in a staggered manner. On the one hand, this facilitates the connection between the other signal lines and the first data lines 20, reducing the difficulty of semiconductor structure fabrication; on the other hand, it reduces the parasitic capacitance between the upper and lower layers of first data lines 20, improving the performance of the semiconductor structure.
[0117] In addition, each third data line 40 extends along the second direction and connects to all second drains 1122 located on the same layer; in two adjacent third data lines 40, the projection of one third data line 40 onto the substrate partially overlaps with the projection of the other third data line 40 onto the substrate; each fourth data line 50 extends along the first direction and connects to the second gate 1125 located in the same first direction.
[0118] This embodiment sets any two adjacent third data lines 40 in a staggered manner. This facilitates the connection between the other signal lines and the third data lines 40, reducing the difficulty of semiconductor structure fabrication. On the other hand, it reduces the parasitic capacitance between the upper and lower third data lines 40, improving the performance of the semiconductor structure.
[0119] The misalignment of all first data lines 20 and all third data lines 40 can be described through the following implementation methods. It should be noted that the following implementation methods are only examples of several feasible implementation methods, and do not limit the structure and shape of the first data lines 20 or the third data lines 40.
[0120] In the second direction, each first data line 20 has a fifth surface 21 and a sixth surface 22 disposed opposite to each other; in the third direction, each first data line 20 has a seventh surface 23 and an eighth surface 24 disposed opposite to each other; Figure 16 and Figure 17 Taking the orientation shown as an example, the fifth surface 21 is the front surface of the first data line 20, the sixth surface 22 is the rear surface of the first data line 20, the seventh surface 23 is the left surface of the first data line 20, and the eighth surface 24 is the right surface of the first data line 20.
[0121] In one example, one of the fifth surface 21 and the sixth surface 22 of all the first data lines 20 is aligned, and the other forms a step from top to bottom along the first direction; or all the second data lines 30 are of the same length, and the fifth surface 21 and the sixth surface 22 of any two adjacent first data lines 20 are not aligned.
[0122] In yet another example, one of the seventh surface 23 and the eighth surface 24 of all the first data lines 20 is aligned, while the other forms a step from top to bottom along the first direction.
[0123] It should be noted that the layout of the first data line 20 in this embodiment is similar to that of the second data line 30 in the above embodiment, which has a stepped layout. Therefore, this embodiment will not elaborate further.
[0124] In this embodiment, since the third data line 40 is used to connect the second drain 1122 of all the second transistors 112 in the same layer, in order to facilitate the connection of other data lines with the third data line 40, the structure of the third data line 40 can be the same as the structure of the first data line 20. The structure of the third data line 40 can refer to the structure of the first data line 20. This embodiment will not be described in detail here.
[0125] In some embodiments, continue to refer to Figure 4 and Figure 6 The first data line 20 is the read bit line, the second data line 30 is the read word line, the third data line 40 is the write bit line, and the fourth data line 50 is the write word line.
[0126] When the potential of the fourth data line 50 is high, this high level can control the gate of the second transistor 112 to turn on, and a voltage difference is generated between the second source 1121 and the second drain 1122 of the second transistor 112, so that the second source 1121 and the second drain 1122 of the second transistor 112 are turned on. The voltage on the third data line 40 will act on the gate of the first transistor 111, and write the data on the third data line 40 into the first transistor 111, thus realizing the data writing.
[0127] When it is necessary to read the data in the first transistor 111, the gate of the first transistor 111 will be turned on, so that the first source 1111 and the first drain 1112 of the first transistor 111 will be connected. At this time, the data in the first transistor 111 will be transmitted to the peripheral circuit through the second data line 30. The peripheral circuit will process the data to realize the memory read function.
[0128] In some embodiments, an insulating layer 60 is provided between the third data line 40 and the fourth data line 50. This prevents electrical connection between the third data line 40 and the fourth data line 50, thereby improving the yield of the semiconductor structure. The insulating layer 60 may be made of silicon nitride, but is not limited to this.
[0129] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.
[0130] In the description of this specification, references to terms such as “one embodiment,” “some embodiments,” “illustrative embodiment,” “example,” “specific example,” or “some examples” refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this disclosure.
[0131] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.
[0132] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.
Claims
1. A semiconductor structure, characterized in that, include: Base; A dielectric layer disposed on the substrate; Multiple memory cell layers are spaced apart within the dielectric layer along a first direction, and any two adjacent memory cell layers project onto the substrate; each memory cell layer includes multiple memory cells spaced apart along a second direction, and each memory cell includes a first transistor and a second transistor connected to the first transistor; the first source, first channel, and first drain of the first transistor are arranged along a third direction, which is parallel to the substrate; the first direction, the second direction, and the third direction are perpendicular to each other, and the second direction and the third direction are located in the same horizontal plane; The first transistor is a columnar transistor. The first transistor further includes a first gate and a first gate oxide layer. The first gate oxide layer and the first channel sequentially surround a portion of the first gate. The first source and the first drain are disposed on the first channel at a distance. The second transistor is a pillar transistor, and the second transistor includes a second gate, a second channel, a second source, a second drain, and a second gate oxide layer; the second source is electrically connected to the exposed portion of the first gate; The second gate oxide layer and the second channel sequentially surround a portion of the second gate, and the second source and the second drain are disposed at intervals on the second channel.
2. The semiconductor structure according to claim 1, characterized in that, Along the third direction, the first source and the first drain respectively wrap around the two opposite ends of the first channel.
3. The semiconductor structure according to claim 1, characterized in that, The second source and the second drain respectively wrap around the two opposite ends of the second channel.
4. The semiconductor structure according to claim 3, characterized in that, The first channel and the second channel are made of the same material, including any one of indium gallium zinc oxide, silicon, and silicon germanium.
5. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a first data line, a second data line, a third data line, and a fourth data line; Of the first data line and the second data line, one is used to connect the first source or the first drain of all the first transistors located in the same first direction, and the other is used to connect the first drain or the first source of all the first transistors located on the same layer. Of the third data line and the fourth data line, one is used to connect the second drain or the second gate of the second transistor located in the same first direction, and the other is used to connect the second gate or the second drain of all the second transistors located on the same layer.
6. The semiconductor structure according to claim 5, characterized in that, The number of the first data line, the second data line, the third data line, and the fourth data line is multiple; Multiple first data lines are spaced apart along the second direction, each first data line extending along the first direction and connecting all first source electrodes located in the same first direction; Multiple second data lines are spaced apart along the first direction, each second data line extends along the second direction and connects to all the first drains located on the same layer; in two adjacent second data lines, the projection of one second data line on the substrate partially overlaps with the projection of the other second data line on the substrate. Multiple third data lines are spaced apart along the second direction, each third data line extends along the first direction and connects to all second drains located in the same first direction; Multiple fourth data lines are spaced apart along the first direction, each fourth data line extends along the second direction and connects to all second gates located on the same layer; in two adjacent fourth data lines, the projection of one fourth data line on the substrate partially overlaps with the projection of the other fourth data line on the substrate.
7. The semiconductor structure according to claim 6, characterized in that, Along the second direction, each of the second data lines has a first surface and a second surface that are disposed opposite to each other; One of the first and second surfaces of all the second data lines is aligned, and the other forms a step from top to bottom along the first direction; or, all the second data lines are of the same length, and the first and second surfaces of any two adjacent second data lines are not aligned.
8. The semiconductor structure according to claim 6, characterized in that, Along the third direction, each of the second data lines has a third surface and a fourth surface that are disposed opposite to each other; One of the third and fourth surfaces of all the second data lines is aligned, and the other forms a step from top to bottom along the first direction.
9. The semiconductor structure according to claim 7 or 8, characterized in that, The structure of the fourth data line is the same as that of the second data line.
10. The semiconductor structure according to claim 5, characterized in that, Each of the first data lines extends along the second direction and connects all the first sources located on the same layer. In two adjacent first data lines, the projection of one of the first data lines onto the substrate partially overlaps with the projection of the other first data line onto the substrate. Each of the second data lines extends along a first direction and is connected to a first drain located in the same first direction; Each of the third data lines extends along the second direction and connects all the second drains located on the same layer; in two adjacent third data lines, the projection of one of the third data lines onto the substrate partially coincides with the projection of the other third data line onto the substrate. Each of the fourth data lines extends along the first direction and connects to the second gate located in the same first direction.
11. The semiconductor structure according to claim 10, characterized in that, Along the second direction, each of the first data lines has a fifth surface and a sixth surface disposed opposite to each other; One of the fifth and sixth surfaces of all the first data lines is aligned, and the other forms a step from top to bottom along the first direction; or, all the first data lines are of the same length; the fifth and sixth surfaces of any two adjacent first data lines are not aligned.
12. The semiconductor structure according to claim 11, characterized in that, Along the third direction, each of the first data lines has a seventh surface and an eighth surface that are disposed opposite to each other; One of the seventh and eighth surfaces of all the first data lines is aligned, and the other is formed into a step from top to bottom along the first direction.
13. The semiconductor structure according to claim 11 or 12, characterized in that, The structure of the third data line is the same as that of the first data line.
14. The semiconductor structure according to claim 5, characterized in that, The first data line is a read bit line, the second data line is a read word line, the third data line is a write bit line, and the fourth data line is a write word line.
15. The semiconductor structure according to claim 14, characterized in that, An insulating layer is provided between the third data line and the fourth data line.