Calibration circuit, calibration method and filter device for a filter

Abstract

The application discloses a filter calibration circuit, a calibration method and a filtering device. The calibration circuit comprises a signal receiving end connected with the filter and used for receiving an output signal from the filter; a frequency detection module connected with the signal receiving end and used for obtaining a count value based on the output signal, the count value representing the frequency of the output signal; and an adjustment module connected with the frequency detection module and used for adjusting a control signal according to the count value and a target value representing a target frequency, so as to adjust the frequency of the output signal provided by the filter until a calibration value of the control signal is determined, which makes the count value consistent with the target value; wherein the filter performs filtering based on the control signal with the calibration value in a working stage. The calibration circuit uses feedback regulation of the filter to realize bandwidth calibration, has high calibration precision and simple circuit structure.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more specifically, to a calibration circuit, calibration method, and filtering device for a filter. Background Technology

[0002] With the development of technology, communication systems are increasingly being applied in various fields such as education, transportation, scientific research, and daily life. In the receiver of a communication system, the filter is an indispensable module. Bandwidth is one of the important parameters of a filter; excessively high bandwidth will degrade the system's noise performance and may even affect its linearity, while insufficient bandwidth will filter out useful signals, increase the bit error rate, and reduce receiver performance. Therefore, accurately controlling the filter's bandwidth is of great significance. When a filter has a suitable bandwidth, it can effectively filter out out-of-band noise and interference and improve the receiver's sensitivity. However, it is currently difficult to achieve precise bandwidth for filters. Summary of the Invention

[0003] This application provides a calibration circuit, calibration method, and filtering device for a filter, with the aim of improving the accuracy of the filtering bandwidth.

[0004] Firstly, a calibration circuit for a filter is provided. The filter performs filtering under the configuration of a control signal to provide an output signal. The calibration circuit includes: a signal receiving terminal connected to the filter for receiving the output signal from the filter; a frequency detection module connected to the signal receiving terminal for obtaining a count value based on the output signal, the count value representing the frequency of the output signal; and an adjustment module connected to the frequency detection module for adjusting the control signal according to the count value and a target value representing a target frequency, thereby adjusting the frequency of the output signal provided by the filter until a calibration value of the control signal that makes the count value consistent with the target value is determined. The filter performs filtering based on the control signal having the calibration value during its operation. This calibration circuit can adjust the output signal of the filter to have a target frequency, realizing the filter's own feedback adjustment, and has high bandwidth calibration accuracy, a simple circuit structure, and advantages such as high integration, accurate bandwidth, and low power consumption.

[0005] Optionally, the adjustment module is further configured to provide an initial value for the control signal, so that the filter, during the startup phase prior to the operating phase, first provides an output signal with an initial frequency based on the control signal having the initial value. In this technical solution, the configuration of the initial value enables the control signal to exert its control effect on the filter at different stages, which can further simplify the circuit structure.

[0006] Optionally, the adjustment module stores multiple control signals with different initial values. After acquiring the target value, the adjustment module selects the control signal from the multiple control signals that minimizes the difference between the initial frequency and the target frequency of the output signal and provides it to the filter. In this technical solution, selecting a suitable initial value for the control signal based on the target frequency can save time required for bandwidth calibration and reduce circuit power consumption.

[0007] Optionally, the frequency detection module includes: a level shifter connected to the signal input terminal for amplifying the output signal; a comparator connected to the level shifter for comparing the amplitude of the amplified output signal with a reference value to generate a square wave signal; and a counter connected to the comparator for counting the rising edges of the square wave signal to obtain the count value. In this technical solution, the level shifter is advantageous for frequency detection of output signals with small voltage amplitudes. It should be understood that in some practical applications, the level shifter can be omitted. This frequency detection module uses a comparator to convert the output signal into a square wave signal so that the counter can count the rising edges, enabling simple and rapid detection of the output signal's frequency.

[0008] Optionally, the adjustment module includes: a difference calculator for calculating the difference between the count value and the target value; a binary search calculation unit for adjusting a control signal based on the difference, the control signal being used to control the conduction state of each filter element in the filter; and a storage unit for storing the initial value of the control signal, a control signal that makes the difference relatively small, and a calibration value of the control signal. This adjustment module uses the binary search principle to find the calibration value of the control signal, enabling rapid lookup and saving time required for bandwidth calibration while reducing circuit power consumption.

[0009] Optionally, when the count value matches the target value, the difference calculator provides a difference signal with a first error sign bit; when the count value does not match the target value and the count value is greater than the target value, the difference calculator provides a difference signal with a second error sign bit at a first level; when the count value does not match the target value and the count value is less than the target value, the difference calculator provides a difference signal with a second error sign bit at a second level. In this technical solution, the difference signal has two error sign bits and two level states to facilitate binary search.

[0010] Optionally, the adjustment module further includes a register for storing the target value.

[0011] In a second aspect, a filtering device is provided, comprising a filter and a calibration circuit as described above, the calibration circuit being connected to the filter, wherein the filter is used to filter an input signal to obtain an output signal; and the calibration circuit is used to provide a control signal to adjust the output signal to have a target frequency.

[0012] Optionally, the filter first provides the output signal with an initial frequency based on the control signal with an initial value during the startup phase, and then performs filtering based on the control signal with a calibration value during the operation phase after the startup phase.

[0013] Optionally, the filter includes multiple filtering elements, and the control signal is used to control the conduction state of the multiple filtering elements, thereby adjusting the frequency of the output signal, wherein the multiple filtering elements are a capacitor array and / or a resistor array.

[0014] The beneficial effects of the second aspect and each optional implementation method can be found in the description of the first aspect, and will not be repeated here.

[0015] Thirdly, a method for calibrating a filter is provided, the filter filtering under the configuration of a control signal to provide an output signal, the calibration method comprising: receiving the output signal from the filter; obtaining a count value based on the output signal, the count value representing the frequency of the output signal; and adjusting the control signal according to the count value and a target value representing a target frequency to adjust the frequency of the output signal provided by the filter, until a calibration value of the control signal that makes the count value consistent with the target value is determined; wherein the filter filters based on the control signal having the calibration value during an operational phase.

[0016] Optionally, the filter first provides the output signal with an initial frequency based on a control signal with an initial value during the startup phase prior to the operating phase.

[0017] Optionally, it further includes: storing a plurality of control signals with different initial values, and after obtaining the target value, selecting one of the plurality of control signals that minimizes the difference between the initial frequency and the target frequency of the output signal and providing it to the filter.

[0018] Optionally, obtaining a count value based on the output signal includes: amplifying the output signal; comparing the amplitude of the amplified output signal with a reference value to generate a square wave signal; and counting the rising edges of the square wave signal to obtain the count value.

[0019] Optionally, adjusting the control signal based on the comparison result between the count value and a target value representing the target frequency includes: calculating the difference between the count value and the target value to provide a difference signal; adjusting the control signal based on the difference signal, the control signal being used to control the conduction state of each filter element in the filter; and storing and sending a control signal to the filter such that the difference is relatively small, wherein, when the count value is consistent with the target value, a difference signal with a first error sign bit is provided; when the count value is inconsistent with the target value and the count value is greater than the target value, a difference signal with a second error sign bit at a first level is provided; and when the count value is inconsistent with the target value and the count value is less than the target value, a difference signal with a second error sign bit at a second level is provided.

[0020] The beneficial effects of the third aspect and each optional implementation method can be found in the description of the first aspect, and will not be repeated here.

[0021] The calibration circuit, calibration method, and filtering device provided in this application count the output signal of the filter and gradually adjust the control signal to the calibration value according to the difference between the count value and the target value. The control signal is used to control the filter, thereby gradually adjusting the output signal of the filter to have the target frequency. This technical solution realizes the filter's own feedback regulation, has high bandwidth calibration accuracy, simple circuit structure, and has advantages such as high integration, accurate bandwidth, and low power consumption.

[0022] Furthermore, the technical solution of this application also provides an initial value for the control signal, so that the filter can first provide an output signal with an initial frequency based on the control signal with the initial value during the startup stage before the working stage. There is no need to set up other circuit structures to provide an output signal with an initial frequency, which saves cost and power consumption, reduces the circuit area occupied, and is conducive to further improving the circuit integration.

[0023] Furthermore, in the technical solution of this application, multiple control signals with different initial values ​​are stored. After obtaining the target value, the adjustment module selects the control signal from the multiple control signals that minimizes the difference between the initial frequency and the target frequency of the output signal and provides it to the filter. Therefore, the initial value of the control signal can be selected according to the target frequency, which can save the time required for bandwidth calibration and reduce circuit power consumption.

[0024] In addition, this application also provides a computer-readable storage medium storing a program for bandwidth calibration of a filter, wherein when the program for bandwidth calibration of the filter is executed by at least one processor, the calibration method of the filter as described above is implemented. Attached Figure Description

[0025] Figure 1 A circuit diagram of a conventional filtering device provided in an embodiment of this application is shown;

[0026] Figure 2 A block diagram of a filtering device according to an embodiment of this application is shown;

[0027] Figure 3 A circuit diagram of a filtering device according to an embodiment of this application is shown;

[0028] Figure 4 A circuit diagram of a filter according to an embodiment of this application is shown;

[0029] Figure 5 A circuit diagram of the filter element array in the filter of an embodiment of this application is shown;

[0030] Figure 6 A flowchart illustrating a filter calibration method according to an embodiment of this application is shown. Detailed Implementation

[0031] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown in the drawings.

[0032] Many specific details of this application, such as the structure, materials, dimensions, processing techniques, and methods of the devices, are described below to provide a clearer understanding of the application. However, as those skilled in the art will understand, this application may be implemented without adhering to these specific details.

[0033] It should be understood that the connection / coupling of A and B in the embodiments of this application means that A and B can be connected in series or in parallel, or A and B can be connected through other devices. The embodiments of this application do not limit this.

[0034] The calibration circuit, calibration method, and filtering device of the filter provided in this application can be applied to receivers in various communication systems, such as radar equipment, communication equipment, navigation equipment, satellite ground stations, and electronic countermeasures equipment. These communication systems may include, for example, Long Term Evolution (LTE) systems, LTE Frequency Division Duplex (FDD) systems, LTE Time Division Duplex (TDD) systems, Universal Mobile Telecommunication System (UMTS), Worldwide Interoperability for Microwave Access (WiMAX) systems, Wireless Local Area Networks (WLANs), Bluetooth systems, and 5G (5th Generation Mobile Communication Technology) systems. 5G communication systems may include, for example, New Radio (NR) systems. It is understood that the calibration circuit, calibration method, and filtering device of the filter provided in this application can also be applied to various future communication systems, and this application does not limit their application.

[0035] The primary function of a filter is to effectively filter out frequencies other than the target frequency from the input signal, resulting in an output signal at the target frequency. With the development of wireless communication systems such as 5G, more and more electronic devices support higher frequencies and wider frequency ranges, thus placing higher demands on the operating bandwidth of filters. Furthermore, the market is increasingly demanding that single chips support multiple standards; different standards have different requirements for filter bandwidth, and even when the same standard is used in different application scenarios, a wide range of adjustable filter bandwidth is required.

[0036] The operating bandwidth (or operating frequency range) of a filter is one of its important parameters, and it usually refers to the upper limit of the operating frequency f. H and lower limit f L The difference between them, that is: B = f H -f L The relative bandwidth B of the filter device f =(f H -f L ) / f0 can also be used to characterize the operating bandwidth, where f0 refers to the center frequency of the operating bandwidth.

[0037] In modern semiconductor manufacturing processes, parameters such as the resistivity of resistors and the capacitance of capacitors can vary significantly with the process, affecting the positions of the zeros and poles of operational amplifiers, and consequently the bandwidth of filters. The bandwidth of filters often deviates from the preset value to varying degrees. Reduced bandwidth accuracy naturally leads to an increase in bit error rate or a decrease in signal-to-noise ratio. Therefore, calibration circuits are an indispensable part of modern filtering devices.

[0038] Figure 1 A circuit diagram of a conventional filtering device is shown. Figure 1 As shown, the filtering device includes a filter circuit 10 and a bandwidth calibration circuit 20, which performs bandwidth calibration based on the principle of resistor calibration. The filter circuit 10 includes a resistor array 11, a resistor array 12, a capacitor array 13, and an operational amplifier 14. The resistor array 11 is used to calibrate the filter bandwidth accuracy, the resistor array 12 is used to change the filter gain, and the capacitor array 13 is used to adjust the filter bandwidth. The bandwidth calibration circuit 20 includes a switched capacitor circuit, a voltage divider circuit, a comparator 23, and a binary search algorithm module 24. The switched capacitor circuit includes a fixed capacitor 21, a first current source 27, and clock-controlled switches 28 and 29. The voltage divider circuit consists of a resistor array 22 and a second current source 26. The outputs of the switched capacitor circuit and the voltage divider circuit are compared by the comparator 23. Under the control of the clock signal, the binary search algorithm module 24 processes the results to output a stable frequency control code, enabling the filter 10 to achieve the corresponding bandwidth accuracy.

[0039] For bandwidth calibration based on the principle of capacitance calibration, and Figure 1 The examples listed are similar, except that the resistor array 11 used to calibrate the filter bandwidth accuracy is replaced with a capacitor array, and it can be placed in other suitable locations in the circuit. Then, the capacitor array is controlled by the stable frequency control code provided by the bandwidth calibration circuit 20, so that the filter 10 achieves the corresponding bandwidth accuracy. The capacitor calibration will not be described in detail here.

[0040] However, the two bandwidth calibration circuits mentioned above result in only one of the capacitors and resistors being able to be used to adjust the filter's bandwidth during the filter design process, while the other is used to calibrate the bandwidth deviation. This type of bandwidth calibration circuit directly leads to a waste of the degree of freedom in bandwidth adjustment.

[0041] Figure 1 In a corresponding embodiment, bandwidth calibration is achieved by compensating for deviations in filter bandwidth caused by process variations and temperature changes. However, this bandwidth calibration scheme is not precise enough. Another bandwidth calibration scheme can achieve filter bandwidth calibration by designing complex circuits. This scheme improves the filter calibration circuitry, resulting in a more complex circuit structure.

[0042] Based on this, embodiments of this application provide a filtering device, and embodiments of the filtering device provided in this application will be described below with reference to the accompanying drawings.

[0043] Figure 2 A block diagram of a filtering device according to an embodiment of this application is shown. It should be understood that the filtering device in the embodiments of this application can be applied to architectures such as digital filters, analog filters, low-pass filters, high-pass filters, band-pass filters, surface acoustic wave filters, dielectric filters, and active power filters, or to other types of filter architectures. The embodiments of this application do not limit this application.

[0044] like Figure 2 As shown, the filtering device in this embodiment includes a filter 100 and a calibration circuit 200. The calibration circuit 200 includes a signal receiving terminal 210, a frequency detection module 220, and an adjustment module 230. In this embodiment, the bandwidth of the filter 100 is adjustable. Specifically, the filter 100 can filter the input signal Vi to provide an output signal Vo under the configuration of the control signal provided by the calibration circuit 200.

[0045] The signal receiver 210 is connected to the filter 100 and is used to receive the output signal Vo from the filter 100. In actual operation, the signal receiver 210 can be a metal wire connected to the output of the filter 100, or it can be a pin, pad, special connector, buffer, or other structure set in the calibration circuit 200, as long as it can achieve the function of signal transmission. It should be understood that this application does not limit the specific implementation of the signal receiver 210.

[0046] The frequency detection module 220 is connected to the signal receiver 210 and is used to obtain a count value N_cal based on the output signal Vo, where the count value N_cal represents the frequency of the output signal Vo. In this embodiment, the frequency detection module 220 can be implemented in various ways to obtain the count value N_cal representing the frequency of the output signal Vo. For example, the frequency detection module 220 uses an amplitude comparator to compare the amplitude of the output signal Vo with the amplitude of a reference voltage to convert the output signal Vo into a square wave signal. Then, a counter is used to count the rising or falling edge of the square wave signal to obtain the count value N_cal. Alternatively, a frequency detector can be directly set in the frequency detection module 220 to detect the frequency of the output signal Vo to obtain the count value N_cal. The frequency detector may include components such as an oscillator, frequency divider, gate circuit, gate circuit, trigger, and counter. This application does not limit the specific implementation of the frequency detector.

[0047] The adjustment module 230 is connected to the frequency detection module 220 and is used to provide a control signal Vc. It adjusts the control signal Vc based on the count value N_cal and the target value N_target, which represents the target frequency, to adjust the frequency of the output signal Vo provided by the filter 100 until a calibration value for the control signal Vc that makes the count value N_cal consistent with the target value N_target is determined. After acquiring and storing the calibration value of the control signal Vc, the adjustment module 230 continuously provides a control signal with the calibration value to the filter 100 during its operation phase. This allows the filter 100 to perform filtering based on the control signal Vc with the calibration value during its operation phase to obtain an output signal Vo with the target frequency.

[0048] In this embodiment, the control signal provided by the adjustment module 230 is, for example, one or more signal groups, including multiple digital control bits, used to control the conduction state of each filter element in the filter 100 to adjust the bandwidth of the filter 100. The filter elements are, for example, capacitor arrays and / or resistor arrays, and the conduction state of each filter element is controlled, for example, by controlling a switch connected in series with each filter element. Optionally, the control signal provided by the adjustment module 230 can be a numerical control signal or an analog control signal, and the switches in the filter 100 can be digitally controlled switches or analog switches. The module switches are, for example, bipolar transistors, field-effect transistors, or other types of transistors.

[0049] During operation, in the startup phase of the filter, the calibration circuit 200 first provides a control signal Vc with an initial value. The filter 100 then provides an output signal Vo with an initial frequency based on the control signal Vc. The calibration circuit 200 then gradually adjusts the frequency of the output signal Vo by adjusting the control signal Vc until the filter 100 can provide an output signal Vo with the target frequency. At this point, the calibration circuit 200 has calibrated the control signal Vc to a calibrated value and stores this calibrated control signal Vc. During the working phase of the filter, the calibration circuit 200 continuously provides a control signal Vc with a calibrated value, and the filter 100 filters the input signal based on the calibrated control signal Vc to provide an output signal Vo with the target frequency. This embodiment of the application achieves simple and precise feedback adjustment of the bandwidth of the filter 100 by configuring different stages of the control signal.

[0050] In some optional embodiments, the adjustment module 230 stores multiple control signals Vc with different initial values. During the startup phase of the filtering device, after acquiring the target value N_target, the adjustment module 230 selects the control signal Vc that minimizes the difference between the initial frequency and the target frequency of the output signal Vo and provides it to the filter 100. In this embodiment, the initial value of the control signal Vc can be selected according to the target frequency. For example, the adjustment module 230 stores the initial values ​​of control signals that make the frequency of the output signal Vo of the filter 100 10kHz, 20kHz, 30kHz, 40kHz, and 50kHz respectively. If the target frequency is set to 18kHz, then a control signal with a frequency of 20kHz is selected and provided to the filter. Then, the calibration circuit 200 is used to perform feedback adjustment on the filter 100, gradually adjusting the frequency of the output signal Vo of the filter 100 to 18kHz. The calibration circuit 200 in this embodiment can save the time and power consumption required for bandwidth calibration of the filter 100, which is beneficial for fast and accurate bandwidth calibration.

[0051] The calibration circuit and filtering device in this application embodiment achieve feedback adjustment of the filter, resulting in high bandwidth calibration accuracy, simple circuit structure, and advantages such as high integration, accurate bandwidth, and low power consumption. The following will combine... Figures 3 to 6 A detailed description of an exemplary filtering device provided in this application is given below.

[0052] Figure 3 A circuit diagram of a filtering device according to an embodiment of this application is shown. Figure 3 As shown, the filtering device in this embodiment includes a filter 100 and a calibration circuit 200, wherein the calibration circuit 200 includes a signal receiver 210, a frequency detection module 220, and an adjustment module 230. The basic functions and connections of each module in this embodiment are similar to those shown in the diagram. Figure 1 They are the same, and I will not go into the similarities here.

[0053] In this embodiment, the signal receiving end 210 is a metal wire connected to the output end of the filter 100, the frequency detection module 220 includes a level shifter 221, a comparator 222 and a counter 223, and the adjustment module 230 includes a difference calculator 231, a binary search calculation unit 232 and a storage unit 233.

[0054] Level shifter 221 is connected to signal input 210 and is used to amplify the output signal Vc. In alternative embodiments, an amplifier circuit such as a power amplifier can be used instead of level shifter 221. In other alternative embodiments, when the output signal Vc has a sufficiently large amplitude, the output signal Vc itself is within the operating range of comparator 222, and the configuration of level shifter 221 can be omitted. For example, if the peak voltage of the output signal Vc is 6 volts (Volt, V) and the operating range of the comparator is 1-10V, then the output signal Vc can be directly input to comparator 222 without amplification.

[0055] Comparator 222 is connected to level shifter 221 and is used to compare the amplitude of the amplified output signal with a reference value to generate a square wave signal. For example, comparator 222 is a voltage comparator, whose non-inverting input receives the amplified output signal and whose inverting input receives a reference voltage. When the amplitude of the amplified output signal is greater than or equal to the amplitude of the reference voltage, comparator 222 outputs a high-level voltage; when the amplitude of the amplified output signal is less than the amplitude of the reference voltage, comparator 222 outputs a low-level voltage. Thus, comparator 222 converts the amplified output signal into a square wave signal, which can characterize the frequency of the output signal Vc generated by the filter.

[0056] Counter 223 is connected to comparator 222 and is used to count the rising edge of the square wave signal to obtain the count value N_cal. Counter 223 is, for example, an RS flip-flop, a T flip-flop, a D flip-flop, a JK flip-flop, or other types of flip-flops, or it can be a combinational circuit formed by the aforementioned flip-flops.

[0057] In some embodiments not shown, since counter 223 calculates the frequency within a certain time range, for example, if it counts 100 times within 1 second (s), the system would determine that the frequency of the output signal is 100Hz. However, in reality, the frequency of the output signal may not be uniformly distributed within 1 second. For example, the frequency of the output signal may gradually change from 50Hz to 200Hz, so the count value within 1 second may also be 100. In this case, the count value provided by counter 223 cannot accurately represent the frequency of the output signal Vc. In an optional embodiment, a logic circuit with a buffer function is added after counter 223 to store and calculate the count values ​​of multiple consecutive segments. When several consecutive count values ​​are basically consistent, the average count value is provided to the back-end circuit, which can increase the accuracy of frequency detection. In addition, counter 223 can select irregular time periods for counting, such as 1s, 1.5s, and 2s for counting, and then calculate the average of the count values ​​per unit time, to avoid the influence of regular changes in the output signal on the frequency detection result.

[0058] Specifically, as an example, the back end of counter 223 is also connected to a first logic circuit, which includes a buffer and a calculation unit. The buffer stores the count values ​​N_cal1-N_caln obtained by counter 223 in multiple consecutive time periods. The calculation unit determines whether the count values ​​N_cal1-N_caln are basically consistent. When the difference between the count values ​​N_cal1-N_caln is within the allowable error range, the calculation unit calculates the average value of the count values ​​N_cal1-N_caln and provides it to the difference calculator 231. For example, if counter 223 provides a count value every 1 second, then the buffer stores three count values ​​within 3 seconds. When the difference between the three count values ​​does not exceed 5%, the calculation unit calculates the average value of the count values ​​and provides it to the difference calculator 231. In this embodiment, the first logic circuit provides a count value to the subsequent circuit only when the frequency of the output signal is basically consistent over multiple consecutive time periods. This improves the accuracy of frequency detection and avoids the problem that the count value cannot accurately represent the frequency of the output signal due to the change in the frequency of the output signal within the counting time range of the counter.

[0059] As another example, counter 223 counts the square wave signal at multiple time intervals of varying durations. A second logic circuit is connected to the back end of counter 223, including a buffer and a calculation unit. The buffer stores the count values ​​N_cal1-N_caln obtained by counter 223 during the multiple time intervals. The calculation unit calculates the count value per unit time within each time interval based on the duration of each time interval and its corresponding count value. When the difference between the count values ​​per unit time is within the allowable error range, the calculation unit calculates the average of the count values ​​per unit time and provides it to the difference calculator 231. For example, if counter 223 provides count values ​​at intervals of 1 second, 1.5 seconds, and 2 seconds, the buffer stores three count values ​​within 4.5 seconds. The calculation unit divides each of the three count values ​​by its corresponding time. When the difference between the count values ​​per unit time does not exceed 5%, the calculation unit calculates the average of the count values ​​per unit time and provides it to the difference calculator 231. In the technical solution of this embodiment, the first logic circuit will only provide a count value to the subsequent circuit when the count value of the frequency of the output signal is basically consistent within a unit time of multiple time periods with different durations. This can improve the accuracy of further frequency detection and avoid the problem that the count value cannot accurately represent the frequency of the output signal due to the regular change of the frequency of the output signal within the counting time range of the counter.

[0060] The difference calculator 231 is connected to the counter 223 and is used to calculate the difference between the count value N_cal and the target value N_target. Specifically, when the count value matches the target value, the difference calculator 231 provides a difference signal with a first error sign bit, which indicates that the frequency of the output signal has reached the target frequency. At this time, the control signal stored in the storage unit 233 has also reached the calibration value. When the count value does not match the target value and the count value is greater than the target value, the difference calculator 231 provides a difference signal with a second error sign bit at a first level. At this time, the interpolation signal needs to be sent to the binary search unit 232 so that the binary search unit 232 can search upward for the control signal of the standard value. When the count value does not match the target value and the count value is less than the target value, the difference calculator 231 provides a difference signal with a second error sign bit at a second level. At this time, the interpolation signal also needs to be sent to the binary search unit 232 so that the binary search unit 232 can search downward for the control signal of the standard value.

[0061] The binary search calculation unit 232 is connected to the difference calculator 231 and is used to adjust the control signal according to the difference. Specifically, it adjusts the control signal based on the difference signal provided by the difference calculator 231. For example, the first error sign bit of the difference signal is Equivalent, indicating that the calibration has reached the target value, and the second error sign bit is Sign, indicating that the calibration target has not been reached. The binary search calculation unit 232 continues the calibration process according to the Sign indicator bit. When Sign is 1, the digital control bit of the control signal searches upward (the adjusted control signal will increase the capacitance or resistance value in the filter 100), and when Sign is 0, it searches downward (the adjusted control signal will decrease the capacitance or resistance value in the filter 100). The adjusted capacitor array and / or resistor array will affect the frequency of the output signal of the filter 100, thereby affecting the counting of the counter 223. The digital control bit of the control signal adjusted each time is stored in the storage unit 233 and compared with the digital control bit of the control signal adjusted next time. The digital control bit of the control signal that results in a relatively small difference between the count value and the target value is stored, and calibration continues. When Equivalent is high, it indicates that the calibration has reached the target value. At this time, the value of the digital control bit of the control signal is saved and used as the calibration value of the control signal and sent to filter 100, thus ending the calibration process in the startup phase.

[0062] The storage unit 233 is connected to the difference calculator 231 and the binary search calculation unit 232. It is used to store the digital control bits of the control signals in each stage. Specifically, it stores the initial value of the control signal, the control signal that makes the difference relatively small, and the calibration value of the control signal. After obtaining the control signal that makes the difference relatively large, the digital control bits of the control signal that makes the difference relatively large can be deleted to save memory.

[0063] Optionally, the filtering device also includes a register 240 for storing the target value N_target. In an alternative embodiment, register 240 can be omitted, and the target value N_target can be directly input to the difference calculator 231.

[0064] The calibration circuit and filtering device in this application embodiment realize feedback adjustment of the filter, with high bandwidth calibration accuracy, simple circuit structure, and advantages such as high integration, accurate bandwidth, and low power consumption.

[0065] Figure 4 A circuit diagram of a filter according to an embodiment of this application is shown; Figure 5 A circuit diagram of a filter element array in a filter according to an embodiment of this application is shown. It should be understood that... Figure 4The filter structure shown is only an example. The filter used in this application can be any structure, as long as it contains at least one capacitor array, resistor array or inductor array, so that the bandwidth of the filter 100 is adjustable.

[0066] like Figure 4 As shown, the filter 100 includes a first resistor module 110, a second resistor module 120, a first capacitor module 130, a second capacitor module 140, and an operational amplifier 150. The first terminal of the first resistor module 110 receives the input signal Vi, and its second terminal is connected to the first terminal of the second resistor module 120. The second terminal of the second resistor module 120 is connected to the non-inverting input terminal of the operational amplifier 150, and the second terminal of the second resistor module 120 is also connected to a reference ground potential via the first capacitor module 130. The inverting input terminal of the operational amplifier 150 is connected to its output terminal, and the output terminal of the operational amplifier 150 is also connected to the first terminal of the second resistor module 120 via the second capacitor module 140. The output terminal of the operational amplifier 150 serves as the output terminal of the filter 100, providing the output signal Vo.

[0067] In this embodiment, at least one of the first resistor module 110, the second resistor module 120, the first capacitor module 130, and the second capacitor module 140 is a filter element array. The filter element array includes multiple filter elements connected in parallel. Each filter element is connected in series with a switch. By adjusting the conduction state of any filter element in the filter element array, the frequency of the output signal Vo can be adjusted.

[0068] As an example, such as Figure 5 As shown, the second capacitor module 140 is a filter element array, comprising seven capacitors C1-C7 connected in parallel. Each capacitor C1-C7 is connected in series with its corresponding switch S1-S7. Each switch S1-S7 is controlled by a control signal. In this example, the control signal includes at least seven digital control bits to control each switch S1-S7 individually. Alternatively, the control signal may include eight digital control bits, with one bit being invalid. Optionally, the capacitance values ​​of each capacitor increase exponentially; for example, capacitor C1 has a capacitance of 1 microfarad (μF), capacitor C2 has a capacitance of 2 μF, capacitor C3 has a capacitance of 4 μF, capacitor C4 has a capacitance of 8 μF, capacitor C5 has a capacitance of 16 μF, capacitor C6 has a capacitance of 32 μF, and capacitor C7 has a capacitance of 64 μF.

[0069] The foregoing has described some examples of filtering devices according to embodiments of this application. However, the embodiments of this application are not limited thereto, and there may be other extensions and modifications.

[0070] For example, it should be understood that the reference ground potential in the foregoing embodiments may be replaced in alternative embodiments with other non-zero reference potentials (with positive or negative voltage amplitudes) or a controlled-change reference signal.

[0071] For example, the inductors and capacitors provided in the embodiments of this application can be lumped-parameter capacitor elements and inductor elements, or other equivalent elements with similar functions to capacitors and inductors. The equivalent structures described herein are, for example, but not limited to, microstrip lines, varactors, conductor structures with certain patterns, etc., which can provide inductive impedance and / or capacitive impedance.

[0072] For example, the aforementioned filtering device can be a discrete component, a single circuit unit, or combined into a high-efficiency, high-linearity broadband power amplifier module. In other implementations, the aforementioned filter 100 can be packaged within a device, while the calibration circuit 200 can serve as a load line structure surrounding that device.

[0073] Furthermore, those skilled in the art will recognize that the structures and methods described in conjunction with the embodiments disclosed herein can be used with different configuration or adjustment methods to achieve the described functions for each structure or reasonable variations thereof, but such implementations should not be considered beyond the scope of this application. Moreover, it should be understood that the connection relationships between the various components of the amplifier in the foregoing figures in the embodiments of this application are illustrative examples and do not impose any limitations on the embodiments of this application.

[0074] Figure 6 A flowchart of a filter calibration method according to an embodiment of this application is shown.

[0075] like Figure 6 As shown, the calibration method for this filter includes steps S1-S3.

[0076] In step S1, the output signal from the filter is received. During the startup phase before the operating phase, the filter first provides an output signal with an initial frequency based on a control signal with an initial value. Multiple control signals with different initial values ​​are stored. After obtaining the target value, the control signal that minimizes the difference between the initial frequency and the target frequency of the output signal is selected and provided to the filter.

[0077] In step S2, a count value is obtained based on the output signal, and the count value represents the frequency of the output signal. In this step, the output signal is amplified; the amplitude of the amplified output signal is compared with a reference value to generate a square wave signal; and the rising edges of the square wave signal are counted to obtain the count value.

[0078] In step S3, the control signal is adjusted according to the count value and the target value representing the target frequency to adjust the frequency of the output signal provided by the filter until a calibration value of the control signal that makes the count value consistent with the target value is determined. The filter performs filtering based on the control signal with the calibration value during the working phase.

[0079] In this step, for example, the difference between the count value and the target value is calculated to provide a difference signal; a control signal is adjusted based on the difference signal, the control signal being used to control the conduction state of each filter element in the filter; and a control signal is stored and sent to the filter to make the difference relatively small. Specifically, when the count value matches the target value, a difference signal with a first error sign bit is provided; when the count value does not match the target value and the count value is greater than the target value, a difference signal with a second error sign bit at a first level is provided; when the count value does not match the target value and the count value is less than the target value, a difference signal with a second error sign bit at a second level is provided.

[0080] Specifically, the first error sign bit of the difference signal is Equivalent, indicating that the calibration has reached the target value. The second error sign bit is Sign, indicating that the calibration target has not been reached. The calibration process continues according to the Sign indicator bit. When Sign is 1, the digital control bit of the control signal searches upwards (the adjusted control signal will increase the capacitance or resistance value in the filter). When Sign is 0, it searches downwards (the adjusted control signal will decrease the capacitance or resistance value in the filter). The adjusted capacitor array and / or resistor array will affect the frequency of the filter's output signal, thus affecting the counter's count. The digital control bit of the control signal adjusted each time is stored in the storage unit and compared with the digital control bit of the control signal adjusted next time. The digital control bit of the control signal that results in a relatively small difference between the count value and the target value is saved, and calibration continues. When Equivalent is high, it indicates that the calibration has reached the target value. At this time, the value of the digital control bit of the control signal is saved and used as the calibration value of the control signal and sent to the filter, ending the calibration process in the startup phase.

[0081] In summary, this application provides a filter calibration circuit, a calibration method, and a filtering device and electronic device including the calibration circuit. The calibration circuit provided in this application counts the output signal of the filter and gradually adjusts the control signal to the calibration value based on the difference between the count value and the target value. The control signal is used to control the filter, thereby gradually adjusting the filter's output signal to have the target frequency. This technical solution achieves self-feedback adjustment of the filter, has high bandwidth calibration accuracy, a simple circuit structure, and advantages such as high integration, accurate bandwidth, and low power consumption.

[0082] Furthermore, this application also provides a computer-readable storage medium (not shown) storing a program for bandwidth calibration of a filter. When executed by at least one processor, the program for bandwidth calibration of the filter implements the steps of a calibration method for the filter, wherein the calibration method for the filter is as follows: Figure 6 As shown, it will not be elaborated further here.

[0083] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0084] As described above, these embodiments of this application do not exhaustively cover all details, nor do they limit the application to merely the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A calibration circuit for a filter, characterized in that, The filter performs filtering under the configuration of the control signal to provide an output signal, and the calibration circuit includes: A signal receiving end, connected to the filter, is used to receive the output signal from the filter; A frequency detection module, connected to the signal receiver, is used to obtain a count value based on the output signal, the count value representing the frequency of the output signal; and An adjustment module, connected to the frequency detection module, is used to adjust the control signal according to the count value and the target value representing the target frequency, so as to adjust the frequency of the output signal provided by the filter until a calibration value of the control signal that makes the count value consistent with the target value is determined; The filter performs filtering based on the control signal having the calibration value during the operation phase. The frequency detection module counts based on the output signal in multiple time periods of varying durations. The frequency detection module also includes a buffer and a calculation unit. The buffer stores multiple count values ​​obtained within the multiple time periods. The calculation unit obtains the count value per unit time within each time period based on its duration and corresponding count value, and determines whether the difference between the count values ​​per unit time is within a preset error range. When the difference is within the preset error range, the calculation unit calculates the average value of the count values ​​per unit time and outputs it as the count value to the adjustment module.

2. The calibration circuit according to claim 1, characterized in that, The adjustment module is also used to provide an initial value for the control signal so that the filter first provides the output signal with an initial frequency based on the control signal having the initial value during the startup phase before the working phase.

3. The calibration circuit according to claim 2, characterized in that, The adjustment module stores multiple control signals with different initial values. After obtaining the target value, the adjustment module selects the control signal from the multiple control signals that minimizes the difference between the initial frequency and the target frequency of the output signal and provides it to the filter.

4. The calibration circuit according to any one of claims 1-3, characterized in that, The frequency detection module includes: A level shifter, connected to the signal receiving terminal, is used to amplify the output signal; A comparator, connected to the level shifter, is used to compare the amplitude of the amplified output signal with a reference value to generate a square wave signal; and A counter, connected to the comparator, is used to count the rising edges of the square wave signal to obtain the count value.

5. The calibration circuit according to any one of claims 1-3, characterized in that, The adjustment module includes: A difference calculator calculates the difference between the count value and the target value; The binary search calculation unit adjusts the control signal according to the difference, the control signal being used to control the conduction state of each filter element in the filter; and The storage unit stores the initial value of the control signal, the control signal that makes the difference relatively small, and the calibration value of the control signal.

6. The calibration circuit according to claim 5, characterized in that, When the count value matches the target value, the difference calculator provides a difference signal with a first error sign bit; When the count value is inconsistent with the target value and the count value is greater than the target value, the difference calculator provides a difference signal of the second error sign bit at the first level; When the count value is inconsistent with the target value and the count value is less than the target value, the difference calculator provides a difference signal of the second error sign bit at the second level.

7. The calibration circuit according to claim 5, characterized in that, The adjustment module further includes a register for storing the target value.

8. A filtering device, characterized in that, Includes a filter and a calibration circuit as described in any one of claims 1-6, wherein the calibration circuit is connected to the filter. The filter is used to filter the input signal to obtain an output signal; the calibration circuit is used to provide a control signal to adjust the output signal to a target frequency.

9. The filtering device according to claim 8, characterized in that, The filter first provides an output signal with an initial frequency based on the control signal with an initial value during the startup phase, and then performs filtering based on the control signal with a calibration value during the operation phase after the startup phase.

10. The filtering device according to claim 8 or 9, characterized in that, The filter includes multiple filtering elements, and the control signal is used to control the conduction state of the multiple filtering elements, thereby adjusting the frequency of the output signal. The plurality of filter elements are capacitor arrays and / or resistor arrays.

11. A method for calibrating a filter, characterized in that, The filter performs filtering under the configuration of a control signal to provide an output signal, and the calibration method includes: Receive the output signal from the filter; A count value is obtained based on the output signal, the count value representing the frequency of the output signal. Counting is performed on the output signal in multiple time periods of varying durations, and multiple count values ​​obtained within these time periods are stored. The count value per unit time within each time period is obtained based on the duration of each time period and its corresponding count value. It is then determined whether the difference between the count values ​​per unit time is within a preset error range. When the difference is within the preset error range, the average value of the count values ​​per unit time is calculated and output as the count value. The control signal is adjusted based on the count value and the target value representing the target frequency to adjust the frequency of the output signal provided by the filter until a calibration value of the control signal that makes the count value consistent with the target value is determined. The filter performs filtering based on the control signal having the calibration value during the working phase.

12. The calibration method according to claim 11, characterized in that, The filter first provides the output signal with an initial frequency based on a control signal with an initial value during the startup phase before the working phase.

13. The calibration method according to claim 12, characterized in that, Also includes: The control signals with different initial values ​​are stored. After the target value is obtained, the control signal that minimizes the difference between the initial frequency and the target frequency of the output signal is selected and provided to the filter.

14. The calibration method according to any one of claims 11-13, characterized in that, Obtaining the count value based on the output signal includes: The output signal is amplified. The amplitude of the amplified output signal is compared with a reference value to generate a square wave signal; and The rising edges of the square wave signal are counted to obtain the count value.

15. The calibration method according to any one of claims 11-13, characterized in that, Adjusting the control signal based on the comparison result between the count value and the target value representing the target frequency includes: Calculate the difference between the count value and the target value to provide a difference signal; The control signal is adjusted according to the difference signal, and the control signal is used to control the conduction state of each filter element in the filter; and Store and send a control signal to the filter to make the difference relatively small. Wherein, when the count value is consistent with the target value, a difference signal with a first error sign bit is provided; When the count value is inconsistent with the target value and the count value is greater than the target value, a difference signal of the second error sign bit at the first level is provided; When the count value is inconsistent with the target value and the count value is less than the target value, a difference signal of the second error sign bit at the second level is provided.

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