Image sensing device

Abstract

The present disclosure relates to an image sensing device. An image sensing device includes: a pixel array including a plurality of unit pixels connected to a plurality of row lines, wherein at least one of the unit pixels includes a photodiode for generating photocharges corresponding to incident light and a transfer transistor for transferring the photocharges to a floating diffusion FD node in response to a transfer control signal transmitted through the corresponding row line; a row control circuit disposed on a first side of the pixel array and adapted to provide a transfer control signal having a voltage level between a first voltage and a second voltage to each row line; and a bias compensation circuit disposed on a second side of the pixel array and adapted to drive the transfer control signal to a second voltage during a reset readout period of each of the row lines.

Description

Technical Field

[0001] The present disclosure relates to semiconductor design technology, and more particularly, to an image sensing device for eliminating horizontal banding noise. Background Art

[0002] An image sensor is a device that captures light from an optical image or one or more objects using a photosensitive semiconductor element and converts the captured colored light into an electrical signal. With the recent development of the automotive, medical, computer, and communication industries, the demand for high-performance image sensors is increasing in various devices such as smartphones, digital cameras, game consoles, the Internet of Things (IoT), robots, surveillance cameras, medical miniature cameras, etc.

[0003] One common type of image sensing device is the charge coupled device (CCD), which has dominated the field of image sensors for a long time. Another common type of image sensing device is the complementary metal oxide semiconductor (CMOS) image sensing device. In terms of noise characteristics and image quality, CCD image sensors are superior to CMOS image sensors. However, CMOS image sensors are now widely used due to their advantages over CCD image sensors, such as higher frame rates and shutter speeds. In addition, CMOS image sensors and signal processing circuits can be integrated into a single chip, making it possible to miniaturize electronic devices while achieving lower power consumption. In addition, the use of CMOS manufacturing technology can reduce production costs. These characteristics of CMOS image sensors make these sensors more suitable for implementation in mobile devices. Summary of the invention

[0004] Various embodiments are directed to an image sensing device capable of eliminating or minimizing horizontal stripe noise that may occur between pixels in the same row during a reset readout period.

[0005] According to one embodiment, an image sensing device includes: a pixel array, the pixel array including a plurality of unit pixels connected to a plurality of row lines, wherein at least one of the unit pixels includes a photodiode for generating photocharges corresponding to incident light, and a transfer transistor for transferring the photocharges to a floating diffusion (FD) node in response to a transfer control signal transmitted through the corresponding row line; a row control circuit, the row control circuit is arranged on a first side of the pixel array and is suitable for providing a transfer control signal having a voltage level between a first voltage and a second voltage to each row line; and a bias compensation circuit, the bias compensation circuit is arranged on a second side of the pixel array and is suitable for driving the transfer control signal to a second voltage during a reset readout period of each of the row lines.

[0006] According to one embodiment, an image sensing device includes: a pixel array, the pixel array including a plurality of unit pixels connected to a plurality of row lines, wherein each unit pixel includes a photodiode for generating photocharges corresponding to incident light and a transfer transistor for transferring the photocharges to a floating diffusion (FD) node in response to a transfer control signal transmitted through the corresponding row line; a first row control circuit, the first row control circuit being arranged on a first side of the pixel array and being adapted to provide a transfer control signal having a voltage level between a first voltage and a second voltage to odd-numbered row lines among the row lines; a second row control circuit, the second row control circuit being arranged on a second side of the pixel array and being adapted to provide a transfer control signal to even-numbered row lines among the row lines; a first bias compensation circuit, the first bias compensation circuit being arranged on the second side and being adapted to drive the transfer control signal to a second voltage during a reset readout period of the odd-numbered row lines; and a second bias compensation circuit, the second bias compensation circuit being arranged on the first side and being adapted to drive the transfer control signal to a second voltage during a reset readout period of the even-numbered row lines.

[0007] According to one embodiment, an image sensing device includes: a pixel array, the pixel array including a plurality of unit pixels connected to a plurality of row lines, wherein each unit pixel includes a photodiode for generating photocharges corresponding to incident light, a transfer transistor for transferring the photocharges to a floating diffusion (FD) node in response to a transfer control signal, and a gain transistor for connecting the FD node to a dynamic range capacitor in response to a gain control signal; a row control circuit, the row control circuit being disposed on a first side of the pixel array and being suitable for providing a gain control signal having a voltage level between a third voltage and a fourth voltage to each of the row lines; and a bias compensation circuit, the bias compensation circuit being disposed on a second side of the pixel array and being suitable for driving the gain control signal to a third voltage during a reset readout period of each of the row lines.

[0008] According to one embodiment, an image sensing device includes: a pixel array, the pixel array including a plurality of unit pixels connected to a plurality of row lines, wherein each unit pixel includes a photodiode for generating photocharges corresponding to incident light, a transfer transistor for transferring the photocharges to a floating diffusion (FD) node in response to a transfer control signal, and a gain transistor for connecting the FD node to a dynamic range capacitor in response to a gain control signal; a first row control circuit, the first row control circuit being arranged on a first side of the pixel array and being adapted to provide a gain control signal having a voltage level between a third voltage and a fourth voltage to odd-numbered row lines among the row lines; a second row control circuit, the second row control circuit being arranged on a second side of the pixel array and being adapted to provide a gain control signal to even-numbered row lines among the row lines; a first bias compensation circuit, the first bias compensation circuit being arranged on the second side and being adapted to drive the gain control signal to a third voltage during a reset readout period of the odd-numbered row lines; and a second bias compensation circuit, the second bias compensation circuit being arranged on the first side and being adapted to drive the gain control signal to the third voltage during a reset readout period of the even-numbered row lines.

[0009] According to one embodiment, an image sensing device includes unit pixels connected to row lines, each unit pixel including: a reset transistor configured to initialize a floating diffusion (FD) node in response to a reset signal; a transfer transistor configured to transfer photocharge to the FD node in response to a transfer control signal; and a row control circuit and a bias compensation circuit, which are arranged on opposite sides of the unit pixel in a row direction and connected to corresponding ends of the row line, wherein the row control circuit is configured to provide a reset signal and a transfer control signal having a voltage level between a first voltage and a second voltage through the row line, and wherein the bias compensation circuit is configured to drive the transfer control signal to the second voltage through the row line during a period from disabling the reset signal to enabling the transfer control signal.

[0010] The first voltage has a voltage level equal to or higher than the source voltage level, and the second voltage has a voltage level lower than the ground voltage level. Each of the unit pixels also includes a gain transistor configured to couple the FD node to the dynamic range capacitor in response to a gain control signal. The row control circuit is also configured to provide a gain control signal having a voltage level between a third voltage and a fourth voltage through a row line, and the bias compensation circuit is also configured to drive the gain control signal to the third voltage through the row line during the period. The third voltage has a voltage level higher than the source voltage level, and the fourth voltage has a voltage level equal to or lower than the ground voltage level.

[0011] According to one embodiment, an image sensing device includes unit pixels connected to row lines, each unit pixel including: a reset transistor configured to initialize a floating diffusion (FD) node in response to a reset signal; a transfer transistor configured to transfer photocharge to the FD node in response to a transfer control signal; a gain transistor configured to connect the FD node to a dynamic range capacitor in response to the gain control signal; and a row control circuit and a bias compensation circuit, which are arranged on opposite sides of the unit pixel in a row direction and connected to corresponding ends of the row line, wherein the row control circuit is configured to provide a gain control signal having a voltage level between a third voltage and a fourth voltage through the row line, and wherein the bias compensation circuit is configured to drive the gain control signal to the third voltage through the row line during a period from disabling the reset signal to enabling the transfer control signal.

[0012] The third voltage has a voltage level higher than the source voltage level, and the fourth voltage has a voltage level equal to or lower than the ground voltage level.

[0013] According to the above-mentioned embodiment, the image sensing device can be provided with a bias compensation circuit and a row control circuit arranged on opposite sides relative to the pixel array, and the bias compensation circuit is suitable for driving the row control signal to a low voltage or a high voltage during the reset readout period. Therefore, the horizontal stripe noise component between pixels in the same row can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a diagram showing the configuration of an image sensing device.

[0015] Figure 2 It is shown Figure 1 Circuit diagram of a unit pixel.

[0016] Figure 3 is the explanation Figure 1 Timing diagram of the operation of a unit pixel.

[0017] Figure 4 Yes Figure 1 Diagram of modeling unit pixels of an image sensing device connected to the same row line.

[0018] Figure 5A and Figure 5B is a diagram explaining why the transmission control signal is driven to a low voltage.

[0019] Figure 6 is the explanation Figure 4 Timing diagram of the operation of a unit pixel.

[0020] Figure 7is a configuration diagram showing an image sensing device according to a first embodiment of the present invention.

[0021] Figure 8 It is shown Figure 7 Circuit diagram of the row control circuit and bias compensation circuit.

[0022] Fig. 9 is the explanation Figure 8 Timing diagram of the operation of a unit pixel.

[0023] Fig. 10A and Fig. 10B is a graph comparing error rates in a column direction of unit pixels connected to the same row line in a conventional image sensing device and an image sensing device according to another embodiment of the present invention.

[0024] Fig.11 is a circuit diagram showing an offset compensation circuit according to another embodiment of the present invention.

[0025] Fig.12 is a configuration diagram showing an image sensing device according to a second embodiment of the present invention.

[0026] Fig.13 It is shown Fig.12 Circuit diagram of a first row control circuit and a second row control circuit and a first bias compensation circuit and a second bias compensation circuit.

[0027] Fig.14 is a circuit diagram showing a unit pixel supporting a dual conversion gain (DCG) operation.

[0028] Fig.15 is a circuit diagram showing a row control circuit and an offset compensation circuit included in an image sensing device according to a third embodiment of the present invention.

[0029] Fig.16 is a circuit diagram showing first and second row control circuits and first and second offset compensation circuits included in an image sensing device according to a fourth embodiment of the present invention. DETAILED DESCRIPTION

[0030] Various embodiments are described below with reference to the accompanying drawings. However, the embodiments may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Throughout the disclosure, in the various drawings and embodiments of the present invention, the same reference numerals represent the same components. It should be noted that references to "one embodiment" or "another embodiment" and the like do not necessarily refer to only one embodiment, and different references to any such phrases are not necessarily directed to the same embodiment. When used herein, the term "embodiment" does not necessarily refer to all embodiments.

[0031] It should be understood that although the terms "first", "second", "third", etc. may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element that would otherwise have the same or similar name. Therefore, a first element in one example may also be referred to as a second element or a third element in another example without indicating any changes in the elements themselves.

[0032] It should also be understood that when an element is referred to as being "connected to" or "coupled to" another element, the element may be directly located on, connected to, or coupled to the other element, or one or more intervening elements may be present. It should be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or one or more intervening elements may be present. Whether directly or indirectly connected / coupled, the communication between the two elements may be wired or wireless, unless otherwise specified or the context indicates otherwise.

[0033] As used herein, singular forms may also include plural forms and vice versa, unless the context clearly indicates otherwise.

[0034] It should also be understood that when used in this specification, the terms "include", "comprising", "having" and "containing" specify the presence of the elements described, and do not exclude the presence or addition of one or more other elements. When used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0035] Figure 1 is a diagram showing the configuration of the image sensing device 1 .

[0036] Reference Figure 1 The image sensing device 1 may include a pixel array 10 , a row control circuit 12 , a readout circuit 14 , a timing controller 15 , and a ramp voltage generating circuit 16 .

[0037] The pixel array 10 may include a plurality of unit pixels PX arranged in an array type in the row direction and the column direction. The unit pixel PX may be connected to the row control circuit 12 through a plurality of row lines RLn, and may be connected to the readout circuit 14 through a plurality of column lines CLm. Each unit pixel PX may include at least one of a red pixel for converting light from a red spectrum region into an electrical signal, a green pixel for converting light from a green spectrum region into an electrical signal, and a blue pixel for converting light from a blue spectrum region into an electrical signal, thereby converting a photocharge into an electrical signal. The pixel array 10 may be controlled by a row control signal RCS provided from the row control circuit 12 through the row line RLn. The pixel array 10 may generate a photocharge corresponding to the amount of incident light, accumulate the generated photocharge in a floating diffusion (FD) node, and provide an electrical signal corresponding to the photocharge as a pixel voltage VPIXEL through the column line CLm by converting a voltage level of the FD node into an electrical signal.

[0038] The row control circuit 12 may generate a row control signal RCS including a transmission control signal TX, a reset signal RX, and a selection signal SX according to a first timing control signal RCTRL provided from the timing controller 15, and may provide the row control signal RCS to the pixel array 10 through a row line RLn. The transmission control signal TX, the reset signal RX, and the selection signal SX may be provided to each row line RLn. The row control circuit 12 may generate a selection signal SX for selecting any one row line from the row lines RLn according to the first timing control signal RCTRL. According to the first timing control signal RCTRL, the row control circuit 12 may sequentially enable the reset signal RX and the transmission control signal TX at a preset timing, and output the reset signal RX and the transmission control signal TX to the unit pixel PX connected to the selected row line.

[0039] The timing controller 15 may generate a first timing control signal RCTRL and a second timing control signal CCTRL including a clock signal, thereby controlling the pixel array 10 , the row control circuit 12 , the readout circuit 14 , and the ramp voltage generating circuit 16 .

[0040] According to the control of the timing controller 15 , the slope voltage generating circuit 16 can generate a slope voltage VRAMP that decreases (or increases) over time.

[0041] The readout circuit 14 can convert the pixel voltage VPIXEL into a digital signal based on the ramp voltage VRAMP according to the second timing control signal CCTRL, and output the digital signal as the image data DOUT. The readout circuit 14 may include a sampler, an analog-to-digital converter and / or an output buffer. The sampler in the readout circuit 14 may sequentially sample and hold the pixel voltage VPIXEL transmitted from the pixel array 10 to each column line CLm. The analog-to-digital converter in the readout circuit 14 may convert the pixel voltage VPIXEL of the analog signal provided from the sampler into a digital signal based on the ramp voltage VRAMP. According to the second timing control signal CCTRL, the output buffer in the readout circuit 14 may output the image data DOUT in columns by latching the digital signal provided from the analog-to-digital converter. The output buffer may include a column decoder for outputting the image data DOUT in columns.

[0042] Figure 2 It is shown Figure 1 Circuit diagram of a unit pixel PX. Figure 3 is the explanation Figure 1 1 is a timing diagram of the operation of the unit pixel PX.

[0043] Reference Figure 2 , the unit pixel PX may include a photodiode PD, a transfer transistor M1, a reset transistor M2, a drive transistor M3, and a selection transistor M4. A floating diffusion (FD) node may be a common node of the transfer transistor M1 and the reset transistor M2.

[0044] The photodiode PD can perform a photoelectric conversion operation. That is, the photodiode PD can accumulate the amount of incident light to generate photocharges. In response to the transmission control signal TX applied to the gate of the transfer transistor M1, the transfer transistor M1 can transfer the photocharge of the photodiode PD electrically connected to one end thereof to the FD node electrically connected to the other end thereof. In response to the reset signal RX applied to the gate of the reset transistor M2, the reset transistor M2 can transfer the source voltage VDDPX applied from one terminal thereof to the FD node electrically connected to the other terminal thereof. That is, the reset transistor M2 can reset the photocharge stored in the FD node to the voltage level of the source voltage VDDPX in response to the reset signal RX. The drive transistor M3 can have a terminal electrically connected to the source voltage VDDPX terminal, generate an electrical signal corresponding to the charge stored in the FD node electrically connected to its gate terminal, and output the electrical signal to the other terminal. The drive transistor M3 can be used as a source follower buffer amplifier. The selection transistor M4 can operate in response to the selection signal SX and output the electrical signal provided from the drive transistor M3 as the pixel voltage VPIXEL. The selection transistor M4 may perform a switching operation for selecting the unit pixel PX and an address operation in response to a selection signal SX applied to a gate of the selection transistor M4 .

[0045] For reference, the FD node may be a diffusion region formed at a common node of the transfer transistor M1 and the reset transistor M2. The FD node may store charges corresponding to photocharges, or charges corresponding to an initialization voltage (ie, a source voltage VDDPX). Therefore, the FD node may be modeled as a capacitor C1.

[0046] Meanwhile, in the case of a CMOS image sensor, in order to eliminate or remove the inherent offset value of each pixel, the CMOS image sensor may compare a pixel signal (i.e., a reset signal) obtained before light is incident on the corresponding pixel with a pixel signal (i.e., an image signal) obtained after light is incident on the corresponding pixel. In this way, the CMOS image sensor can obtain a pixel signal for each pixel caused by the actual incident light without being affected by other factors (e.g., the offset value of each pixel). The above scheme will be referred to as a correlated double sampling (CDS) scheme hereinafter.

[0047] Reference Figure 3In the CDS scheme, the reset transistor M2 is turned on in response to the reset signal RX, and therefore, a charge corresponding to the voltage level of the source voltage VDDPX is charged into the FD node. As a result, the FD node is initialized. The selection transistor M4 is turned on in response to the selection signal SX, and therefore, the electrical signal provided from the FD node is output as the pixel voltage VPIXEL. The pixel voltage VPIXEL can be used as a reference signal. The time section (temporal section) from disabling the reset signal RX to enabling the transmission control signal TX (i.e., the time period for outputting the pixel voltage VPIXEL corresponding to the reference signal) can be defined as a "reset readout period". Since the transmission control signal TX, the reset signal RX and the selection signal SX can be provided for each row line RLn, the reset readout period can be equally applied to other row lines.

[0048] When the transmission control signal TX is activated after the reset readout period, the transfer transistor M1 is turned on. At this time, the selection transistor M4 is turned off in response to the selection signal SX. By turning off the selection transistor M4 when the transmission control signal TX is switched (toggle), the voltage level of the pixel voltage VPIXEL can be prevented from increasing and the settling time of the pixel voltage VPIXEL can be reduced. The transfer transistor M1 is turned on in response to the transmission control signal TX, so that the photocharge of the photodiode PD is transferred to the FD node. Thereafter, the selection transistor M4 is turned on in response to the selection signal SX, and therefore, the electrical signal provided from the FD node is output as the pixel voltage VPIXEL. The pixel voltage VPIXEL can be used as an image signal.

[0049] The readout circuit 14 may sample the pixel voltage VPIXEL twice according to the second timing control signal CCTRL, and output image data DOUT by converting a voltage difference between a reference signal and an image signal into a digital signal based on the ramp voltage VRAMP.

[0050] Figure 4 is shown connected to Figure 1 FIG. 1 is a diagram of unit pixels PX1 to PX5 in the same row of the image sensing device 1 . Figure 5A and Figure 5B is a diagram explaining why the transmission control signal TX is driven to a low voltage. Figure 6 is the explanation Figure 4 1 is a timing diagram of operations of the unit pixels PX1 to PX5.

[0051] Reference Figure 4 , Figure 4A circuit for modeling the first to fifth unit pixels PX1 to PX5 is shown, and the first to fifth unit pixels PX1 to PX5 are connected through a transmission driver TX_DRV of the row control circuit 12 and a signal line (hereinafter referred to as a "TX line") through which a transmission control signal TX is transmitted. An RC component may exist between each of the first to fifth unit pixels PX1 to PX5 and the TX line.

[0052] When too strong light is applied to the pixel array 10, overflow may occur, in which photocharges are excited from the photodiode PD to the FD node. A current path may be formed due to the overflow, causing the voltage level of the FD node to change. For example, when the voltage level of the FD node changes due to the photocharge being transferred to the FD node of the third unit pixel PX3, this affects the voltage level of the FD nodes of the remaining unit pixels connected to the same row line due to the capacitive coupling effect. In this way, the noise generated by the change in the voltage level of the FD node of any unit pixel that affects the remaining unit pixels connected to the same row line is called stripe noise.

[0053] In this example, in response to the transmission control signal TX applied to the gate of the transmission transistor M1, the transmission transistor M1 transmits the photocharge of the photodiode PD electrically coupled to one end thereof to the FD node electrically coupled to the other end thereof. Compared with the case where the voltage level of the transmission control signal TX is set to the ground voltage VSSPX level (i.e., 0V), in the case where the voltage level of the transmission control signal TX is set to a voltage level lower than the ground voltage level (e.g., -0.9V), the thickness of hole accumulation can be increased. That is, as Figure 5A As shown in FIG. 1 , the closer the voltage level of the transmission control signal TX is to the ground voltage level, the lower the current barrier between the photodiode PD and the FD node is, making it easier for a current path to be formed due to overflow. Figure 5B As shown, the lower the voltage level of the transmission control signal TX is than the ground voltage level, the higher the current barrier between the photodiode PD and the FD node is, which can significantly reduce the possibility of a current path being formed due to overflow. Therefore, by driving the transmission control signal TX to a voltage VBB lower than the ground voltage level during the reset readout period, even if too strong light is applied to the pixel array 10, it is possible to prevent photocharge from being transferred from the photodiode PD to the FD node.

[0054] Return to reference Figure 4, when a current path is formed due to overflow, a gradient voltage drop may occur in the voltage level of the transmission control signal TX provided from the row control circuit 12 to the first unit pixel PX1 to the fifth unit pixel PX5 due to the parasitic capacitance of the RC component of the TX line of the pixel array 10. For example, when the voltage level of the FD node changes due to the photocharge being transferred to the FD node of the third unit pixel PX3, a gradient voltage drop may occur from the output node (point A) of the transmission driver TX_DRV to the connection node (point D) of the third unit pixel PX3. That is, as Figure 6 As shown, the voltage level of the TX line through which the transmission control signal is transmitted may gradually decrease from the output node of the transmission driver TX_DRV to the third unit pixel PX3. However, in this example where the overflow occurs in PD3, no further voltage drop occurs from the connection node (point D) of the third unit pixel PX3 to the connection node (point G) after the fifth unit pixel PX5. That is, the voltage level of the TX line remains constant from the connection node (point D) to the connection node (point G).

[0055] During the reset readout period from disabling the reset signal RX to enabling the transmission control signal TX, such a change in the voltage level of the TX line may be a factor that increases the voltage level of the pixel voltage VPIXEL corresponding to the reference signal, which further aggravates the stripe noise. In addition, as described above, the voltage drop of the transmission control signal TX supplied from the row control circuit 12 to the first unit pixel PX1 to the fifth unit pixel PX5 is not uniform, making it difficult to compensate for the stripe noise.

[0056] Hereinafter, according to one embodiment of the present invention, a scheme for compensating for stripe noise by causing a symmetric voltage drop on the same row line through a configuration of a bias compensation circuit and a row control circuit disposed at opposite sides relative to a pixel array will be described. The bias compensation circuit is adapted to drive the row control signal to a voltage level lower than the ground voltage VSSPX level during a reset readout period, thereby preventing stripe noise.

[0057] Figure 7 is a diagram showing a configuration of an image sensing device 100 according to a first embodiment of the present invention.

[0058] Reference Figure 7 The image sensing device 100 may include a pixel array 110 , a row control circuit 120 , a bias compensation circuit 130 , a readout circuit 140 , a timing controller 150 , a ramp voltage generating circuit 160 , and a compensation controller 170 .

[0059] The pixel array 110 may include a plurality of unit pixels PX arranged in an array type in the row direction and the column direction. Each unit pixel PX may include Figure 2 The configuration is basically the same as that of Figure 3 The operation shown is substantially the same operation. The unit pixel PX may be connected to the row control circuit 120 through a plurality of row lines RLn, and may be connected to the readout circuit 140 through a plurality of column lines CLm. The pixel array 110 may be controlled by a row control signal RCS provided from the row control circuit 120 through the row lines RLn. The pixel array 110 may generate photocharges corresponding to the amount of incident light, accumulate the generated photocharges in a floating diffusion (FD) node, and provide an electrical signal corresponding to the photocharges as a pixel voltage VPIXEL through the column line CLm by converting a voltage level of the FD node into an electrical signal.

[0060] The row control circuit 120 may be provided at a first side of the pixel array 110. According to the first timing control signal RCTRL provided from the timing controller 150, the row control circuit 120 may generate a row control signal RCS including a transmission control signal TX, a reset signal RX, and a selection signal SX, and provide the row control signal RCS to the pixel array 110 through the row line RLn. The row control circuit 120 may provide the row control signal RCS to the unit pixel PX at the same row line provided in the row lines RLn. In particular, the row control circuit 120 may provide the transmission control signal TX having a voltage level between the first voltage and the second voltage to each row line RLn. For example, the first voltage may have a source voltage VDDPX level, and the second voltage may have a voltage VBB level lower than the ground voltage VSSPX level. According to one embodiment, the first voltage may have a voltage VPP level higher than the source voltage VDDPX level, and the second voltage may have the above-mentioned lower voltage VBB level. The row control circuit 120 may generate a selection signal SX for selecting any one of the row lines RLn according to the first timing control signal RCTRL. The row control circuit 120 may sequentially activate the reset signal RX and the transmission control signal TX at a preset timing according to the first timing control signal RCTRL, and output the reset signal RX and the transmission control signal TX to the unit pixel PX coupled to the selected row line.

[0061] The bias compensation circuit 130 may be disposed at a second side of the pixel array 110. The second side may be opposite to the first side relative to the pixel array 110. That is, the row control circuit 120 and the bias compensation circuit 130 may be located at opposite sides in the length direction of the row line RLn relative to the pixel array 110. According to a plurality of compensation enable signals EN respectively corresponding to the row lines RLn provided from the compensation controller 170, the bias compensation circuit 130 may drive the transmission control signal TX for each row line RLn to a second voltage (i.e., a lower voltage VBB level).

[0062] The timing controller 150 may generate a first timing control signal RCTRL and a second timing control signal CCTRL including a clock signal, thereby controlling the pixel array 110, the row control circuit 120, the readout circuit 140, the ramp voltage generating circuit 160, and the compensation controller 170. The timing controller 150 may include a logic control circuit, a phase-locked loop (PLL) circuit, a timing control circuit, and a communication interface circuit.

[0063] According to the control of the timing controller 150 , the slope voltage generating circuit 160 may generate a slope voltage VRAMP that decreases (or increases) over time.

[0064] The readout circuit 140 may convert the pixel voltage VPIXEL into a digital signal based on the ramp voltage VRAMP according to the second timing control signal CCTRL, and output the digital signal as the image data DOUT. The readout circuit 140 may include a sampler, an analog-to-digital converter, and / or an output buffer. The output buffer may also include a column decoder for outputting the image data DOUT by column.

[0065] The compensation controller 170 may generate a plurality of compensation enable signals EN in response to the first timing control signal RCTRL. Each compensation enable signal EN may be enabled during a reset readout period of a unit pixel PX connected to a corresponding one of the row lines RLn. That is, the compensation enable signal EN may be enabled during a reset readout period of a corresponding one of the row lines RLn. For reference, the reset readout period may be defined as a time period from disabling the reset signal RX of the corresponding row line to enabling the transmission control signal TX, that is, a time period for outputting a pixel voltage VPIXEL corresponding to a reference signal. Therefore, the bias compensation circuit 130 may drive the transmission control signal TX of the corresponding row line to a lower voltage VBB level.

[0066] Hereinafter, detailed configurations of the row control circuit 120 and the offset compensation circuit 130 will be explained. Figure 7 and Figure 8 4×4 unit pixels PX coupled between 4 row lines and 4 column lines are shown in FIG.

[0067] Figure 8 It is shown Figure 7 1 is a circuit diagram of a row control circuit 120 and a bias compensation circuit 130. Fig. 9 is the explanation Figure 8 1 is a timing diagram of the operation of the unit pixel PX.

[0068] Reference Figure 8, the row control circuit 120 may include first to fourth transmission drivers 121 to 124, and the first to fourth transmission drivers 121 to 124 are used to provide first to fourth transmission control signals TX<1:4> to the first to fourth row lines RL<1:4>, respectively. For example, the first transmission driver 121 may include a terminal connected in series between a source voltage VDDPX terminal and a lower voltage VBB terminal and having a function of receiving a first timing control signal RCTRL_T <1> The gates of the PMOS transistor 121P and the NMOS transistor 121N. The first transmission control signal TX <1> The common node of the PMOS transistor 121P and the NMOS transistor 121N may be output to the pixel array 110. According to one embodiment, the PMOS transistor 121P and the NMOS transistor 121N may be connected in series between a higher voltage VPP terminal and a lower voltage VBB terminal. The row control circuit 120 may also include a plurality of reset drivers for providing a plurality of reset signals RX, and a plurality of selection drivers for providing a plurality of selection signals SX.

[0069] The offset compensation circuit 130 may include first to fourth compensators 131 to 134 corresponding to the first to fourth row lines RL<1:4>, respectively. For example, the first compensator 131 may include a first compensator 131 connected in series to the first row line RL <1> The first compensation transistor N1 and the second compensation transistor N2 are connected between the terminal of the lower voltage VBB. The first compensation transistor N1 may have a gate receiving the source voltage VDDPX, and the second compensation transistor N2 may have a gate receiving the first compensation enable signal EN <1> The first compensation transistor N1 and the second compensation transistor N2 may be implemented using NMOS transistors. Since the first compensation transistor N1 operates according to the source voltage VDDPX, a gate induced drain leakage (GIDL) current due to the gate-drain voltage may be reduced. According to one embodiment, the first to fourth compensators 131 to 134 may include a plurality of first compensation transistors connected in parallel and a plurality of second compensation transistors connected in parallel, wherein the first compensation transistors and the second compensation transistors are connected in series between each row line RL<1:4> and a lower voltage VBB terminal.

[0070] At the same time, if Figure 2 As shown, each unit pixel PX may include a photodiode PD, a transfer transistor M1, a reset transistor M2, a drive transistor M3, and a selection transistor M4. An FD node may be formed at a common node of the transfer transistor M1 and the reset transistor M2.

[0071] Reference Fig. 9 , showing the connection to the same row line (eg, the first row line RL <1> ) operation of the unit pixel PX.

[0072] The reset transistor M2 is turned on in response to the reset signal RX, and thus, a charge corresponding to the voltage level of the source voltage VDDPX is charged into the FD node. As a result, the FD node is initialized. The selection transistor M4 is turned on in response to the selection signal SX, and thus, the electrical signal provided from the FD node is output as the pixel voltage VPIXEL. The pixel voltage VPIXEL can be used as a reference signal. In response to the timing control signal RCTRL_T of the logic high level (for example, the first timing control signal RCTRL_T <1> ), the first transmission driver 121 may transmit the transmission control signal TX (eg, the first transmission control signal TX <1> ) is driven to a lower voltage VBB.

[0073] During the reset readout period from disabling the reset signal RX to enabling the transmission control signal TX, the compensation enable signal EN (eg, the first compensation enable signal EN <1> ) is enabled to a logic high level. Therefore, the first compensator 131 can drive the transmission control signal TX to a lower voltage VBB. That is, the first row line RL <1> One terminal of the first row line RL is biased to a lower voltage VBB by the first transmission driver 121, and the first row line RL <1> The other terminal of is biased to a lower voltage VBB by the first compensator 131. Therefore, even if a current path caused by overflow is formed on any unit pixel, a symmetrical voltage drop can be formed on both terminals of the same row line.

[0074] After the reset readout period, the first transmission driver 121 can drive the transmission control signal TX to the source voltage VDDPX, so that the transmission transistor M1 is turned on. At this time, the selection transistor M4 is turned off in response to the selection signal SX. By turning off the selection transistor M4 when the transmission control signal TX is switched, the voltage level of the pixel voltage VPIXEL can be prevented from increasing and the stabilization time of the pixel voltage VPIXEL can be reduced. The transmission transistor M1 is turned on in response to the transmission control signal TX, thereby transferring the photocharge of the photodiode PD to the FD node. Thereafter, the selection transistor M4 is turned on in response to the selection signal SX, and therefore, the electrical signal provided from the FD node is output as the pixel voltage VPIXEL. The pixel voltage VPIXEL can be used as an image signal.

[0075] The readout circuit 140 samples the pixel voltage VPIXEL twice according to the second timing control signal CCTRL, and outputs the image data DOUT by converting a voltage difference between the reference signal and the image signal into a digital signal based on the ramp voltage VRAMP.

[0076] Fig. 10A and Fig. 10Bis a graph for comparing error rates in the column direction of unit pixels connected to the same row line in the conventional image sensing device 1 and the image sensing device 100 according to the embodiment of the present invention.

[0077] Reference Fig. 10A In the conventional image sensing device 1, during the reset readout period, when overflow occurs at any unit pixel, it affects the voltage level of the FD nodes of the remaining unit pixels connected to the same row line due to the capacitive coupling effect. Figure 4 As shown in the modeling circuit of , when overflow occurs at the third unit pixel PX3, a gradient voltage drop may occur from the output node (point A) of the transmission driver TX_DRV to the connection node (point D) of the third unit pixel PX3, while no further voltage drop occurs from the connection node (point D) of the third unit pixel PX3 to the connection node (point G) after the fifth unit pixel PX5. As a result, as Fig. 10A As shown, the error rate in the column direction is similar to the distribution of the voltage drop. Even if an offset value is set to compensate for the error relative to point A or point D, it is not easy to correct the error because the number of unit pixels that are not within the target range increases.

[0078] and Fig. 10A In contrast, in the image sensing device 100 according to the embodiment of the present invention, during the reset readout period, the first transmission driver 121 may <1> The first compensator 131 can bias one terminal of the first row line RL to a lower voltage VBB. <1> The other terminal of is biased to a lower voltage VBB, so that even if a current path caused by overflow is formed on any unit pixel, a symmetrical voltage drop will be caused on the two terminals of the same row line. Fig. 10B As shown, the error rate in the column direction is also symmetrical similar to the distribution of the voltage drop. When the offset value is set to compensate for the error relative to point A or point D, it is relatively easy to correct the error because the number of unit pixels within the target range increases.

[0079] As described above, according to the first embodiment, the image sensing device 100 may be provided with the offset compensation circuit 130 and the row control circuit 120 disposed at opposite sides relative to the pixel array 110, thereby compensating for stripe noise by causing symmetrical voltage drops on the same row line.

[0080] Fig.11 is a circuit diagram showing an offset compensation circuit 130 according to another embodiment of the present invention.

[0081] Reference Fig.11, the bias compensation circuit 130 may include first to fourth compensation drivers 135 to 138 corresponding to the first to fourth row lines RL<1:4>, respectively. For example, the first compensation driver 135 may include a first compensation signal generator 135A and a first compensator 135B. The first compensation signal generator 135A may be configured to generate a compensation signal based on the selection signal SX and the first compensation enable signal EN <1> The first period determination signal SX_EN is generated <1> .

[0082] The first compensation signal generator 135A may include a NAND gate ND1, an inverter INV1, and a level shifter LS. The NAND gate ND1 and the inverter INV1 may generate a first compensation enable signal EN1 and a first compensation signal SX. <1> A logical AND operation is performed. The NAND gate ND1 and the inverter INV1 may output a signal having a voltage level between the source voltage VDDPX level and the ground voltage VSSPX level. The level shifter LS may output a first period determination signal SX_EN swinging between the source voltage VDDPX level and the lower voltage VBB level by shifting the voltage level of the signal output from the inverter INV1 swinging between the source voltage VDDPX level and the ground voltage VSSPX level. <1> .

[0083] With the above configuration, when the first compensation enable signal EN is enabled in the state where the selection signal SX is enabled <1> When the first compensation signal generator 135A can determine the first period of time signal SX_EN <1> According to one embodiment, the first compensation enable signal EN <1> It may be a signal that is enabled not only for the reset readout period but also for other periods for different purposes.

[0084] The first compensator 135B may include a first row line RL connected in series <1> The third compensation transistor N3 and the fourth compensation transistor N4 are connected between the terminal of the lower voltage VBB. The third compensation transistor N3 may have a gate receiving the source voltage VDDPX, and the fourth compensation transistor N4 may have a gate receiving the first period determination signal SX_EN. <1> of the gate.

[0085] As described above, the offset compensation circuit 130 can be configured to generate a compensation signal based on the selection signal SX and the first compensation enable signal EN. <1> The row lines RL<1:4> are driven to a lower voltage VBB level.

[0086] Fig.12 is a diagram showing a configuration of an image sensing device 200 according to a second embodiment of the present invention.

[0087] Reference Fig.12The image sensing device 200 may include a pixel array 210, a first row control circuit 222, a second row control circuit 224, a first bias compensation circuit 232, a second bias compensation circuit 234, a readout circuit 240, a timing controller 250, a ramp voltage generating circuit 260 and a compensation controller 270.

[0088] The pixel array 210 may include a plurality of unit pixels PX arranged in an array type in the row direction and the column direction. Each unit pixel PX may include Figure 2 The configuration is basically the same as that of Figure 3 The operation shown is essentially the same operation.

[0089] The first row control circuit 222 may be provided at a first side of the pixel array 210. According to the first timing control signal RCTRL provided from the timing controller 250, the first row control circuit 222 may generate a row control signal RCS including a transmission control signal TX, a reset signal RX, and a selection signal SX, and may provide the row control signal RCS to the unit pixel PX connected to the odd row line among the row lines RLn. In particular, in the second embodiment of the present invention, the first row control circuit 222 may provide the transmission control signal TX having a voltage level between the first voltage and the second voltage to the unit pixel PX connected to the odd row line. For example, the first voltage may have a source voltage VDDPX level or a voltage VPP level higher than the source voltage VDDPX level, and the second voltage may have a voltage VBB level lower than the ground voltage VSSPX level.

[0090] The second row control circuit 224 may be disposed at a second side of the pixel array 210. The second side may be opposite to the first side with respect to the pixel array 210. According to the first timing control signal RCTRL, the second row control circuit 224 may generate a row control signal RCS including a transmission control signal TX, a reset signal RX, and a selection signal SX, and may provide the row control signal RCS to the unit pixels PX connected to the even-numbered row lines among the row lines RLn. In particular, in the second embodiment of the present invention, the second row control circuit 224 may provide the transmission control signal TX having a voltage level between the first voltage and the second voltage to the unit pixels PX connected to the even-numbered row lines.

[0091] The first bias compensation circuit 232 may be disposed on the same side as the second row control circuit 224 relative to the pixel array 210. That is, the first row control circuit 222 and the first bias compensation circuit 232 may be located on opposite sides in the length direction of the row line RLn relative to the pixel array 210. During the reset readout period of the odd row lines, the first bias compensation circuit 232 may drive the transmission control signal TX to a second voltage (i.e., a lower voltage VBB level). According to another embodiment, the first bias compensation circuit 232 may be disposed between the pixel array 210 and the second row control circuit 224.

[0092] The second bias compensation circuit 234 may be disposed on the same side as the first row control circuit 222 relative to the pixel array 210. That is, the second row control circuit 224 and the second bias compensation circuit 234 may be located on opposite sides in the length direction of the row line RLn relative to the pixel array 210. During the reset readout period of the even-numbered row lines, the second bias compensation circuit 234 may drive the transmission control signal TX to a lower voltage VBB level. According to another embodiment, the second bias compensation circuit 234 may be disposed between the pixel array 210 and the first row control circuit 222.

[0093] The timing controller 250 may generate a first timing control signal RCTRL and a second timing control signal CCTRL, thereby controlling the pixel array 210, the first row control circuit 222, the second row control circuit 224, the readout circuit 240, the ramp voltage generating circuit 260, and the compensation controller 270. The timing controller 150 may include a logic control circuit, a phase-locked loop (PLL) circuit, a timing control circuit, and a communication interface circuit. The second timing control signal RCTRL may be divided into a first row timing control signal and a second row timing control signal. The first row timing control signal may be provided to control the unit pixel PX connected to the odd row line, and the second row timing control signal may be provided to control the unit pixel PX connected to the even row line.

[0094] The ramp voltage generating circuit 260 and the readout circuit 240 can be respectively connected to Figure 7 The ramp voltage generating circuit 160 and the readout circuit 140 have substantially the same configuration and operation.

[0095] The compensation controller 270 may generate a plurality of compensation enable signals EN in response to the first timing control signal RCTRL. Each compensation enable signal EN may be enabled during the reset readout period of the unit pixel PX of the same row line connected to the row line RLn. The compensation enable signal may be divided into a first compensation enable signal and a second compensation enable signal. The first compensation enable signal may be enabled during the reset readout period of the odd row line, and the second compensation enable signal may be enabled during the reset readout period of the even row line. Therefore, the first bias compensation circuit 232 may drive the transmission control signal TX to a lower voltage VBB level during the reset readout period of the odd row line, and the second bias compensation circuit 234 may drive the transmission control signal TX to a lower voltage VBB level during the reset readout period of the even row line.

[0096] Fig.13 It is shown Fig.12 A circuit diagram of a first row control circuit 222 and a second row control circuit 224 and a first bias compensation circuit 232 and a second bias compensation circuit 234 is shown.

[0097] Reference Fig.13 The first row control circuit 222 may include a first transmission driver 222_1 and a third transmission driver 222_2, the first transmission driver 222_1 and the third transmission driver 222_2 are used to respectively transmit the first row line RL <1> and the third line RL <3> Provide a first transmission control signal TX <1> and the third transmission control signal TX <3> The second row control circuit 224 may include a second transmission driver 224_1 and a fourth transmission driver 224_2, and the second transmission driver 224_1 and the fourth transmission driver 224_2 are used to respectively transmit the second row line RL <2> and the fourth line RL <4> Provide a second transmission control signal TX <2> and the fourth transmission control signal TX <4> The first row control circuit 222 and the second row control circuit 224 may further include a plurality of reset drivers for providing a plurality of reset signals RX, and a plurality of selection drivers for providing a plurality of selection signals SX. The first to fourth transmission drivers 222_1, 224_1, 222_2, and 224_2 may be respectively connected to Figure 8 The first to fourth transmission drivers 121 to 124 have substantially the same configuration and operation.

[0098] The first offset compensation circuit 232 may include two circuits corresponding to the first row lines RL <1> and the third line RL <3> The second offset compensation circuit 234 may include a first compensator 232_1 and a third compensator 232_2 corresponding to the second row line RL <2> and the fourth line RL <4> The first to fourth compensators 232_1, 234_1, 232_2, and 234_2 may be respectively connected to Figure 8 The first compensator 131 to the fourth compensator 134 have substantially the same configuration and operation. According to one embodiment, the first bias compensation circuit 232 and the second bias compensation circuit 234 may be implemented as Fig.11 The first compensation driver 135 to the fourth compensation driver 138 are implemented.

[0099] As described above, according to the second embodiment, the image sensing device 200 may be provided with a first row control circuit 222 and a second row control circuit 224 arranged on both sides of the pixel array 210, and may be provided with a first bias compensation circuit 232 and a second bias compensation circuit 234 arranged on both sides of the pixel array 210, so that the first row control circuit 222 and the first bias compensation circuit 232 are arranged on opposite sides relative to the pixel array 210, and the second row control circuit 224 and the second bias compensation circuit 234 are arranged on opposite sides relative to the pixel array 210, thereby compensating for stripe noise by causing symmetrical voltage drops on the same row line.

[0100] The criteria for determining the quality of image sensors include dynamic range. In general, dynamic range represents the maximum range over which an image sensor can process a signal without distorting the input signal. As the dynamic range widens, the image obtained by the image sensor can become clearer over a wide range of illumination. Typically, in the case where a specific color is saturated due to a narrow dynamic range, the image sensor cannot represent the original color of the image. In order to overcome the above-mentioned problems caused by the narrow dynamic range, various attempts have been made to achieve wide dynamic range (WDR) pixels. For example, there are technologies that allow image sensors to achieve WDR or increase the capacity of FD nodes while adjusting the illumination time of the incident light.

[0101] Fig.14 is a circuit diagram showing a unit pixel supporting a dual conversion gain (DCG) operation.

[0102] Reference Fig.14, the unit pixel PX may include a photodiode PD, a transfer transistor M1, a reset transistor M2, a drive transistor M3, a selection transistor M4, a gain transistor M5, and a dynamic range capacitor C2. The FD node may be a diffusion region formed at a common node of the transfer transistor M1 and the reset transistor M2. The FD node may store a charge corresponding to a photocharge, or a charge corresponding to an initialization voltage (ie, a source voltage VDDPX). Therefore, the FD node may be modeled as a capacitor C1.

[0103] Fig.14 The photodiode PD, the transfer transistor M1, the reset transistor M2, the drive transistor M3 and the selection transistor M4 may have Figure 3 Basically the same configuration and operation.

[0104] The gain transistor M5 may transfer photo charges stored at the FD node electrically coupled to one end thereof to the dynamic range capacitor C2 electrically coupled to the other end thereof in response to a gain control signal DCGX applied to the gate of the gain transistor M5 .

[0105] The dynamic range capacitor C2 may be coupled between the other end of the gain transistor M5 and the ground voltage VSSPX terminal.

[0106] In high illumination mode, the gain control signal DCGX is enabled to a logic high level, and the gain transistor M5 is turned on, so that the dynamic range capacitor C2 is connected to the FD node. Therefore, in high illumination mode, the overflowing charge from the photodiode PD to the FD node is shared by the dynamic range capacitor C2. In high illumination mode, a large amount of overflowing charge from the photodiode PD can be integrated instead of discarding them. For example, in this embodiment, a large amount of overflowing charge from the photodiode PD is not discarded, but used as image information sensed at relatively high illumination. In contrast, in low illumination mode, the gain control signal DCGX is disabled, and the gain transistor M5 is turned off, so that the dynamic range capacitor C2 is electrically disconnected from the FD node. Therefore, in this embodiment, the charge transferred from the photodiode PD to the FD node in low illumination mode is only stored in the FD node. In this way, by using the gain transistor M5 and the dynamic range capacitor C2, different conversion gains can be provided in high illumination mode and low illumination mode, thereby achieving high conversion gain and low noise characteristics.

[0107] In an image sensing device supporting DCG operation, a gain control signal DCGX may be provided to a pixel array from a row control circuit via a row line as Figure 7In one embodiment, the row control circuit may drive the gain control signal DCGX to a voltage VPP higher than the source voltage VDDPX level during the reset readout period. Therefore, the stripe noise may be compensated by maintaining uniform capacitance by ensuring that the MOS capacitance of the gain transistor M5 and the capacitance of the dynamic range capacitor C2 are uniform.

[0108] In the following, reference is made to Fig.15 and Fig.16 , an image sensing device supporting a DCG operation according to third and fourth embodiments of the present invention will be described. Fig.15 and Fig.16 A 4×4 unit pixel PX coupled between 4 row lines and 4 column lines is shown.

[0109] Fig.15 is a circuit diagram showing a row control circuit 320 and an offset compensation circuit 330 included in an image sensing device 300 according to a third embodiment of the present invention.

[0110] Reference Fig.15 , the row control circuit 320 may be disposed on a first side of the pixel array 310, and the bias compensation circuit 330 may be disposed on a second side of the pixel array 310. The row control circuit 320 and the bias compensation circuit 330 may be located at opposite sides of the length direction of the first to fourth row lines RL<1:4> relative to the pixel array 310.

[0111] The row control circuit 320 may provide first to fourth gain control signals DCGX<1:4> having a voltage level between a third voltage and a fourth voltage to each of the first to fourth row lines RL<1:4>. For example, the third voltage may have a voltage VPP level higher than the source voltage VDDPX level, and the fourth voltage may have a ground voltage VSSPX level. According to one embodiment, the third voltage may have a higher voltage VPP level, and the fourth voltage may have a voltage VBB level lower than the ground voltage VSSPX level.

[0112] The row control circuit 320 may include first to fourth gain drivers 321 to 324, and the first to fourth gain drivers 321 to 324 are used to provide first to fourth gain control signals DCGX<1:4> to the first to fourth row lines RL<1:4>, respectively. For example, the first gain driver 321 may include a terminal connected in series between a higher voltage VPP terminal and a ground voltage VSSPX terminal and having a first timing control signal RCTRL_D <1> The gates of the PMOS transistor 321P and the NMOS transistor 321N. The first gain control signal DCGX <1> The common node of the PMOS transistor 321P and the NMOS transistor 321N may be output to the pixel array 310. According to one embodiment, the PMOS transistor 321P and the NMOS transistor 321N may be connected in series between a higher voltage VPP terminal and a lower voltage VBB terminal. The row control circuit 320 may also include a plurality of transmission drivers for providing a plurality of transmission control signals TX, a plurality of reset drivers for providing a plurality of reset signals RX, and a plurality of selection drivers for providing a plurality of selection signals SX.

[0113] The bias compensation circuit 330 may drive the first to fourth gain control signals DCGX<1:4> to a third voltage (i.e., a higher voltage VPP level) during a reset readout period of each row line according to the first to fourth inverted compensation enable signals ENB<1:4> respectively corresponding to the first to fourth row lines RL<1:4>. The bias compensation circuit 330 may include first to fourth compensators 331 to 334 respectively corresponding to the first to fourth row lines RL<1:4>. For example, the first compensator 331 may include a first compensator 331 connected in series to the first row line RL<1:4>. <1> The first compensation transistor P1 and the second compensation transistor P2 are connected between the terminals of the compensation transistor P1 and the higher voltage VPP. The first compensation transistor P1 may have a gate receiving the ground voltage VSSPX, and the second compensation transistor P2 may have a gate receiving the first inverted compensation enable signal ENB. <1> The first compensation transistor P1 and the second compensation transistor P2 can be implemented by PMOS transistors. For reference, since the first compensation transistor P1 and the second compensation transistor P2 can be implemented by PMOS transistors, Fig.15 The first to fourth inverted compensation enable signals ENB<1:4> may have the same Figure 8 Since the first compensation transistor P1 operates according to the ground voltage VSSPX, a gate induced drain leakage (GIDL) current generated due to a gate-drain voltage may be reduced.

[0114] In one embodiment, in the image sensing device 300, the row control circuit 320 may also provide a transmission control signal TX having a voltage level between a first voltage and a second voltage to the transmission transistor of the unit pixel PX through each row line. For example, the first voltage may have a source voltage VDDPX level or a higher voltage VPP level, and the second voltage may have a lower voltage VBB level. According to any one of the compensation enable signals EN<1:4>, the bias compensation circuit 330 may drive the transmission control signal TX to the second voltage (i.e., a lower voltage VBB level) during the reset readout period of each row line. The bias compensation circuit 330 may receive the compensation enable signal EN<1:4> for driving the transmission control signal TX to a lower voltage VBB level, while receiving the inverted compensation enable signal ENB<1:4> for driving the gain control signal DCGX<1:4> to a higher voltage VPP level.

[0115] As described above, according to the third embodiment, the image sensing device 300 supporting the DCG operation may be provided with a bias compensation circuit 330 and a row control circuit 320 arranged on opposite sides relative to the pixel array 310, thereby further compensating for the stripe noise by causing a symmetrical voltage drop on the same row line, wherein the bias compensation circuit 330 drives the gain control signal DCGX to a higher voltage VPP level during the reset readout period of each row line.

[0116] Fig.16 4 is a circuit diagram showing first and second row control circuits 422 and 424 and first and second offset compensation circuits 432 and 434 included in an image sensing device 400 according to a fourth embodiment of the present invention.

[0117] Reference Fig.16 The first row control circuit 422 may be disposed at a first side of the pixel array 410. The first row control circuit 422 may respectively control odd-numbered row lines RL connected to the first to fourth row lines RL<1:4>. <1> and RL <3> The unit pixel PX provides a gain control signal DCG having a voltage level between the third voltage and the fourth voltage. <1> and DCG <3> .

[0118] The second row control circuit 424 may be disposed on a second side of the pixel array 410. The second side may be opposite to the first side relative to the pixel array 410. The second row control circuit 424 may control the even-numbered row lines RL connected to the first to fourth row lines RL<1:4>, respectively. <2> and RL <4> The unit pixel PX provides a gain control signal DCG having a voltage level between the third voltage and the fourth voltage. <2> and DCG <4> .

[0119] The first bias compensation circuit 432 may be disposed on one side of the second row control circuit 424. That is, the first row control circuit 422 and the first bias compensation circuit 432 may be located on opposite sides of the length direction of the first to fourth row lines RL<1:4> relative to the pixel array 410. <1> and RL <3> During each reset readout period, the first bias compensation circuit 432 can respectively set the gain control signal DCG <1> and DCG <3> According to another embodiment, the first bias compensation circuit 432 may be disposed between the pixel array 410 and the second row control circuit 424 .

[0120] The second bias compensation circuit 434 may be disposed on one side of the first row control circuit 422. That is, the second row control circuit 424 and the second bias compensation circuit 434 may be located on opposite sides of the length direction of the first row line to the fourth row line RL<1:4> relative to the pixel array 410. <2> and RL <4> During each reset readout period, the second bias compensation circuit 434 can respectively set the gain control signal DCG <2> and DCG <4> According to another embodiment, the second bias compensation circuit 434 may be disposed between the pixel array 410 and the first row control circuit 422 .

[0121] The first row control circuit 422 and the second row control circuit 424 can be connected to Fig.15 The row control circuit 320 has substantially the same configuration and operation. The first bias compensation circuit 432 and the second bias compensation circuit 434 may be connected to Fig.15 The bias compensation circuit 330 has substantially the same configuration and operation.

[0122] As described above, according to the fourth embodiment, the image sensing device 400 may be provided with a first row control circuit 422 and a second row control circuit 424 arranged on both sides of the pixel array 410, and may be provided with a first bias compensation circuit 432 and a second bias compensation circuit 434 arranged on both sides of the pixel array 410, so that the first row control circuit 422 and the first bias compensation circuit 432 are arranged on opposite sides relative to the pixel array 410, and the second row control circuit 424 and the second bias compensation circuit 434 are arranged on opposite sides relative to the pixel array 410, thereby compensating for stripe noise by causing symmetrical voltage drops on the same row lines.

[0123] As described above, according to an embodiment of the present invention, an image sensing device may be provided with a bias compensation circuit and a row control circuit arranged on opposite sides relative to a pixel array, and the bias compensation circuit is suitable for driving the row control signal to a preset voltage during a reset readout period of each row line. Therefore, stripe noise can be compensated by causing a symmetrical voltage drop on the same row line. In various embodiments of the present invention, although it is explained as an example that the bias compensation circuit for biasing the transmission control signal TX and the gain control signal DCGX is placed on the opposite side of the row control circuit, the present invention is not limited to this. According to one embodiment, the row control circuit and the bias compensation circuit for biasing the reset signal RX or the selection signal SX can be placed on opposite sides relative to the pixel array, thereby compensating for stripe noise by causing a symmetrical voltage drop on the same row line.

[0124] It should be noted that although the technical spirit of the present disclosure has been described in conjunction with the preferred embodiments of the present disclosure, this is for descriptive purposes only and should not be interpreted as limiting. It should be understood by those skilled in the art that various changes may be made to the present disclosure without departing from the technical spirit of the present disclosure.

[0125] For example, for the logic gates and transistors provided as examples in the above-mentioned embodiments, different positions and types may be implemented according to the polarity of the input signal.

[0126] CROSS-REFERENCE TO RELATED APPLICATIONS

[0127] This application claims priority to Korean Patent Application No. 10-2021-0028172 filed on Mar. 3, 2021, which is hereby incorporated by reference in its entirety.

Claims

1. An image sensing device, comprising: a pixel array including a plurality of unit pixels coupled to a plurality of row lines, wherein at least one of the plurality of unit pixels includes a photodiode for generating photocharges corresponding to incident light and a transfer transistor for transferring the photocharges to a floating diffusion FD node in response to a transfer control signal transmitted through a corresponding row line; a row control circuit disposed at a first side of the pixel array and providing the transfer control signal having a voltage level between a first voltage and a second voltage to each row line; and A bias compensation circuit is arranged on the second side of the pixel array and drives the transfer control signal to the second voltage during a reset readout period of each of the plurality of row lines, wherein the bias compensation circuit includes a plurality of compensators connected to the respective row lines, and wherein at least one of the plurality of compensators includes a first compensation transistor and a second compensation transistor, and the first compensation transistor and the second compensation transistor are connected in series between the corresponding row line and a second voltage terminal.

2. The image sensing device according to claim 1, in, Each of the plurality of unit pixels further includes a reset transistor that initializes the FD node according to a reset signal provided from the row control circuit, The reset readout period is included in a period from disabling the reset signal to enabling the transfer control signal.

3. The image sensing device according to claim 1, wherein: The first voltage has a source voltage level, and the second voltage has a voltage level lower than a ground voltage level.

4. The image sensing device according to claim 1, wherein: The first voltage has a voltage level higher than a source voltage level, and the second voltage has a voltage level lower than a ground voltage level.

5. The image sensing device according to claim 1, in, The first compensation transistor and the second compensation transistor have gates receiving a source voltage signal and a compensation enable signal enabled during the reset readout period, respectively.

6. The image sensing device according to claim 1, wherein: Each of the plurality of unit pixels further includes: a drive transistor that generates an electrical signal corresponding to the charge stored in the FD node; and a selection transistor that outputs the electric signal supplied from the drive transistor as a pixel voltage according to a selection signal supplied from the row control circuit.

7. The image sensing device according to claim 6, in, At least one of the plurality of compensators further comprises: a compensation signal generator that generates a period determination signal based on the selection signal and a compensation enable signal enabled during the reset readout period; and The first compensation transistor and the second compensation transistor have gates receiving a source voltage and the period determination signal respectively.

8. An image sensing device, comprising: a pixel array including a plurality of unit pixels coupled to a plurality of row lines, wherein each unit pixel includes a photodiode for generating photocharges corresponding to incident light and a transfer transistor for transferring the photocharges to a floating diffusion FD node in response to a transfer control signal transmitted through a corresponding row line; a first row control circuit disposed at a first side of the pixel array and providing the transmission control signal having a voltage level between a first voltage and a second voltage to odd-numbered row lines among the plurality of row lines; a second row control circuit, the second row control circuit being disposed at a second side of the pixel array and providing the transmission control signal to even-numbered row lines among the plurality of row lines; a first bias compensation circuit that is disposed at the second side and drives the transfer control signal to the second voltage during a reset readout period of the odd-numbered row lines; and A second bias compensation circuit is provided at the first side and drives the transfer control signal to the second voltage during a reset readout period of the even-numbered row line.

9. The image sensing device according to claim 8, in, Each of the plurality of unit pixels further includes a reset transistor that initializes the FD node according to a reset signal provided from the first row control circuit or the second row control circuit, The reset readout period is included in a period from disabling the reset signal to enabling the transfer control signal.

10. The image sensing device according to claim 8, wherein: The first voltage has a source voltage level or a voltage level higher than the source voltage level, and the second voltage has a voltage level lower than a ground voltage level.

11. The image sensing device according to claim 8, in, Each of the first bias compensation circuit and the second bias compensation circuit includes a plurality of compensators coupled to respective row lines, and Each of the plurality of compensators includes a first compensation transistor and a second compensation transistor, the first compensation transistor and the second compensation transistor are connected in series between the corresponding row line and the second voltage terminal, and have gates for respectively receiving a source voltage and a compensation enable signal enabled during the reset readout period.

12. The image sensing device according to claim 8, in, Each of the plurality of unit pixels further includes: a drive transistor that generates an electrical signal corresponding to the charge stored in the FD node; and a selection transistor that outputs the electric signal supplied from the driving transistor as a pixel voltage according to a selection signal supplied from the first row control circuit or the second row control circuit, and wherein each of the first bias compensation circuit and the second bias compensation circuit comprises a plurality of compensators connected to respective row lines, Wherein, each of the plurality of compensators comprises: a compensation signal generator that generates a period determination signal based on the selection signal and a compensation enable signal enabled during the reset readout period; and A third compensation transistor and a fourth compensation transistor are coupled in series between the corresponding row line and the second voltage terminal and have gates receiving a source voltage and the period determination signal, respectively.

13. An image sensing device, comprising: a pixel array comprising a plurality of unit pixels coupled to a plurality of row lines, wherein each unit pixel comprises a photodiode for generating photocharges corresponding to incident light, a transfer transistor for transferring the photocharges to a floating diffusion FD node in response to a transfer control signal, and a gain transistor for coupling the FD node to a dynamic range capacitor in response to a gain control signal; a row control circuit disposed at a first side of the pixel array and providing the gain control signal having a voltage level between a third voltage and a fourth voltage to each row line; and A bias compensation circuit is disposed at a second side of the pixel array and drives the gain control signal to the third voltage during a reset readout period of each of the plurality of row lines.

14. The image sensing device according to claim 13, in, Each of the plurality of unit pixels further includes a reset transistor that initializes the FD node according to a reset signal provided from the row control circuit, The reset readout period is included in a period from disabling the reset signal to enabling the transfer control signal.

15. The image sensing device according to claim 13, wherein: The third voltage has a voltage level higher than a source voltage level, and the fourth voltage has a ground voltage level or a voltage level lower than the ground voltage level.

16. The image sensing device according to claim 13, in, The bias compensation circuit includes a plurality of compensators coupled to each row line, and Wherein, each of the plurality of compensators includes a first compensation transistor and a second compensation transistor, the first compensation transistor and the second compensation transistor are connected in series between the corresponding row line and the third voltage terminal, and have gates for respectively receiving a ground voltage and a compensation enable signal enabled during the reset readout period.

17. The image sensing device according to claim 13, in, Each of the plurality of unit pixels further includes: a drive transistor that generates an electrical signal corresponding to the charge stored in the FD node; and a selection transistor that outputs an electric signal supplied from the drive transistor as a pixel voltage according to a selection signal supplied from the row control circuit, The bias compensation circuit includes a plurality of compensators respectively connected to the plurality of row lines, and Wherein, each of the plurality of compensators comprises: a compensation signal generator that generates a period determination signal based on the selection signal and a compensation enable signal enabled during the reset readout period; and A third compensation transistor and a fourth compensation transistor are coupled in series between the corresponding row line and the third voltage terminal and have gates receiving a ground voltage and the period determination signal, respectively.

18. The image sensing device according to claim 13, in, The row control circuit further provides the transmission control signal having a voltage level between the first voltage and the second voltage to each row line, and The bias compensation circuit further drives the transmission control signal to the second voltage during the reset readout period.

19. The image sensing device according to claim 18, wherein: The first voltage has a source voltage level or a voltage level higher than the source voltage level, and the second voltage has a voltage level lower than a ground voltage level.

20. An image sensing device, comprising: a pixel array comprising a plurality of unit pixels coupled to a plurality of row lines, wherein each unit pixel comprises a photodiode for generating photocharges corresponding to incident light, a transfer transistor for transferring the photocharges to a floating diffusion FD node in response to a transfer control signal, and a gain transistor for coupling the FD node to a dynamic range capacitor in response to a gain control signal; a first row control circuit disposed at a first side of the pixel array and providing the gain control signal having a voltage level between a third voltage and a fourth voltage to odd-numbered row lines of the plurality of row lines; a second row control circuit, the second row control circuit being disposed at a second side of the pixel array and providing the gain control signal to even-numbered row lines among the plurality of row lines; a first bias compensation circuit disposed at the second side and driving the gain control signal to the third voltage during a reset readout period of the odd-numbered row lines; and A second bias compensation circuit is provided at the first side and drives the gain control signal to the third voltage during a reset readout period of the even-numbered row lines.

Images