Silicon-based josephson junctions for quantum devices

Abstract

Techniques are provided regarding quantum bit devices including silicon-based Josephson junctions and / or fabrication of quantum bit devices including silicon-based Josephson junctions. For example, one or more embodiments described herein can include an apparatus that can include a Josephson junction including a tunnel barrier between two vertically-stacked superconducting silicon electrodes.

Description

Background Technology

[0001] This topic disclosure relates to one or more silicon-based Josephson junctions that can be incorporated into a qubit device, and more specifically, to Josephson junctions comprising superconducting silicon materials that can be realized in a vertical structural orientation. Summary of the Invention

[0002] The following overview is provided to offer a basic understanding of one or more embodiments of the invention. This overview is not intended to identify key or essential elements, or to depict any scope of a particular embodiment or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that follows. In one or more embodiments described herein, apparatus and / or methods relating to silicon-based Josephson junctions for one or more qubit devices are described.

[0003] According to one embodiment, an apparatus is provided. The apparatus may include a Josephson junction, which includes a tunnel barrier located between two vertically stacked superconducting silicon electrodes.

[0004] According to another embodiment, an apparatus is provided. The apparatus may include a Josephson junction, which includes a dielectric tunnel barrier located between two superconducting silicon electrodes.

[0005] According to one embodiment, a method is provided. The method may include doping a portion of a silicon substrate to form a first superconducting electrode. The method may further include depositing a silicon layer onto the first superconducting electrode via an epitaxial growth process to form a tunnel barrier. Furthermore, the method may include doping a portion of the tunnel barrier to form a second superconducting electrode, thereby forming a Josephson junction. Attached Figure Description

[0006] Figure 1A A diagram showing an example non-limiting cross-sectional view of a device including a silicon-based Josephson junction that can be oriented in a vertical stack, according to one or more embodiments described herein.

[0007] Figure 1B An illustration of an example non-limiting top view of a device comprising a silicon-based Josephson junction that can be oriented in a vertical stack, according to one or more embodiments described herein.

[0008] Figure 2 A diagram showing an example non-limiting cross-sectional view of a device including a silicon-based Josephson junction during the first stage of fabrication according to one or more embodiments described herein.

[0009] Figure 3 A diagram showing an example non-limiting cross-sectional view of a device including a silicon-based Josephson junction during the second stage of fabrication according to one or more embodiments described herein.

[0010] Figure 4 A diagram showing an example non-limiting cross-sectional view of a device including a silicon-based Josephson junction during the third stage of fabrication according to one or more embodiments described herein.

[0011] Figure 5A An example non-limiting cross-sectional view of a device including a silicon-based Josephson junction during the fourth stage of manufacturing, according to one or more embodiments described herein.

[0012] Figure 5B An illustration of an example non-limiting top view of a device including a silicon-based Josephson junction during the fourth stage of manufacturing, according to one or more embodiments described herein.

[0013] Figure 6A An example non-limiting cross-sectional view of a device including a silicon-based Josephson junction during the fifth stage of manufacturing, according to one or more embodiments described herein.

[0014] Figure 6B An illustration of an example non-limiting top view of a device including a silicon-based Josephson junction during the fifth stage of manufacturing, according to one or more embodiments described herein.

[0015] Figure 7A An example non-limiting cross-sectional view of a device including a silicon-based Josephson junction during the sixth stage of manufacturing, according to one or more embodiments described herein.

[0016] Figure 7B An illustration of an example non-limiting top view of a device including a silicon-based Josephson junction during the sixth stage of manufacturing, according to one or more embodiments described herein.

[0017] Figure 8A An illustration of an example non-limiting cross-sectional view of a device including a silicon-based Josephson junction during the seventh stage of manufacturing, according to one or more embodiments described herein.

[0018] Figure 8B An illustration of an example non-limiting top view of a device including a silicon-based Josephson junction during the seventh stage of manufacturing, according to one or more embodiments described herein.

[0019] Figure 9A An example non-limiting cross-sectional view of a device including a silicon-based Josephson junction during the eighth stage of manufacturing, according to one or more embodiments described herein.

[0020] Figure 9BAn illustration of an example non-limiting top view of a device including a silicon-based Josephson junction during the eighth stage of manufacturing, according to one or more embodiments described herein.

[0021] Figure 10A An example non-limiting cross-sectional view of a device including a silicon-based Josephson junction during the ninth stage of manufacturing, according to one or more embodiments described herein.

[0022] Figure 10B An illustration of an example non-limiting top view of a device including a silicon-based Josephson junction during the ninth stage of manufacturing, according to one or more embodiments described herein.

[0023] Figure 11A An illustration of an example non-limiting cross-sectional view of a device including a silicon-based Josephson junction during the tenth stage of manufacturing, according to one or more embodiments described herein.

[0024] Figure 11B An illustration of an example non-limiting top view of a device including a silicon-based Josephson junction during the tenth stage of manufacturing, according to one or more embodiments described herein.

[0025] Figure 12A A diagram showing an example non-limiting cross-sectional view of a device including a silicon-based Josephson junction having one or more isolation implants according to one or more embodiments described herein.

[0026] Figure 12B An illustration of an example non-limiting top view of a device including a silicon-based Josephson junction having one or more isolation implants according to one or more embodiments described herein is shown.

[0027] Figure 13 A diagram showing an example non-limiting cross-sectional view of a device including a silicon-based Josephson junction during the first stage of fabrication according to one or more embodiments described herein.

[0028] Figure 14A An example non-limiting cross-sectional view of a device including a silicon-based Josephson junction during the second stage of fabrication according to one or more embodiments described herein is shown.

[0029] Figure 14B An illustration of an example non-limiting top view of a device including a silicon-based Josephson junction during the second stage of fabrication according to one or more embodiments described herein.

[0030] Figure 15AA diagram showing an example non-limiting cross-sectional view of a device including a silicon-based Josephson junction during the third stage of fabrication according to one or more embodiments described herein.

[0031] Figure 15B A diagram showing an example non-limiting top view of a device including a silicon-based Josephson junction during the third stage of manufacturing, according to one or more embodiments described herein.

[0032] Figure 16A An example non-limiting cross-sectional view of a device including a silicon-based Josephson junction during the fourth stage of manufacturing, according to one or more embodiments described herein.

[0033] Figure 16B An illustration of an example non-limiting top view of a device including a silicon-based Josephson junction during the fourth stage of manufacturing, according to one or more embodiments described herein.

[0034] Figure 17A A diagram showing an example non-limiting cross-sectional view of a device including a silicon-based Josephson junction during the fifth stage of manufacturing, according to one or more embodiments described herein.

[0035] Figure 17B An illustration of an example non-limiting top view of a device including a silicon-based Josephson junction during the fifth stage of manufacturing, according to one or more embodiments described herein.

[0036] Figure 18A An example non-limiting cross-sectional view of a device including a silicon-based Josephson junction during the sixth stage of manufacturing, according to one or more embodiments described herein.

[0037] Figure 18B A diagram showing an example non-limiting top view of a device including a silicon-based Josephson junction during the sixth stage of manufacturing, according to one or more embodiments described herein.

[0038] Figure 19A An illustration of an example non-limiting cross-sectional view of a device including a silicon-based Josephson junction during the seventh stage of manufacturing, according to one or more embodiments described herein.

[0039] Figure 19B An illustration of an example non-limiting top view of a device including a silicon-based Josephson junction during the seventh stage of manufacturing, according to one or more embodiments described herein.

[0040] Figure 20A A diagram showing an example non-limiting cross-sectional view of a device including a silicon-based Josephson junction during the eighth stage of manufacturing, according to one or more embodiments described herein.

[0041] Figure 20B A diagram showing an example non-limiting top view of a device including a silicon-based Josephson junction during the eighth stage of manufacturing, according to one or more embodiments described herein.

[0042] Figure 21A An example non-limiting cross-sectional view of a device including a silicon-based Josephson junction during the ninth stage of manufacturing, according to one or more embodiments described herein.

[0043] Figure 21B An illustration of an example non-limiting top view of a device including a silicon-based Josephson junction during the ninth stage of manufacturing, according to one or more embodiments described herein.

[0044] Figure 22A A diagram showing an example non-limiting cross-sectional view of a device including a silicon-based Josephson junction during the tenth stage of manufacturing, according to one or more embodiments described herein.

[0045] Figure 22B A diagram showing an example non-limiting top view of a device including a silicon-based Josephson junction during the tenth stage of manufacturing, according to one or more embodiments described herein.

[0046] Figure 23A A diagram showing an example non-limiting cross-sectional view of a device including a silicon-based Josephson junction during the eleventh stage of manufacturing, according to one or more embodiments described herein.

[0047] Figure 23B A diagram showing an example non-limiting top view of a device including a silicon-based Josephson junction during the eleventh stage of manufacturing, according to one or more embodiments described herein.

[0048] Figure 24A A diagram showing an example non-limiting cross-sectional view of a device including a silicon-based Josephson junction during the twelfth stage of manufacturing, according to one or more embodiments described herein.

[0049] Figure 24B A diagram showing an example non-limiting top view of a device including a silicon-based Josephson junction during the twelfth stage of manufacturing, according to one or more embodiments described herein.

[0050] Figure 25A A diagram showing an example non-limiting cross-sectional view of a device including a silicon-based Josephson junction during the thirteenth stage of manufacturing, according to one or more embodiments described herein.

[0051] Figure 25BA diagram showing an example non-limiting top view of a device including a silicon-based Josephson junction during the thirteenth stage of manufacturing, according to one or more embodiments described herein.

[0052] Figure 26A An illustration of an example non-limiting cross-sectional view of a device including a silicon-based Josephson junction during the fourteenth stage of manufacturing, according to one or more embodiments described herein.

[0053] Figure 26B An illustration of an example non-limiting top view of a device including a silicon-based Josephson junction during the fourteenth stage of manufacturing, according to one or more embodiments described herein.

[0054] Figure 27A A diagram showing an example non-limiting cross-sectional view of a device including a silicon-based Josephson junction during the fifteenth stage of manufacturing, according to one or more embodiments described herein.

[0055] Figure 27B A diagram showing an example non-limiting top view of a device including a silicon-based Josephson junction during the fifteenth stage of manufacturing, according to one or more embodiments described herein.

[0056] Figure 28 A flowchart illustrating an example non-limiting method for facilitating the fabrication of one or more silicon-based Josephson junctions according to one or more embodiments described herein is shown.

[0057] Figure 29 A flowchart illustrating an example non-limiting method for facilitating the fabrication of one or more silicon-based Josephson junctions according to one or more embodiments described herein is shown. Detailed Implementation

[0058] The following detailed description is illustrative only and is not intended to limit the embodiments and / or their application or use. Furthermore, it is not intended to be construed as being bound by any express or implied information presented in the foregoing Background or Summary of the Invention or Detailed Description sections.

[0059] One or more embodiments will now be described with reference to the accompanying drawings, wherein the same reference numerals are always used to denote the same elements. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent in various cases that one or more of the described embodiments may be practiced without these specific details. Additionally, features depicted in the drawings with similar shading, crosshairs, and / or coloring may include shared components and / or materials.

[0060] Josephson junctions have been used to fabricate qubits (e.g., superconducting qubits) to increase the coherence time exhibited by quantum computing devices. However, the theoretical coherence time associated with a Josephson junction is often less than the actual coherence time exhibited by the qubit. The material composition of a Josephson junction can affect the coherence time. For example, the type of superconducting material used, impurities in the superconducting material, and / or defects introduced by the fabrication processes associated with the superconducting material can adversely affect the coherence time exhibited by the Josephson junction qubit. For instance, an aluminum-based Josephson junction can exhibit a longer coherence time than a niobium-based Josephson junction, but may still experience decoherence due to defects typically introduced during the fabrication and / or deposition of aluminum and / or aluminum derivatives (e.g., alumina defects).

[0061] The various embodiments described herein may relate to apparatus and / or methods for fabricating silicon-based Josephson junctions for incorporation into one or more qubit devices. For example, one or more embodiments may relate to such a Josephson junction comprising a silicon material, which may be crystalline, such as doped superconducting silicon electrodes, wherein a single-crystal undoped silicon is used as the junction. By using silicon materials, chemical purification, crystal growth, and / or defect control can be achieved in the various embodiments described herein while implementing complementary metal-oxide-semiconductor (“CMOS”) technology. In one or more embodiments, the silicon-based Josephson junction may include a silicon dielectric material as a tunnel barrier between two superconducting silicon electrodes. Furthermore, one or more embodiments may include a vertically oriented silicon-based Josephson junction structure. Additionally, in various embodiments, electrical isolation of the Josephson junction may be achieved by intrinsic silicon and / or by incorporating one or more isolation implants within the silicon.

[0062] As described herein, the term "superconductivity" can characterize a material that exhibits superconducting properties at or below the superconducting critical temperature. Furthermore, as described herein, the terms "deposition process" and / or "multiple deposition processes" can refer to any process capable of growing, coating, depositing, and / or otherwise transferring one or more first materials onto one or more second materials. Exemplary deposition processes may include, but are not limited to: physical vapor deposition (“PVD”), chemical vapor deposition (“CVD”), electrochemical deposition (“ECD”), atomic layer deposition (“ALD”), low-pressure chemical vapor deposition (“LPCVD”), plasma-enhanced chemical vapor deposition (“PECVD”), high-density plasma chemical vapor deposition (“HDPCVD”), subatmospheric pressure chemical vapor deposition (“SACVD”), rapid thermochemical vapor deposition (“RTCVD”), in-situ radical-assisted deposition, high-temperature oxide deposition (“HTO”), low-temperature oxide deposition (“LTO”), limited reaction process CVD (“LRPCVD”), ultra-high vacuum chemical vapor deposition (“UHVCVD”), metal-organic chemical vapor deposition (“MOCVD”), physical vapor deposition (“PVD”), chemical oxidation, sputtering, electroplating, evaporation, spin coating, ion beam deposition, electron beam deposition, laser-assisted deposition, chemical solution deposition, combinations thereof, and / or similar methods.

[0063] As described herein, the terms "epitaxy growth process" and / or "multiple epitaxial growth processes" can refer to any process of growing an epitaxial material (e.g., a crystalline semiconductor material) on a deposition surface of another semiconductor material, wherein the grown epitaxial material has substantially the same crystal properties as the semiconductor material on the deposition surface. In an epitaxial deposition process, chemical reactants provided by a source gas (e.g., a silicon- and / or germanium-containing gas) and / or a source liquid can be controlled, and system parameters can be set such that the deposited atoms reach the deposition surface with sufficient energy to move on the surface and orient themselves toward the crystalline arrangement of atoms on the deposition surface. Therefore, the grown epitaxial material has substantially the same crystal properties as the deposition surface on which the epitaxial material is formed. For example, deposited on... <100> Epitaxially grown semiconductor materials on oriented crystal surfaces can exhibit <100> Orientation. Exemplary epitaxial growth processes may include, but are not limited to: vapor phase epitaxy (“VPE”), molecular beam epitaxy (“MBE”), liquid phase epitaxy (“LPE”), combinations thereof and / or similar methods.

[0064] As described herein, the terms “etching process,” “etching process,” “removal process,” and / or “removal process” can refer to any process that removes one or more first materials from one or more second materials. Exemplary etching and / or removal processes can include, but are not limited to, wet etching, dry etching (e.g., reactive ion etching (“RIE”)), chemical mechanical planarization (“CMP”), and combinations thereof.

[0065] As described herein, the terms "laser doping process" and / or "multiple laser doping processes" can refer to one or more gas immersion laser doping techniques that can achieve uniformly doped silicon layers with different activity concentrations and / or thicknesses. The laser doping process can be performed in an ultra-high vacuum ("UHV") chamber, where a precursor gas (e.g., boron trichloride) can be injected into the chamber and onto the surface of the silicon material (e.g., thereby saturating one or more chemisorption sites of the silicon material). Subsequently, a pulsed laser (e.g., a pulsed excimer XeCl laser) can be used to melt the silicon material to heat it for a defined duration. One or more dopants (e.g., boron, gallium, and / or germanium) from the precursor gas can diffuse into the silicon material and be alternatively incorporated. Thus, silicon-doped (e.g., silicon-boron (Si:B), silicon-germanium (Si:Ge), and / or silicon-gallium (Si:Ga)) crystals can be grown on the underlying silicon layer via one or more epitaxial growth processes.

[0066] Figure 1A 1B illustrates a diagram of an exemplary non-limiting qubit device 100 according to one or more embodiments described herein, the qubit device including a silicon-based Josephson junction, the Josephson junction including a first superconducting silicon electrode 102, a second superconducting silicon electrode 104, and / or a tunnel barrier 106. Figure 1A A cross-sectional view of the qubit device 100 is described. Figure 1B A top view of the quantum bit device 100 is depicted. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted.

[0067] like Figure 1A As shown, a silicon-based Josephson junction may be located on a semiconductor substrate 108. Furthermore, a first superconducting silicon electrode 102, a second superconducting silicon electrode 104, and / or a dielectric tunnel barrier 106 may be stacked on the semiconductor substrate 108 in a vertical orientation (e.g., along the "Y" axis). Additionally, at least a portion of the semiconductor substrate 108 and one or more isolation layers 110 may form an isolation region 112 adjacent to the silicon-based Josephson junction (e.g., depicted by a thick dashed line). Furthermore, the silicon-based Josephson junction may include a first metal contact 114 operably coupled to the first superconducting silicon electrode 102, and / or a second metal contact 116 operably coupled to the second superconducting silicon electrode 104.

[0068] The semiconductor substrate 108 can be crystalline, semi-crystalline, microcrystalline, or amorphous. Semiconductor substrate 108 may substantially (e.g., except for contaminants) comprise a single element (e.g., silicon or germanium) and / or compounds (e.g., alumina, silicon dioxide, gallium arsenide, silicon carbide, silicon germanium, combinations thereof, and / or the like). Semiconductor substrate 110 may also have multiple material layers, such as, but not limited to, semiconductor-on-insulator (“SeOI”), silicon-on-insulator (“SOI”), germanium-on-insulator (“GeOI”), silicon-on-germanium (“SGOI”), combinations thereof, and / or the like. Additionally, semiconductor substrate 110 may have other layers, such as oxides (“high-K oxides”) and / or nitrides having high dielectric constants. In one or more embodiments, semiconductor substrate 110 may be a silicon wafer. In various embodiments, semiconductor substrate 110 may comprise single-crystal silicon (Si), silicon germanium (e.g., characterized by the chemical formula SiGe), group III-V semiconductor wafers, or surface / active layers, combinations thereof, and / or the like.

[0069] In one or more embodiments, at least one top portion of the semiconductor substrate 108 may be a silicon-based Josephson junction and / or a quantum bit device 100 (e.g., as shown in the image). Figure 1A The semiconductor substrate 108 (as shown in 1B) provides structural support. In various embodiments, at least the top portion of the semiconductor substrate 108 may include intrinsic silicon. In some embodiments, at least the top of the semiconductor substrate 108 may include silicon germanium (SiGe).

[0070] The first superconducting silicon electrode 102 may comprise laser-doped crystalline silicon material. For example, one or more dopants may be incorporated into a portion of the silicon material via one or more laser doping processes to enhance superconductivity. Examples of dopants that may be included in the first superconducting silicon electrode 102 may include, but are not limited to, boron, gallium, germanium, combinations thereof, and / or the like. In one or more embodiments, the first superconducting silicon electrode 102 may have an active concentration of dopants ranging from, for example, greater than or equal to 4 atomic percent (At%) and less than or equal to 40 At% (e.g., at least 4 At% to 11 At% in the case where the first superconducting electrode 102 comprises a boron dopant, and / or at least 10 At% to 40 At% in the case where the first superconducting electrode 102 comprises a gallium dopant). In various embodiments, the critical temperature of the first superconducting electrode 102 can be in the range of, for example, greater than or equal to 500 milliklvin (mK) and less than or equal to 6K (e.g., 500 mK to 600 mK in the case where the first superconducting electrode 102 contains boron dopant, and / or 5K to 6K in the case where the first superconducting electrode 102 contains gallium dopant).

[0071] Those skilled in the art will recognize that the length of the first superconducting silicon electrode 102 (e.g., along the "X" axis) can vary depending on the function of the silicon-based Josephson junction and / or the structure of the qubit device 100. For example, the length of the first superconducting silicon electrode 102 (e.g., along the "X" axis) can be greater than or equal to 100 nanometers (nm) and less than or equal to several hundred micrometers (e.g., 500 nm to 1,000 nm). Similarly, the thickness of the first superconducting silicon electrode 102 (e.g., along the "Y" axis) can vary depending on the function of the silicon-based Josephson junction and / or the structure of the qubit device 100. For example, the thickness of the first superconducting silicon electrode 102 (e.g., along the "Y" axis) can be greater than or equal to 5 nm and less than or equal to 500 nm (e.g., 10 nm to 50 nm). Additionally, in one or more embodiments, the first superconducting silicon electrode 102 can be embedded within a semiconductor substrate 108 (e.g., as shown in the image). Figure 1A (As shown).

[0072] In one or more embodiments, the tunnel barrier 106, one or more isolation layers 110, and / or the first metal contact may be located above (e.g., directly above) the first superconducting silicon electrode 102. The tunnel barrier 106 is located in... Figure 1A The tunnel barrier 106 is depicted by dashed lines. In various embodiments, the tunnel barrier 106 may include a dielectric material to make the silicon-based Josephson junction a superconductor-insulator-superconductor (“SIS”) Josephson junction. For example, the tunnel barrier 106 may include intrinsic silicon material. In one or more embodiments, the tunnel barrier 106 may include doped silicon to make the silicon-based Josephson junction a superconductor-normal (“SNS”) Josephson junction. For example, one or more dopants that may be included in the tunnel barrier 106 may include, but are not limited to, phosphorus (P), arsenic (As), combinations thereof, and / or the like. Those skilled in the art will recognize that the length of the tunnel barrier 106 (e.g., along the “X” axis) may vary depending on the function of the silicon-based Josephson junction and / or the qubit device 100. For example, the length of the tunnel barrier 106 (e.g., along the “X” axis) may be greater than or equal to 30 nm and less than or equal to 1,000 nm (e.g., 100 nm to 300 nm). Similarly, the thickness of the tunnel barrier 106 (e.g., along the “Y” axis) can vary depending on the functionality of the silicon-based Josephson junction and / or the qubit device 100. For example, the thickness of the tunnel barrier 106 (e.g., along the “Y” axis) can be greater than or equal to 0.5 nm and less than or equal to 300 nm.

[0073] The second superconducting silicon electrode 104 can be positioned on the tunnel barrier 106, such that the tunnel barrier 106 is located between the first superconducting silicon electrode 102 and the second superconducting silicon electrode 104. In one or more embodiments, the second superconducting silicon electrode 104 may include the same or substantially the same composition as the first superconducting silicon electrode 102. Alternatively, in one or more embodiments, the second superconducting silicon electrode 104 may include a different composition than the first superconducting silicon electrode 102.

[0074] For example, the second superconducting silicon electrode 104 may comprise laser-doped crystalline silicon material. For example, one or more dopants may be incorporated into a portion of the silicon material via one or more laser doping processes to enhance superconductivity. Examples of dopants that may be included in the second superconducting silicon electrode 104 may include, but are not limited to, boron, gallium, combinations thereof, and / or the like. In one or more embodiments, the second superconducting silicon electrode 104 may have an active concentration of dopants ranging from, for example, greater than or equal to 4 At% and less than or equal to 40 At% (e.g., at least 4 At% to 11 At% in the case where the first superconducting electrode 102 comprises a boron dopant, and / or at least 10 At% to 40 At% in the case where the first superconducting electrode 102 comprises a gallium dopant). In various embodiments, the critical temperature of the second superconducting silicon electrode 104 may be in the range, for example, greater than or equal to 500 mK and less than or equal to 6 K (e.g., 500 mK to 600 mK in the case where the second superconducting electrode 104 comprises a boron dopant, and / or 5 K to 6 K in the case where the second superconducting electrode 104 comprises a gallium dopant).

[0075] Those skilled in the art will recognize that the length of the second superconducting silicon electrode 104 (e.g., along the "X" axis) can vary depending on the function of the silicon-based Josephson junction and / or qubit device 100. For example, the length of the second superconducting silicon electrode 104 (e.g., along the "X" axis) can be greater than or equal to 10 nm and less than or equal to several hundred micrometers (e.g., 500 nm to 1,000 nm). Similarly, the thickness of the second superconducting silicon electrode 104 (e.g., along the "Y" axis) can vary depending on the function of the silicon-based Josephson junction and / or qubit device 100. For example, the thickness of the second superconducting silicon electrode 104 (e.g., along the "Y" axis) can be greater than or equal to 5 nm and less than or equal to 500 nm (e.g., 10 nm to 50 nm).

[0076] In one or more embodiments, one or more isolation layers 110 may be adjacent to the first superconducting silicon electrode 102, the tunnel barrier 106, and / or the second superconducting silicon electrode 104. One or more isolation layers 110 may include one or more insulating materials and / or may electrically isolate the silicon-based Josephson junction from adjacent hardware and / or devices (e.g., adjacent qubit devices 100). In various embodiments, one or more isolation layers 110 may include intrinsic silicon and / or may be deposited within the same fabrication steps as the tunnel barrier 106. At least a portion of one or more isolation layers 110 and / or the semiconductor substrate 108 may define an isolation region 112 (e.g., in…). Figure 1A (Drawn by thick dashed lines). For example... Figure 1A As shown, in one or more embodiments, the semiconductor substrate 108, the tunnel barrier 106, and / or the isolation layer 110 may comprise the same or substantially the same material (e.g., intrinsic silicon).

[0077] like Figure 1A As shown, the first metal contact 114 and / or the second metal contact 116 may be adjacent to the isolation region 112 (e.g., on top of the isolation region 112, where the first superconducting silicon electrode 102, the tunnel barrier 106, and / or the second superconducting silicon electrode 104 are arranged in a stacked vertical orientation). The second metal contact 116 may be operatively coupled to (e.g., in direct contact with) the second superconducting silicon electrode 104. Furthermore, the first metal contact 114 may extend through a region that would otherwise be part of the isolation region 112 to be operatively coupled to the first superconducting silicon electrode 102. The first metal contact 114 and / or the second metal contact 116 may comprise conductive superconductors, such as, but not limited to: aluminum (Al), niobium (Nb), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), vanadium (V), tin (Sb), lead (Pb), combinations thereof, and / or the like.

[0078] Figure 1B Described Figure 1A The diagram shows a top view of the qubit device 100, and / or illustrates exemplary positioning and / or structural configuration of one or more features of the qubit device 100 along the "Z" axis. Although Figure 1A 1B describes a qubit device comprising a single Josephson junction located on a semiconductor substrate 108, but the structure of the qubit device 100 is not limited thereto. For example, qubit devices 100 comprising multiple Josephson junctions (e.g., multiple first superconducting silicon electrodes 102, tunnel barriers 106, and / or second superconducting silicon electrodes 104) are also contemplated. For example, one or more qubit devices 100 may include multiple Josephson junctions including the features described herein (e.g., in...). Figure 1A (and / or as depicted in 1B) and positioned adjacent to each other on the semiconductor substrate 108.

[0079] Figure 2 A diagram of an exemplary, non-limiting qubit device 100 during the first stage of fabrication according to one or more embodiments described herein is shown. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. During the first stage of fabrication, one or more resist masks 202 may be deposited onto a semiconductor substrate 108 via one or more deposition processes. The thickness of the resist mask 202 (e.g., along the “Y” axis) may vary, for example, ranging from greater than or equal to 100 and less than or equal to 1,000 nm (e.g., 100 nm to 300 nm). Exposed areas of the semiconductor substrate 108 (e.g., not covered by the resist mask 202) may define one or more boundaries of a silicon-based Josephson junction.

[0080] Figure 3 A schematic diagram of an exemplary, non-limiting quantum bit device 100 during a second stage of fabrication, according to one or more embodiments described herein, is provided. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. During the second stage of fabrication, a first superconducting silicon electrode 102 may be formed, and / or the resist mask 202 may be removed.

[0081] In one or more embodiments, exposed regions of the semiconductor substrate 108 (e.g., not covered by the photoresist mask 202) may undergo one or more laser doping processes to form a first superconducting silicon electrode 102. For example, the exposed regions may undergo one or more laser doping processes to implant boron dopant and form the first superconducting silicon electrode 102. In one or more embodiments, the first superconducting silicon electrode 102 may be formed by etching trenches into the exposed regions of the semiconductor substrate 108 (e.g., via one or more etching processes). Subsequently, epitaxial silicon material (e.g., epitaxial silicon dopant material (e.g., Si:Ga, Si:Ge, and / or Ge)) may be selectively deposited into the trenches via one or more epitaxial growth processes. The first superconducting silicon electrode 102 is grown via one or more epitaxial growth processes, and the thickness of the first superconducting silicon electrode 102 (e.g., along the "Y" axis) may be defined via one or more CMP processes. The photoresist mask 202 may be removed by one or more etching processes.

[0082] Figure 4A schematic diagram of an exemplary, non-limiting quantum bit device 100 during the third stage of fabrication, according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. During the third stage of fabrication, one or more silicon layers 402 may be deposited onto a first superconducting electrode 102 and / or a semiconductor substrate 108 via one or more deposition processes and / or epitaxial growth processes. In one or more embodiments, the one or more silicon layers 402 may be deposited at low temperatures (e.g., at temperatures below 500 degrees Celsius (°C) via one or more epitaxial growth processes, such as molecular beam epitaxy (“MBE”).

[0083] In one or more embodiments, one or more silicon layers 402 may subsequently form a tunnel barrier 106 and / or one or more isolation layers 110. Thus, the thickness of the one or more silicon layers 402 (e.g., along the “Y” axis) can vary depending on the desired thickness of the tunnel barrier 106, the one or more isolation layers 110, and / or the second superconducting silicon electrode 104. For example, the thickness of the one or more silicon layers 402 (e.g., along the “Y” axis) can be in the range of greater than or equal to 5 nm and less than or equal to 500 nm (e.g., 20 nm to 50 nm).

[0084] Figure 5A 5B illustrates a schematic diagram of an exemplary non-limiting qubit device 100 in the fourth stage of fabrication according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 5A Cross-sectional views of the qubit device 100 during the fourth stage of fabrication are depicted, and / or Figure 5B A top view of the qubit device 100 is depicted during the fourth stage of fabrication. During this fourth stage, one or more resist masks 202 may be deposited onto one or more silicon layers 402 via one or more deposition processes. Exposed areas of the one or more silicon layers 402 (e.g., not covered by the resist mask 202) may define one or more boundaries of the second superconducting silicon electrode 104.

[0085] Figure 6A 6B illustrates a schematic diagram of an exemplary non-limiting qubit device 100 in the fifth stage of fabrication according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 6A Describing cross-sectional views of the qubit device 100 during the fifth manufacturing stage, and / or Figure 6B A top view depicting the qubit device 100 during the fifth manufacturing stage. During the fifth manufacturing stage, a second superconducting silicon electrode 104 may be formed.

[0086] In one or more embodiments, exposed regions of one or more silicon layers 402 (e.g., not covered by the resist mask 202) may undergo one or more laser doping processes to form a second superconducting silicon electrode 104. For example, the exposed regions may undergo one or more laser doping processes to implant dopants (e.g., boron) and form the second superconducting silicon electrode 104. In one or more embodiments, the second superconducting silicon electrode 104 may be formed by etching trenches into the exposed regions of one or more silicon layers 402 (e.g., via one or more etching processes). Subsequently, epitaxial silicon material (e.g., epitaxial silicon dopant material (e.g., Si:Ga, Si:Ge, and / or Ge)) may be selectively deposited into the trenches via one or more epitaxial growth processes. The second superconducting silicon electrode 104 may be grown via one or more epitaxial growth processes, and the thickness of the second superconducting silicon electrode 104 (e.g., along the "Y" axis) may be defined via one or more CMP processes.

[0087] The formation of the second superconducting silicon electrode 104 can thereby define a tunnel barrier 106 and / or one or more isolation layers 110 and the remainder of one or more silicon layers 402. For example, the portion of one or more silicon layers 402 retained between the first superconducting silicon electrode 102 and the second superconducting silicon electrode 104 can be the tunnel barrier 106. For example, the tunnel barrier 106 can include intrinsic silicon (e.g., which can be used as a dielectric at a critical temperature of about 20 mK). Additionally, the portion of one or more silicon layers 402 adjacent to the second superconducting silicon electrode 104 and the tunnel barrier 106 can be one or more isolation layers 110.

[0088] In one or more embodiments, the remaining portion of the silicon layer 402 that can become a tunnel barrier 106 may be doped (e.g., with P, As, and / or the like) to form a normal metal tunnel barrier 106. For example, the remaining portion of the silicon layer 402 that can become a tunnel barrier 106 may be doped prior to an epitaxial growth process in which a second superconducting silicon electrode 104 may be formed.

[0089] Figure 7A 7B illustrates a schematic diagram of an exemplary, non-limiting qubit device 100 in the sixth stage of fabrication according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 7A A cross-sectional view depicting the qubit device 100 during the sixth stage of fabrication, and / or Figure 7B A top view depicting the qubit device 100 during the sixth stage of fabrication. During the sixth stage of fabrication, one or more resist masks 202 may be removed from one or more isolation layers 110 via one or more etching processes.

[0090] Figure 8A 8B illustrates a schematic diagram of an exemplary non-limiting qubit device 100 in the seventh stage of fabrication according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 8A Describing a cross-sectional view of the qubit device 100 during the seventh stage of fabrication, and / or Figure 8B A top view depicting the seventh stage of manufacturing of the qubit device 100.

[0091] During the seventh stage of manufacturing, one or more resist masks 202 may be deposited onto one or more isolation layers 110 and / or second superconducting silicon electrodes 104 via one or more deposition processes. Figure 8A As shown in 8B, a resist mask 202 can be deposited to leave a portion of one or more isolation layers 110 exposed. Furthermore, the exposed portions of one or more isolation layers 110 (e.g., portions not covered by the resist mask 202) can be aligned along the "Y" axis with a portion of the first superconducting silicon electrode 102 (e.g., as shown in 8B). Figure 8A (As shown).

[0092] Figure 9A 9B and / or 9B illustrate a schematic diagram of an exemplary non-limiting qubit device 100 in the eighth stage of fabrication according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 9A Cross-sectional views of the qubit device 100 during the eighth stage of fabrication are depicted, and / or Figure 9B A top view of the qubit device 100 is depicted during the eighth stage of manufacturing.

[0093] In the eighth stage of manufacturing, one or more exposed portions of the isolation layer 110 may be etched away (e.g., by one or more etching processes, such as RIE) to form contact holes 902 in the isolation layer 110 that can extend to the first superconducting silicon electrode 102. Figure 9A As shown in 9B, etching the contact hole 902 can expose a portion of the first superconducting silicon electrode 102 (e.g., by removing at least a portion of the isolation layer 110 previously covering the first superconducting silicon electrode 102). After etching the contact hole 902, one or more resist masks 202 can be removed (e.g., by one or more etching processes), and / or the exposed surfaces of the qubit device 100 can be cleaned (e.g., using DHF).

[0094] Figure 10AAnd / or 10B illustrates a schematic diagram of an exemplary non-limiting qubit device 100 in the ninth stage of fabrication according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 10A Cross-sectional views of the qubit device 100 during the ninth stage of fabrication are depicted, and / or Figure 10B A top view of the qubit device 100 during the ninth stage of manufacturing is depicted.

[0095] In the ninth stage of fabrication, one or more resist masks 202 may be patterned onto the second superconducting silicon electrode 104 and / or the isolation layer 110 (e.g., via one or more lift-off processes) to facilitate the formation of one or more metal contacts and / or bonding for one or more capacitors and / or resonators for the quantum bit device 100. Figure 10A As shown in 10B, at least a portion of the first superconducting silicon electrode 102 and / or the second superconducting silicon electrode may remain exposed (e.g., not covered) by one or more resist masks 202 deposited during the ninth stage of manufacturing.

[0096] Figure 11A And / or 11B illustrates a schematic diagram of an exemplary non-limiting qubit device 100 according to one or more embodiments described herein at the tenth stage of fabrication. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 11A Cross-sectional views of the qubit device 100 are depicted during the tenth stage of fabrication, and / or Figure 11B A top view of the qubit device 100 during the tenth stage of manufacturing is shown.

[0097] In the tenth stage of manufacturing, conductive metal material 1102 can be deposited (e.g., via one or more deposition processes) onto the exposed surfaces of the qubit device 100 and / or one or more resist masks 202. After depositing the conductive metal material 1102, the resist mask 202 and portions of the conductive metal material 1102 on the resist mask 202 can be removed (e.g., via one or more etching processes) to form a first metal contact 114 and / or a second metal contact 116 (e.g., as shown in the image). Figure 1A (As shown in 1B). Therefore, the conductive metal material 1102 can be the same metal included within the first metal contact 114 and / or the second metal contact 116. Figure 11AAs shown, conductive metal material can be deposited into contact hole 902, thereby depositing conductive metal material onto first superconducting silicon electrode 102. Those skilled in the art will recognize that the thickness of conductive metal material 1102 (e.g., along the "Y" axis) can vary depending on the functionality of qubit device 100 and / or the structural characteristics of first metal contact 114 and / or second metal contact 116.

[0098] Figure 12A 12B illustrates a schematic diagram of an exemplary, non-limiting qubit device 100 having an isolation layer 110 according to one or more embodiments described herein, the isolation layer including one or more isolation injectors. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. Figure 12A Cross-sectional views of a quantum bit device 100 including isolated injection are depicted, and / or Figure 12B A top view of a quantum bit device 100 including isolated injection is described.

[0099] In one or more embodiments, one or more isolation implants may be incorporated into one or more portions of one or more silicon layers 402 and / or semiconductor substrate 108 to form one or more isolation layers 110. Examples of isolation implants may include, but are not limited to, carbon, oxygen, nitrogen, combinations thereof, and / or the like. For example, one or more plasma immersion processes may be used to incorporate one or more isolation implants into portions of one or more silicon layers 402 and / or semiconductor substrate 108. In one or more embodiments, one or more isolation implants may be carbon implants, wherein acetylene, benzene, combinations thereof, etc., may be used as carbon sources in one or more plasma immersion processes. The one or more isolation implants may quench the conductivity of one or more isolation layers 110, thereby defining isolation regions 112. According to the various embodiments described herein, a quantum bit device 100 including isolation implants may include one or more silicon-based Josephson junctions arranged in a stacked, vertical orientation. Additionally, according to different embodiments described herein, the tunnel barrier 106 of a quantum bit device 100 including isolation implants may include a dielectric material or a common metallic material.

[0100] Figure 13A schematic diagram of an exemplary, non-limiting qubit device 100 comprising one or more isolation implants during a first stage of fabrication, according to one or more embodiments described herein, is shown. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. During the first stage of fabrication, a capping layer 1302 may be deposited (e.g., via one or more deposition processes) onto a multilayer structure comprising a semiconductor substrate 108, one or more superconducting silicon layers 1304, and / or a silicon barrier layer 1306. Exemplary materials that may be included within the capping layer 1302 may include, but are not limited to, silicon oxide, silicon nitride, silicon, CVD carbon, combinations thereof, and / or the like. Those skilled in the art will recognize that the thickness of the capping layer 1302 (e.g., along the “Y” axis) may vary. For example, the thickness of the capping layer 1302 (e.g., along the “Y” axis) may be greater than or equal to 5 nm and less than or equal to 500 nm (e.g., 30 nm to 100 nm).

[0101] like Figure 13 As shown, a silicon barrier layer 1306 may be located on one superconducting silicon layer 1304 (e.g., on a semiconductor substrate 108) and another superconducting silicon layer 1304 (e.g., adjacent to a capping layer 1302). In one or more embodiments, the superconducting silicon layer 1304 may continue to form the first superconducting silicon electrode 102 and / or the second superconducting silicon electrode 104 in subsequent manufacturing steps. Therefore, the superconducting silicon layer 1304 may comprise the same material as the first superconducting silicon electrode 102 and / or the second superconducting silicon electrode 104 according to the various embodiments described herein. Furthermore, in one or more embodiments, the multilayer structure may be based on one or more embodiments described herein (e.g., according to...). Figure 2-7B The features shown are formed via one or more laser doping processes, epitaxial growth processes, and / or etching processes.

[0102] Figure 14A And / or 14B illustrates a schematic diagram of an exemplary, non-limiting qubit device 100 comprising one or more isolation injectors during the second stage of fabrication, according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. Figure 14A A cross-sectional view of a quantum bit device 100 including one or more isolation injections during the second stage of fabrication, and / or Figure 14BA top view depicting a qubit device 100 including one or more isolation injections during a second stage of fabrication. During the second stage of fabrication of the qubit device 100 including one or more isolation injections, one or more resist layers 202 may be deposited (e.g., via one or more deposition processes) onto a capping layer 1302. In one or more embodiments, one or more resist layers 202 may cover a portion of the capping layer 1302 aligned with the defined boundary of a silicon-based Josephson junction.

[0103] Figure 15A And / or 15B illustrates a schematic diagram of an exemplary, non-limiting qubit device 100 comprising one or more isolation injectors in the third stage of fabrication according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 15A A cross-sectional view depicting a quantum bit device 100 including one or more isolation injections during the third stage of fabrication, and / or Figure 15B A top view depicting a qubit device 100 including one or more isolation injections during the third stage of fabrication. During the third stage of fabrication of the qubit device 100 including one or more isolation injections, one or more exposed portions (e.g., portions not covered by one or more resist masks 202) of the capping layer 1302 may be removed by one or more etching processes (e.g., using dilute hydrofluoric acid (“DHF”) and / or oxygen plasma).

[0104] Figure 16A And / or 16B illustrates a schematic diagram of an exemplary, non-limiting qubit device 100 comprising one or more isolation injectors in the fourth stage of fabrication according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. Figure 16A A cross-sectional view of a quantum bit device 100 including one or more isolation injections during the fourth stage of fabrication, and / or Figure 16B A top view depicting a qubit device 100 including one or more isolation injections during the fourth stage of fabrication. During the fourth stage of fabrication of the qubit device 100 including one or more isolation injections, one or more resist layers 202 may be removed by one or more etching processes to expose the remainder of the capping layer 1302.

[0105] Figure 17A And / or 17B shows a schematic diagram of an exemplary, non-limiting qubit device 100 comprising one or more isolation injectors in the fifth stage of fabrication according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 17A Cross-sectional views of a quantum bit device 100 including one or more isolation injections are depicted during the fifth stage of fabrication, and / or Figure 17B A top view of a quantum bit device 100 including one or more isolation injectors is depicted during the fifth stage of fabrication.

[0106] In the fifth stage of fabricating a quantum bit device 100 comprising one or more isolated injection sources, a capping layer 1302 and / or one or more portions of the multilayer stack (e.g., comprising one or more superconducting silicon layers 1304 and / or silicon barrier layers 1306) may be subjected to a first plasma immersion 1702 having one or more isolated injection sources. For example, where the one or more isolated injection sources are carbon, the capping layer 1302 and / or one or more portions of the multilayer stack may be subjected to a first plasma immersion 1702 having one or more carbon sources, such as acetylene, benzene, combinations thereof, and / or the like. Figure 17A As shown in 17B, the capping layer 1302 and / or one or more portions of the multilayer stack can be saturated with an isolated injection source (e.g., a carbon source, such as acetylene, benzene, or combinations thereof).

[0107] In various embodiments, one or more portions of the multilayer stack subjected to the first plasma immersion 1702 may be isolation regions 112 of the qubit device 100. Thus, the first plasma immersion 1702 may define one or more boundaries of one or more Josephson junctions contained within the qubit device 100. For example, the first plasma immersion 1702 may define the structural boundaries of the first superconducting silicon electrode 102 and / or the tunnel barrier 106 (e.g., as shown in the image). Figure 17A (As shown).

[0108] Figure 18A And / or 18B illustrates a schematic diagram of an exemplary, non-limiting qubit device 100 comprising one or more isolation injectors in the sixth stage of fabrication according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. Figure 18A A cross-sectional view of a quantum bit device 100 including one or more isolation injections during the sixth stage of fabrication, and / or Figure 18B A top view depicting a quantum bit device 100 including one or more isolation injections during the sixth stage of fabrication.

[0109] In the sixth stage of fabrication of a qubit device 100 including one or more isolation implants, portions of the qubit device 100 saturated with isolation implant sources may be annealed (e.g., laser annealing) to implant (e.g., and / or reduce lattice damage) isolation implants. For example, laser annealing can melt silicon in the irradiated region, where the pulse duration can be established based on the desired amount of silicon to be melted. For example, in one or more embodiments, isolation region 112 may be annealed (e.g., laser annealing) to form one or more isolation layers 110 that can suppress conductivity within isolation region 112. For example, in various embodiments, isolation region 112 may be saturated with a carbon source in the fifth stage and laser annealed in the sixth stage to implant one or more carbon isolation implants into isolation region 112 to form one or more isolation layers 110. Figure 18A As shown in 18B, the capping layer 1302 can protect the superconducting silicon layer 1304, the tunnel barrier 106, and / or the first superconducting silicon electrode 102 from being implanted with isolation injectants during the sixth stage.

[0110] Figure 19A And / or 19B illustrates a schematic diagram of an exemplary, non-limiting qubit device 100 comprising one or more isolation injectors in the seventh stage of fabrication according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. Figure 19A A cross-sectional view of a quantum bit device 100 including one or more isolation injections during the seventh stage of fabrication, and / or Figure 19B A top view depicting a quantum bit device 100 including one or more isolation injections during the seventh stage of fabrication.

[0111] In the seventh stage of fabricating a quantum bit device 100 including one or more isolation injectors, one or more resist layers 202 may be deposited (e.g., via one or more deposition processes) onto a capping layer 1302. In one or more embodiments, one or more resist layers 202 may cover a portion of the capping layer 1302 aligned with the defined boundary of the second superconducting silicon electrode 104.

[0112] Figure 20A And / or 20B illustrates a schematic diagram of an exemplary, non-limiting qubit device 100 comprising one or more isolation injectors in the eighth stage of fabrication according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 20A Cross-sectional views of a quantum bit device 100, including one or more isolation injections, are depicted in the eighth stage of fabrication, and / or Figure 20BA top view of a qubit device 100 including one or more isolation injections is depicted in the eighth stage of fabrication. In the eighth stage of fabrication of the qubit device 100 including one or more isolation injections, one or more exposed portions (e.g., portions not covered by one or more resist masks 202) of the capping layer 1302 can be removed by one or more etching processes (e.g., using DHF). Subsequently, the remaining portions of one or more resist masks 202 can be removed. Thus, the remaining portions of the capping layer 1302 can be positioned above the desired location of the second superconducting silicon electrode 104 (e.g., along the "Y" axis).

[0113] Figure 21A And / or 21B illustrates a schematic diagram of an exemplary, non-limiting qubit device 100 comprising one or more isolation injectors in the ninth stage of fabrication according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. Figure 21A Cross-sectional views of a quantum bit device 100 including one or more isolation injections are depicted during the ninth stage of fabrication, and / or Figure 21B A top view of a quantum bit device 100 including one or more isolation injectors is depicted during the ninth stage of fabrication.

[0114] In the ninth stage of fabrication of the quantum bit device 100, which includes one or more isolation injectors, one or more portions of the capping layer 1302 and / or the remaining superconducting silicon layer 1304 may be subjected to a second plasma immersion 2102 having one or more isolation injector sources. For example, where one or more isolation injectors are carbon, one or more portions of the capping layer 1302 and / or the superconducting silicon layer 1304 may be subjected to a second plasma immersion 2102 having one or more carbon sources, such as acetylene, benzene, or combinations thereof. Figure 21A As shown in 21B, one or more portions of the capping layer 1302 and / or the superconducting silicon layer 1304 can be saturated with an isolation injection source (e.g., a carbon source, such as acetylene, benzene, combinations thereof, etc.). In various embodiments, one or more portions of the superconducting silicon layer 1304 subjected to a second plasma immersion 2102 can extend the isolation region 112 of the qubit device 100 (e.g., in...). Figure 21A (Depicted by thick dashed lines). Thus, the second plasma immersion 2102 can define one or more boundaries of the second superconducting silicon electrode 104 (e.g., as shown in the image). Figure 21A (and / or as shown in 21B).

[0115] Figure 22AAnd / or 22B illustrates a schematic diagram of an exemplary, non-limiting qubit device 100 comprising one or more isolation injectors according to one or more embodiments described herein, in the tenth stage of fabrication. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. Figure 22A Cross-sectional views of a quantum bit device 100 including one or more isolation injections are depicted during the tenth stage of fabrication, and / or Figure 22B A top view of a quantum bit device 100 including one or more isolation injectors is depicted during the tenth stage of fabrication.

[0116] In the tenth stage of fabrication of a qubit device 100 including one or more isolation injectors, a portion of the qubit device 100 saturated with an isolation injection source may be annealed (e.g., laser annealing) to inject the isolation injector. For example, in one or more embodiments, isolation region 112 may be annealed (e.g., laser annealing) to form one or more isolation layers 110 that can suppress conductivity within isolation region 112. For example, in various embodiments, isolation region 112 may be saturated with a carbon source in the ninth stage and laser annealed in the tenth stage to inject one or more carbon isolation injectors into isolation region 112 to extend one or more isolation layers 110. Figure 22A As shown in 22B, the capping layer 1302 can protect the second superconducting silicon electrode 104 from being implanted with isolation implant during the tenth stage. Furthermore, in one or more embodiments, the tunnel barrier 106 and / or the first superconducting silicon electrode 102 can remain unimplanted with isolation implant during the tenth stage, thereby controlling the saturation depth of the isolation implantation source during the ninth stage of fabrication (e.g., along the "Y" axis), and thus controlling the depth of the isolation implantation bonding during the tenth stage of fabrication (e.g., along the "Y" axis).

[0117] Figure 23A And / or 23B shows a schematic diagram of an exemplary, non-limiting quantum bit device 100 in the eleventh stage of fabrication according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 23A A cross-sectional view depicting the qubit device 100 during the eleventh stage of fabrication, and / or Figure 23B A top view depicting the 11th stage of manufacturing of the qubit device 100.

[0118] During the eleventh stage of manufacturing, one or more resist masks 202 may be deposited onto one or more isolation layers 110 and / or capping layers 1302 via one or more deposition processes. For example... Figure 23AAs shown in 23B, a resist mask 202 can be deposited to leave a portion of one or more isolation layers 110 exposed. Furthermore, the exposed portions of one or more isolation layers 110 (e.g., portions not covered by the resist mask 202) can be aligned along the "Y" axis with a portion of the first superconducting silicon electrode 102 (e.g., as shown in 23B). Figure 23A (As shown).

[0119] Figure 24A And / or 24B shows a schematic diagram of an exemplary non-limiting qubit device 100 according to one or more embodiments described herein at the twelfth stage of fabrication. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 24A A cross-sectional view of the qubit device 100 during the twelfth stage of fabrication, and / or Figure 24B A top-down view depicting the qubit device 100 during the twelfth stage of manufacturing.

[0120] During the twelfth stage of manufacturing, one or more exposed portions of the isolation layer 110 may be etched away (e.g., via one or more etching processes, such as RIE) to form contact holes 902 in the isolation layer 110 that can extend to the first superconducting silicon electrode 102. Figure 9A As shown in 9B, etching the contact hole 902 can expose a portion of the first superconducting silicon electrode 102 (e.g., by removing at least a portion of the isolation layer 110 and / or tunnel barrier 106 previously covering the first superconducting silicon electrode 102). After etching the contact hole 902, one or more resist masks 202 can be removed (e.g., by one or more etching processes), and / or the exposed surfaces of the qubit device 100 can be cleaned (e.g., using DHF).

[0121] Figure 25A 25B illustrates a schematic diagram of an exemplary non-limiting qubit device 100 according to one or more embodiments described herein at the thirteenth stage of fabrication. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. Figure 25A A cross-sectional view depicting the qubit device 100 during the thirteenth stage of fabrication, and / or Figure 25B A top view depicting the qubit device 100 during the thirteenth stage of fabrication is shown. During the thirteenth stage of fabrication, the capping layer 1302 may be etched away (e.g., via one or more etching processes, such as RIE) to expose the second superconducting silicon electrode 104. Furthermore, the exposed surfaces of the qubit device 100 may be cleaned (e.g., using DHF).

[0122] Figure 26AAnd / or 26B shows a schematic diagram of an exemplary non-limiting qubit device 100 according to one or more embodiments described herein at the fourteenth stage of fabrication. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 26A A cross-sectional view depicting the qubit device 100 during the fourteenth stage of fabrication, and / or Figure 26B A top view depicting the qubit device 100 during the fourteenth stage of manufacturing.

[0123] During the fourteenth stage of fabrication, one or more resist masks 202 may be patterned onto the second superconducting silicon electrode 104 and / or the isolation layer 110 (e.g., via one or more lift-off processes) to facilitate the formation of one or more metal contacts and / or integration with one or more capacitors and / or resonators for the quantum bit device 100. Figure 26A As shown in 26B, at least a portion of the first superconducting silicon electrode 102 and / or the second superconducting silicon electrode may remain exposed (e.g., not covered) by one or more resist masks 202.

[0124] Figure 27A And / or 27B shows a schematic diagram of an exemplary non-limiting qubit device 100 according to one or more embodiments described herein in the fifteenth stage of fabrication. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 27A A cross-sectional view of the qubit device 100 during the fifteenth stage of fabrication, and / or Figure 27B A top view depicting the qubit device 100 during the fifteenth stage of manufacturing.

[0125] During the fifteenth stage of manufacturing, conductive metal material 1102 may be deposited (e.g., via one or more deposition processes) onto the exposed surfaces of the qubit device 100 and / or one or more resist masks 202. After the conductive metal material 1102 is deposited, the resist mask 202 and portions of the conductive metal material 1102 on the resist mask 202 may be removed (e.g., via one or more etching processes) to form a first metal contact 114 and / or a second metal contact 116 (e.g., as shown in the image). Figure 12A (As shown in 12B). Therefore, the conductive metal material 1102 can be the same metal included within the first metal contact 114 and / or the second metal contact 116. Figure 27AAs shown, conductive metal material can be deposited into contact hole 902, thereby depositing conductive metal material onto first superconducting silicon electrode 102. Those skilled in the art will recognize that the thickness of conductive metal material 1102 (e.g., along the "Y" axis) can vary depending on the functionality of qubit device 100 and / or the structural characteristics of first metal contact 114 and / or second metal contact 116.

[0126] Figure 28 A flowchart illustrating an exemplary, non-limiting method 2800 according to one or more embodiments described herein is shown, which can facilitate the fabrication of one or more quantum bit devices 100 including one or more silicon-based Josephson junctions. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted.

[0127] At 2802, method 2800 may include a portion of a doped semiconductor substrate 108 to form a first superconducting electrode (e.g., a first superconducting silicon electrode 102). For example, the doping at 2802 may be based on at least Figure 3 The second stage of manufacturing, as described herein, is performed, for example, the first superconducting electrode may be a first superconducting silicon electrode 102, and / or doping may include one or more laser doping processes according to one or more embodiments described herein.

[0128] At 2804, method 2800 may include depositing a silicon layer onto a first superconducting electrode via an epitaxial growth process to form a tunnel barrier 106. For example, the deposition at 2804 may be based on at least... Figure 4 The third stage of fabrication described herein is performed, for example, in one or more embodiments, the deposition at 2804 may grow an intrinsic silicon layer that can serve as a dielectric tunnel barrier 106 for a silicon-based Josephson junction during operation of the qubit device 100 at near-zero temperatures. In another example, according to one or more embodiments described herein, the deposition at 2804 may further include doping one or more portions of the deposited silicon layer to form a normal metal tunnel barrier 106.

[0129] At 2806, method 2800 may include one or more portions of the doped tunnel barrier 106 to form a second superconducting electrode (e.g., a second superconducting silicon electrode 104) thereby forming a Josephson junction. For example, it may be based on at least... Figure 6AThe doping at 2806 may be performed in the fifth stage of fabrication as described in 6B. For example, the second superconducting electrode may be a second superconducting silicon electrode 104, and / or the doping may include one or more laser doping processes according to one or more embodiments described herein. In various embodiments, the Josephson junction formed by method 2800 may be a silicon-based Josephson junction including a superconducting silicon electrode. Furthermore, superconducting silicon electrodes may be stacked in the vertical direction. Additionally, in one or more embodiments, the tunnel barrier 106 may be a dielectric tunnel barrier including intrinsic silicon.

[0130] Figure 29 A flowchart illustrating an exemplary, non-limiting method 2900 according to one or more embodiments described herein is shown, which can facilitate the fabrication of one or more qubit devices 100, comprising one or more silicon-based Josephson junctions electrically isolated by one or more isolation layers 110, which may include one or more isolation implants. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted.

[0131] At 2902, method 2900 may include a portion of a doped semiconductor substrate 108 to form a first superconducting electrode (e.g., a first superconducting silicon electrode 102). For example, the doping at 2902 may be based on at least Figure 3 The second stage of manufacturing, as described herein, is performed, for example, the first superconducting electrode may be a first superconducting silicon electrode 102, and / or doping may include one or more laser doping processes according to one or more embodiments described herein.

[0132] At 2904, method 2900 may include depositing a silicon layer onto the first superconducting electrode via an epitaxial growth process to form a tunnel barrier 106. For example, the deposition at 2904 may be based on at least Figure 4 The third stage of fabrication described herein may be carried out, for example, in one or more embodiments, the deposition at 2904 may grow an intrinsic silicon layer that can serve as a dielectric tunnel barrier 106 for a silicon-based Josephson junction during operation of the qubit device 100 at near-zero temperatures. In another example, according to one or more embodiments described herein, the deposition at 2904 may further include doping one or more portions of the deposited silicon layer to form a normal metal tunnel barrier 106.

[0133] At 2906, method 2900 may include doping one or more portions of tunnel barrier 106 to form a second superconducting electrode (e.g., a second superconducting silicon electrode 104) to form a Josephson junction. For example, it may be based on at least... Figure 6AThe fifth stage of fabrication as depicted in 6B is used to perform doping at 2806. For example, the second superconducting electrode may be a second superconducting silicon electrode 104, and / or the doping may include one or more laser doping processes according to one or more embodiments described herein. In various embodiments, the Josephson junction formed at 2906 may be a multilayer stacked structure, such as... Figure 13 The multilayer stack described herein, wherein one or more subsequent manufacturing processes may further define one or more structural features of the Josephson junction and / or electrically isolate the Josephson junction via combined isolation injection.

[0134] At 2908, method 2900 may include forming an isolation region 112 from the Josephson junction by immersing one or more isolation injection plasmas into portions of the first superconducting electrode (e.g., the first superconducting silicon electrode 102), the tunnel barrier 106, and the second superconducting electrode (e.g., the second superconducting silicon electrode 104). For example, forming the isolation region at 2908 may be based on… Figures 17A to 22B The process is performed in stages five through ten of the manufacturing process described herein. For example, forming the isolation zone at 2908 may include one or more plasma immersion processes and / or annealing processes according to one or more embodiments described herein.

[0135] In 2910, method 2900 may include forming a contact hole 902 in the isolation region 112 that can extend to the first superconducting electrode (e.g., the first superconducting silicon electrode 102). For example, it may be based on Figures 23A to 24B The eleventh and twelfth stages of manufacturing shown are used to form the contact hole 902.

[0136] At 2912, method 2900 may include depositing a first metal layer (e.g., conductive metal material 1102) into contact hole 902 to form a first metal contact 114 operatively coupled to a first superconducting electrode (e.g., a first superconducting silicon electrode 102). For example, forming the first metal contact 114 at 2912 may be based on… Figures 26A-27B Performed in the fourteenth and / or fifteenth stages of manufacturing as described in 12A-12B.

[0137] At 2914, method 2900 may include depositing a second metal layer (e.g., a conductive metal material 1102) onto a second superconducting electrode (e.g., a second superconducting silicon electrode 104) to form a second metal contact 116 operatively coupled to the second superconducting electrode (e.g., the second superconducting silicon electrode 104). For example, forming the first metal contact 114 at 2914 may be based on... Figures 26A-27B Performed in the fourteenth and / or fifteenth stages of manufacturing as described in 12A-12B.

[0138] Furthermore, the term "or" is intended to indicate an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X adopts A or B" is intended to indicate any natural inclusive permutation. That is, if X adopts A; X adopts B; or X adopts both A and B, then "X adopts A or B" is satisfied in any of the foregoing instances. Furthermore, unless otherwise specified or clear from the context to refer to the singular form, the articles "a" and "an" as used in this specification and figures should generally be interpreted as meaning "one or more". As used herein, the terms "example" and / or "exemplary" are used to indicate that something is used as an example, instance, or illustration. To avoid ambiguity, the subject matter disclosed herein is not limited to these examples. Moreover, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs, nor does it exclude equivalent exemplary structures and techniques known to those skilled in the art.

[0139] Of course, it is impossible to describe every conceivable combination of components, products, and / or methods for the purpose of describing this disclosure; however, those skilled in the art will recognize that many further combinations and substitutions of this disclosure are possible. Furthermore, with regard to the use of the terms “comprising,” “having,” “possessing,” etc., in the detailed description, claims, appendices, and drawings, these terms are intended to be inclusive in a similar manner to how the term “inclusive” is interpreted when used as a transitional term in the claims. Various embodiments have been described for illustrative purposes but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or improvements to existing technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A Josephson junction device, comprising: A Josephson junction includes a tunnel barrier between two vertically stacked superconducting silicon electrodes, wherein the two vertically stacked superconducting silicon electrodes include a first superconducting silicon electrode and a second superconducting silicon electrode situated on top of the first superconducting silicon electrode; and An isolation layer is located on the tunnel barrier and surrounds the second superconducting silicon electrode, wherein the top surface of the isolation layer is coplanar with the top surface of the second superconducting silicon electrode, and wherein the boundary between the isolation layer and the second superconducting silicon electrode is defined by an isolation implant of material injected into the second superconducting silicon electrode.

2. The Josephson junction device according to claim 1, wherein, The two vertically stacked superconducting silicon electrodes comprise silicon doped with at least one dopant selected from the group consisting of boron, gallium, and germanium.

3. The Josephson junction device according to claim 2, wherein the at least one dopant is boron, and wherein the two vertically stacked superconducting silicon electrodes each comprise greater than 4 atomic percent boron and less than or equal to 11 atomic percent boron.

4. The Josephson knot device according to any one of claims 1 to 3, further comprising: A first metal contact is operatively coupled to the first superconducting silicon electrode; as well as A second metal contact is operatively coupled to the second superconducting silicon electrode. The isolation layer electrically isolates the first metal contact from the second metal contact, wherein the isolation layer includes carbon implantation within silicon.

5. The Josephson knot device according to any one of claims 1 to 3, further comprising: A first metal contact is operatively coupled to the first superconducting silicon electrode; A second metal contact is operatively coupled to the second superconducting silicon electrode. The isolation layer electrically isolates the first metal contact from the second metal contact, wherein the isolation layer comprises intrinsic silicon.

6. The Josephson junction device according to any one of claims 1 to 3, wherein the tunnel barrier is doped with at least one dopant selected from the group consisting of phosphorus and arsenic.

7. The Josephson junction device according to any one of claims 1 to 3, wherein the tunnel barrier comprises intrinsic crystalline silicon.

8. A Josephson junction device, comprising: A Josephson junction includes a dielectric tunneling barrier located between two superconducting silicon electrodes, wherein the two superconducting silicon electrodes include a first superconducting silicon electrode and a second superconducting silicon electrode located on top of the first superconducting silicon electrode; and An isolation layer is located on the dielectric tunnel barrier and surrounds the second superconducting silicon electrode, wherein the top surface of the isolation layer is coplanar with the top surface of the second superconducting silicon electrode, and wherein the boundary between the isolation layer and the second superconducting silicon electrode is defined by an isolation implant of material injected into the second superconducting silicon electrode.

9. The Josephson junction device according to claim 8, wherein, The two superconducting silicon electrodes comprise silicon doped with at least one dopant selected from the group consisting of boron, germanium, and gallium.

10. The Josephson junction device of claim 9, wherein the at least one dopant is boron, and wherein the two superconducting silicon electrodes each comprise greater than 4 atomic percent boron and less than or equal to 11 atomic percent boron, respectively.

11. The Josephson knot device according to any one of claims 8 to 10, further comprising: A first metal contact is operatively coupled to the first superconducting silicon electrode; A second metal contact is operatively coupled to the second superconducting silicon electrode. The isolation layer electrically isolates the first metal contact from the second metal contact, wherein the isolation layer includes carbon implantation within silicon.

12. The apparatus according to any one of claims 8 to 10, further comprising: A first metal contact is operatively coupled to the first superconducting silicon electrode; A second metal contact is operatively coupled to the second superconducting silicon electrode. The isolation layer electrically isolates the first metal contact from the second metal contact, wherein the isolation layer comprises intrinsic silicon.

13. The apparatus according to any one of claims 8 to 10, wherein, The dielectric tunneling barrier comprises intrinsic crystalline silicon.

14. The apparatus according to any one of claims 8 to 10, wherein, The two superconducting silicon electrodes and the dielectric tunnel barrier are stacked vertically on the dielectric substrate.

15. A method for manufacturing a Josephson junction device, comprising: A portion of the silicon substrate is doped to form the first superconducting electrode; A silicon layer is deposited on the first superconducting electrode by an epitaxial growth process to form a tunnel barrier. as well as A portion of the tunnel barrier is doped to form a second superconducting electrode to form a Josephson junction; An isolation region is formed on the tunnel barrier and surrounding the second superconducting electrode, wherein the top surface of the isolation region is coplanar with the top surface of the second superconducting electrode, and wherein the boundary between the isolation region and the second superconducting electrode is defined by an isolation injector of material injected into the second superconducting electrode.

16. The method of claim 15, wherein the first dopant added by doping said portion of the silicon substrate and the second dopant added by doping said portion of the silicon layer are at least one selected from the group consisting of boron, gallium, and germanium.

17. The method according to claim 15 or 16, wherein, The formation of the isolation zone includes: The isolation region is formed from the Josephson junction by immersing a portion of the isolation injection plasma into the first superconducting electrode, the tunnel barrier, and the second superconducting electrode.

18. The method of claim 17, further comprising: A contact hole extending to the first superconducting electrode is formed in the isolation region; A first metal layer is deposited into the contact hole to form a first metal contact operably coupled to the first superconducting electrode; as well as A second metal layer is deposited onto the second superconducting electrode to form a second metal contact operatively coupled to the second superconducting electrode.

19. The method according to any one of claims 15, 16, and 18, wherein, The undoped portion of the silicon substrate and the undoped portion of the silicon layer define the isolation region adjacent to the Josephson junction.

20. The method of claim 19, further comprising: A contact hole extending to the first superconducting electrode is formed in the isolation region; A first metal layer is deposited into the contact hole to form a first metal contact operably coupled to the first superconducting electrode; as well as A second metal layer is deposited onto the second superconducting electrode to form a second metal contact operatively coupled to the second superconducting electrode.

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