Gallium nitride electronic devices and methods of making the same

Abstract

This invention discloses a gallium nitride (GaN) electronic device and its fabrication method. The fabrication method includes: providing an epitaxial structure layer comprising a lightly doped GaN layer, an aluminum-containing group III nitride semiconductor insertion layer, and a p-type GaN layer sequentially stacked on a substrate; processing a designated area on the surface of the p-type GaN layer to form a groove structure in the designated area, thereby exposing a portion of the aluminum-containing group III nitride semiconductor insertion layer within the groove structure; forming a first electrode within the groove structure, the first electrode forming a Schottky contact with the insertion layer; and fabricating a second electrode and a third electrode forming an ohmic contact with the epitaxial structure layer. The gallium nitride electronic device provided by this invention overcomes the shortcomings of existing technologies and has advantages such as stable and controllable junction region, good forward conduction, high reverse breakdown voltage, and good lateral forward current extension.

Description

Technical Field

[0001] This invention relates in particular to a gallium nitride electronic device and its fabrication method, belonging to the field of semiconductor technology. Background Technology

[0002] Currently, power conversion devices are mainly based on first-generation semiconductor silicon (Si) materials. However, as societal demands for power conversion devices continue to increase, the performance of silicon devices is increasingly approaching the theoretical limits determined by the material itself, making them unable to meet application requirements. Third-generation semiconductor materials, represented by gallium nitride (GaN), are rapidly becoming the preferred material for high-frequency, high-power electronic products due to their superior material properties (such as high critical breakdown field strength and high electron saturation drift velocity). Compared to Si and SiC materials, GaN materials possess an extremely high Baliga figure of merit (BFOM), enabling GaN-based power switching devices to achieve the same reverse breakdown voltage V0. B It has a lower on-resistance Ron than Si and SiC devices, and therefore its power loss is lower.

[0003] The basic structures of GaN-based power electronic devices can be divided into lateral and vertical structures. Lateral power devices based on AlGaN / GaN heterojunctions mainly rely on the high-density, high-mobility two-dimensional electron gas (2DEG) at the heterojunction interface for operation. Their advantages include fast switching speed and low series resistance. However, lateral structure devices face challenges in reliability and manufacturing cost, and their breakdown voltage is easily affected by the surface electric field (V0). B ∝Ec·d), in order to improve the withstand voltage of the device, the anode-cathode distance d needs to be increased; this leads to an increase in device size and cost; compared with the lateral structure, the peak electric field of the vertical structure device is far away from the surface, the current density in the drift region is uniform, and the device has good heat dissipation performance and high reliability.

[0004] As a typical representative of vertical devices, GaN-based Schottky barrier diodes (SBDs) have low on-state voltage (<1V) and rely on majority carriers for operation, exhibiting no conductivity modulation effect and very high switching frequency. However, due to surface states and image forces, GaN-based SBDs have high reverse leakage current, severely limiting their breakdown voltage. In contrast, PiN power diodes rely on the PN junction to withstand voltage, resulting in lower reverse leakage current and higher reverse breakdown voltage. However, due to the larger bandgap of GaN, the forward turn-on voltage of these devices is typically higher (>3V).

[0005] To balance turn-on voltage and improve reverse breakdown voltage, a new type of GaN-based vertical power device has been developed: the Junction Barrier Schottky (JBS) power diode, sometimes also called a Merged PiN-Schottky (MPS) power diode. This device features a PN junction alternating grid structure in its anode region. During forward conduction, the Schottky junction is primarily on, resulting in a low turn-on voltage, similar to a SBD. When a reverse bias is applied, the depletion regions of adjacent PN junctions expand, shifting the high electric field region from the surface to the bulk, resulting in low leakage current and high reverse breakdown voltage, similar to a PiN diode. Figure 1 As shown, JBS combines the advantages of SBD and PiN devices while avoiding their disadvantages, and has significant advantages such as low forward turn-on voltage, fast switching frequency, and high reverse withstand voltage.

[0006] Currently, GaN-based JBS is mainly prepared using three technical approaches:

[0007] (1) Selective doping, such as Figure 2 As shown, the main method involves selective Mg ion implantation to form a locally Mg-doped lightly doped GaN layer, followed by high-temperature annealing to form a locally p-type GaN, thereby creating an effective local PN junction depletion region on the GaN-based SBD. This technique is relatively mature in the fabrication of Si or SiC-based JBS devices. However, realizing GaN-based JBS using this method is very difficult, mainly due to the following reasons: 1) Large-scale Mg ion implantation can cause lattice damage to GaN (donor-type nitrogen vacancies), thereby compensating for Mg acceptors and affecting the hole concentration of pGaN; 2) Mg acceptors implanted in GaN require extremely high temperature (>1000℃) and high-pressure annealing activation, which is demanding and the GaN surface is prone to degradation; 3) During the high-temperature annealing activation of Mg, Mg ion diffusion can easily lead to PN junction drift, affecting the forward turn-on and turn-off of the device.

[0008] (2) First, "dry etching the groove" followed by "secondary epitaxy of pGaN", such as... Figure 3 As shown, a groove is first generated by selective etching, and then pGaN is epitaxially grown in the groove. The difficulties in preparing JBS by this method are: 1) Dry etching damage in the groove is difficult to repair well, affecting the quality of the groove PN junction; 2) High-temperature decomposition of the mask medium during the secondary epitaxial growth process leads to severe contamination of the interface impurities in the groove; 3) The growth anisotropy of GaN in the groove, the growth rate and Mg doping efficiency of p-type GaN on the sidewall (non-polar surface) and bottom (polar surface) of the groove are very different, which seriously affects the quality of the PN junction.

[0009] (3) The closest implementation to this invention: such as patent CN 110752260 A, firstly, p-type GaN is grown in one step, and then dry etching is used to form p-type GaN floating islands (exposing the n-lightly doped GaN layer), thereby effectively avoiding the problems of secondary epitaxy of pGaN trenches and Mg activation, greatly reducing the difficulty and complexity of the process. The principle is as follows: Figure 4 As shown; however, while this solution significantly reduces the technological difficulty, it faces the following problems:

[0010] 1) The depth of the pGaN groove is difficult to control precisely. In order to expose the surface of the n-lightly doped GaN layer to prepare the Schottky contact, pGaN usually needs to be over-etched. This leads to the weakening or even disappearance of the pinch-off effect of the lateral expansion of the PN junction depletion region under reverse bias voltage (red dashed area) on the Schottky depletion region. As a result, it is impossible to shield the electric field of the Schottky depletion region, which does not help to improve the breakdown voltage.

[0011] 2) Surface etching damage to the etched grooves is difficult to repair, significantly affecting the Schottky contact; interface state defects such as etching damage (N vacancies) on the surface of the n-lightly doped GaN layer can not only pin the Fermi level, causing a decrease in the height of the Schottky barrier, but also assist electron hopping and tunneling, leading to an increase in reverse leakage current of the Schottky contact, thereby affecting the device breakdown voltage.

[0012] 3) The forward conduction and reverse turn-off characteristics of the device cannot be optimized simultaneously. For GaN-based trench-structured JBS, although the pn junction pinch-off effect on both sides of the trench can suppress the reduction of the Schottky barrier height caused by the image force, the Schottky barrier height is still an important factor determining the reverse leakage current of the device. Unilaterally increasing the Schottky barrier height in the trench can reduce the off-state leakage current, but it will lead to an increase in the turn-on voltage, making it impossible to improve the forward turn-on and reverse turn-off characteristics of the device simultaneously.

[0013] As mentioned above, although the dry etching technique for preparing JBS can avoid the problems of secondary epitaxy of pGaN grooves and Mg activation, it faces many pain points such as uncontrollable groove depth, high interface state density, and inability to simultaneously improve conduction and turn-off characteristics, which greatly reduces the performance of actual devices compared to the ideal situation. Summary of the Invention

[0014] The main objective of this invention is to provide a gallium nitride electronic device and its fabrication method, so as to overcome the shortcomings of the prior art.

[0015] To achieve the aforementioned objectives, the technical solution adopted by this invention includes:

[0016] One embodiment of the present invention provides a method for fabricating a gallium nitride electronic device, comprising:

[0017] An epitaxial structure layer is provided, the epitaxial structure layer comprising a lightly doped GaN layer, an aluminum-containing group III nitride semiconductor insertion layer and a p-type GaN layer sequentially stacked on a substrate;

[0018] A designated area on the surface of the p-type GaN layer is processed to form a groove structure in the designated area on the surface of the p-type GaN layer, while a floating island structure is formed in the area outside the designated area, and a portion of the aluminum-containing group III nitride semiconductor insertion layer is exposed from the groove structure.

[0019] A first electrode is formed within the groove structure, and a Schottky contact is formed between the first electrode and the aluminum-containing group III nitride semiconductor intercalation layer; and

[0020] A second electrode and a third electrode are fabricated, both of which form ohmic contacts with the epitaxial structure layer.

[0021] Another aspect of the present invention provides a gallium nitride electronic device prepared by the aforementioned preparation method.

[0022] Compared with the prior art, the advantages of the present invention include:

[0023] 1) The method for fabricating a gallium nitride electronic device provided in this embodiment of the invention can achieve precise control of the groove depth by introducing an Al-containing group III nitride semiconductor insertion layer;

[0024] 2) The method for fabricating a gallium nitride electronic device provided in this embodiment of the invention can effectively repair interface etching damage and reduce interface state density through thermal decomposition.

[0025] 3) The method for fabricating a gallium nitride electronic device provided in this embodiment of the invention can improve the Schottky contact barrier between the metal and GaN by introducing an Al-containing group III nitride semiconductor insertion layer, thereby improving the reverse breakdown voltage capability;

[0026] 4) The method for fabricating a gallium nitride electronic device provided in this embodiment of the invention effectively utilizes the polarization electric field between Al-containing group III nitride semiconductors / GaN (typically AlGaN / GaN) to reduce the width of the Schottky depletion region, thereby enhancing forward electron tunneling and reducing the turn-on voltage, thus simultaneously improving the forward and reverse characteristics of the device.

[0027] 5) The method for fabricating gallium nitride electronic devices provided in this embodiment of the invention can effectively utilize the 2DEG induced by the polarization electric field between Al-containing group III nitride semiconductors / GaN (typically AlGaN / GaN) to enhance the forward current spread and reduce the on-resistance of the device. Attached Figure Description

[0028] Figure 1 This is a comparison chart of the IV characteristics of SBD, PiN, and JBS vertical power devices;

[0029] Figure 2 This is a schematic diagram illustrating the technical principle of JBS achieved through Mg ion implantation in existing technologies;

[0030] Figure 3 This is a schematic diagram illustrating the technical principle of JBS achieved through dry etching combined with secondary epitaxy in existing technologies.

[0031] Figure 4 This is a schematic diagram illustrating the technical principle of JBS achieved by dry etching pGaN in existing technologies;

[0032] Figure 5 This is a schematic diagram of the principle structure of achieving precise and controllable etching depth through an Al-containing etch-resistant group III nitride semiconductor in a typical embodiment of the present invention.

[0033] Figure 6 This is a schematic diagram of a GaN all-vertical structure electronic device provided in a typical embodiment of the present invention;

[0034] Figure 7 This is a schematic diagram of the epitaxial structure of a GaN fully vertical structure electronic device provided in a typical embodiment of the present invention;

[0035] Figure 8 This is a schematic diagram of the structure for preparing a mask pattern on the surface of an Al-containing group III nitride semiconductor capping layer in a typical embodiment of the present invention;

[0036] Figure 9 This is a schematic diagram of the structure after selective etching of p-type GaN to form a groove structure in a typical embodiment of the present invention;

[0037] Figure 10 This is a schematic diagram of the structure after removing the p-type GaN mask medium and repairing the p-type GaN sidewall etching damage by wet etching in a typical embodiment of the present invention.

[0038] Figure 11 This is a schematic diagram of the structure after the p-type GaN in the groove structure is removed by thermal decomposition method and the Al-containing group III nitride semiconductor insertion layer is exposed in a typical embodiment of the present invention.

[0039] Figure 12 This is a schematic diagram of the structure after depositing an anode Schottky contact metal in a groove structure in a typical embodiment of the present invention;

[0040] Figure 13This is a schematic diagram of the final device structure after ohmic contact electrodes are fabricated on the p-type GaN layer and the back side of the substrate in a typical embodiment of the present invention.

[0041] Figure 14 This is a schematic diagram of a GaN quasi-vertical structure electronic device provided in a typical embodiment of the present invention;

[0042] Figure 15 This is a schematic diagram of the epitaxial structure of a GaN quasi-vertical structure electronic device provided in a typical embodiment of the present invention;

[0043] Figure 16 This is a schematic diagram of the structure after mask pattern preparation and selective etching to expose the n+GaN epitaxial layer on the surface of an Al-containing group III nitride semiconductor capping layer, according to a typical embodiment of the present invention.

[0044] Figure 17 This is a schematic diagram of a groove structure formed by selective etching of a p-type GaN layer in a typical embodiment of the present invention;

[0045] Figure 18 This is a schematic diagram of the structure after removing the surface mask medium of the p-type GaN layer and repairing the etching damage on the sidewall of the groove structure in the p-type GaN layer by wet etching in a typical embodiment of the present invention.

[0046] Figure 19 This is a schematic diagram of the structure after removing the remaining p-type GaN in the groove structure and depositing the anode Schottky metal in a typical embodiment of the present invention using the thermal decomposition method;

[0047] Figure 20 This is a schematic diagram of the final device structure after ohmic contact electrodes are fabricated on p-type GaN layers and n+GaN epitaxial layers in a typical embodiment of the present invention. Detailed Implementation

[0048] In view of the shortcomings of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. The following will further explain and illustrate this technical solution, its implementation process, and its principles.

[0049] One embodiment of the present invention provides a method for fabricating a gallium nitride electronic device, comprising:

[0050] An epitaxial structure layer is provided, the epitaxial structure layer comprising a lightly doped GaN layer, an aluminum-containing group III nitride semiconductor insertion layer and a p-type GaN layer sequentially stacked on a substrate;

[0051] A designated area on the surface of the p-type GaN layer is processed to form a groove structure in the designated area on the surface of the p-type GaN layer, while a floating island structure is formed in the area outside the designated area, and a portion of the aluminum-containing group III nitride semiconductor insertion layer is exposed from the groove structure.

[0052] A first electrode is formed within the groove structure, and a Schottky contact is formed between the first electrode and the aluminum-containing group III nitride semiconductor intercalation layer; and

[0053] A second electrode and a third electrode are fabricated, both of which form ohmic contacts with the epitaxial structure layer.

[0054] In some more specific embodiments, the preparation method specifically includes: etching a designated area on the surface of the p-type GaN layer, and causing the etching reaction to stop automatically when it reaches or enters the aluminum-containing group III nitride semiconductor insertion layer, thereby forming the groove structure in the p-type GaN layer.

[0055] In some more specific embodiments, the preparation method specifically includes: first, etching a designated area on the surface of the p-type GaN layer to form a groove structure, and retaining a p-type GaN of a designated thickness at the bottom of the groove structure; then, removing the remaining p-type GaN at the bottom of the groove structure by thermal decomposition, and causing the thermal decomposition reaction to stop automatically when it reaches or enters the aluminum-containing group III nitride semiconductor insertion layer, so as to expose the aluminum-containing group III nitride semiconductor insertion layer.

[0056] Furthermore, the preparation method specifically includes: removing the p-type GaN remaining at the bottom of the groove structure by thermal decomposition reaction under N2 atmosphere or a mixed atmosphere of N2 and NH3 at 700-1000℃.

[0057] Furthermore, the thickness of the p-type GaN remaining at the bottom of the groove structure is 1-100 nm.

[0058] In some more specific implementations, the preparation method further includes: using wet etching to repair the internal damage of the groove structure, and annealing the exposed p-type GaN layer in the groove structure to activate the p-type GaN layer.

[0059] Furthermore, the etching solution used in the wet etching method includes any one or a combination of two or more of tetramethylammonium hydroxide (TMAH), potassium hydroxide solution, and sodium hydroxide solution, but is not limited thereto.

[0060] Furthermore, the annealing treatment is performed at a temperature of 500-1000℃ for a time of 10s-30min.

[0061] In some more specific embodiments, the preparation method further includes: forming an insulating dielectric layer on the sidewall of the groove structure.

[0062] Furthermore, the material of the insulating dielectric layer includes any one or a combination of two or more of SiO2, SiNx (0 < x < 1), SiON, Al2O3, AlON, SiAlON, TiO2, Ta2O5, ZrO2, and the thickness is 0 - 1 μm.

[0063] Furthermore, the material of the aluminum-containing group III nitride semiconductor insertion layer includes any one or a combination of two or more of AlN, AlGaN, AlInN, AlScN, AlInGaN, BAlN, BAlGaN, BAlInN, but is not limited thereto.

[0064] Furthermore, the content of Al in the aluminum-containing group III nitride semiconductor insertion layer is 0 - 50%, preferably 5 - 50%.

[0065] Furthermore, the content of Al in the aluminum-containing group III nitride semiconductor insertion layer gradually changes along its thickness direction.

[0066] Furthermore, the thickness of the aluminum-containing group III nitride semiconductor insertion layer is 0 - 50 nm.

[0067] Furthermore, an aluminum-containing group III nitride semiconductor cap layer is formed on the floating island structure.

[0068] Furthermore, the material of the aluminum-containing group III nitride semiconductor cap layer includes any one or a combination of two or more of AlN, AlGaN, AlInN, AlScN, AlInGaN, BAlN, BAlGaN, BAlInN, but is not limited thereto.

[0069] Furthermore, the content of Al in the aluminum-containing group III nitride semiconductor cap layer is 1 - 100%.

[0070] Furthermore, the thickness of the aluminum-containing group III nitride semiconductor cap layer is 0 - 30 nm.

[0071] Furthermore, the shape of the floating island structure includes any one or a combination of two or more of annular, strip-shaped, square, hexagonal, triangular, serrated, but is not limited thereto.

[0072] Furthermore, the lightly doped GaN layer includes an n+-type GaN epitaxial layer and an n-type GaN epitaxial layer arranged in a stacked manner, and the aluminum-containing group III nitride semiconductor insertion layer is arranged in a stacked manner on the n-type GaN epitaxial layer.

[0073] Furthermore, the gallium nitride electronic device has a fully vertical structure, the second electrode is disposed on the surface of the p-type GaN layer and forms an ohmic contact with the p-type GaN layer, and the third electrode is disposed on the back side of the substrate opposite to the lightly doped GaN layer.

[0074] Alternatively, the gallium nitride electronic device has a quasi-vertical structure, with the second electrode disposed on the surface of the p-type GaN layer and forming an ohmic contact with the p-type GaN layer, and the third electrode disposed on the surface of the n+ type GaN epitaxial layer and forming an ohmic contact with the n+ type GaN epitaxial layer.

[0075] Another aspect of the present invention provides a gallium nitride electronic device prepared by the aforementioned preparation method.

[0076] The following will further explain the technical solution, its implementation process and principle in conjunction with the accompanying drawings and specific implementation examples. Unless otherwise specified, the MOCVD and other methods, etching processes, etching solutions, etchants and masks, and other processes, materials and testing methods used in the embodiments of the present invention can all be those known to those skilled in the art.

[0077] To address the shortcomings of existing technologies, such as Figure 5 As shown, this invention proposes a gallium nitride electronic device and its fabrication method. An etch-resistant Al-containing group III nitride semiconductor alloy (i.e., the Al-containing group III nitride semiconductor insertion layer, typically represented by AlGaN) is grown between an n-type lightly doped GaN layer (also referred to as n-GaN) and a p-type GaN layer (also referred to as pGaN). Utilizing the advantage that the Al-N bond energy is larger than the Ga-N bond energy, a natural termination barrier is provided for the etching of the groove structure within the p-type GaN layer. By selecting a suitable temperature window and employing a near-destructive thermal decomposition method, precise and controllable termination of the pGaN / n-GaN interface etching is achieved, ensuring that the etching of the groove structure stops precisely at the pn junction interface. This addresses a significant shortcoming of the conventional "dry etching pGaN to prepare GaN-based JBS technology".

[0078] Furthermore, the gallium nitride electronic device and its fabrication method proposed in this embodiment of the invention also significantly reduce the interface state density by introducing an Al-containing group III nitride semiconductor insertion layer and combining it with a thermal decomposition method. Specifically, pGaN is first selectively etched to form a groove structure until a certain thickness of pGaN remains at the bottom of the groove structure. Then, the remaining pGaN at the bottom of the groove structure is removed by thermal decomposition. Since the thermal decomposition process does not involve ion bombardment damage as in conventional dry etching, an Al-containing group III nitride semiconductor surface with low surface state density can be achieved for the fabrication of Schottky contacts.

[0079] On the one hand, the preparation method provided by the embodiments of the present invention can achieve precise control of the groove structure depth and a groove structure surface with low interface state density, and has good consistency, uniformity and repeatability; on the other hand, the exposed Al-containing group III nitride semiconductor (wider band gap) has a higher Schottky contact barrier with the metal, which is beneficial to improving the reverse breakdown voltage of the device.

[0080] Furthermore, the fabrication method provided in this embodiment of the invention can reduce the width of the Schottky depletion region and enhance electron tunneling during forward turn-on by controlling the composition and thickness of the Al-containing group III nitride semiconductor and utilizing the polarization electric field between the Al-containing group III nitride semiconductor and GaN, thereby reducing the turn-on voltage. Finally, the two-dimensional electron gas (2DEG) induced by the polarization electric field between the Al-containing group III nitride semiconductor and the lightly doped GaN layer helps to enhance the lateral electron transport (current spread) during forward turn-on, thereby reducing the on-resistance of the device at low operating current densities.

[0081] Please see Figure 6 A GaN all-vertical structure electronic device structure, from bottom to top, includes a cathode ohmic contact electrode (i.e., the aforementioned third electrode, the same below) 10, a substrate 20, an n+ type GaN epitaxial layer 30, an n- type GaN epitaxial layer 40, an Al-containing group III nitride semiconductor insertion layer 50, a p-type GaN layer 60, an Al-containing group III nitride semiconductor capping layer 70, an anode Schottky contact electrode (i.e., the aforementioned first electrode, the same below) 100, and a pGaN ohmic contact electrode (i.e., the aforementioned second electrode, the same below) 110.

[0082] A method for fabricating a GaN vertical structure electronic device, comprising:

[0083] (1) Provide a GaN self-supporting substrate 20;

[0084] (2) An n+ type GaN epitaxial layer 30, an n- type GaN epitaxial layer 40, an Al-containing group III nitride semiconductor insertion layer 50, a p-type GaN layer 60, and an Al-containing group III nitride semiconductor capping layer 70 are sequentially grown on the front side of the GaN self-supporting substrate 20 using methods such as MOCVD. Figure 7 As shown;

[0085] (3) A mask pattern 80 is prepared on the surface of the Al-containing group III nitride semiconductor capping layer 70 by means of photolithography, such as... Figure 8 As shown;

[0086] (4) The Al-containing group III nitride semiconductor capping layer 70 and the p-type GaN layer 60 in the selected area are removed using methods such as dry etching, wet etching, and nanoimprinting. This forms a groove structure within the p-type GaN layer 60 in the selected area, a floating island structure in the area outside the selected area, and a certain thickness of p-type GaN is retained at the bottom of the groove structure. Figure 9 As shown;

[0087] (5) Preliminary repair of etching damage to the groove structure is carried out using methods such as wet etching, for example... Figure 10 As shown, the p-type GaN layer 60 is then activated by annealing; optionally, an insulating dielectric layer is subsequently deposited on the sidewalls of the groove structure.

[0088] (6) Remove the mask pattern from the p-type GaN surface, and then completely remove the residual p-type GaN at the bottom of the groove using methods such as thermal decomposition to expose the Al-containing group III nitride semiconductor insertion layer, forming a floating island structure of pGaN, such as... Figure 11 As shown;

[0089] (7) Anode Schottky metal is deposited in the groove structure using methods such as thermal evaporation and then annealed to form the first electrode 100, so that the first electrode 100 forms a good Schottky contact with the exposed Al-containing group III nitride semiconductor insertion layer 50, such as... Figure 12 As shown;

[0090] (8) Ohmic contact metals were deposited on the surface of the epitaxial structure layer and the back side of the substrate 20 using methods such as electron beam evaporation, followed by annealing to form the pGaN ohmic contact electrode 110 and the cathode ohmic contact electrode, respectively, thus completing the device fabrication. Figure 13 As shown.

[0091] Please refer to the following: Figure 14 A GaN quasi-vertical structure electronic device structure, from bottom to top, includes a substrate 201, a transition layer 301, an unintentionally doped GaN layer 401, an n+ type GaN epitaxial layer 501, an n- type GaN epitaxial layer 601, an Al-containing group III nitride semiconductor insertion layer 701, a p-type GaN layer 801, an Al-containing group III nitride semiconductor capping layer 901, an anode Schottky contact electrode (i.e., the aforementioned first electrode, the same below) 120, a p-type GaN ohmic contact electrode (i.e., the aforementioned second electrode, the same below) 130, and an n+ type GaN ohmic contact electrode (i.e., the aforementioned third electrode, the same below) 140.

[0092] A method for fabricating a GaN quasi-vertical structure electronic device, comprising:

[0093] (1) A substrate 201 is provided, which can be a substrate such as silicon, silicon carbide, SOI, diamond, zinc oxide, gallium oxide, etc.;

[0094] (2) Using methods such as MOCVD, a transition layer 301, an unintentionally doped GaN layer 401, an n+ type GaN epitaxial layer 501, an n- type GaN epitaxial layer 601, an Al-containing group III nitride semiconductor insertion layer 701, a p-type GaN layer 801, and an Al-containing group III nitride semiconductor capping layer 901 are sequentially grown on substrate 201. Figure 15 As shown;

[0095] (3) A mask pattern 101 is fabricated on the surface of the Al-containing group III nitride semiconductor capping layer 901 using photolithography and other methods. Then, the n+ type GaN epitaxial layer 501 is exposed using dry etching and other methods for subsequent fabrication of the cathode ohmic contact electrode. Afterward, part of the mask dielectric is removed using wet etching and other methods to locally expose the Al-containing group III nitride semiconductor capping layer on the surface, such as... Figure 16 As shown;

[0096] (4) A mask pattern is prepared using photolithography or similar methods. Then, the Al-containing group III nitride semiconductor capping layer 901 and the p-type GaN layer 801 in the selected area are removed using dry etching or similar methods to form a groove structure in the selected area and a floating island structure in the area outside the selected area. A certain thickness of p-type GaN is retained at the bottom of the groove structure. Figure 17 As shown;

[0097] (5) Wet etching and other techniques were used to repair the etching damage on the sidewalls of the groove structure within the p-type GaN layer, and the p-GaN epitaxial layer was activated by annealing; then, the surface mask medium was removed using wet etching, such as... Figure 18 As shown; optionally, an insulating dielectric layer is then deposited on the sidewalls of the groove structure;

[0098] (6) The formed epitaxial wafer is placed in the MOCVD reaction chamber, and the residual p-type GaN at the bottom of the trench structure is completely removed by methods such as thermal decomposition to expose the Al-containing group III nitride semiconductor insertion layer. Then, the first electrode is deposited in the trench structure by methods such as thermal evaporation and annealing, so that the formed first electrode 120 forms a good Schottky contact with the exposed Al-containing group III nitride semiconductor insertion layer surface, such as... Figure 19 As shown;

[0099] (7) Ohmic contact metals are deposited on the floating island structure of the p-type GaN layer and the exposed n+ GaN epitaxial layer 501 by methods such as electron beam evaporation, and then annealed to form p-type GaN ohmic contact electrodes 130 and n+ GaN ohmic contact electrodes 140, respectively, to complete the device fabrication, such as... Figure 20 As shown.

[0100] The present invention will now be described in detail with reference to the embodiments.

[0101] Example 1: Fabrication of vertical JBS structure using GaN self-supporting substrate

[0102] S1: A 2 μm n+ type GaN epitaxial layer (Si doping concentration 3 × 10⁻⁶) was sequentially epitaxially grown on a self-supporting GaN substrate using a metal-organic chemical vapor deposition (MOCVD) system. 18 cm -3 ), 6 μm n-type GaN epitaxial layer (Si doping concentration 2×10⁻⁶) 16 cm -3 ), a 5nm AlGaN insertion layer with 25% Al composition, and a 100nm p-type GaN layer (Mg doping concentration 3×10⁻⁶). 19 cm -3 ), 5 nm Mg-doped p-type GaN layer (Mg doping concentration 1×10⁻⁵) 20 cm -3 ), 1nm AlN capping layer, such as Figure 7 As shown;

[0103] S2: A strip-shaped mask is fabricated on the surface of the AlN capping layer using photolithography. The width ratio of the mask area to the window area is 1:1, and the window area width is 5 μm. Figure 8 As shown; then, the p-type GaN layer is selectively etched using ICP dry etching to form a groove structure within the p-type GaN layer corresponding to the window region, and a 10nm p-type GaN layer is retained at the bottom of the groove structure, as shown. Figure 9 As shown;

[0104] S3: At 85℃, perform wet etching treatment on the interior of the groove structure with tetramethylammonium hydroxide (TMAH) solution (potassium hydroxide solution, sodium hydroxide solution, etc. can also be used) for 10 minutes to initially repair the etching damage inside the groove structure of the p-type GaN layer. Figure 10 As shown;

[0105] S4: The photoresist mask on the AlN capping layer surface is removed using a resist remover. The epitaxial wafer is then placed in an MOCVD reaction chamber and heated to 850°C under a N2 and NH3 atmosphere to thermally decompose and remove the p-type GaN remaining at the bottom of the trench structure, exposing the low interface state density Al. 0.25 Ga 0.75 N-intercalation layers are used to form p-type GaN layers with floating island structures, such as Figure 11 As shown;

[0106] S5: Anneal the exposed p-type GaN in the groove structure for 30 seconds at 700℃ in a N2 atmosphere to activate the p-type GaN layer. Then, deposit a Ni (50nm) / Au (150nm) anode Schottky metal in the groove structure using a thermal evaporation process. Figure 12 As shown;

[0107] S6: An electron beam evaporation process is used to deposit a 100nm thickened Au metal on the surface of the AlN capping layer corresponding to the p-type GaN floating island structure as an ohmic contact electrode.

[0108] S7: A Ti / Al / Ti / Au (20 / 130 / 50 / 150nm) ohmic contact metal was deposited on the back side of a self-supporting GaN substrate using thermal evaporation. This was followed by annealing at 550℃ in a N2 atmosphere for 60 seconds to form the cathode ohmic contact electrode, thus completing the device fabrication. The final device structure is shown below. Figure 6 As shown.

[0109] Figure 6 The GaN vertical structure JBS prepared in Example 1 was tested using IV, and the results showed that the turn-on voltage of the GaN vertical structure JBS device obtained in Example 1 was 0.6V, and the on-resistance was only 0.7mΩ·cm. 2 The reverse leakage current is 1×10 -10 cm -2 It has a reverse withstand voltage of up to 1600V, which is about 400V higher than that of conventional GaN JBS devices.

[0110] Example 2: Fabrication of GaN quasi-vertical JBS structure using silicon substrate

[0111] S1: A 1 μm AlN / AlGaN transition layer, a 1 μm unintentionally doped GaN layer, and a 1 μm n+ type GaN epitaxial layer were sequentially epitaxially grown on a Si(111) substrate using an MOCVD apparatus (Si doping concentration 3×10⁻⁶). 18 cm -3 ), 4 μm n-type GaN epitaxial layer (Si doping concentration 1×10⁻⁴) 16 cm -3 AlGaN insertion layers with Al composition linearly varying from 0 to 25% at 5 nm, and p-type GaN layers at 150 nm (Mg doping concentration 2×10⁻⁶). 19 cm -3 ), 2nm Al 0.5 Ga 0.5 N capping layer, such as Figure 15 As shown;

[0112] S2: Using photolithography to fabricate Al epitaxial structures 0.5 Ga 0.5 An annular mask pattern is prepared on the surface of the N capping layer, with an inner ring diameter of 10 μm and an outer ring diameter of 20 μm. Then, the outer ring region is etched using an ICP dry etching process to expose the n+ type GaN epitaxial layer for subsequent preparation of the cathode ohmic contact electrode.

[0113] S3: Secondary photolithography mask. A SiNx layer is deposited in the inner ring region using PECVD. Then, a wet etching method is used to remove part of the mask medium and expose part of the Al. 0.5 Ga 0.5 N capping surface, such as Figure 16 As shown;

[0114] S4: Photolithography is used to prepare the mask pattern. ICP dry etching is then used to remove the exposed epitaxial structure, forming a groove structure within the p-type GaN layer. A 15nm p-type GaN layer is retained at the bottom of the groove structure. Figure 17 As shown;

[0115] S5: At 75℃, the interior of the groove structure was wet-etched with TMAH alkaline solution for 20 minutes to repair the etching damage inside the groove structure of the p-type GaN layer. Then, BOE solution was used to remove the SiNx mask dielectric. Figure 18 As shown;

[0116] S6: The formed epitaxial wafer is placed in the MOCVD reaction chamber and thermally decomposed at 800℃ under NH3 protection to remove the p-type GaN remaining at the bottom of the groove structure, so as to expose the AlGaN insertion layer with a gradual change in Al composition, thereby forming a p-type GaN layer with a floating island structure.

[0117] S7: The exposed p-type GaN layer inside the groove structure was thermally annealed for 10 minutes at 550℃ in a N2 atmosphere to activate the p-type GaN layer; then, Pd (50nm) / Au (150nm) Schottky contact electrodes were fabricated in the groove structure by electron beam evaporation, such as... Figure 19 As shown;

[0118] S8: A 100nm thickened Au electrode is deposited on the floating island of the p-type GaN layer by thermal evaporation, and the SiNx mask medium on the surface of the n+GaN epitaxial layer is removed by BOE solution. Then, Ti / Al / Ti / Au (20 / 130 / 50 / 150nm) ohmic contact metal is deposited on the surface of the n+GaN epitaxial layer by thermal evaporation.

[0119] S9: The ohmic contact metal was annealed at 750℃ in a N2 atmosphere for 60s to form a good gold-semiconductor contact, thus completing the device fabrication. The structure of the obtained silicon-based GaN vertical structure JBS is as follows: Figure 20 As shown.

[0120] Figure 14 The diagram shows the structure of the silicon-based GaN vertical structure JBS prepared in Example 2. IV testing shows that the turn-on voltage of the silicon-based GaN vertical structure JBS device prepared in Example 2 is 0.7V, and the on-resistance is only 0.9mΩ·cm. 2Reverse leakage current 1×10 -10 cm -2 It has a reverse withstand voltage of up to 950V, which is about twice that of conventional silicon-based GaN JBS devices.

[0121] The method for fabricating a GaN vertical structure JBS provided in this invention mainly utilizes an Al-containing group III nitride semiconductor intercalation layer (including but not limited to AlN, AlGaN, AlInN, AlScN, AlInGaN, BAlN, BAlGaN, BAlInN, etc.) to effectively control the positions of the PN junction depletion region and the gold half-Schottky junction depletion region in the JBS device, and effectively controls the interface state density of the groove region through thermal decomposition, thereby reducing the reverse leakage current of the device, suppressing the peak electric field at the edge of the Schottky junction, and significantly improving the breakdown voltage of the GaN-based JBS device.

[0122] This invention provides a method for fabricating a GaN vertical structure JBS. By introducing an Al-containing group III nitride semiconductor intercalation layer into the traditional GaN-based JBS device epitaxial structure to achieve self-termination of the etching process, this method not only ensures precise control of the gold-semiconductor Schottky junction region position and maximizes the coupling between the electric fields of the PN junction depletion region and the Schottky depletion region, but also leverages the advantages of thermal decomposition and selective etching to achieve a low interface state density gold-semiconductor Schottky contact. This significantly suppresses reverse leakage current and improves the device's breakdown voltage. Furthermore, the Al-containing group III nitride semiconductor intercalation layer also enables precise control of the etching depth of the pGaN groove structure within the GaN vertical structure electronic device.

[0123] This invention provides a method for fabricating a GaN vertical structure JBS, which utilizes an Al-containing group III nitride semiconductor insertion layer to achieve precise control over the position of the gold halftone Schottky junction region and maximize the coupling between the PN junction region and the Schottky junction region.

[0124] This invention provides a method for fabricating a GaN vertical structure JBS. First, a thin Al-containing group III nitride semiconductor insertion layer is epitaxially grown on a lightly doped GaN layer. Then, p-type GaN is grown, and a groove structure is formed by selected area etching. Next, a near-equilibrium thermal decomposition method is used to remove the residual p-type GaN within the groove structure. Taking advantage of the higher Al-N bond energy compared to Ga-N, the thermal decomposition within the groove structure terminates at the Al-containing group III nitride semiconductor insertion layer. This overcomes the drawback of uncontrollable groove depth in traditional pGaN JBSs, achieving precise control over the pGaN groove depth with excellent consistency, uniformity, and repeatability.

[0125] This invention provides a method for fabricating a GaN vertical structure JBS, which utilizes an Al-containing group III nitride semiconductor intercalation layer to simultaneously improve the device's reverse breakdown voltage, forward turn-on voltage, and conduction characteristics. Furthermore, by introducing an Al-containing group III nitride semiconductor intercalation layer, this invention can reduce reverse leakage current and improve reverse breakdown voltage, mainly in the following aspects:

[0126] 1) By using thermal decomposition technology to decompose p-type GaN into an Al-containing group III nitride semiconductor insertion layer, the depth of the groove structure can be precisely controlled, thereby maximizing the coupling between the electric field of the PN junction depletion region and the electric field of the metal / Al-containing group III nitride semiconductor Schottky depletion region. This is beneficial to weaken the peak electric field at the edge of the Schottky junction and improve the reverse breakdown voltage of the device.

[0127] 2) Compared with the surface of the groove structure formed by dry etching, the surface of the Al-containing group III nitride semiconductor insertion layer with thermal decomposition self-termination has a lower surface state density and good consistency, uniformity and repeatability. It can significantly suppress the hopping transport of electrons through the interface state energy level under reverse bias, and effectively suppress leakage current.

[0128] 3) Compared with metal / GaN Schottky contacts, the Schottky contact barrier between metal and Al-containing group III nitride semiconductor insertion layers with wider band gaps is higher, which is more conducive to suppressing electron leakage and improving the reverse breakdown voltage of the device.

[0129] Furthermore, the polarization field between the Al-containing group III nitride semiconductor and GaN can significantly reduce the depletion region width of the Schottky junction, thereby improving the forward tunneling capability of electrons and further reducing the turn-on voltage of GaN-based JBS / MPS. Simultaneously, the polarization field between the Al-containing group III nitride semiconductor and GaN can induce a certain concentration of 2DEG to enhance the lateral transport of forward electrons, resulting in lower on-resistance of the device at low currents (when the pn junction is not turned on). Therefore, using an Al-containing group III nitride semiconductor intercalation layer can improve the reverse breakdown voltage while simultaneously reducing the forward turn-on voltage and on-resistance of GaN vertical structure electronic devices.

[0130] The present invention provides a novel grooved GaN-based JBS structure and its preparation method, which can overcome the shortcomings of existing technical solutions and has the advantages of stability and controllability, good forward conductivity and high reverse withstand voltage, and has broad application prospects.

[0131] Compared with the prior art, the present invention provides a novel grooved structure GaN-based JBS / MPS and its preparation method. By introducing an Al-containing group III nitride semiconductor intercalation layer, the groove structure depth can be precisely controlled. The interface etching damage in the groove structure can be effectively repaired and the interface state density reduced by thermal decomposition. The introduction of the Al-containing group III nitride semiconductor intercalation layer can also improve the Schottky contact barrier between the metal and GaN, thereby improving the reverse breakdown voltage capability.

[0132] The fabrication method provided in this embodiment of the invention effectively utilizes the polarization electric field between Al-containing group III nitride semiconductors / GaN (typically AlGaN / GaN) to reduce the width of the Schottky depletion region, thereby enhancing forward electron tunneling and reducing the turn-on voltage, thus simultaneously improving the forward and reverse characteristics of the device. Furthermore, the fabrication method provided in this embodiment of the invention can also effectively utilize the 2DEG induced by the polarization electric field between Al-containing group III nitride semiconductors / GaN (typically AlGaN / GaN) to enhance forward current spread and reduce the on-resistance of the device.

[0133] This invention provides a novel grooved GaN-based JBS / MPS structure and its fabrication method, which has advantages such as stable and controllable junction region, good forward conduction, high reverse breakdown voltage, and good lateral expansion of forward current. The aluminum-containing group III nitride semiconductor insertion layer it contains integrates the dual functions of groove interface control and bandgap modulation. It has a huge advantage of achieving two goals at once: stable and near-damage-free controllable fabrication of p-GaN grooves and synchronous correlation control of the turn-on and turn-off characteristics of JBS devices. It has broad application prospects.

[0134] It should be understood that the above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A method of fabricating a gallium nitride electronic device, comprising: Comprising: ​ Providing an epitaxial structure layer, which includes a lightly doped GaN layer, an aluminum-containing group-III nitride semiconductor insertion layer, and a p-type GaN layer that are sequentially stacked on a substrate. First, etching is performed on a specified area on the surface of the p-type GaN layer to form a groove structure, and p-type GaN with a thickness of 1 - 100 nm is retained at the bottom of the groove structure, and an island structure is formed in the area outside the specified area, and a part of the aluminum-containing group-III nitride semiconductor insertion layer is exposed from within the groove structure. Then, the remaining p-type GaN at the bottom of the groove structure is removed by a thermal decomposition method, and the thermal decomposition reaction stops automatically when it reaches or enters the aluminum-containing group-III nitride semiconductor insertion layer, so as to expose the aluminum-containing group-III nitride semiconductor insertion layer. Forming a first electrode in the groove structure, and making the first electrode form a Schottky contact with the aluminum-containing group-III nitride semiconductor insertion layer. And Fabricating a second electrode and a third electrode, both of which form ohmic contacts with the epitaxial structure layer.

2. The preparation method according to claim 1, characterized in that... Specifically including: Etching a specified area on the surface of the p-type GaN layer, and making the etching reaction stop automatically when it reaches or enters the aluminum-containing group-III nitride semiconductor insertion layer, so as to form the groove structure in the p-type GaN layer.

3. The preparation method according to claim 1, characterized in that, Specifically including: The preparation method specifically includes: under a N2 atmosphere or a mixed atmosphere of N2 and NH3, at a temperature of 700 - 1000 °C, the remaining p-type GaN at the bottom of the groove structure undergoes a thermal decomposition reaction and is removed.

4. The preparation method according to claim 2 or 3, characterized in that, Further including: Using a wet etching method to repair the etching damage inside the groove structure, and annealing the p-type GaN layer exposed in the groove structure to activate the p-type GaN layer.

5. The preparation method according to claim 4, characterized in that: The etching solution used in the wet etching method includes any one or a combination of two or more of tetramethylammonium hydroxide (TMAH), potassium hydroxide solution, and sodium hydroxide solution.

6. The preparation method according to claim 4, characterized in that: The temperature of the annealing treatment is 500 - 1000 °C, and the time is 10 s - 30 min.

7. The preparation method according to claim 4, characterized in that, Further including: Forming an insulating dielectric layer on the side wall of the groove structure.

8. The preparation method according to claim 7, characterized in that: The material of the insulating dielectric layer includes any one or a combination of two or more of SiO2, SiNx (0 < x < 1), SiON, Al2O3, AlON, SiAlON, TiO2, Ta2O5, ZrO2, and the thickness of the insulating dielectric layer is 0 - 1 μm.

9. The preparation method according to claim 1, characterized in that: The material of the aluminum-containing group-III nitride semiconductor insertion layer includes any one or a combination of two or more of AlN, AlGaN, AlInN, AlScN, AlInGaN, BAlN, BAlGaN, BAlInN.

10. The preparation method according to claim 9, characterized in that: The content of Al in the aluminum-containing group-III nitride semiconductor insertion layer is 0 - 50%.

11. The preparation method according to claim 10, characterized in that: The content of Al in the aluminum-containing group-III nitride semiconductor insertion layer is 5 - 50%.

12. The preparation method according to claim 9, 10, or 11, characterized in that: The content of Al in the aluminum-containing group-III nitride semiconductor insertion layer varies gradually along its thickness direction.

13. The preparation method according to claim 1 or 9, characterized in that: The thickness of the aluminum-containing group-III nitride semiconductor insertion layer is 0 - 50 nm.

14. The preparation method according to claim 1, characterized in that: An Al-containing group III nitride semiconductor capping layer is also formed on the floating island structure.

15. The preparation method according to claim 14, characterized in that: The material of the Al-containing group III nitride semiconductor capping layer includes any one or a combination of two or more of AlN, AlGaN, AlInN, AlScN, AlInGaN, BAlN, BAlGaN, and BAlInN.

16. The preparation method according to claim 14, characterized in that: The Al content in the Al-containing group III nitride semiconductor capping layer is 1-100%.

17. The preparation method according to claim 14, characterized in that: The thickness of the Al-containing group III nitride semiconductor capping layer is 0-30 nm.

18. The preparation method according to claim 14, characterized in that: The shape of the floating island structure includes any one or a combination of two or more of the following: ring-shaped, strip-shaped, square, hexagonal, triangular, and serrated.

19. The preparation method according to claim 1, characterized in that: The lightly doped GaN layer includes an n+ type GaN epitaxial layer and an n- type GaN epitaxial layer stacked together, and the aluminum-containing group III nitride semiconductor insertion layer is stacked on the n- type GaN epitaxial layer.

20. The preparation method according to claim 19, characterized in that: The gallium nitride electronic device has a fully vertical structure. The second electrode is disposed on the surface of the p-type GaN layer and forms an ohmic contact with the p-type GaN layer. The third electrode is disposed on the back side of the substrate opposite to the lightly doped GaN layer. Alternatively, the gallium nitride electronic device has a quasi-vertical structure, with the second electrode disposed on the surface of the p-type GaN layer and forming an ohmic contact with the p-type GaN layer, and the third electrode disposed on the surface of the n+ type GaN epitaxial layer and forming an ohmic contact with the n+ type GaN epitaxial layer.

21. A gallium nitride electronic device prepared by any one of claims 1-20.

Images